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4acb54ba EI |
1 | /* |
2 | * MicroBlaze virtual CPU header | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
ee452036 | 9 | * version 2.1 of the License, or (at your option) any later version. |
4acb54ba EI |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
4acb54ba | 18 | */ |
07f5a258 MA |
19 | |
20 | #ifndef MICROBLAZE_CPU_H | |
21 | #define MICROBLAZE_CPU_H | |
4acb54ba | 22 | |
ffa3a3c6 | 23 | #include "cpu-qom.h" |
74433bf0 | 24 | #include "exec/cpu-defs.h" |
69242e7e | 25 | #include "qemu/cpu-float.h" |
4acb54ba | 26 | |
1ea4a06a | 27 | typedef struct CPUArchState CPUMBState; |
4acb54ba EI |
28 | #if !defined(CONFIG_USER_ONLY) |
29 | #include "mmu.h" | |
30 | #endif | |
31 | ||
2161be35 MT |
32 | #define EXCP_MMU 1 |
33 | #define EXCP_IRQ 2 | |
f5235314 | 34 | #define EXCP_SYSCALL 3 /* user-only */ |
2161be35 MT |
35 | #define EXCP_HW_BREAK 4 |
36 | #define EXCP_HW_EXCP 5 | |
4acb54ba | 37 | |
85097db6 RH |
38 | /* MicroBlaze-specific interrupt pending bits. */ |
39 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 | |
40 | ||
73c69456 AF |
41 | /* Meanings of the MBCPU object's two inbound GPIO lines */ |
42 | #define MB_CPU_IRQ 0 | |
43 | #define MB_CPU_FIR 1 | |
44 | ||
4acb54ba EI |
45 | /* Register aliases. R0 - R15 */ |
46 | #define R_SP 1 | |
47 | #define SR_PC 0 | |
48 | #define SR_MSR 1 | |
49 | #define SR_EAR 3 | |
50 | #define SR_ESR 5 | |
51 | #define SR_FSR 7 | |
52 | #define SR_BTR 0xb | |
53 | #define SR_EDR 0xd | |
54 | ||
55 | /* MSR flags. */ | |
56 | #define MSR_BE (1<<0) /* 0x001 */ | |
57 | #define MSR_IE (1<<1) /* 0x002 */ | |
58 | #define MSR_C (1<<2) /* 0x004 */ | |
59 | #define MSR_BIP (1<<3) /* 0x008 */ | |
60 | #define MSR_FSL (1<<4) /* 0x010 */ | |
61 | #define MSR_ICE (1<<5) /* 0x020 */ | |
62 | #define MSR_DZ (1<<6) /* 0x040 */ | |
63 | #define MSR_DCE (1<<7) /* 0x080 */ | |
64 | #define MSR_EE (1<<8) /* 0x100 */ | |
65 | #define MSR_EIP (1<<9) /* 0x200 */ | |
8a84fc6b | 66 | #define MSR_PVR (1<<10) /* 0x400 */ |
4acb54ba EI |
67 | #define MSR_CC (1<<31) |
68 | ||
69 | /* Machine State Register (MSR) Fields */ | |
70 | #define MSR_UM (1<<11) /* User Mode */ | |
71 | #define MSR_UMS (1<<12) /* User Mode Save */ | |
72 | #define MSR_VM (1<<13) /* Virtual Mode */ | |
73 | #define MSR_VMS (1<<14) /* Virtual Mode Save */ | |
74 | ||
75 | #define MSR_KERNEL MSR_EE|MSR_VM | |
76 | //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE | |
77 | #define MSR_KERNEL_VMS MSR_EE|MSR_VMS | |
78 | //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE | |
79 | ||
80 | /* Exception State Register (ESR) Fields */ | |
81 | #define ESR_DIZ (1<<11) /* Zone Protection */ | |
ab0c8d0f | 82 | #define ESR_W (1<<11) /* Unaligned word access */ |
4acb54ba EI |
83 | #define ESR_S (1<<10) /* Store instruction */ |
84 | ||
85453641 EI |
85 | #define ESR_ESS_FSL_OFFSET 5 |
86 | ||
ab0c8d0f RH |
87 | #define ESR_ESS_MASK (0x7f << 5) |
88 | ||
cedb936b EI |
89 | #define ESR_EC_FSL 0 |
90 | #define ESR_EC_UNALIGNED_DATA 1 | |
91 | #define ESR_EC_ILLEGAL_OP 2 | |
92 | #define ESR_EC_INSN_BUS 3 | |
93 | #define ESR_EC_DATA_BUS 4 | |
94 | #define ESR_EC_DIVZERO 5 | |
95 | #define ESR_EC_FPU 6 | |
96 | #define ESR_EC_PRIVINSN 7 | |
5818dee5 | 97 | #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ |
cedb936b EI |
98 | #define ESR_EC_DATA_STORAGE 8 |
99 | #define ESR_EC_INSN_STORAGE 9 | |
100 | #define ESR_EC_DATA_TLB 10 | |
101 | #define ESR_EC_INSN_TLB 11 | |
3b584046 | 102 | #define ESR_EC_MASK 31 |
4acb54ba | 103 | |
bdc0bf29 EI |
104 | /* Floating Point Status Register (FSR) Bits */ |
105 | #define FSR_IO (1<<4) /* Invalid operation */ | |
106 | #define FSR_DZ (1<<3) /* Divide-by-zero */ | |
107 | #define FSR_OF (1<<2) /* Overflow */ | |
108 | #define FSR_UF (1<<1) /* Underflow */ | |
109 | #define FSR_DO (1<<0) /* Denormalized operand error */ | |
110 | ||
4acb54ba EI |
111 | /* Version reg. */ |
112 | /* Basic PVR mask */ | |
113 | #define PVR0_PVR_FULL_MASK 0x80000000 | |
114 | #define PVR0_USE_BARREL_MASK 0x40000000 | |
115 | #define PVR0_USE_DIV_MASK 0x20000000 | |
116 | #define PVR0_USE_HW_MUL_MASK 0x10000000 | |
117 | #define PVR0_USE_FPU_MASK 0x08000000 | |
118 | #define PVR0_USE_EXC_MASK 0x04000000 | |
119 | #define PVR0_USE_ICACHE_MASK 0x02000000 | |
120 | #define PVR0_USE_DCACHE_MASK 0x01000000 | |
71446123 | 121 | #define PVR0_USE_MMU_MASK 0x00800000 |
c4374bb7 | 122 | #define PVR0_USE_BTC 0x00400000 |
a88bbb00 | 123 | #define PVR0_ENDI_MASK 0x00200000 |
c4374bb7 | 124 | #define PVR0_FAULT 0x00100000 |
4acb54ba EI |
125 | #define PVR0_VERSION_MASK 0x0000FF00 |
126 | #define PVR0_USER1_MASK 0x000000FF | |
9aaaa181 | 127 | #define PVR0_SPROT_MASK 0x00000001 |
4acb54ba | 128 | |
79549c99 EI |
129 | #define PVR0_VERSION_SHIFT 8 |
130 | ||
4acb54ba EI |
131 | /* User 2 PVR mask */ |
132 | #define PVR1_USER2_MASK 0xFFFFFFFF | |
133 | ||
134 | /* Configuration PVR masks */ | |
135 | #define PVR2_D_OPB_MASK 0x80000000 | |
136 | #define PVR2_D_LMB_MASK 0x40000000 | |
137 | #define PVR2_I_OPB_MASK 0x20000000 | |
138 | #define PVR2_I_LMB_MASK 0x10000000 | |
139 | #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 | |
140 | #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 | |
141 | #define PVR2_D_PLB_MASK 0x02000000 /* new */ | |
142 | #define PVR2_I_PLB_MASK 0x01000000 /* new */ | |
143 | #define PVR2_INTERCONNECT 0x00800000 /* new */ | |
144 | #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ | |
145 | #define PVR2_USE_FSL_EXC 0x00040000 /* new */ | |
146 | #define PVR2_USE_MSR_INSTR 0x00020000 | |
147 | #define PVR2_USE_PCMP_INSTR 0x00010000 | |
148 | #define PVR2_AREA_OPTIMISED 0x00008000 | |
149 | #define PVR2_USE_BARREL_MASK 0x00004000 | |
150 | #define PVR2_USE_DIV_MASK 0x00002000 | |
151 | #define PVR2_USE_HW_MUL_MASK 0x00001000 | |
152 | #define PVR2_USE_FPU_MASK 0x00000800 | |
153 | #define PVR2_USE_MUL64_MASK 0x00000400 | |
154 | #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ | |
155 | #define PVR2_USE_IPLBEXC 0x00000100 | |
156 | #define PVR2_USE_DPLBEXC 0x00000080 | |
157 | #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 | |
158 | #define PVR2_UNALIGNED_EXC_MASK 0x00000020 | |
159 | #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 | |
160 | #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 | |
161 | #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 | |
162 | #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 | |
163 | #define PVR2_FPU_EXC_MASK 0x00000001 | |
164 | ||
165 | /* Debug and exception PVR masks */ | |
166 | #define PVR3_DEBUG_ENABLED_MASK 0x80000000 | |
167 | #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 | |
168 | #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 | |
169 | #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 | |
170 | #define PVR3_FSL_LINKS_MASK 0x00000380 | |
171 | ||
172 | /* ICache config PVR masks */ | |
173 | #define PVR4_USE_ICACHE_MASK 0x80000000 | |
174 | #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 | |
175 | #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 | |
176 | #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 | |
177 | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 | |
178 | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 | |
179 | ||
180 | /* DCache config PVR masks */ | |
181 | #define PVR5_USE_DCACHE_MASK 0x80000000 | |
182 | #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 | |
183 | #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 | |
184 | #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 | |
185 | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 | |
186 | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 | |
c4374bb7 | 187 | #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 |
4acb54ba EI |
188 | |
189 | /* ICache base address PVR mask */ | |
190 | #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF | |
191 | ||
192 | /* ICache high address PVR mask */ | |
193 | #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF | |
194 | ||
195 | /* DCache base address PVR mask */ | |
196 | #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF | |
197 | ||
198 | /* DCache high address PVR mask */ | |
199 | #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF | |
200 | ||
201 | /* Target family PVR mask */ | |
202 | #define PVR10_TARGET_FAMILY_MASK 0xFF000000 | |
d248e1be | 203 | #define PVR10_ASIZE_SHIFT 18 |
4acb54ba EI |
204 | |
205 | /* MMU descrtiption */ | |
206 | #define PVR11_USE_MMU 0xC0000000 | |
207 | #define PVR11_MMU_ITLB_SIZE 0x38000000 | |
208 | #define PVR11_MMU_DTLB_SIZE 0x07000000 | |
209 | #define PVR11_MMU_TLB_ACCESS 0x00C00000 | |
7458a432 | 210 | #define PVR11_MMU_ZONES 0x003E0000 |
4acb54ba EI |
211 | /* MSR Reset value PVR mask */ |
212 | #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF | |
213 | ||
6fad9e98 AF |
214 | #define C_PVR_NONE 0 |
215 | #define C_PVR_BASIC 1 | |
216 | #define C_PVR_FULL 2 | |
4acb54ba EI |
217 | |
218 | /* CPU flags. */ | |
219 | ||
220 | /* Condition codes. */ | |
221 | #define CC_GE 5 | |
222 | #define CC_GT 4 | |
223 | #define CC_LE 3 | |
224 | #define CC_LT 2 | |
225 | #define CC_NE 1 | |
226 | #define CC_EQ 0 | |
227 | ||
85453641 EI |
228 | #define STREAM_EXCEPTION (1 << 0) |
229 | #define STREAM_ATOMIC (1 << 1) | |
230 | #define STREAM_TEST (1 << 2) | |
231 | #define STREAM_CONTROL (1 << 3) | |
232 | #define STREAM_NONBLOCK (1 << 4) | |
233 | ||
683a247e RH |
234 | #define TARGET_INSN_START_EXTRA_WORDS 1 |
235 | ||
ea2ccb65 JK |
236 | /* use-non-secure property masks */ |
237 | #define USE_NON_SECURE_M_AXI_DP_MASK 0x1 | |
238 | #define USE_NON_SECURE_M_AXI_IP_MASK 0x2 | |
239 | #define USE_NON_SECURE_M_AXI_DC_MASK 0x4 | |
240 | #define USE_NON_SECURE_M_AXI_IC_MASK 0x8 | |
241 | ||
1ea4a06a | 242 | struct CPUArchState { |
b9c58aab RH |
243 | uint32_t bvalue; /* TCG temporary, only valid during a TB */ |
244 | uint32_t btarget; /* Full resolved branch destination */ | |
4acb54ba EI |
245 | |
246 | uint32_t imm; | |
5c594ef3 | 247 | uint32_t regs[32]; |
0f96e96b | 248 | uint32_t pc; |
1074c0fb RH |
249 | uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */ |
250 | uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */ | |
19f27b6c | 251 | target_ulong ear; |
6efd5599 | 252 | uint32_t esr; |
86017ccf | 253 | uint32_t fsr; |
ccf628b7 | 254 | uint32_t btr; |
39db007e | 255 | uint32_t edr; |
97694c57 | 256 | float_status fp_status; |
5818dee5 EI |
257 | /* Stack protectors. Yes, it's a hw feature. */ |
258 | uint32_t slr, shr; | |
4acb54ba | 259 | |
8cc9b43f PC |
260 | /* lwx/swx reserved address */ |
261 | #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ | |
403322ea | 262 | target_ulong res_addr; |
11a76217 | 263 | uint32_t res_val; |
8cc9b43f | 264 | |
4acb54ba | 265 | /* Internal flags. */ |
7b34f45f RH |
266 | #define IMM_FLAG (1 << 0) |
267 | #define BIMM_FLAG (1 << 1) | |
ab0c8d0f RH |
268 | #define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */ |
269 | /* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flags */ | |
2c32179f RH |
270 | /* MSR_UM (1 << 11) */ |
271 | /* MSR_VM (1 << 13) */ | |
ab0c8d0f | 272 | /* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */ |
64603d1e | 273 | #define D_FLAG (1 << 12) /* Bit in ESR. */ |
4acb54ba EI |
274 | #define DRTI_FLAG (1 << 16) |
275 | #define DRTE_FLAG (1 << 17) | |
276 | #define DRTB_FLAG (1 << 18) | |
31f163d3 | 277 | |
68cee38a | 278 | /* TB dependent CPUMBState. */ |
88e74b61 RH |
279 | #define IFLAGS_TB_MASK (D_FLAG | BIMM_FLAG | IMM_FLAG | \ |
280 | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) | |
31f163d3 RH |
281 | #define MSR_TB_MASK (MSR_UM | MSR_VM | MSR_EE) |
282 | ||
4acb54ba EI |
283 | uint32_t iflags; |
284 | ||
4acb54ba EI |
285 | #if !defined(CONFIG_USER_ONLY) |
286 | /* Unified MMU. */ | |
8ce97bc1 | 287 | MicroBlazeMMU mmu; |
4acb54ba EI |
288 | #endif |
289 | ||
1f5c00cf AB |
290 | /* Fields up to this point are cleared by a CPU reset */ |
291 | struct {} end_reset_fields; | |
292 | ||
8bac2242 | 293 | /* These fields are preserved on reset. */ |
ae7d54d4 | 294 | }; |
4acb54ba | 295 | |
84bf3249 RH |
296 | /* |
297 | * Microblaze Configuration Settings | |
a0b2d16a RH |
298 | * |
299 | * Note that the structure is sorted by type and size to minimize holes. | |
84bf3249 RH |
300 | */ |
301 | typedef struct { | |
a0b2d16a RH |
302 | char *version; |
303 | ||
de73ee1a RH |
304 | uint64_t addr_mask; |
305 | ||
84bf3249 | 306 | uint32_t base_vectors; |
a0b2d16a | 307 | uint32_t pvr_user2; |
a4bcfc33 | 308 | uint32_t pvr_regs[13]; |
a0b2d16a | 309 | |
84bf3249 RH |
310 | uint8_t addr_size; |
311 | uint8_t use_fpu; | |
312 | uint8_t use_hw_mul; | |
a0b2d16a RH |
313 | uint8_t pvr_user1; |
314 | uint8_t pvr; | |
de73ee1a RH |
315 | uint8_t mmu; |
316 | uint8_t mmu_tlb_access; | |
317 | uint8_t mmu_zones; | |
a0b2d16a RH |
318 | |
319 | bool stackprot; | |
84bf3249 RH |
320 | bool use_barrel; |
321 | bool use_div; | |
322 | bool use_msr_instr; | |
323 | bool use_pcmp_instr; | |
324 | bool use_mmu; | |
ea2ccb65 | 325 | uint8_t use_non_secure; |
84bf3249 RH |
326 | bool dcache_writeback; |
327 | bool endi; | |
328 | bool dopb_bus_exception; | |
329 | bool iopb_bus_exception; | |
330 | bool illegal_opcode_exception; | |
331 | bool opcode_0_illegal; | |
332 | bool div_zero_exception; | |
333 | bool unaligned_exceptions; | |
84bf3249 RH |
334 | } MicroBlazeCPUConfig; |
335 | ||
ffa3a3c6 PB |
336 | /** |
337 | * MicroBlazeCPU: | |
338 | * @env: #CPUMBState | |
339 | * | |
340 | * A MicroBlaze CPU. | |
341 | */ | |
b36e239e | 342 | struct ArchCPU { |
ffa3a3c6 PB |
343 | /*< private >*/ |
344 | CPUState parent_obj; | |
345 | ||
346 | /*< public >*/ | |
ea2ccb65 JK |
347 | bool ns_axi_dp; |
348 | bool ns_axi_ip; | |
349 | bool ns_axi_dc; | |
350 | bool ns_axi_ic; | |
ffa3a3c6 | 351 | |
5b146dc7 RH |
352 | CPUNegativeOffsetState neg; |
353 | CPUMBState env; | |
84bf3249 | 354 | MicroBlazeCPUConfig cfg; |
ffa3a3c6 PB |
355 | }; |
356 | ||
ffa3a3c6 | 357 | |
eb3ef313 | 358 | #ifndef CONFIG_USER_ONLY |
ffa3a3c6 PB |
359 | void mb_cpu_do_interrupt(CPUState *cs); |
360 | bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); | |
eb3ef313 | 361 | #endif /* !CONFIG_USER_ONLY */ |
8905770b MAL |
362 | G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, |
363 | MMUAccessType access_type, | |
364 | int mmu_idx, uintptr_t retaddr); | |
90c84c56 | 365 | void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
43a9ede1 JK |
366 | hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, |
367 | MemTxAttrs *attrs); | |
a010bdbe | 368 | int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
ffa3a3c6 | 369 | int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
b77f98ca | 370 | |
1074c0fb RH |
371 | static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) |
372 | { | |
373 | /* Replicate MSR[C] to MSR[CC]. */ | |
374 | return env->msr | (env->msr_c * (MSR_C | MSR_CC)); | |
375 | } | |
376 | ||
377 | static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val) | |
378 | { | |
379 | env->msr_c = (val >> 2) & 1; | |
380 | /* | |
381 | * Clear both MSR[C] and MSR[CC] from the saved copy. | |
382 | * MSR_PVR is not writable and is always clear. | |
383 | */ | |
384 | env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR); | |
385 | } | |
386 | ||
cd0c24f9 | 387 | void mb_tcg_init(void); |
4acb54ba | 388 | |
0dacec87 | 389 | #define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU |
b33ab1f7 | 390 | |
4acb54ba | 391 | /* MMU modes definitions */ |
4acb54ba EI |
392 | #define MMU_NOMMU_IDX 0 |
393 | #define MMU_KERNEL_IDX 1 | |
394 | #define MMU_USER_IDX 2 | |
395 | /* See NB_MMU_MODES further up the file. */ | |
396 | ||
022c62cb | 397 | #include "exec/cpu-all.h" |
4acb54ba | 398 | |
31f163d3 RH |
399 | /* Ensure there is no overlap between the two masks. */ |
400 | QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); | |
401 | ||
68cee38a | 402 | static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, |
89fee74a | 403 | target_ulong *cs_base, uint32_t *flags) |
4acb54ba | 404 | { |
76e8187d | 405 | *pc = env->pc; |
31f163d3 | 406 | *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); |
d7ecb757 | 407 | *cs_base = (*flags & IMM_FLAG ? env->imm : 0); |
4acb54ba | 408 | } |
faed1c2a | 409 | |
3c7b48b7 | 410 | #if !defined(CONFIG_USER_ONLY) |
fd297732 RH |
411 | bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
412 | MMUAccessType access_type, int mmu_idx, | |
413 | bool probe, uintptr_t retaddr); | |
414 | ||
bdff8123 PM |
415 | void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, |
416 | unsigned size, MMUAccessType access_type, | |
417 | int mmu_idx, MemTxAttrs attrs, | |
418 | MemTxResult response, uintptr_t retaddr); | |
4acb54ba | 419 | #endif |
f081c76c | 420 | |
f5c7e93a RH |
421 | static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) |
422 | { | |
423 | MicroBlazeCPU *cpu = env_archcpu(env); | |
424 | ||
425 | /* Are we in nommu mode?. */ | |
2e5282ca | 426 | if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { |
f5c7e93a RH |
427 | return MMU_NOMMU_IDX; |
428 | } | |
429 | ||
2e5282ca | 430 | if (env->msr & MSR_UM) { |
f5c7e93a RH |
431 | return MMU_USER_IDX; |
432 | } | |
433 | return MMU_KERNEL_IDX; | |
434 | } | |
435 | ||
77f63e1d RH |
436 | #ifndef CONFIG_USER_ONLY |
437 | extern const VMStateDescription vmstate_mb_cpu; | |
438 | #endif | |
439 | ||
3c7b48b7 | 440 | #endif |