[mirror_qemu.git] / target / microblaze / cpu.h

/*
 *  MicroBlaze virtual CPU header
 *
 *  Copyright (c) 2009 Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef MICROBLAZE_CPU_H
#define MICROBLAZE_CPU_H

#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "qemu/cpu-float.h"

/* MicroBlaze is always in-order. */
#define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL

typedef struct CPUArchState CPUMBState;
#if !defined(CONFIG_USER_ONLY)
#include "mmu.h"
#endif

#define EXCP_MMU        1
#define EXCP_IRQ        2
#define EXCP_SYSCALL    3  /* user-only */
#define EXCP_HW_BREAK   4
#define EXCP_HW_EXCP    5

/* MicroBlaze-specific interrupt pending bits.  */
#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3

/* Meanings of the MBCPU object's two inbound GPIO lines */
#define MB_CPU_IRQ 0
#define MB_CPU_FIR 1

/* Register aliases. R0 - R15 */
#define R_SP     1
#define SR_PC    0
#define SR_MSR   1
#define SR_EAR   3
#define SR_ESR   5
#define SR_FSR   7
#define SR_BTR   0xb
#define SR_EDR   0xd

/* MSR flags.  */
#define MSR_BE  (1<<0) /* 0x001 */
#define MSR_IE  (1<<1) /* 0x002 */
#define MSR_C   (1<<2) /* 0x004 */
#define MSR_BIP (1<<3) /* 0x008 */
#define MSR_FSL (1<<4) /* 0x010 */
#define MSR_ICE (1<<5) /* 0x020 */
#define MSR_DZ  (1<<6) /* 0x040 */
#define MSR_DCE (1<<7) /* 0x080 */
#define MSR_EE  (1<<8) /* 0x100 */
#define MSR_EIP (1<<9) /* 0x200 */
#define MSR_PVR (1<<10) /* 0x400 */
#define MSR_CC  (1<<31)

/* Machine State Register (MSR) Fields */
#define MSR_UM (1<<11) /* User Mode */
#define MSR_UMS        (1<<12) /* User Mode Save */
#define MSR_VM (1<<13) /* Virtual Mode */
#define MSR_VMS        (1<<14) /* Virtual Mode Save */

#define MSR_KERNEL      MSR_EE|MSR_VM
//#define MSR_USER     MSR_KERNEL|MSR_UM|MSR_IE
#define MSR_KERNEL_VMS  MSR_EE|MSR_VMS
//#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE

/* Exception State Register (ESR) Fields */
#define          ESR_DIZ       (1<<11) /* Zone Protection */
#define          ESR_W         (1<<11) /* Unaligned word access */
#define          ESR_S         (1<<10) /* Store instruction */

#define          ESR_ESS_FSL_OFFSET     5

#define          ESR_ESS_MASK  (0x7f << 5)

#define          ESR_EC_FSL             0
#define          ESR_EC_UNALIGNED_DATA  1
#define          ESR_EC_ILLEGAL_OP      2
#define          ESR_EC_INSN_BUS        3
#define          ESR_EC_DATA_BUS        4
#define          ESR_EC_DIVZERO         5
#define          ESR_EC_FPU             6
#define          ESR_EC_PRIVINSN        7
#define          ESR_EC_STACKPROT       7  /* Same as PRIVINSN.  */
#define          ESR_EC_DATA_STORAGE    8
#define          ESR_EC_INSN_STORAGE    9
#define          ESR_EC_DATA_TLB        10
#define          ESR_EC_INSN_TLB        11
#define          ESR_EC_MASK            31

/* Floating Point Status Register (FSR) Bits */
#define FSR_IO          (1<<4) /* Invalid operation */
#define FSR_DZ          (1<<3) /* Divide-by-zero */
#define FSR_OF          (1<<2) /* Overflow */
#define FSR_UF          (1<<1) /* Underflow */
#define FSR_DO          (1<<0) /* Denormalized operand error */

/* Version reg.  */
/* Basic PVR mask */
#define PVR0_PVR_FULL_MASK              0x80000000
#define PVR0_USE_BARREL_MASK            0x40000000
#define PVR0_USE_DIV_MASK               0x20000000
#define PVR0_USE_HW_MUL_MASK            0x10000000
#define PVR0_USE_FPU_MASK               0x08000000
#define PVR0_USE_EXC_MASK               0x04000000
#define PVR0_USE_ICACHE_MASK            0x02000000
#define PVR0_USE_DCACHE_MASK            0x01000000
#define PVR0_USE_MMU_MASK               0x00800000
#define PVR0_USE_BTC			0x00400000
#define PVR0_ENDI_MASK                  0x00200000
#define PVR0_FAULT			0x00100000
#define PVR0_VERSION_MASK               0x0000FF00
#define PVR0_USER1_MASK                 0x000000FF
#define PVR0_SPROT_MASK                 0x00000001

#define PVR0_VERSION_SHIFT              8

/* User 2 PVR mask */
#define PVR1_USER2_MASK                 0xFFFFFFFF

/* Configuration PVR masks */
#define PVR2_D_OPB_MASK                 0x80000000
#define PVR2_D_LMB_MASK                 0x40000000
#define PVR2_I_OPB_MASK                 0x20000000
#define PVR2_I_LMB_MASK                 0x10000000
#define PVR2_INTERRUPT_IS_EDGE_MASK     0x08000000
#define PVR2_EDGE_IS_POSITIVE_MASK      0x04000000
#define PVR2_D_PLB_MASK                 0x02000000      /* new */
#define PVR2_I_PLB_MASK                 0x01000000      /* new */
#define PVR2_INTERCONNECT               0x00800000      /* new */
#define PVR2_USE_EXTEND_FSL             0x00080000      /* new */
#define PVR2_USE_FSL_EXC                0x00040000      /* new */
#define PVR2_USE_MSR_INSTR              0x00020000
#define PVR2_USE_PCMP_INSTR             0x00010000
#define PVR2_AREA_OPTIMISED             0x00008000
#define PVR2_USE_BARREL_MASK            0x00004000
#define PVR2_USE_DIV_MASK               0x00002000
#define PVR2_USE_HW_MUL_MASK            0x00001000
#define PVR2_USE_FPU_MASK               0x00000800
#define PVR2_USE_MUL64_MASK             0x00000400
#define PVR2_USE_FPU2_MASK              0x00000200      /* new */
#define PVR2_USE_IPLBEXC                0x00000100
#define PVR2_USE_DPLBEXC                0x00000080
#define PVR2_OPCODE_0x0_ILL_MASK        0x00000040
#define PVR2_UNALIGNED_EXC_MASK         0x00000020
#define PVR2_ILL_OPCODE_EXC_MASK        0x00000010
#define PVR2_IOPB_BUS_EXC_MASK          0x00000008
#define PVR2_DOPB_BUS_EXC_MASK          0x00000004
#define PVR2_DIV_ZERO_EXC_MASK          0x00000002
#define PVR2_FPU_EXC_MASK               0x00000001

/* Debug and exception PVR masks */
#define PVR3_DEBUG_ENABLED_MASK         0x80000000
#define PVR3_NUMBER_OF_PC_BRK_MASK      0x1E000000
#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
#define PVR3_FSL_LINKS_MASK             0x00000380

/* ICache config PVR masks */
#define PVR4_USE_ICACHE_MASK            0x80000000
#define PVR4_ICACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR4_ICACHE_USE_FSL_MASK        0x02000000
#define PVR4_ICACHE_ALLOW_WR_MASK       0x01000000
#define PVR4_ICACHE_LINE_LEN_MASK       0x00E00000
#define PVR4_ICACHE_BYTE_SIZE_MASK      0x001F0000

/* DCache config PVR masks */
#define PVR5_USE_DCACHE_MASK            0x80000000
#define PVR5_DCACHE_ADDR_TAG_BITS_MASK  0x7C000000
#define PVR5_DCACHE_USE_FSL_MASK        0x02000000
#define PVR5_DCACHE_ALLOW_WR_MASK       0x01000000
#define PVR5_DCACHE_LINE_LEN_MASK       0x00E00000
#define PVR5_DCACHE_BYTE_SIZE_MASK      0x001F0000
#define PVR5_DCACHE_WRITEBACK_MASK      0x00004000

/* ICache base address PVR mask */
#define PVR6_ICACHE_BASEADDR_MASK       0xFFFFFFFF

/* ICache high address PVR mask */
#define PVR7_ICACHE_HIGHADDR_MASK       0xFFFFFFFF

/* DCache base address PVR mask */
#define PVR8_DCACHE_BASEADDR_MASK       0xFFFFFFFF

/* DCache high address PVR mask */
#define PVR9_DCACHE_HIGHADDR_MASK       0xFFFFFFFF

/* Target family PVR mask */
#define PVR10_TARGET_FAMILY_MASK        0xFF000000
#define PVR10_ASIZE_SHIFT               18

/* MMU descrtiption */
#define PVR11_USE_MMU                   0xC0000000
#define PVR11_MMU_ITLB_SIZE             0x38000000
#define PVR11_MMU_DTLB_SIZE             0x07000000
#define PVR11_MMU_TLB_ACCESS            0x00C00000
#define PVR11_MMU_ZONES                 0x003E0000
/* MSR Reset value PVR mask */
#define PVR11_MSR_RESET_VALUE_MASK      0x000007FF

#define C_PVR_NONE                      0
#define C_PVR_BASIC                     1
#define C_PVR_FULL                      2

/* CPU flags.  */

/* Condition codes.  */
#define CC_GE  5
#define CC_GT  4
#define CC_LE  3
#define CC_LT  2
#define CC_NE  1
#define CC_EQ  0

#define STREAM_EXCEPTION (1 << 0)
#define STREAM_ATOMIC    (1 << 1)
#define STREAM_TEST      (1 << 2)
#define STREAM_CONTROL   (1 << 3)
#define STREAM_NONBLOCK  (1 << 4)

#define TARGET_INSN_START_EXTRA_WORDS 1

/* use-non-secure property masks */
#define USE_NON_SECURE_M_AXI_DP_MASK 0x1
#define USE_NON_SECURE_M_AXI_IP_MASK 0x2
#define USE_NON_SECURE_M_AXI_DC_MASK 0x4
#define USE_NON_SECURE_M_AXI_IC_MASK 0x8

struct CPUArchState {
    uint32_t bvalue;   /* TCG temporary, only valid during a TB */
    uint32_t btarget;  /* Full resolved branch destination */

    uint32_t imm;
    uint32_t regs[32];
    uint32_t pc;
    uint32_t msr;    /* All bits of MSR except MSR[C] and MSR[CC] */
    uint32_t msr_c;  /* MSR[C], in low bit; other bits must be 0 */
    target_ulong ear;
    uint32_t esr;
    uint32_t fsr;
    uint32_t btr;
    uint32_t edr;
    float_status fp_status;
    /* Stack protectors. Yes, it's a hw feature.  */
    uint32_t slr, shr;

    /* lwx/swx reserved address */
#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
    target_ulong res_addr;
    uint32_t res_val;

    /* Internal flags.  */
#define IMM_FLAG        (1 << 0)
#define BIMM_FLAG       (1 << 1)
#define ESR_ESS_FLAG    (1 << 2)  /* indicates ESR_ESS_MASK is present */
/* MSR_EE               (1 << 8)  -- these 3 are not in iflags but tb_flags */
/* MSR_UM               (1 << 11) */
/* MSR_VM               (1 << 13) */
/* ESR_ESS_MASK         [11:5]    -- unwind into iflags for unaligned excp */
#define D_FLAG		(1 << 12)  /* Bit in ESR.  */
#define DRTI_FLAG	(1 << 16)
#define DRTE_FLAG	(1 << 17)
#define DRTB_FLAG	(1 << 18)

/* TB dependent CPUMBState.  */
#define IFLAGS_TB_MASK  (D_FLAG | BIMM_FLAG | IMM_FLAG | \
                         DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
#define MSR_TB_MASK     (MSR_UM | MSR_VM | MSR_EE)

    uint32_t iflags;

#if !defined(CONFIG_USER_ONLY)
    /* Unified MMU.  */
    MicroBlazeMMU mmu;
#endif

    /* Fields up to this point are cleared by a CPU reset */
    struct {} end_reset_fields;

    /* These fields are preserved on reset.  */
};

/*
 * Microblaze Configuration Settings
 *
 * Note that the structure is sorted by type and size to minimize holes.
 */
typedef struct {
    char *version;

    uint64_t addr_mask;

    uint32_t base_vectors;
    uint32_t pvr_user2;
    uint32_t pvr_regs[13];

    uint8_t addr_size;
    uint8_t use_fpu;
    uint8_t use_hw_mul;
    uint8_t pvr_user1;
    uint8_t pvr;
    uint8_t mmu;
    uint8_t mmu_tlb_access;
    uint8_t mmu_zones;

    bool stackprot;
    bool use_barrel;
    bool use_div;
    bool use_msr_instr;
    bool use_pcmp_instr;
    bool use_mmu;
    uint8_t use_non_secure;
    bool dcache_writeback;
    bool endi;
    bool dopb_bus_exception;
    bool iopb_bus_exception;
    bool illegal_opcode_exception;
    bool opcode_0_illegal;
    bool div_zero_exception;
    bool unaligned_exceptions;
} MicroBlazeCPUConfig;

/**
 * MicroBlazeCPU:
 * @env: #CPUMBState
 *
 * A MicroBlaze CPU.
 */
struct ArchCPU {
    /*< private >*/
    CPUState parent_obj;

    /*< public >*/
    bool ns_axi_dp;
    bool ns_axi_ip;
    bool ns_axi_dc;
    bool ns_axi_ic;

    CPUNegativeOffsetState neg;
    CPUMBState env;
    MicroBlazeCPUConfig cfg;
};


#ifndef CONFIG_USER_ONLY
void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
                                        MemTxAttrs *attrs);
#endif /* !CONFIG_USER_ONLY */
G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
                                           MMUAccessType access_type,
                                           int mmu_idx, uintptr_t retaddr);
void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg);
int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int reg);

static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
{
    /* Replicate MSR[C] to MSR[CC]. */
    return env->msr | (env->msr_c * (MSR_C | MSR_CC));
}

static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
{
    env->msr_c = (val >> 2) & 1;
    /*
     * Clear both MSR[C] and MSR[CC] from the saved copy.
     * MSR_PVR is not writable and is always clear.
     */
    env->msr = val & ~(MSR_C | MSR_CC | MSR_PVR);
}

void mb_tcg_init(void);

#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU

/* MMU modes definitions */
#define MMU_NOMMU_IDX   0
#define MMU_KERNEL_IDX  1
#define MMU_USER_IDX    2
/* See NB_MMU_MODES in cpu-defs.h. */

#include "exec/cpu-all.h"

/* Ensure there is no overlap between the two masks. */
QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);

static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
                                        uint64_t *cs_base, uint32_t *flags)
{
    *pc = env->pc;
    *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
    *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
}

#if !defined(CONFIG_USER_ONLY)
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                     MMUAccessType access_type, int mmu_idx,
                     bool probe, uintptr_t retaddr);

void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
                               unsigned size, MMUAccessType access_type,
                               int mmu_idx, MemTxAttrs attrs,
                               MemTxResult response, uintptr_t retaddr);
#endif

static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
{
    MicroBlazeCPU *cpu = env_archcpu(env);

    /* Are we in nommu mode?.  */
    if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
        return MMU_NOMMU_IDX;
    }

    if (env->msr & MSR_UM) {
        return MMU_USER_IDX;
    }
    return MMU_KERNEL_IDX;
}

#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_mb_cpu;
#endif

#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze virtual CPU header
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
ee452036	9	* version 2.1 of the License, or (at your option) any later version.
4acb54ba EI	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba	18	*/
07f5a258 MA	19
	20	#ifndef MICROBLAZE_CPU_H
	21	#define MICROBLAZE_CPU_H
4acb54ba	22
ffa3a3c6	23	#include "cpu-qom.h"
74433bf0	24	#include "exec/cpu-defs.h"
69242e7e	25	#include "qemu/cpu-float.h"
4acb54ba	26
f6ff4923 RH	27	/* MicroBlaze is always in-order. */
	28	#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
	29
1ea4a06a	30	typedef struct CPUArchState CPUMBState;
4acb54ba EI	31	#if !defined(CONFIG_USER_ONLY)
	32	#include "mmu.h"
	33	#endif
	34
2161be35 MT	35	#define EXCP_MMU 1
2161be35 MT	36	#define EXCP_IRQ 2
f5235314	37	#define EXCP_SYSCALL 3 /* user-only */
2161be35 MT	38	#define EXCP_HW_BREAK 4
2161be35 MT	39	#define EXCP_HW_EXCP 5
4acb54ba	40
85097db6 RH	41	/* MicroBlaze-specific interrupt pending bits. */
	42	#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
	43
73c69456 AF	44	/* Meanings of the MBCPU object's two inbound GPIO lines */
	45	#define MB_CPU_IRQ 0
	46	#define MB_CPU_FIR 1
	47
4acb54ba EI	48	/* Register aliases. R0 - R15 */
	49	#define R_SP 1
	50	#define SR_PC 0
	51	#define SR_MSR 1
	52	#define SR_EAR 3
	53	#define SR_ESR 5
	54	#define SR_FSR 7
	55	#define SR_BTR 0xb
	56	#define SR_EDR 0xd
	57
	58	/* MSR flags. */
	59	#define MSR_BE (1<<0) /* 0x001 */
	60	#define MSR_IE (1<<1) /* 0x002 */
	61	#define MSR_C (1<<2) /* 0x004 */
	62	#define MSR_BIP (1<<3) /* 0x008 */
	63	#define MSR_FSL (1<<4) /* 0x010 */
	64	#define MSR_ICE (1<<5) /* 0x020 */
	65	#define MSR_DZ (1<<6) /* 0x040 */
	66	#define MSR_DCE (1<<7) /* 0x080 */
	67	#define MSR_EE (1<<8) /* 0x100 */
	68	#define MSR_EIP (1<<9) /* 0x200 */
8a84fc6b	69	#define MSR_PVR (1<<10) /* 0x400 */
4acb54ba EI	70	#define MSR_CC (1<<31)
	71
	72	/* Machine State Register (MSR) Fields */
	73	#define MSR_UM (1<<11) /* User Mode */
	74	#define MSR_UMS (1<<12) /* User Mode Save */
	75	#define MSR_VM (1<<13) /* Virtual Mode */
	76	#define MSR_VMS (1<<14) /* Virtual Mode Save */
	77
	78	#define MSR_KERNEL MSR_EE\|MSR_VM
	79	//#define MSR_USER MSR_KERNEL\|MSR_UM\|MSR_IE
	80	#define MSR_KERNEL_VMS MSR_EE\|MSR_VMS
	81	//#define MSR_USER_VMS MSR_KERNEL_VMS\|MSR_UMS\|MSR_IE
	82
	83	/* Exception State Register (ESR) Fields */
	84	#define ESR_DIZ (1<<11) /* Zone Protection */
ab0c8d0f	85	#define ESR_W (1<<11) /* Unaligned word access */
4acb54ba EI	86	#define ESR_S (1<<10) /* Store instruction */
4acb54ba EI	87
85453641 EI	88	#define ESR_ESS_FSL_OFFSET 5
85453641 EI	89
ab0c8d0f RH	90	#define ESR_ESS_MASK (0x7f << 5)
ab0c8d0f RH	91
cedb936b EI	92	#define ESR_EC_FSL 0
	93	#define ESR_EC_UNALIGNED_DATA 1
	94	#define ESR_EC_ILLEGAL_OP 2
	95	#define ESR_EC_INSN_BUS 3
	96	#define ESR_EC_DATA_BUS 4
	97	#define ESR_EC_DIVZERO 5
	98	#define ESR_EC_FPU 6
	99	#define ESR_EC_PRIVINSN 7
5818dee5	100	#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */
cedb936b EI	101	#define ESR_EC_DATA_STORAGE 8
	102	#define ESR_EC_INSN_STORAGE 9
	103	#define ESR_EC_DATA_TLB 10
	104	#define ESR_EC_INSN_TLB 11
3b584046	105	#define ESR_EC_MASK 31
4acb54ba	106
bdc0bf29 EI	107	/* Floating Point Status Register (FSR) Bits */
	108	#define FSR_IO (1<<4) /* Invalid operation */
	109	#define FSR_DZ (1<<3) /* Divide-by-zero */
	110	#define FSR_OF (1<<2) /* Overflow */
	111	#define FSR_UF (1<<1) /* Underflow */
	112	#define FSR_DO (1<<0) /* Denormalized operand error */
	113
4acb54ba EI	114	/* Version reg. */
	115	/* Basic PVR mask */
	116	#define PVR0_PVR_FULL_MASK 0x80000000
	117	#define PVR0_USE_BARREL_MASK 0x40000000
	118	#define PVR0_USE_DIV_MASK 0x20000000
	119	#define PVR0_USE_HW_MUL_MASK 0x10000000
	120	#define PVR0_USE_FPU_MASK 0x08000000
	121	#define PVR0_USE_EXC_MASK 0x04000000
	122	#define PVR0_USE_ICACHE_MASK 0x02000000
	123	#define PVR0_USE_DCACHE_MASK 0x01000000
71446123	124	#define PVR0_USE_MMU_MASK 0x00800000
c4374bb7	125	#define PVR0_USE_BTC 0x00400000
a88bbb00	126	#define PVR0_ENDI_MASK 0x00200000
c4374bb7	127	#define PVR0_FAULT 0x00100000
4acb54ba EI	128	#define PVR0_VERSION_MASK 0x0000FF00
4acb54ba EI	129	#define PVR0_USER1_MASK 0x000000FF
9aaaa181	130	#define PVR0_SPROT_MASK 0x00000001
4acb54ba	131
79549c99 EI	132	#define PVR0_VERSION_SHIFT 8
79549c99 EI	133
4acb54ba EI	134	/* User 2 PVR mask */
	135	#define PVR1_USER2_MASK 0xFFFFFFFF
	136
	137	/* Configuration PVR masks */
	138	#define PVR2_D_OPB_MASK 0x80000000
	139	#define PVR2_D_LMB_MASK 0x40000000
	140	#define PVR2_I_OPB_MASK 0x20000000
	141	#define PVR2_I_LMB_MASK 0x10000000
	142	#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
	143	#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
	144	#define PVR2_D_PLB_MASK 0x02000000 /* new */
	145	#define PVR2_I_PLB_MASK 0x01000000 /* new */
	146	#define PVR2_INTERCONNECT 0x00800000 /* new */
	147	#define PVR2_USE_EXTEND_FSL 0x00080000 /* new */
	148	#define PVR2_USE_FSL_EXC 0x00040000 /* new */
	149	#define PVR2_USE_MSR_INSTR 0x00020000
	150	#define PVR2_USE_PCMP_INSTR 0x00010000
	151	#define PVR2_AREA_OPTIMISED 0x00008000
	152	#define PVR2_USE_BARREL_MASK 0x00004000
	153	#define PVR2_USE_DIV_MASK 0x00002000
	154	#define PVR2_USE_HW_MUL_MASK 0x00001000
	155	#define PVR2_USE_FPU_MASK 0x00000800
	156	#define PVR2_USE_MUL64_MASK 0x00000400
	157	#define PVR2_USE_FPU2_MASK 0x00000200 /* new */
	158	#define PVR2_USE_IPLBEXC 0x00000100
	159	#define PVR2_USE_DPLBEXC 0x00000080
	160	#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
	161	#define PVR2_UNALIGNED_EXC_MASK 0x00000020
	162	#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
	163	#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
	164	#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
	165	#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
	166	#define PVR2_FPU_EXC_MASK 0x00000001
	167
	168	/* Debug and exception PVR masks */
	169	#define PVR3_DEBUG_ENABLED_MASK 0x80000000
	170	#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
	171	#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
	172	#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
	173	#define PVR3_FSL_LINKS_MASK 0x00000380
	174
	175	/* ICache config PVR masks */
	176	#define PVR4_USE_ICACHE_MASK 0x80000000
	177	#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
	178	#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
	179	#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
	180	#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
	181	#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
	182
	183	/* DCache config PVR masks */
	184	#define PVR5_USE_DCACHE_MASK 0x80000000
	185	#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
	186	#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
	187	#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
	188	#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
	189	#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
c4374bb7	190	#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
4acb54ba EI	191
	192	/* ICache base address PVR mask */
	193	#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
	194
	195	/* ICache high address PVR mask */
	196	#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
	197
	198	/* DCache base address PVR mask */
	199	#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
	200
	201	/* DCache high address PVR mask */
	202	#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
	203
	204	/* Target family PVR mask */
	205	#define PVR10_TARGET_FAMILY_MASK 0xFF000000
d248e1be	206	#define PVR10_ASIZE_SHIFT 18
4acb54ba EI	207
	208	/* MMU descrtiption */
	209	#define PVR11_USE_MMU 0xC0000000
	210	#define PVR11_MMU_ITLB_SIZE 0x38000000
	211	#define PVR11_MMU_DTLB_SIZE 0x07000000
	212	#define PVR11_MMU_TLB_ACCESS 0x00C00000
7458a432	213	#define PVR11_MMU_ZONES 0x003E0000
4acb54ba EI	214	/* MSR Reset value PVR mask */
	215	#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
	216
6fad9e98 AF	217	#define C_PVR_NONE 0
	218	#define C_PVR_BASIC 1
	219	#define C_PVR_FULL 2
4acb54ba EI	220
	221	/* CPU flags. */
	222
	223	/* Condition codes. */
	224	#define CC_GE 5
	225	#define CC_GT 4
	226	#define CC_LE 3
	227	#define CC_LT 2
	228	#define CC_NE 1
	229	#define CC_EQ 0
	230
85453641 EI	231	#define STREAM_EXCEPTION (1 << 0)
	232	#define STREAM_ATOMIC (1 << 1)
	233	#define STREAM_TEST (1 << 2)
	234	#define STREAM_CONTROL (1 << 3)
	235	#define STREAM_NONBLOCK (1 << 4)
	236
683a247e RH	237	#define TARGET_INSN_START_EXTRA_WORDS 1
683a247e RH	238
ea2ccb65 JK	239	/* use-non-secure property masks */
	240	#define USE_NON_SECURE_M_AXI_DP_MASK 0x1
	241	#define USE_NON_SECURE_M_AXI_IP_MASK 0x2
	242	#define USE_NON_SECURE_M_AXI_DC_MASK 0x4
	243	#define USE_NON_SECURE_M_AXI_IC_MASK 0x8
	244
1ea4a06a	245	struct CPUArchState {
b9c58aab RH	246	uint32_t bvalue; /* TCG temporary, only valid during a TB */
b9c58aab RH	247	uint32_t btarget; /* Full resolved branch destination */
4acb54ba EI	248
4acb54ba EI	249	uint32_t imm;
5c594ef3	250	uint32_t regs[32];
0f96e96b	251	uint32_t pc;
1074c0fb RH	252	uint32_t msr; /* All bits of MSR except MSR[C] and MSR[CC] */
1074c0fb RH	253	uint32_t msr_c; /* MSR[C], in low bit; other bits must be 0 */
19f27b6c	254	target_ulong ear;
6efd5599	255	uint32_t esr;
86017ccf	256	uint32_t fsr;
ccf628b7	257	uint32_t btr;
39db007e	258	uint32_t edr;
97694c57	259	float_status fp_status;
5818dee5 EI	260	/* Stack protectors. Yes, it's a hw feature. */
5818dee5 EI	261	uint32_t slr, shr;
4acb54ba	262
8cc9b43f PC	263	/* lwx/swx reserved address */
8cc9b43f PC	264	#define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */
403322ea	265	target_ulong res_addr;
11a76217	266	uint32_t res_val;
8cc9b43f	267
4acb54ba	268	/* Internal flags. */
7b34f45f RH	269	#define IMM_FLAG (1 << 0)
7b34f45f RH	270	#define BIMM_FLAG (1 << 1)
ab0c8d0f RH	271	#define ESR_ESS_FLAG (1 << 2) /* indicates ESR_ESS_MASK is present */
ab0c8d0f RH	272	/* MSR_EE (1 << 8) -- these 3 are not in iflags but tb_flags */
2c32179f RH	273	/* MSR_UM (1 << 11) */
2c32179f RH	274	/* MSR_VM (1 << 13) */
ab0c8d0f	275	/* ESR_ESS_MASK [11:5] -- unwind into iflags for unaligned excp */
64603d1e	276	#define D_FLAG (1 << 12) /* Bit in ESR. */
4acb54ba EI	277	#define DRTI_FLAG (1 << 16)
	278	#define DRTE_FLAG (1 << 17)
	279	#define DRTB_FLAG (1 << 18)
31f163d3	280
68cee38a	281	/* TB dependent CPUMBState. */
88e74b61 RH	282	#define IFLAGS_TB_MASK (D_FLAG \| BIMM_FLAG \| IMM_FLAG \| \
88e74b61 RH	283	DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)
31f163d3 RH	284	#define MSR_TB_MASK (MSR_UM \| MSR_VM \| MSR_EE)
31f163d3 RH	285
4acb54ba EI	286	uint32_t iflags;
4acb54ba EI	287
4acb54ba EI	288	#if !defined(CONFIG_USER_ONLY)
4acb54ba EI	289	/* Unified MMU. */
8ce97bc1	290	MicroBlazeMMU mmu;
4acb54ba EI	291	#endif
4acb54ba EI	292
1f5c00cf AB	293	/* Fields up to this point are cleared by a CPU reset */
	294	struct {} end_reset_fields;
	295
8bac2242	296	/* These fields are preserved on reset. */
ae7d54d4	297	};
4acb54ba	298
84bf3249 RH	299	/*
84bf3249 RH	300	* Microblaze Configuration Settings
a0b2d16a RH	301	*
a0b2d16a RH	302	* Note that the structure is sorted by type and size to minimize holes.
84bf3249 RH	303	*/
84bf3249 RH	304	typedef struct {
a0b2d16a RH	305	char *version;
a0b2d16a RH	306
de73ee1a RH	307	uint64_t addr_mask;
de73ee1a RH	308
84bf3249	309	uint32_t base_vectors;
a0b2d16a	310	uint32_t pvr_user2;
a4bcfc33	311	uint32_t pvr_regs[13];
a0b2d16a	312
84bf3249 RH	313	uint8_t addr_size;
	314	uint8_t use_fpu;
	315	uint8_t use_hw_mul;
a0b2d16a RH	316	uint8_t pvr_user1;
a0b2d16a RH	317	uint8_t pvr;
de73ee1a RH	318	uint8_t mmu;
	319	uint8_t mmu_tlb_access;
	320	uint8_t mmu_zones;
a0b2d16a RH	321
a0b2d16a RH	322	bool stackprot;
84bf3249 RH	323	bool use_barrel;
	324	bool use_div;
	325	bool use_msr_instr;
	326	bool use_pcmp_instr;
	327	bool use_mmu;
ea2ccb65	328	uint8_t use_non_secure;
84bf3249 RH	329	bool dcache_writeback;
	330	bool endi;
	331	bool dopb_bus_exception;
	332	bool iopb_bus_exception;
	333	bool illegal_opcode_exception;
	334	bool opcode_0_illegal;
	335	bool div_zero_exception;
	336	bool unaligned_exceptions;
84bf3249 RH	337	} MicroBlazeCPUConfig;
84bf3249 RH	338
ffa3a3c6 PB	339	/**
	340	* MicroBlazeCPU:
	341	* @env: #CPUMBState
	342	*
	343	* A MicroBlaze CPU.
	344	*/
b36e239e	345	struct ArchCPU {
ffa3a3c6 PB	346	/< private >/
	347	CPUState parent_obj;
	348
	349	/< public >/
ea2ccb65 JK	350	bool ns_axi_dp;
	351	bool ns_axi_ip;
	352	bool ns_axi_dc;
	353	bool ns_axi_ic;
ffa3a3c6	354
5b146dc7 RH	355	CPUNegativeOffsetState neg;
5b146dc7 RH	356	CPUMBState env;
84bf3249	357	MicroBlazeCPUConfig cfg;
ffa3a3c6 PB	358	};
ffa3a3c6 PB	359
ffa3a3c6	360
eb3ef313	361	#ifndef CONFIG_USER_ONLY
ffa3a3c6 PB	362	void mb_cpu_do_interrupt(CPUState *cs);
ffa3a3c6 PB	363	bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
6d2d454a PMD	364	hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
6d2d454a PMD	365	MemTxAttrs *attrs);
eb3ef313	366	#endif /* !CONFIG_USER_ONLY */
8905770b MAL	367	G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
	368	MMUAccessType access_type,
	369	int mmu_idx, uintptr_t retaddr);
90c84c56	370	void mb_cpu_dump_state(CPUState cpu, FILE f, int flags);
a010bdbe	371	int mb_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
ffa3a3c6	372	int mb_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
c3bef3b4 RH	373	int mb_cpu_gdb_read_stack_protect(CPUArchState cpu, GByteArray buf, int reg);
c3bef3b4 RH	374	int mb_cpu_gdb_write_stack_protect(CPUArchState cpu, uint8_t buf, int reg);
b77f98ca	375
1074c0fb RH	376	static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)
	377	{
	378	/* Replicate MSR[C] to MSR[CC]. */
	379	return env->msr \| (env->msr_c * (MSR_C \| MSR_CC));
	380	}
	381
	382	static inline void mb_cpu_write_msr(CPUMBState *env, uint32_t val)
	383	{
	384	env->msr_c = (val >> 2) & 1;
	385	/*
	386	* Clear both MSR[C] and MSR[CC] from the saved copy.
	387	* MSR_PVR is not writable and is always clear.
	388	*/
	389	env->msr = val & ~(MSR_C \| MSR_CC \| MSR_PVR);
	390	}
	391
cd0c24f9	392	void mb_tcg_init(void);
4acb54ba	393
0dacec87	394	#define CPU_RESOLVING_TYPE TYPE_MICROBLAZE_CPU
b33ab1f7	395
4acb54ba	396	/* MMU modes definitions */
4acb54ba EI	397	#define MMU_NOMMU_IDX 0
	398	#define MMU_KERNEL_IDX 1
	399	#define MMU_USER_IDX 2
da876cc2	400	/* See NB_MMU_MODES in cpu-defs.h. */
4acb54ba	401
022c62cb	402	#include "exec/cpu-all.h"
4acb54ba	403
31f163d3 RH	404	/* Ensure there is no overlap between the two masks. */
	405	QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
	406
bb5de525 AJ	407	static inline void cpu_get_tb_cpu_state(CPUMBState env, vaddr pc,
bb5de525 AJ	408	uint64_t cs_base, uint32_t flags)
4acb54ba	409	{
76e8187d	410	*pc = env->pc;
31f163d3	411	*flags = (env->iflags & IFLAGS_TB_MASK) \| (env->msr & MSR_TB_MASK);
d7ecb757	412	cs_base = (flags & IMM_FLAG ? env->imm : 0);
4acb54ba	413	}
faed1c2a	414
3c7b48b7	415	#if !defined(CONFIG_USER_ONLY)
fd297732 RH	416	bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	417	MMUAccessType access_type, int mmu_idx,
	418	bool probe, uintptr_t retaddr);
	419
bdff8123 PM	420	void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
	421	unsigned size, MMUAccessType access_type,
	422	int mmu_idx, MemTxAttrs attrs,
	423	MemTxResult response, uintptr_t retaddr);
4acb54ba	424	#endif
f081c76c	425
f5c7e93a RH	426	static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
	427	{
	428	MicroBlazeCPU *cpu = env_archcpu(env);
	429
	430	/* Are we in nommu mode?. */
2e5282ca	431	if (!(env->msr & MSR_VM) \|\| !cpu->cfg.use_mmu) {
f5c7e93a RH	432	return MMU_NOMMU_IDX;
	433	}
	434
2e5282ca	435	if (env->msr & MSR_UM) {
f5c7e93a RH	436	return MMU_USER_IDX;
	437	}
	438	return MMU_KERNEL_IDX;
	439	}
	440
77f63e1d RH	441	#ifndef CONFIG_USER_ONLY
	442	extern const VMStateDescription vmstate_mb_cpu;
	443	#endif
	444
3c7b48b7	445	#endif