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eabfc239 AF |
1 | /* |
2 | * MicroBlaze gdb server stub | |
3 | * | |
4 | * Copyright (c) 2003-2005 Fabrice Bellard | |
5 | * Copyright (c) 2013 SUSE LINUX Products GmbH | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
ee452036 | 10 | * version 2.1 of the License, or (at your option) any later version. |
eabfc239 AF |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
8fd9dece | 20 | #include "qemu/osdep.h" |
33c11879 | 21 | #include "cpu.h" |
5b50e790 | 22 | #include "exec/gdbstub.h" |
eabfc239 | 23 | |
8a42ddf0 RH |
24 | /* |
25 | * GDB expects SREGs in the following order: | |
26 | * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI. | |
27 | * | |
28 | * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't | |
29 | * map them to anything and return a value of 0 instead. | |
30 | */ | |
31 | ||
32 | enum { | |
33 | GDB_PC = 32 + 0, | |
34 | GDB_MSR = 32 + 1, | |
35 | GDB_EAR = 32 + 2, | |
36 | GDB_ESR = 32 + 3, | |
37 | GDB_FSR = 32 + 4, | |
38 | GDB_BTR = 32 + 5, | |
39 | GDB_PVR0 = 32 + 6, | |
40 | GDB_PVR11 = 32 + 17, | |
41 | GDB_EDR = 32 + 18, | |
42 | GDB_SLR = 32 + 25, | |
43 | GDB_SHR = 32 + 26, | |
44 | }; | |
45 | ||
a010bdbe | 46 | int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) |
eabfc239 | 47 | { |
5b50e790 | 48 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
8a42ddf0 | 49 | CPUClass *cc = CPU_GET_CLASS(cs); |
5b50e790 | 50 | CPUMBState *env = &cpu->env; |
8a42ddf0 | 51 | uint32_t val; |
5b50e790 | 52 | |
8a42ddf0 RH |
53 | if (n > cc->gdb_num_core_regs) { |
54 | return 0; | |
55 | } | |
56 | ||
57 | switch (n) { | |
58 | case 1 ... 31: | |
59 | val = env->regs[n]; | |
60 | break; | |
61 | case GDB_PC: | |
76e8187d | 62 | val = env->pc; |
8a42ddf0 RH |
63 | break; |
64 | case GDB_MSR: | |
1074c0fb | 65 | val = mb_cpu_read_msr(env); |
8a42ddf0 RH |
66 | break; |
67 | case GDB_EAR: | |
b2e80a3c | 68 | val = env->ear; |
8a42ddf0 RH |
69 | break; |
70 | case GDB_ESR: | |
78e9caf2 | 71 | val = env->esr; |
8a42ddf0 RH |
72 | break; |
73 | case GDB_FSR: | |
5a8e0136 | 74 | val = env->fsr; |
8a42ddf0 RH |
75 | break; |
76 | case GDB_BTR: | |
6fbf78f2 | 77 | val = env->btr; |
8a42ddf0 RH |
78 | break; |
79 | case GDB_PVR0 ... GDB_PVR11: | |
a44e82db | 80 | /* PVR12 is intentionally skipped */ |
a4bcfc33 | 81 | val = cpu->cfg.pvr_regs[n - GDB_PVR0]; |
8a42ddf0 RH |
82 | break; |
83 | case GDB_EDR: | |
af20a93a | 84 | val = env->edr; |
8a42ddf0 RH |
85 | break; |
86 | case GDB_SLR: | |
87 | val = env->slr; | |
88 | break; | |
89 | case GDB_SHR: | |
90 | val = env->shr; | |
91 | break; | |
92 | default: | |
201dd7d3 | 93 | /* Other SRegs aren't modeled, so report a value of 0 */ |
8a42ddf0 RH |
94 | val = 0; |
95 | break; | |
eabfc239 | 96 | } |
8a42ddf0 | 97 | return gdb_get_reg32(mem_buf, val); |
eabfc239 AF |
98 | } |
99 | ||
5b50e790 | 100 | int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) |
eabfc239 | 101 | { |
5b50e790 AF |
102 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); |
103 | CPUClass *cc = CPU_GET_CLASS(cs); | |
104 | CPUMBState *env = &cpu->env; | |
eabfc239 AF |
105 | uint32_t tmp; |
106 | ||
107 | if (n > cc->gdb_num_core_regs) { | |
108 | return 0; | |
109 | } | |
110 | ||
111 | tmp = ldl_p(mem_buf); | |
112 | ||
8a42ddf0 RH |
113 | switch (n) { |
114 | case 1 ... 31: | |
eabfc239 | 115 | env->regs[n] = tmp; |
8a42ddf0 RH |
116 | break; |
117 | case GDB_PC: | |
76e8187d | 118 | env->pc = tmp; |
8a42ddf0 RH |
119 | break; |
120 | case GDB_MSR: | |
1074c0fb | 121 | mb_cpu_write_msr(env, tmp); |
8a42ddf0 RH |
122 | break; |
123 | case GDB_EAR: | |
b2e80a3c | 124 | env->ear = tmp; |
8a42ddf0 RH |
125 | break; |
126 | case GDB_ESR: | |
78e9caf2 | 127 | env->esr = tmp; |
8a42ddf0 RH |
128 | break; |
129 | case GDB_FSR: | |
5a8e0136 | 130 | env->fsr = tmp; |
8a42ddf0 RH |
131 | break; |
132 | case GDB_BTR: | |
6fbf78f2 | 133 | env->btr = tmp; |
8a42ddf0 | 134 | break; |
8a42ddf0 | 135 | case GDB_EDR: |
af20a93a | 136 | env->edr = tmp; |
8a42ddf0 RH |
137 | break; |
138 | case GDB_SLR: | |
139 | env->slr = tmp; | |
140 | break; | |
141 | case GDB_SHR: | |
142 | env->shr = tmp; | |
143 | break; | |
eabfc239 AF |
144 | } |
145 | return 4; | |
146 | } |