[mirror_qemu.git] / target / microblaze / helper.c

/*
 *  MicroBlaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "qemu/host-utils.h"
#include "exec/log.h"

#define D(x)

#if defined(CONFIG_USER_ONLY)

void mb_cpu_do_interrupt(CPUState *cs)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;

    cs->exception_index = -1;
    env->res_addr = RES_ADDR_NONE;
    env->regs[14] = env->sregs[SR_PC];
}

int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
                            int mmu_idx)
{
    cs->exception_index = 0xaa;
    cpu_dump_state(cs, stderr, fprintf, 0);
    return 1;
}

#else /* !CONFIG_USER_ONLY */

int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
                            int mmu_idx)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;
    unsigned int hit;
    int r = 1;
    int prot;

    /* Translate if the MMU is available and enabled.  */
    if (mmu_idx != MMU_NOMMU_IDX) {
        uint32_t vaddr, paddr;
        struct microblaze_mmu_lookup lu;

        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
        if (hit) {
            vaddr = address & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;

            qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
                    mmu_idx, vaddr, paddr, lu.prot);
            tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
            r = 0;
        } else {
            env->sregs[SR_EAR] = address;
            qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
                                        mmu_idx, address);

            switch (lu.err) {
                case ERR_PROT:
                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                case ERR_MISS:
                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
                    env->sregs[SR_ESR] |= (rw == 1) << 10;
                    break;
                default:
                    abort();
                    break;
            }

            if (cs->exception_index == EXCP_MMU) {
                cpu_abort(cs, "recursive faults\n");
            }

            /* TLB miss.  */
            cs->exception_index = EXCP_MMU;
        }
    } else {
        /* MMU disabled or not available.  */
        address &= TARGET_PAGE_MASK;
        prot = PAGE_BITS;
        tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
        r = 0;
    }
    return r;
}

void mb_cpu_do_interrupt(CPUState *cs)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;
    uint32_t t;

    /* IMM flag cannot propagate across a branch and into the dslot.  */
    assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
    assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
/*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
    env->res_addr = RES_ADDR_NONE;
    switch (cs->exception_index) {
        case EXCP_HW_EXCP:
            if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
                qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
                return;
            }

            env->regs[17] = env->sregs[SR_PC] + 4;
            env->sregs[SR_ESR] &= ~(1 << 12);

            /* Exception breaks branch + dslot sequence?  */
            if (env->iflags & D_FLAG) {
                env->sregs[SR_ESR] |= 1 << 12 ;
                env->sregs[SR_BTR] = env->btarget;
            }

            /* Disable the MMU.  */
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            /* Exception in progress.  */
            env->sregs[SR_MSR] |= MSR_EIP;

            qemu_log_mask(CPU_LOG_INT,
                          "hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
                          "esr=%" PRIx64 " iflags=%x\n",
                          env->sregs[SR_PC], env->sregs[SR_EAR],
                          env->sregs[SR_ESR], env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            env->iflags &= ~(IMM_FLAG | D_FLAG);
            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
            break;

        case EXCP_MMU:
            env->regs[17] = env->sregs[SR_PC];

            env->sregs[SR_ESR] &= ~(1 << 12);
            /* Exception breaks branch + dslot sequence?  */
            if (env->iflags & D_FLAG) {
                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
                env->sregs[SR_ESR] |= 1 << 12 ;
                env->sregs[SR_BTR] = env->btarget;

                /* Reexecute the branch.  */
                env->regs[17] -= 4;
                /* was the branch immprefixed?.  */
                if (env->bimm) {
                    qemu_log_mask(CPU_LOG_INT,
                                  "bimm exception at pc=%" PRIx64 " "
                                  "iflags=%x\n",
                                  env->sregs[SR_PC], env->iflags);
                    env->regs[17] -= 4;
                    log_cpu_state_mask(CPU_LOG_INT, cs, 0);
                }
            } else if (env->iflags & IMM_FLAG) {
                D(qemu_log("IMM_FLAG set at exception\n"));
                env->regs[17] -= 4;
            }

            /* Disable the MMU.  */
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            /* Exception in progress.  */
            env->sregs[SR_MSR] |= MSR_EIP;

            qemu_log_mask(CPU_LOG_INT,
                          "exception at pc=%" PRIx64 " ear=%" PRIx64 " "
                          "iflags=%x\n",
                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            env->iflags &= ~(IMM_FLAG | D_FLAG);
            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
            break;

        case EXCP_IRQ:
            assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
            assert(env->sregs[SR_MSR] & MSR_IE);
            assert(!(env->iflags & D_FLAG));

            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;

#if 0
#include "disas/disas.h"

/* Useful instrumentation when debugging interrupt issues in either
   the models or in sw.  */
            {
                const char *sym;

                sym = lookup_symbol(env->sregs[SR_PC]);
                if (sym
                    && (!strcmp("netif_rx", sym)
                        || !strcmp("process_backlog", sym))) {

                    qemu_log(
                         "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
                         sym);

                    log_cpu_state(cs, 0);
                }
            }
#endif
            qemu_log_mask(CPU_LOG_INT,
                         "interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "
                         "iflags=%x\n",
                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);

            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
                                    | MSR_UM | MSR_IE);
            env->sregs[SR_MSR] |= t;

            env->regs[14] = env->sregs[SR_PC];
            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
            //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            break;

        case EXCP_BREAK:
        case EXCP_HW_BREAK:
            assert(!(env->iflags & IMM_FLAG));
            assert(!(env->iflags & D_FLAG));
            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
            qemu_log_mask(CPU_LOG_INT,
                        "break at pc=%" PRIx64 " msr=%" PRIx64 " %x "
                        "iflags=%x\n",
                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
            env->sregs[SR_MSR] |= t;
            env->sregs[SR_MSR] |= MSR_BIP;
            if (cs->exception_index == EXCP_HW_BREAK) {
                env->regs[16] = env->sregs[SR_PC];
                env->sregs[SR_MSR] |= MSR_BIP;
                env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
            } else
                env->sregs[SR_PC] = env->btarget;
            break;
        default:
            cpu_abort(cs, "unhandled exception type=%d\n",
                      cs->exception_index);
            break;
    }
}

hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;
    target_ulong vaddr, paddr = 0;
    struct microblaze_mmu_lookup lu;
    int mmu_idx = cpu_mmu_index(env, false);
    unsigned int hit;

    if (mmu_idx != MMU_NOMMU_IDX) {
        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
        if (hit) {
            vaddr = addr & TARGET_PAGE_MASK;
            paddr = lu.paddr + vaddr - lu.vaddr;
        } else
            paddr = 0; /* ???.  */
    } else
        paddr = addr & TARGET_PAGE_MASK;

    return paddr;
}
#endif

bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    CPUMBState *env = &cpu->env;

    if ((interrupt_request & CPU_INTERRUPT_HARD)
        && (env->sregs[SR_MSR] & MSR_IE)
        && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
        && !(env->iflags & (D_FLAG | IMM_FLAG))) {
        cs->exception_index = EXCP_IRQ;
        mb_cpu_do_interrupt(cs);
        return true;
    }
    return false;
}
Commit	Line	Data
4acb54ba EI	1	/*
	2	* MicroBlaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
4acb54ba EI	20
8fd9dece	21	#include "qemu/osdep.h"
4acb54ba	22	#include "cpu.h"
63c91552	23	#include "exec/exec-all.h"
1de7afc9	24	#include "qemu/host-utils.h"
508127e2	25	#include "exec/log.h"
4acb54ba EI	26
4acb54ba EI	27	#define D(x)
4acb54ba EI	28
	29	#if defined(CONFIG_USER_ONLY)
	30
97a8ea5a	31	void mb_cpu_do_interrupt(CPUState *cs)
4acb54ba	32	{
97a8ea5a AF	33	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
	34	CPUMBState *env = &cpu->env;
	35
27103424	36	cs->exception_index = -1;
8cc9b43f	37	env->res_addr = RES_ADDR_NONE;
4acb54ba EI	38	env->regs[14] = env->sregs[SR_PC];
	39	}
	40
98670d47	41	int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
97b348e7	42	int mmu_idx)
4acb54ba	43	{
27103424	44	cs->exception_index = 0xaa;
7510454e	45	cpu_dump_state(cs, stderr, fprintf, 0);
4acb54ba EI	46	return 1;
	47	}
	48
4acb54ba EI	49	#else /* !CONFIG_USER_ONLY */
4acb54ba EI	50
98670d47	51	int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
7510454e	52	int mmu_idx)
4acb54ba	53	{
7510454e AF	54	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
7510454e AF	55	CPUMBState *env = &cpu->env;
4acb54ba	56	unsigned int hit;
4acb54ba EI	57	int r = 1;
	58	int prot;
	59
4acb54ba	60	/* Translate if the MMU is available and enabled. */
d10367e0	61	if (mmu_idx != MMU_NOMMU_IDX) {
cfeea807	62	uint32_t vaddr, paddr;
4acb54ba EI	63	struct microblaze_mmu_lookup lu;
	64
	65	hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
	66	if (hit) {
	67	vaddr = address & TARGET_PAGE_MASK;
	68	paddr = lu.paddr + vaddr - lu.vaddr;
	69
339aaf5b AP	70	qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
339aaf5b AP	71	mmu_idx, vaddr, paddr, lu.prot);
0c591eb0	72	tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8	73	r = 0;
4acb54ba EI	74	} else {
4acb54ba EI	75	env->sregs[SR_EAR] = address;
339aaf5b AP	76	qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
339aaf5b AP	77	mmu_idx, address);
4acb54ba EI	78
	79	switch (lu.err) {
	80	case ERR_PROT:
	81	env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
	82	env->sregs[SR_ESR] \|= (rw == 1) << 10;
	83	break;
	84	case ERR_MISS:
	85	env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
	86	env->sregs[SR_ESR] \|= (rw == 1) << 10;
	87	break;
	88	default:
	89	abort();
	90	break;
	91	}
	92
27103424	93	if (cs->exception_index == EXCP_MMU) {
a47dddd7	94	cpu_abort(cs, "recursive faults\n");
4acb54ba EI	95	}
	96
	97	/* TLB miss. */
27103424	98	cs->exception_index = EXCP_MMU;
4acb54ba EI	99	}
	100	} else {
	101	/* MMU disabled or not available. */
	102	address &= TARGET_PAGE_MASK;
	103	prot = PAGE_BITS;
0c591eb0	104	tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
d4c430a8	105	r = 0;
4acb54ba EI	106	}
	107	return r;
	108	}
	109
97a8ea5a	110	void mb_cpu_do_interrupt(CPUState *cs)
4acb54ba	111	{
97a8ea5a AF	112	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
97a8ea5a AF	113	CPUMBState *env = &cpu->env;
4acb54ba EI	114	uint32_t t;
4acb54ba EI	115
5225d669	116	/* IMM flag cannot propagate across a branch and into the dslot. */
4acb54ba EI	117	assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
	118	assert(!(env->iflags & (DRTI_FLAG \| DRTE_FLAG \| DRTB_FLAG)));
	119	/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
8cc9b43f	120	env->res_addr = RES_ADDR_NONE;
27103424	121	switch (cs->exception_index) {
cedb936b EI	122	case EXCP_HW_EXCP:
cedb936b EI	123	if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
1d512a65	124	qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
cedb936b EI	125	return;
	126	}
	127
	128	env->regs[17] = env->sregs[SR_PC] + 4;
	129	env->sregs[SR_ESR] &= ~(1 << 12);
	130
	131	/* Exception breaks branch + dslot sequence? */
	132	if (env->iflags & D_FLAG) {
	133	env->sregs[SR_ESR] \|= 1 << 12 ;
	134	env->sregs[SR_BTR] = env->btarget;
	135	}
	136
	137	/* Disable the MMU. */
	138	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	139	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	140	env->sregs[SR_MSR] \|= t;
	141	/* Exception in progress. */
	142	env->sregs[SR_MSR] \|= MSR_EIP;
	143
	144	qemu_log_mask(CPU_LOG_INT,
0a22f8cf EI	145	"hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
0a22f8cf EI	146	"esr=%" PRIx64 " iflags=%x\n",
cedb936b EI	147	env->sregs[SR_PC], env->sregs[SR_EAR],
cedb936b EI	148	env->sregs[SR_ESR], env->iflags);
a0762859	149	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
cedb936b	150	env->iflags &= ~(IMM_FLAG \| D_FLAG);
f27183ab	151	env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
cedb936b EI	152	break;
cedb936b EI	153
4acb54ba EI	154	case EXCP_MMU:
	155	env->regs[17] = env->sregs[SR_PC];
	156
a75cf0c5	157	env->sregs[SR_ESR] &= ~(1 << 12);
4acb54ba EI	158	/* Exception breaks branch + dslot sequence? */
	159	if (env->iflags & D_FLAG) {
	160	D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
	161	env->sregs[SR_ESR] \|= 1 << 12 ;
	162	env->sregs[SR_BTR] = env->btarget;
	163
	164	/* Reexecute the branch. */
	165	env->regs[17] -= 4;
	166	/* was the branch immprefixed?. */
	167	if (env->bimm) {
	168	qemu_log_mask(CPU_LOG_INT,
0a22f8cf EI	169	"bimm exception at pc=%" PRIx64 " "
0a22f8cf EI	170	"iflags=%x\n",
4acb54ba EI	171	env->sregs[SR_PC], env->iflags);
4acb54ba EI	172	env->regs[17] -= 4;
a0762859	173	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba EI	174	}
	175	} else if (env->iflags & IMM_FLAG) {
	176	D(qemu_log("IMM_FLAG set at exception\n"));
	177	env->regs[17] -= 4;
	178	}
	179
	180	/* Disable the MMU. */
	181	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	182	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	183	env->sregs[SR_MSR] \|= t;
	184	/* Exception in progress. */
	185	env->sregs[SR_MSR] \|= MSR_EIP;
	186
	187	qemu_log_mask(CPU_LOG_INT,
0a22f8cf EI	188	"exception at pc=%" PRIx64 " ear=%" PRIx64 " "
0a22f8cf EI	189	"iflags=%x\n",
4acb54ba	190	env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
a0762859	191	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba	192	env->iflags &= ~(IMM_FLAG \| D_FLAG);
f27183ab	193	env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
4acb54ba EI	194	break;
	195
	196	case EXCP_IRQ:
	197	assert(!(env->sregs[SR_MSR] & (MSR_EIP \| MSR_BIP)));
	198	assert(env->sregs[SR_MSR] & MSR_IE);
	199	assert(!(env->iflags & D_FLAG));
	200
	201	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	202
	203	#if 0
76cad711	204	#include "disas/disas.h"
4acb54ba EI	205
	206	/* Useful instrumentation when debugging interrupt issues in either
	207	the models or in sw. */
	208	{
	209	const char *sym;
	210
	211	sym = lookup_symbol(env->sregs[SR_PC]);
	212	if (sym
	213	&& (!strcmp("netif_rx", sym)
	214	\|\| !strcmp("process_backlog", sym))) {
	215
	216	qemu_log(
	217	"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
	218	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
	219	sym);
	220
a0762859	221	log_cpu_state(cs, 0);
4acb54ba EI	222	}
	223	}
	224	#endif
	225	qemu_log_mask(CPU_LOG_INT,
0a22f8cf EI	226	"interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "
0a22f8cf EI	227	"iflags=%x\n",
4acb54ba EI	228	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
	229
	230	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \
	231	\| MSR_UM \| MSR_IE);
	232	env->sregs[SR_MSR] \|= t;
	233
	234	env->regs[14] = env->sregs[SR_PC];
f27183ab	235	env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
a0762859	236	//log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba EI	237	break;
	238
	239	case EXCP_BREAK:
	240	case EXCP_HW_BREAK:
	241	assert(!(env->iflags & IMM_FLAG));
	242	assert(!(env->iflags & D_FLAG));
	243	t = (env->sregs[SR_MSR] & (MSR_VM \| MSR_UM)) << 1;
	244	qemu_log_mask(CPU_LOG_INT,
0a22f8cf EI	245	"break at pc=%" PRIx64 " msr=%" PRIx64 " %x "
0a22f8cf EI	246	"iflags=%x\n",
4acb54ba	247	env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
a0762859	248	log_cpu_state_mask(CPU_LOG_INT, cs, 0);
4acb54ba EI	249	env->sregs[SR_MSR] &= ~(MSR_VMS \| MSR_UMS \| MSR_VM \| MSR_UM);
	250	env->sregs[SR_MSR] \|= t;
	251	env->sregs[SR_MSR] \|= MSR_BIP;
27103424	252	if (cs->exception_index == EXCP_HW_BREAK) {
4acb54ba EI	253	env->regs[16] = env->sregs[SR_PC];
4acb54ba EI	254	env->sregs[SR_MSR] \|= MSR_BIP;
f27183ab	255	env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
4acb54ba EI	256	} else
	257	env->sregs[SR_PC] = env->btarget;
	258	break;
	259	default:
a47dddd7	260	cpu_abort(cs, "unhandled exception type=%d\n",
27103424	261	cs->exception_index);
4acb54ba EI	262	break;
	263	}
	264	}
	265
00b941e5	266	hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4acb54ba	267	{
00b941e5 AF	268	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
00b941e5 AF	269	CPUMBState *env = &cpu->env;
4acb54ba EI	270	target_ulong vaddr, paddr = 0;
4acb54ba EI	271	struct microblaze_mmu_lookup lu;
d10367e0	272	int mmu_idx = cpu_mmu_index(env, false);
4acb54ba EI	273	unsigned int hit;
4acb54ba EI	274
d10367e0	275	if (mmu_idx != MMU_NOMMU_IDX) {
4acb54ba EI	276	hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
	277	if (hit) {
	278	vaddr = addr & TARGET_PAGE_MASK;
	279	paddr = lu.paddr + vaddr - lu.vaddr;
	280	} else
	281	paddr = 0; /* ???. */
	282	} else
	283	paddr = addr & TARGET_PAGE_MASK;
	284
	285	return paddr;
	286	}
	287	#endif
29cd33d3 RH	288
	289	bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
	290	{
	291	MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
	292	CPUMBState *env = &cpu->env;
	293
	294	if ((interrupt_request & CPU_INTERRUPT_HARD)
	295	&& (env->sregs[SR_MSR] & MSR_IE)
	296	&& !(env->sregs[SR_MSR] & (MSR_EIP \| MSR_BIP))
	297	&& !(env->iflags & (D_FLAG \| IMM_FLAG))) {
	298	cs->exception_index = EXCP_IRQ;
	299	mb_cpu_do_interrupt(cs);
	300	return true;
	301	}
	302	return false;
	303	}