[mirror_qemu.git] / target / microblaze / mmu.c

/*
 *  Microblaze MMU emulation for qemu.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"

static unsigned int tlb_decode_size(unsigned int f)
{
    static const unsigned int sizes[] = {
        1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
        1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
    };
    assert(f < ARRAY_SIZE(sizes));
    return sizes[f];
}

static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
    CPUState *cs = CPU(mb_env_get_cpu(env));
    struct microblaze_mmu *mmu = &env->mmu;
    unsigned int tlb_size;
    uint32_t tlb_tag, end, t;

    t = mmu->rams[RAM_TAG][idx];
    if (!(t & TLB_VALID))
        return;

    tlb_tag = t & TLB_EPN_MASK;
    tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
    end = tlb_tag + tlb_size;

    while (tlb_tag < end) {
        tlb_flush_page(cs, tlb_tag);
        tlb_tag += TARGET_PAGE_SIZE;
    }
}

static void mmu_change_pid(CPUMBState *env, unsigned int newpid) 
{
    struct microblaze_mmu *mmu = &env->mmu;
    unsigned int i;
    uint32_t t;

    if (newpid & ~0xff)
        qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);

    for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
        /* Lookup and decode.  */
        t = mmu->rams[RAM_TAG][i];
        if (t & TLB_VALID) {
            if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
                mmu_flush_idx(env, i);
        }
    }
}

/* rw - 0 = read, 1 = write, 2 = fetch.  */
unsigned int mmu_translate(struct microblaze_mmu *mmu,
                           struct microblaze_mmu_lookup *lu,
                           target_ulong vaddr, int rw, int mmu_idx)
{
    unsigned int i, hit = 0;
    unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
    uint64_t tlb_tag, tlb_rpn, mask;
    uint32_t tlb_size, t0;

    lu->err = ERR_MISS;
    for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
        uint64_t t, d;

        /* Lookup and decode.  */
        t = mmu->rams[RAM_TAG][i];
        if (t & TLB_VALID) {
            tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
            if (tlb_size < TARGET_PAGE_SIZE) {
                qemu_log_mask(LOG_UNIMP, "%d pages not supported\n", tlb_size);
                abort();
            }

            mask = ~((uint64_t)tlb_size - 1);
            tlb_tag = t & TLB_EPN_MASK;
            if ((vaddr & mask) != (tlb_tag & mask)) {
                continue;
            }
            if (mmu->tids[i]
                && ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
                continue;
            }

            /* Bring in the data part.  */
            d = mmu->rams[RAM_DATA][i];
            tlb_ex = d & TLB_EX;
            tlb_wr = d & TLB_WR;

            /* Now let's see if there is a zone that overrides the protbits.  */
            tlb_zsel = (d >> 4) & 0xf;
            t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
            t0 &= 0x3;

            if (tlb_zsel > mmu->c_mmu_zones) {
                qemu_log_mask(LOG_GUEST_ERROR,
                              "tlb zone select out of range! %d\n", tlb_zsel);
                t0 = 1; /* Ignore.  */
            }

            if (mmu->c_mmu == 1) {
                t0 = 1; /* Zones are disabled.  */
            }

            switch (t0) {
                case 0:
                    if (mmu_idx == MMU_USER_IDX)
                        continue;
                    break;
                case 2:
                    if (mmu_idx != MMU_USER_IDX) {
                        tlb_ex = 1;
                        tlb_wr = 1;
                    }
                    break;
                case 3:
                    tlb_ex = 1;
                    tlb_wr = 1;
                    break;
                default: break;
            }

            lu->err = ERR_PROT;
            lu->prot = PAGE_READ;
            if (tlb_wr)
                lu->prot |= PAGE_WRITE;
            else if (rw == 1)
                goto done;
            if (tlb_ex)
                lu->prot |=PAGE_EXEC;
            else if (rw == 2) {
                goto done;
            }

            tlb_rpn = d & TLB_RPN_MASK;

            lu->vaddr = tlb_tag;
            lu->paddr = tlb_rpn & mmu->c_addr_mask;
            lu->size = tlb_size;
            lu->err = ERR_HIT;
            lu->idx = i;
            hit = 1;
            goto done;
        }
    }
done:
    qemu_log_mask(CPU_LOG_MMU,
                  "MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
                  vaddr, rw, tlb_wr, tlb_ex, hit);
    return hit;
}

/* Writes/reads to the MMU's special regs end up here.  */
uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
{
    unsigned int i;
    uint32_t r = 0;

    if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
        qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
        return 0;
    }
    if (ext && rn != MMU_R_TLBLO) {
        qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n");
        return 0;
    }

    switch (rn) {
        /* Reads to HI/LO trig reads from the mmu rams.  */
        case MMU_R_TLBLO:
        case MMU_R_TLBHI:
            if (!(env->mmu.c_mmu_tlb_access & 1)) {
                qemu_log_mask(LOG_GUEST_ERROR,
                              "Invalid access to MMU reg %d\n", rn);
                return 0;
            }

            i = env->mmu.regs[MMU_R_TLBX] & 0xff;
            r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32);
            if (rn == MMU_R_TLBHI)
                env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
            break;
        case MMU_R_PID:
        case MMU_R_ZPR:
            if (!(env->mmu.c_mmu_tlb_access & 1)) {
                qemu_log_mask(LOG_GUEST_ERROR,
                              "Invalid access to MMU reg %d\n", rn);
                return 0;
            }
            r = env->mmu.regs[rn];
            break;
        case MMU_R_TLBX:
            r = env->mmu.regs[rn];
            break;
        case MMU_R_TLBSX:
            qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");
            break;
        default:
            qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
            break;
    }
    qemu_log_mask(CPU_LOG_MMU, "%s rn=%d=%x\n", __func__, rn, r);
    return r;
}

void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
{
    MicroBlazeCPU *cpu = mb_env_get_cpu(env);
    uint64_t tmp64;
    unsigned int i;
    qemu_log_mask(CPU_LOG_MMU,
                  "%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]);

    if (env->mmu.c_mmu < 2 || !env->mmu.c_mmu_tlb_access) {
        qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
        return;
    }
    if (ext && rn != MMU_R_TLBLO) {
        qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n");
        return;
    }

    switch (rn) {
        /* Writes to HI/LO trig writes to the mmu rams.  */
        case MMU_R_TLBLO:
        case MMU_R_TLBHI:
            i = env->mmu.regs[MMU_R_TLBX] & 0xff;
            if (rn == MMU_R_TLBHI) {
                if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
                    qemu_log_mask(LOG_GUEST_ERROR,
                             "invalidating index %x at pc=%" PRIx64 "\n",
                             i, env->sregs[SR_PC]);
                env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
                mmu_flush_idx(env, i);
            }
            tmp64 = env->mmu.rams[rn & 1][i];
            env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v);
            break;
        case MMU_R_ZPR:
            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log_mask(LOG_GUEST_ERROR,
                              "Invalid access to MMU reg %d\n", rn);
                return;
            }

            /* Changes to the zone protection reg flush the QEMU TLB.
               Fortunately, these are very uncommon.  */
            if (v != env->mmu.regs[rn]) {
                tlb_flush(CPU(cpu));
            }
            env->mmu.regs[rn] = v;
            break;
        case MMU_R_PID:
            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log_mask(LOG_GUEST_ERROR,
                              "Invalid access to MMU reg %d\n", rn);
                return;
            }

            if (v != env->mmu.regs[rn]) {
                mmu_change_pid(env, v);
                env->mmu.regs[rn] = v;
            }
            break;
        case MMU_R_TLBX:
            /* Bit 31 is read-only.  */
            env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);
            break;
        case MMU_R_TLBSX:
        {
            struct microblaze_mmu_lookup lu;
            int hit;

            if (env->mmu.c_mmu_tlb_access <= 1) {
                qemu_log_mask(LOG_GUEST_ERROR,
                              "Invalid access to MMU reg %d\n", rn);
                return;
            }

            hit = mmu_translate(&env->mmu, &lu,
                                v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
            if (hit) {
                env->mmu.regs[MMU_R_TLBX] = lu.idx;
            } else {
                env->mmu.regs[MMU_R_TLBX] |= R_TBLX_MISS_MASK;
            }
            break;
        }
        default:
            qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
            break;
   }
}

void mmu_init(struct microblaze_mmu *mmu)
{
    int i;
    for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
        mmu->regs[i] = 0;
    }
}
Commit	Line	Data
afeeceb0 EI	1	/*
	2	* Microblaze MMU emulation for qemu.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
afeeceb0 EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
afeeceb0	19	*/
afeeceb0	20
8fd9dece	21	#include "qemu/osdep.h"
afeeceb0	22	#include "cpu.h"
63c91552	23	#include "exec/exec-all.h"
afeeceb0	24
afeeceb0 EI	25	static unsigned int tlb_decode_size(unsigned int f)
	26	{
	27	static const unsigned int sizes[] = {
	28	1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024,
	29	1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024
	30	};
	31	assert(f < ARRAY_SIZE(sizes));
	32	return sizes[f];
	33	}
	34
68cee38a	35	static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
afeeceb0	36	{
31b030d4	37	CPUState *cs = CPU(mb_env_get_cpu(env));
afeeceb0 EI	38	struct microblaze_mmu *mmu = &env->mmu;
	39	unsigned int tlb_size;
	40	uint32_t tlb_tag, end, t;
	41
	42	t = mmu->rams[RAM_TAG][idx];
	43	if (!(t & TLB_VALID))
	44	return;
	45
	46	tlb_tag = t & TLB_EPN_MASK;
	47	tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
	48	end = tlb_tag + tlb_size;
	49
	50	while (tlb_tag < end) {
31b030d4	51	tlb_flush_page(cs, tlb_tag);
afeeceb0 EI	52	tlb_tag += TARGET_PAGE_SIZE;
	53	}
	54	}
	55
68cee38a	56	static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
afeeceb0 EI	57	{
	58	struct microblaze_mmu *mmu = &env->mmu;
	59	unsigned int i;
183aa454	60	uint32_t t;
afeeceb0 EI	61
afeeceb0 EI	62	if (newpid & ~0xff)
1d512a65	63	qemu_log_mask(LOG_GUEST_ERROR, "Illegal rpid=%x\n", newpid);
afeeceb0 EI	64
	65	for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
	66	/* Lookup and decode. */
	67	t = mmu->rams[RAM_TAG][i];
	68	if (t & TLB_VALID) {
afeeceb0 EI	69	if (mmu->tids[i] && ((mmu->regs[MMU_R_PID] & 0xff) == mmu->tids[i]))
	70	mmu_flush_idx(env, i);
	71	}
	72	}
	73	}
	74
	75	/* rw - 0 = read, 1 = write, 2 = fetch. */
	76	unsigned int mmu_translate(struct microblaze_mmu *mmu,
	77	struct microblaze_mmu_lookup *lu,
	78	target_ulong vaddr, int rw, int mmu_idx)
	79	{
	80	unsigned int i, hit = 0;
	81	unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;
d2f004c3 EI	82	uint64_t tlb_tag, tlb_rpn, mask;
d2f004c3 EI	83	uint32_t tlb_size, t0;
afeeceb0 EI	84
	85	lu->err = ERR_MISS;
	86	for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {
d2f004c3	87	uint64_t t, d;
afeeceb0 EI	88
	89	/* Lookup and decode. */
	90	t = mmu->rams[RAM_TAG][i];
afeeceb0 EI	91	if (t & TLB_VALID) {
	92	tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);
	93	if (tlb_size < TARGET_PAGE_SIZE) {
75c9ddce	94	qemu_log_mask(LOG_UNIMP, "%d pages not supported\n", tlb_size);
afeeceb0 EI	95	abort();
	96	}
	97
d2f004c3	98	mask = ~((uint64_t)tlb_size - 1);
afeeceb0 EI	99	tlb_tag = t & TLB_EPN_MASK;
afeeceb0 EI	100	if ((vaddr & mask) != (tlb_tag & mask)) {
afeeceb0 EI	101	continue;
	102	}
	103	if (mmu->tids[i]
	104	&& ((mmu->regs[MMU_R_PID] & 0xff) != mmu->tids[i])) {
afeeceb0 EI	105	continue;
	106	}
	107
	108	/* Bring in the data part. */
	109	d = mmu->rams[RAM_DATA][i];
	110	tlb_ex = d & TLB_EX;
	111	tlb_wr = d & TLB_WR;
	112
e03ba136	113	/* Now let's see if there is a zone that overrides the protbits. */
afeeceb0 EI	114	tlb_zsel = (d >> 4) & 0xf;
	115	t0 = mmu->regs[MMU_R_ZPR] >> (30 - (tlb_zsel * 2));
	116	t0 &= 0x3;
3c50a71f EI	117
3c50a71f EI	118	if (tlb_zsel > mmu->c_mmu_zones) {
75c9ddce EI	119	qemu_log_mask(LOG_GUEST_ERROR,
75c9ddce EI	120	"tlb zone select out of range! %d\n", tlb_zsel);
3c50a71f EI	121	t0 = 1; /* Ignore. */
	122	}
	123
	124	if (mmu->c_mmu == 1) {
	125	t0 = 1; /* Zones are disabled. */
	126	}
	127
afeeceb0 EI	128	switch (t0) {
	129	case 0:
	130	if (mmu_idx == MMU_USER_IDX)
	131	continue;
	132	break;
	133	case 2:
	134	if (mmu_idx != MMU_USER_IDX) {
	135	tlb_ex = 1;
	136	tlb_wr = 1;
	137	}
	138	break;
	139	case 3:
	140	tlb_ex = 1;
	141	tlb_wr = 1;
	142	break;
3c50a71f	143	default: break;
afeeceb0 EI	144	}
afeeceb0 EI	145
afeeceb0 EI	146	lu->err = ERR_PROT;
	147	lu->prot = PAGE_READ;
	148	if (tlb_wr)
	149	lu->prot \|= PAGE_WRITE;
	150	else if (rw == 1)
	151	goto done;
	152	if (tlb_ex)
	153	lu->prot \|=PAGE_EXEC;
	154	else if (rw == 2) {
	155	goto done;
	156	}
	157
	158	tlb_rpn = d & TLB_RPN_MASK;
	159
	160	lu->vaddr = tlb_tag;
3924a9aa	161	lu->paddr = tlb_rpn & mmu->c_addr_mask;
afeeceb0 EI	162	lu->size = tlb_size;
	163	lu->err = ERR_HIT;
	164	lu->idx = i;
	165	hit = 1;
	166	goto done;
	167	}
	168	}
	169	done:
75c9ddce EI	170	qemu_log_mask(CPU_LOG_MMU,
	171	"MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",
	172	vaddr, rw, tlb_wr, tlb_ex, hit);
afeeceb0 EI	173	return hit;
	174	}
	175
	176	/* Writes/reads to the MMU's special regs end up here. */
f0f7e7f7	177	uint32_t mmu_read(CPUMBState *env, bool ext, uint32_t rn)
afeeceb0 EI	178	{
afeeceb0 EI	179	unsigned int i;
bd9e6608	180	uint32_t r = 0;
afeeceb0	181
3c50a71f	182	if (env->mmu.c_mmu < 2 \|\| !env->mmu.c_mmu_tlb_access) {
1d512a65	183	qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
3c50a71f EI	184	return 0;
3c50a71f EI	185	}
f0f7e7f7 EI	186	if (ext && rn != MMU_R_TLBLO) {
	187	qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n");
	188	return 0;
	189	}
3c50a71f	190
afeeceb0 EI	191	switch (rn) {
	192	/* Reads to HI/LO trig reads from the mmu rams. */
	193	case MMU_R_TLBLO:
	194	case MMU_R_TLBHI:
3c50a71f	195	if (!(env->mmu.c_mmu_tlb_access & 1)) {
75c9ddce EI	196	qemu_log_mask(LOG_GUEST_ERROR,
75c9ddce EI	197	"Invalid access to MMU reg %d\n", rn);
3c50a71f EI	198	return 0;
	199	}
	200
afeeceb0	201	i = env->mmu.regs[MMU_R_TLBX] & 0xff;
f0f7e7f7	202	r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32);
afeeceb0 EI	203	if (rn == MMU_R_TLBHI)
	204	env->mmu.regs[MMU_R_PID] = env->mmu.tids[i];
	205	break;
3c50a71f EI	206	case MMU_R_PID:
	207	case MMU_R_ZPR:
	208	if (!(env->mmu.c_mmu_tlb_access & 1)) {
75c9ddce EI	209	qemu_log_mask(LOG_GUEST_ERROR,
75c9ddce EI	210	"Invalid access to MMU reg %d\n", rn);
3c50a71f EI	211	return 0;
	212	}
	213	r = env->mmu.regs[rn];
	214	break;
96716533 EI	215	case MMU_R_TLBX:
	216	r = env->mmu.regs[rn];
	217	break;
bd9e6608 EI	218	case MMU_R_TLBSX:
	219	qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");
	220	break;
afeeceb0	221	default:
96716533	222	qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
afeeceb0 EI	223	break;
afeeceb0 EI	224	}
75c9ddce	225	qemu_log_mask(CPU_LOG_MMU, "%s rn=%d=%x\n", __func__, rn, r);
afeeceb0 EI	226	return r;
	227	}
	228
f0f7e7f7	229	void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
afeeceb0	230	{
00c8cb0a	231	MicroBlazeCPU *cpu = mb_env_get_cpu(env);
f0f7e7f7	232	uint64_t tmp64;
afeeceb0	233	unsigned int i;
75c9ddce EI	234	qemu_log_mask(CPU_LOG_MMU,
75c9ddce EI	235	"%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]);
afeeceb0	236
3c50a71f	237	if (env->mmu.c_mmu < 2 \|\| !env->mmu.c_mmu_tlb_access) {
1d512a65	238	qemu_log_mask(LOG_GUEST_ERROR, "MMU access on MMU-less system\n");
3c50a71f EI	239	return;
3c50a71f EI	240	}
f0f7e7f7 EI	241	if (ext && rn != MMU_R_TLBLO) {
	242	qemu_log_mask(LOG_GUEST_ERROR, "Extended access only to TLBLO.\n");
	243	return;
	244	}
3c50a71f	245
afeeceb0 EI	246	switch (rn) {
	247	/* Writes to HI/LO trig writes to the mmu rams. */
	248	case MMU_R_TLBLO:
	249	case MMU_R_TLBHI:
	250	i = env->mmu.regs[MMU_R_TLBX] & 0xff;
	251	if (rn == MMU_R_TLBHI) {
	252	if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
0a22f8cf EI	253	qemu_log_mask(LOG_GUEST_ERROR,
0a22f8cf EI	254	"invalidating index %x at pc=%" PRIx64 "\n",
afeeceb0 EI	255	i, env->sregs[SR_PC]);
	256	env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
	257	mmu_flush_idx(env, i);
	258	}
f0f7e7f7 EI	259	tmp64 = env->mmu.rams[rn & 1][i];
f0f7e7f7 EI	260	env->mmu.rams[rn & 1][i] = deposit64(tmp64, ext * 32, 32, v);
afeeceb0 EI	261	break;
afeeceb0 EI	262	case MMU_R_ZPR:
3c50a71f	263	if (env->mmu.c_mmu_tlb_access <= 1) {
75c9ddce EI	264	qemu_log_mask(LOG_GUEST_ERROR,
75c9ddce EI	265	"Invalid access to MMU reg %d\n", rn);
3c50a71f EI	266	return;
	267	}
	268
d0f3654f EI	269	/* Changes to the zone protection reg flush the QEMU TLB.
	270	Fortunately, these are very uncommon. */
	271	if (v != env->mmu.regs[rn]) {
d10eb08f	272	tlb_flush(CPU(cpu));
d0f3654f EI	273	}
	274	env->mmu.regs[rn] = v;
	275	break;
afeeceb0	276	case MMU_R_PID:
3c50a71f	277	if (env->mmu.c_mmu_tlb_access <= 1) {
75c9ddce EI	278	qemu_log_mask(LOG_GUEST_ERROR,
75c9ddce EI	279	"Invalid access to MMU reg %d\n", rn);
3c50a71f EI	280	return;
	281	}
	282
afeeceb0 EI	283	if (v != env->mmu.regs[rn]) {
	284	mmu_change_pid(env, v);
	285	env->mmu.regs[rn] = v;
	286	}
	287	break;
fce6a8ec EI	288	case MMU_R_TLBX:
	289	/* Bit 31 is read-only. */
	290	env->mmu.regs[rn] = deposit32(env->mmu.regs[rn], 0, 31, v);
	291	break;
afeeceb0 EI	292	case MMU_R_TLBSX:
	293	{
	294	struct microblaze_mmu_lookup lu;
	295	int hit;
3c50a71f EI	296
3c50a71f EI	297	if (env->mmu.c_mmu_tlb_access <= 1) {
75c9ddce EI	298	qemu_log_mask(LOG_GUEST_ERROR,
75c9ddce EI	299	"Invalid access to MMU reg %d\n", rn);
3c50a71f EI	300	return;
	301	}
	302
afeeceb0	303	hit = mmu_translate(&env->mmu, &lu,
97ed5ccd	304	v & TLB_EPN_MASK, 0, cpu_mmu_index(env, false));
afeeceb0 EI	305	if (hit) {
afeeceb0 EI	306	env->mmu.regs[MMU_R_TLBX] = lu.idx;
a2207b59 EI	307	} else {
	308	env->mmu.regs[MMU_R_TLBX] \|= R_TBLX_MISS_MASK;
	309	}
afeeceb0 EI	310	break;
	311	}
	312	default:
96716533	313	qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);
afeeceb0 EI	314	break;
	315	}
	316	}
	317
	318	void mmu_init(struct microblaze_mmu *mmu)
	319	{
3c50a71f EI	320	int i;
	321	for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
	322	mmu->regs[i] = 0;
	323	}
afeeceb0	324	}