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0f71a709 AF |
1 | /* |
2 | * QEMU MIPS CPU | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
c684822a | 21 | #include "qemu/osdep.h" |
da34e65c | 22 | #include "qapi/error.h" |
0f71a709 | 23 | #include "cpu.h" |
26aa3d9a | 24 | #include "internal.h" |
14c03ab9 | 25 | #include "kvm_mips.h" |
0f71a709 | 26 | #include "qemu-common.h" |
14c03ab9 | 27 | #include "sysemu/kvm.h" |
63c91552 | 28 | #include "exec/exec-all.h" |
0f71a709 AF |
29 | |
30 | ||
f45748f1 AF |
31 | static void mips_cpu_set_pc(CPUState *cs, vaddr value) |
32 | { | |
33 | MIPSCPU *cpu = MIPS_CPU(cs); | |
34 | CPUMIPSState *env = &cpu->env; | |
35 | ||
36 | env->active_tc.PC = value & ~(target_ulong)1; | |
37 | if (value & 1) { | |
38 | env->hflags |= MIPS_HFLAG_M16; | |
39 | } else { | |
40 | env->hflags &= ~(MIPS_HFLAG_M16); | |
41 | } | |
42 | } | |
43 | ||
bdf7ae5b AF |
44 | static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
45 | { | |
46 | MIPSCPU *cpu = MIPS_CPU(cs); | |
47 | CPUMIPSState *env = &cpu->env; | |
48 | ||
49 | env->active_tc.PC = tb->pc; | |
50 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
51 | env->hflags |= tb->flags & MIPS_HFLAG_BMASK; | |
52 | } | |
53 | ||
8c2e1b00 AF |
54 | static bool mips_cpu_has_work(CPUState *cs) |
55 | { | |
56 | MIPSCPU *cpu = MIPS_CPU(cs); | |
57 | CPUMIPSState *env = &cpu->env; | |
58 | bool has_work = false; | |
59 | ||
7540a43a LA |
60 | /* Prior to MIPS Release 6 it is implementation dependent if non-enabled |
61 | interrupts wake-up the CPU, however most of the implementations only | |
8c2e1b00 AF |
62 | check for interrupts that can be taken. */ |
63 | if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && | |
64 | cpu_mips_hw_interrupts_pending(env)) { | |
7540a43a LA |
65 | if (cpu_mips_hw_interrupts_enabled(env) || |
66 | (env->insn_flags & ISA_MIPS32R6)) { | |
71ca034a LA |
67 | has_work = true; |
68 | } | |
8c2e1b00 AF |
69 | } |
70 | ||
71 | /* MIPS-MT has the ability to halt the CPU. */ | |
72 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { | |
73 | /* The QEMU model will issue an _WAKE request whenever the CPUs | |
74 | should be woken up. */ | |
75 | if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { | |
76 | has_work = true; | |
77 | } | |
78 | ||
79 | if (!mips_vpe_active(env)) { | |
80 | has_work = false; | |
81 | } | |
82 | } | |
01bc435b YK |
83 | /* MIPS Release 6 has the ability to halt the CPU. */ |
84 | if (env->CP0_Config5 & (1 << CP0C5_VP)) { | |
85 | if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { | |
86 | has_work = true; | |
87 | } | |
88 | if (!mips_vp_active(env)) { | |
89 | has_work = false; | |
90 | } | |
91 | } | |
8c2e1b00 AF |
92 | return has_work; |
93 | } | |
94 | ||
0f71a709 AF |
95 | /* CPUClass::reset() */ |
96 | static void mips_cpu_reset(CPUState *s) | |
97 | { | |
98 | MIPSCPU *cpu = MIPS_CPU(s); | |
99 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); | |
100 | CPUMIPSState *env = &cpu->env; | |
101 | ||
102 | mcc->parent_reset(s); | |
103 | ||
1f5c00cf | 104 | memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); |
55e5c285 | 105 | |
0f71a709 | 106 | cpu_state_reset(env); |
14c03ab9 JH |
107 | |
108 | #ifndef CONFIG_USER_ONLY | |
109 | if (kvm_enabled()) { | |
110 | kvm_mips_reset_vcpu(cpu); | |
111 | } | |
112 | #endif | |
0f71a709 AF |
113 | } |
114 | ||
63a946c7 | 115 | static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) { |
89a955e8 AM |
116 | MIPSCPU *cpu = MIPS_CPU(s); |
117 | CPUMIPSState *env = &cpu->env; | |
118 | ||
119 | if (!(env->insn_flags & ISA_NANOMIPS32)) { | |
63a946c7 | 120 | #ifdef TARGET_WORDS_BIGENDIAN |
89a955e8 | 121 | info->print_insn = print_insn_big_mips; |
63a946c7 | 122 | #else |
89a955e8 | 123 | info->print_insn = print_insn_little_mips; |
63a946c7 | 124 | #endif |
89a955e8 AM |
125 | } else { |
126 | #if defined(CONFIG_NANOMIPS_DIS) | |
127 | info->print_insn = print_insn_nanomips; | |
128 | #endif | |
129 | } | |
63a946c7 PC |
130 | } |
131 | ||
c1caf1d9 AF |
132 | static void mips_cpu_realizefn(DeviceState *dev, Error **errp) |
133 | { | |
14a10fc3 | 134 | CPUState *cs = CPU(dev); |
df4dc102 | 135 | MIPSCPU *cpu = MIPS_CPU(dev); |
c1caf1d9 | 136 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
137 | Error *local_err = NULL; |
138 | ||
139 | cpu_exec_realizefn(cs, &local_err); | |
140 | if (local_err != NULL) { | |
141 | error_propagate(errp, local_err); | |
142 | return; | |
143 | } | |
c1caf1d9 | 144 | |
df4dc102 PMD |
145 | cpu_mips_realize_env(&cpu->env); |
146 | ||
14a10fc3 AF |
147 | cpu_reset(cs); |
148 | qemu_init_vcpu(cs); | |
c1caf1d9 AF |
149 | |
150 | mcc->parent_realize(dev, errp); | |
151 | } | |
152 | ||
5b0c40f7 AF |
153 | static void mips_cpu_initfn(Object *obj) |
154 | { | |
155 | MIPSCPU *cpu = MIPS_CPU(obj); | |
156 | CPUMIPSState *env = &cpu->env; | |
41da212c | 157 | MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); |
5b0c40f7 | 158 | |
7506ed90 | 159 | cpu_set_cpustate_pointers(cpu); |
41da212c | 160 | env->cpu_model = mcc->cpu_def; |
5b0c40f7 AF |
161 | } |
162 | ||
41da212c IM |
163 | static char *mips_cpu_type_name(const char *cpu_model) |
164 | { | |
a7519f2b | 165 | return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); |
41da212c IM |
166 | } |
167 | ||
168 | static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) | |
169 | { | |
170 | ObjectClass *oc; | |
171 | char *typename; | |
172 | ||
41da212c IM |
173 | typename = mips_cpu_type_name(cpu_model); |
174 | oc = object_class_by_name(typename); | |
175 | g_free(typename); | |
176 | return oc; | |
177 | } | |
178 | ||
0f71a709 AF |
179 | static void mips_cpu_class_init(ObjectClass *c, void *data) |
180 | { | |
181 | MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); | |
182 | CPUClass *cc = CPU_CLASS(c); | |
c1caf1d9 AF |
183 | DeviceClass *dc = DEVICE_CLASS(c); |
184 | ||
bf853881 PMD |
185 | device_class_set_parent_realize(dc, mips_cpu_realizefn, |
186 | &mcc->parent_realize); | |
0f71a709 AF |
187 | mcc->parent_reset = cc->reset; |
188 | cc->reset = mips_cpu_reset; | |
97a8ea5a | 189 | |
41da212c | 190 | cc->class_by_name = mips_cpu_class_by_name; |
8c2e1b00 | 191 | cc->has_work = mips_cpu_has_work; |
97a8ea5a | 192 | cc->do_interrupt = mips_cpu_do_interrupt; |
fa4faba4 | 193 | cc->cpu_exec_interrupt = mips_cpu_exec_interrupt; |
878096ee | 194 | cc->dump_state = mips_cpu_dump_state; |
f45748f1 | 195 | cc->set_pc = mips_cpu_set_pc; |
bdf7ae5b | 196 | cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; |
5b50e790 AF |
197 | cc->gdb_read_register = mips_cpu_gdb_read_register; |
198 | cc->gdb_write_register = mips_cpu_gdb_write_register; | |
931d019f | 199 | #ifndef CONFIG_USER_ONLY |
00b941e5 | 200 | cc->do_unassigned_access = mips_cpu_unassigned_access; |
93e22326 | 201 | cc->do_unaligned_access = mips_cpu_do_unaligned_access; |
00b941e5 | 202 | cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; |
04cd7962 | 203 | cc->vmsd = &vmstate_mips_cpu; |
00b941e5 | 204 | #endif |
63a946c7 | 205 | cc->disas_set_info = mips_cpu_disas_set_info; |
74d7fc7f | 206 | #ifdef CONFIG_TCG |
55c3ceef | 207 | cc->tcg_initialize = mips_tcg_init; |
931d019f | 208 | cc->tlb_fill = mips_cpu_tlb_fill; |
74d7fc7f | 209 | #endif |
a0e372f0 AF |
210 | |
211 | cc->gdb_num_core_regs = 73; | |
2472b6c0 | 212 | cc->gdb_stop_before_watchpoint = true; |
0f71a709 AF |
213 | } |
214 | ||
215 | static const TypeInfo mips_cpu_type_info = { | |
216 | .name = TYPE_MIPS_CPU, | |
217 | .parent = TYPE_CPU, | |
218 | .instance_size = sizeof(MIPSCPU), | |
5b0c40f7 | 219 | .instance_init = mips_cpu_initfn, |
41da212c | 220 | .abstract = true, |
0f71a709 AF |
221 | .class_size = sizeof(MIPSCPUClass), |
222 | .class_init = mips_cpu_class_init, | |
223 | }; | |
224 | ||
41da212c IM |
225 | static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) |
226 | { | |
227 | MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); | |
228 | mcc->cpu_def = data; | |
229 | } | |
230 | ||
231 | static void mips_register_cpudef_type(const struct mips_def_t *def) | |
232 | { | |
233 | char *typename = mips_cpu_type_name(def->name); | |
234 | TypeInfo ti = { | |
235 | .name = typename, | |
236 | .parent = TYPE_MIPS_CPU, | |
237 | .class_init = mips_cpu_cpudef_class_init, | |
238 | .class_data = (void *)def, | |
239 | }; | |
240 | ||
241 | type_register(&ti); | |
242 | g_free(typename); | |
243 | } | |
244 | ||
0f71a709 AF |
245 | static void mips_cpu_register_types(void) |
246 | { | |
41da212c IM |
247 | int i; |
248 | ||
0f71a709 | 249 | type_register_static(&mips_cpu_type_info); |
41da212c IM |
250 | for (i = 0; i < mips_defs_number; i++) { |
251 | mips_register_cpudef_type(&mips_defs[i]); | |
252 | } | |
0f71a709 AF |
253 | } |
254 | ||
255 | type_init(mips_cpu_register_types) |