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07f5a258 MA |
1 | #ifndef MIPS_CPU_H |
2 | #define MIPS_CPU_H | |
6af0bf9c | 3 | |
d94f0a8e | 4 | #define ALIGNED_ONLY |
4ad40f36 | 5 | |
9349b4f9 | 6 | #define CPUArchState struct CPUMIPSState |
c2764719 | 7 | |
9a78eead | 8 | #include "qemu-common.h" |
416bf936 | 9 | #include "cpu-qom.h" |
6af0bf9c | 10 | #include "mips-defs.h" |
022c62cb | 11 | #include "exec/cpu-defs.h" |
6b4c305c | 12 | #include "fpu/softfloat.h" |
6af0bf9c | 13 | |
ead9360e | 14 | struct CPUMIPSState; |
6af0bf9c | 15 | |
ead9360e | 16 | typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; |
51b2772f | 17 | |
e97a391d YK |
18 | /* MSA Context */ |
19 | #define MSA_WRLEN (128) | |
20 | ||
e97a391d YK |
21 | typedef union wr_t wr_t; |
22 | union wr_t { | |
23 | int8_t b[MSA_WRLEN/8]; | |
24 | int16_t h[MSA_WRLEN/16]; | |
25 | int32_t w[MSA_WRLEN/32]; | |
26 | int64_t d[MSA_WRLEN/64]; | |
27 | }; | |
28 | ||
c227f099 AL |
29 | typedef union fpr_t fpr_t; |
30 | union fpr_t { | |
ead9360e TS |
31 | float64 fd; /* ieee double precision */ |
32 | float32 fs[2];/* ieee single precision */ | |
33 | uint64_t d; /* binary double fixed-point */ | |
34 | uint32_t w[2]; /* binary single fixed-point */ | |
e97a391d YK |
35 | /* FPU/MSA register mapping is not tested on big-endian hosts. */ |
36 | wr_t wr; /* vector data */ | |
ead9360e TS |
37 | }; |
38 | /* define FP_ENDIAN_IDX to access the same location | |
4ff9786c | 39 | * in the fpr_t union regardless of the host endianness |
ead9360e | 40 | */ |
e2542fe2 | 41 | #if defined(HOST_WORDS_BIGENDIAN) |
ead9360e TS |
42 | # define FP_ENDIAN_IDX 1 |
43 | #else | |
44 | # define FP_ENDIAN_IDX 0 | |
c570fd16 | 45 | #endif |
ead9360e TS |
46 | |
47 | typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; | |
48 | struct CPUMIPSFPUContext { | |
6af0bf9c | 49 | /* Floating point registers */ |
c227f099 | 50 | fpr_t fpr[32]; |
6ea83fed | 51 | float_status fp_status; |
5a5012ec | 52 | /* fpu implementation/revision register (fir) */ |
6af0bf9c | 53 | uint32_t fcr0; |
7c979afd | 54 | #define FCR0_FREP 29 |
b4dd99a3 | 55 | #define FCR0_UFRP 28 |
ba5c79f2 | 56 | #define FCR0_HAS2008 23 |
5a5012ec TS |
57 | #define FCR0_F64 22 |
58 | #define FCR0_L 21 | |
59 | #define FCR0_W 20 | |
60 | #define FCR0_3D 19 | |
61 | #define FCR0_PS 18 | |
62 | #define FCR0_D 17 | |
63 | #define FCR0_S 16 | |
64 | #define FCR0_PRID 8 | |
65 | #define FCR0_REV 0 | |
6ea83fed | 66 | /* fcsr */ |
599bc5e8 | 67 | uint32_t fcr31_rw_bitmask; |
6ea83fed | 68 | uint32_t fcr31; |
77be4199 | 69 | #define FCR31_FS 24 |
ba5c79f2 LA |
70 | #define FCR31_ABS2008 19 |
71 | #define FCR31_NAN2008 18 | |
f01be154 TS |
72 | #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) |
73 | #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0) | |
74 | #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1)) | |
5a5012ec TS |
75 | #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) |
76 | #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) | |
77 | #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) | |
78 | #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0) | |
79 | #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0) | |
80 | #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0) | |
81 | #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0) | |
6ea83fed FB |
82 | #define FP_INEXACT 1 |
83 | #define FP_UNDERFLOW 2 | |
84 | #define FP_OVERFLOW 4 | |
85 | #define FP_DIV0 8 | |
86 | #define FP_INVALID 16 | |
87 | #define FP_UNIMPLEMENTED 32 | |
ead9360e TS |
88 | }; |
89 | ||
42c86612 | 90 | #define NB_MMU_MODES 4 |
c20d594e | 91 | #define TARGET_INSN_START_EXTRA_WORDS 2 |
6ebbf390 | 92 | |
ead9360e TS |
93 | typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; |
94 | struct CPUMIPSMVPContext { | |
95 | int32_t CP0_MVPControl; | |
96 | #define CP0MVPCo_CPA 3 | |
97 | #define CP0MVPCo_STLB 2 | |
98 | #define CP0MVPCo_VPC 1 | |
99 | #define CP0MVPCo_EVP 0 | |
100 | int32_t CP0_MVPConf0; | |
101 | #define CP0MVPC0_M 31 | |
102 | #define CP0MVPC0_TLBS 29 | |
103 | #define CP0MVPC0_GS 28 | |
104 | #define CP0MVPC0_PCP 27 | |
105 | #define CP0MVPC0_PTLBE 16 | |
106 | #define CP0MVPC0_TCA 15 | |
107 | #define CP0MVPC0_PVPE 10 | |
108 | #define CP0MVPC0_PTC 0 | |
109 | int32_t CP0_MVPConf1; | |
110 | #define CP0MVPC1_CIM 31 | |
111 | #define CP0MVPC1_CIF 30 | |
112 | #define CP0MVPC1_PCX 20 | |
113 | #define CP0MVPC1_PCP2 10 | |
114 | #define CP0MVPC1_PCP1 0 | |
115 | }; | |
116 | ||
c227f099 | 117 | typedef struct mips_def_t mips_def_t; |
ead9360e TS |
118 | |
119 | #define MIPS_SHADOW_SET_MAX 16 | |
120 | #define MIPS_TC_MAX 5 | |
f01be154 | 121 | #define MIPS_FPU_MAX 1 |
ead9360e | 122 | #define MIPS_DSP_ACC 4 |
e98c0d17 | 123 | #define MIPS_KSCRATCH_NUM 6 |
f6d4dd81 | 124 | #define MIPS_MAAR_MAX 16 /* Must be an even number. */ |
ead9360e | 125 | |
e97a391d | 126 | |
a86d421e AM |
127 | /* |
128 | * Summary of CP0 registers | |
129 | * ======================== | |
130 | * | |
131 | * | |
132 | * Register 0 Register 1 Register 2 Register 3 | |
133 | * ---------- ---------- ---------- ---------- | |
134 | * | |
135 | * 0 Index Random EntryLo0 EntryLo1 | |
136 | * 1 MVPControl VPEControl TCStatus GlobalNumber | |
137 | * 2 MVPConf0 VPEConf0 TCBind | |
138 | * 3 MVPConf1 VPEConf1 TCRestart | |
139 | * 4 VPControl YQMask TCHalt | |
140 | * 5 VPESchedule TCContext | |
141 | * 6 VPEScheFBack TCSchedule | |
142 | * 7 VPEOpt TCScheFBack TCOpt | |
143 | * | |
144 | * | |
145 | * Register 4 Register 5 Register 6 Register 7 | |
146 | * ---------- ---------- ---------- ---------- | |
147 | * | |
148 | * 0 Context PageMask Wired HWREna | |
149 | * 1 ContextConfig PageGrain SRSConf0 | |
150 | * 2 UserLocal SegCtl0 SRSConf1 | |
151 | * 3 XContextConfig SegCtl1 SRSConf2 | |
152 | * 4 DebugContextID SegCtl2 SRSConf3 | |
153 | * 5 MemoryMapID PWBase SRSConf4 | |
154 | * 6 PWField PWCtl | |
155 | * 7 PWSize | |
156 | * | |
157 | * | |
158 | * Register 8 Register 9 Register 10 Register 11 | |
159 | * ---------- ---------- ----------- ----------- | |
160 | * | |
161 | * 0 BadVAddr Count EntryHi Compare | |
162 | * 1 BadInstr | |
163 | * 2 BadInstrP | |
164 | * 3 BadInstrX | |
165 | * 4 GuestCtl1 GuestCtl0Ext | |
166 | * 5 GuestCtl2 | |
167db30e YK |
167 | * 6 SAARI GuestCtl3 |
168 | * 7 SAAR | |
a86d421e AM |
169 | * |
170 | * | |
171 | * Register 12 Register 13 Register 14 Register 15 | |
172 | * ----------- ----------- ----------- ----------- | |
173 | * | |
174 | * 0 Status Cause EPC PRId | |
175 | * 1 IntCtl EBase | |
176 | * 2 SRSCtl NestedEPC CDMMBase | |
177 | * 3 SRSMap CMGCRBase | |
178 | * 4 View_IPL View_RIPL BEVVA | |
179 | * 5 SRSMap2 NestedExc | |
180 | * 6 GuestCtl0 | |
181 | * 7 GTOffset | |
182 | * | |
183 | * | |
184 | * Register 16 Register 17 Register 18 Register 19 | |
185 | * ----------- ----------- ----------- ----------- | |
186 | * | |
187 | * 0 Config LLAddr WatchLo WatchHi | |
188 | * 1 Config1 MAAR WatchLo WatchHi | |
189 | * 2 Config2 MAARI WatchLo WatchHi | |
190 | * 3 Config3 WatchLo WatchHi | |
191 | * 4 Config4 WatchLo WatchHi | |
192 | * 5 Config5 WatchLo WatchHi | |
193 | * 6 WatchLo WatchHi | |
194 | * 7 WatchLo WatchHi | |
195 | * | |
196 | * | |
197 | * Register 20 Register 21 Register 22 Register 23 | |
198 | * ----------- ----------- ----------- ----------- | |
199 | * | |
200 | * 0 XContext Debug | |
201 | * 1 TraceControl | |
202 | * 2 TraceControl2 | |
203 | * 3 UserTraceData1 | |
204 | * 4 TraceIBPC | |
205 | * 5 TraceDBPC | |
206 | * 6 Debug2 | |
207 | * 7 | |
208 | * | |
209 | * | |
210 | * Register 24 Register 25 Register 26 Register 27 | |
211 | * ----------- ----------- ----------- ----------- | |
212 | * | |
213 | * 0 DEPC PerfCnt ErrCtl CacheErr | |
214 | * 1 PerfCnt | |
215 | * 2 TraceControl3 PerfCnt | |
216 | * 3 UserTraceData2 PerfCnt | |
217 | * 4 PerfCnt | |
218 | * 5 PerfCnt | |
219 | * 6 PerfCnt | |
220 | * 7 PerfCnt | |
221 | * | |
222 | * | |
223 | * Register 28 Register 29 Register 30 Register 31 | |
224 | * ----------- ----------- ----------- ----------- | |
225 | * | |
226 | * 0 DataLo DataHi ErrorEPC DESAVE | |
227 | * 1 TagLo TagHi | |
228 | * 2 DataLo DataHi KScratch<n> | |
229 | * 3 TagLo TagHi KScratch<n> | |
230 | * 4 DataLo DataHi KScratch<n> | |
231 | * 5 TagLo TagHi KScratch<n> | |
232 | * 6 DataLo DataHi KScratch<n> | |
233 | * 7 TagLo TagHi KScratch<n> | |
234 | * | |
50e7edc5 | 235 | */ |
04992c8c AM |
236 | #define CP0_REGISTER_00 0 |
237 | #define CP0_REGISTER_01 1 | |
238 | #define CP0_REGISTER_02 2 | |
239 | #define CP0_REGISTER_03 3 | |
240 | #define CP0_REGISTER_04 4 | |
241 | #define CP0_REGISTER_05 5 | |
242 | #define CP0_REGISTER_06 6 | |
243 | #define CP0_REGISTER_07 7 | |
244 | #define CP0_REGISTER_08 8 | |
245 | #define CP0_REGISTER_09 9 | |
246 | #define CP0_REGISTER_10 10 | |
247 | #define CP0_REGISTER_11 11 | |
248 | #define CP0_REGISTER_12 12 | |
249 | #define CP0_REGISTER_13 13 | |
250 | #define CP0_REGISTER_14 14 | |
251 | #define CP0_REGISTER_15 15 | |
252 | #define CP0_REGISTER_16 16 | |
253 | #define CP0_REGISTER_17 17 | |
254 | #define CP0_REGISTER_18 18 | |
255 | #define CP0_REGISTER_19 19 | |
256 | #define CP0_REGISTER_20 20 | |
257 | #define CP0_REGISTER_21 21 | |
258 | #define CP0_REGISTER_22 22 | |
259 | #define CP0_REGISTER_23 23 | |
260 | #define CP0_REGISTER_24 24 | |
261 | #define CP0_REGISTER_25 25 | |
262 | #define CP0_REGISTER_26 26 | |
263 | #define CP0_REGISTER_27 27 | |
264 | #define CP0_REGISTER_28 28 | |
265 | #define CP0_REGISTER_29 29 | |
266 | #define CP0_REGISTER_30 30 | |
267 | #define CP0_REGISTER_31 31 | |
268 | ||
269 | ||
270 | /* CP0 Register 00 */ | |
271 | #define CP0_REG00__INDEX 0 | |
272 | #define CP0_REG00__VPCONTROL 4 | |
273 | /* CP0 Register 01 */ | |
274 | /* CP0 Register 02 */ | |
275 | #define CP0_REG02__ENTRYLO0 0 | |
276 | /* CP0 Register 03 */ | |
277 | #define CP0_REG03__ENTRYLO1 0 | |
278 | #define CP0_REG03__GLOBALNUM 1 | |
279 | /* CP0 Register 04 */ | |
280 | #define CP0_REG04__CONTEXT 0 | |
281 | #define CP0_REG04__USERLOCAL 2 | |
282 | #define CP0_REG04__DBGCONTEXTID 4 | |
283 | #define CP0_REG00__MMID 5 | |
284 | /* CP0 Register 05 */ | |
285 | #define CP0_REG05__PAGEMASK 0 | |
286 | #define CP0_REG05__PAGEGRAIN 1 | |
287 | /* CP0 Register 06 */ | |
288 | #define CP0_REG06__WIRED 0 | |
289 | /* CP0 Register 07 */ | |
290 | #define CP0_REG07__HWRENA 0 | |
291 | /* CP0 Register 08 */ | |
292 | #define CP0_REG08__BADVADDR 0 | |
293 | #define CP0_REG08__BADINSTR 1 | |
294 | #define CP0_REG08__BADINSTRP 2 | |
295 | /* CP0 Register 09 */ | |
296 | #define CP0_REG09__COUNT 0 | |
297 | #define CP0_REG09__SAARI 6 | |
298 | #define CP0_REG09__SAAR 7 | |
299 | /* CP0 Register 10 */ | |
300 | #define CP0_REG10__ENTRYHI 0 | |
301 | #define CP0_REG10__GUESTCTL1 4 | |
302 | #define CP0_REG10__GUESTCTL2 5 | |
303 | /* CP0 Register 11 */ | |
304 | #define CP0_REG11__COMPARE 0 | |
305 | #define CP0_REG11__GUESTCTL0EXT 4 | |
306 | /* CP0 Register 12 */ | |
307 | #define CP0_REG12__STATUS 0 | |
308 | #define CP0_REG12__INTCTL 1 | |
309 | #define CP0_REG12__SRSCTL 2 | |
310 | #define CP0_REG12__GUESTCTL0 6 | |
311 | #define CP0_REG12__GTOFFSET 7 | |
312 | /* CP0 Register 13 */ | |
313 | #define CP0_REG13__CAUSE 0 | |
314 | /* CP0 Register 14 */ | |
315 | #define CP0_REG14__EPC 0 | |
316 | /* CP0 Register 15 */ | |
317 | #define CP0_REG15__PRID 0 | |
318 | #define CP0_REG15__EBASE 1 | |
319 | #define CP0_REG15__CDMMBASE 2 | |
320 | #define CP0_REG15__CMGCRBASE 3 | |
321 | /* CP0 Register 16 */ | |
322 | #define CP0_REG16__CONFIG 0 | |
323 | #define CP0_REG16__CONFIG1 1 | |
324 | #define CP0_REG16__CONFIG2 2 | |
325 | #define CP0_REG16__CONFIG3 3 | |
326 | #define CP0_REG16__CONFIG4 4 | |
327 | #define CP0_REG16__CONFIG5 5 | |
328 | #define CP0_REG00__CONFIG7 7 | |
329 | /* CP0 Register 17 */ | |
330 | #define CP0_REG17__LLADDR 0 | |
331 | #define CP0_REG17__MAAR 1 | |
332 | #define CP0_REG17__MAARI 2 | |
333 | /* CP0 Register 18 */ | |
334 | #define CP0_REG18__WATCHLO0 0 | |
335 | #define CP0_REG18__WATCHLO1 1 | |
336 | #define CP0_REG18__WATCHLO2 2 | |
337 | #define CP0_REG18__WATCHLO3 3 | |
338 | /* CP0 Register 19 */ | |
339 | #define CP0_REG19__WATCHHI0 0 | |
340 | #define CP0_REG19__WATCHHI1 1 | |
341 | #define CP0_REG19__WATCHHI2 2 | |
342 | #define CP0_REG19__WATCHHI3 3 | |
343 | /* CP0 Register 20 */ | |
344 | #define CP0_REG20__XCONTEXT 0 | |
345 | /* CP0 Register 21 */ | |
346 | /* CP0 Register 22 */ | |
347 | /* CP0 Register 23 */ | |
348 | #define CP0_REG23__DEBUG 0 | |
349 | /* CP0 Register 24 */ | |
350 | #define CP0_REG24__DEPC 0 | |
351 | /* CP0 Register 25 */ | |
352 | #define CP0_REG25__PERFCTL0 0 | |
353 | #define CP0_REG25__PERFCNT0 1 | |
354 | #define CP0_REG25__PERFCTL1 2 | |
355 | #define CP0_REG25__PERFCNT1 3 | |
356 | #define CP0_REG25__PERFCTL2 4 | |
357 | #define CP0_REG25__PERFCNT2 5 | |
358 | #define CP0_REG25__PERFCTL3 6 | |
359 | #define CP0_REG25__PERFCNT3 7 | |
360 | /* CP0 Register 26 */ | |
361 | #define CP0_REG00__ERRCTL 0 | |
362 | /* CP0 Register 27 */ | |
363 | #define CP0_REG27__CACHERR 0 | |
364 | /* CP0 Register 28 */ | |
365 | #define CP0_REG28__ITAGLO 0 | |
366 | #define CP0_REG28__IDATALO 1 | |
367 | #define CP0_REG28__DTAGLO 2 | |
368 | #define CP0_REG28__DDATALO 3 | |
369 | /* CP0 Register 29 */ | |
370 | #define CP0_REG29__IDATAHI 1 | |
371 | #define CP0_REG29__DDATAHI 3 | |
372 | /* CP0 Register 30 */ | |
373 | #define CP0_REG30__ERROREPC 0 | |
374 | /* CP0 Register 31 */ | |
375 | #define CP0_REG31__DESAVE 0 | |
376 | #define CP0_REG31__KSCRATCH1 2 | |
377 | #define CP0_REG31__KSCRATCH2 3 | |
378 | #define CP0_REG31__KSCRATCH3 4 | |
379 | #define CP0_REG31__KSCRATCH4 5 | |
380 | #define CP0_REG31__KSCRATCH5 6 | |
381 | #define CP0_REG31__KSCRATCH6 7 | |
ea9c5e83 AM |
382 | |
383 | ||
384 | typedef struct TCState TCState; | |
385 | struct TCState { | |
386 | target_ulong gpr[32]; | |
387 | target_ulong PC; | |
388 | target_ulong HI[MIPS_DSP_ACC]; | |
389 | target_ulong LO[MIPS_DSP_ACC]; | |
390 | target_ulong ACX[MIPS_DSP_ACC]; | |
391 | target_ulong DSPControl; | |
392 | int32_t CP0_TCStatus; | |
393 | #define CP0TCSt_TCU3 31 | |
394 | #define CP0TCSt_TCU2 30 | |
395 | #define CP0TCSt_TCU1 29 | |
396 | #define CP0TCSt_TCU0 28 | |
397 | #define CP0TCSt_TMX 27 | |
398 | #define CP0TCSt_RNST 23 | |
399 | #define CP0TCSt_TDS 21 | |
400 | #define CP0TCSt_DT 20 | |
401 | #define CP0TCSt_DA 15 | |
402 | #define CP0TCSt_A 13 | |
403 | #define CP0TCSt_TKSU 11 | |
404 | #define CP0TCSt_IXMT 10 | |
405 | #define CP0TCSt_TASID 0 | |
406 | int32_t CP0_TCBind; | |
407 | #define CP0TCBd_CurTC 21 | |
408 | #define CP0TCBd_TBE 17 | |
409 | #define CP0TCBd_CurVPE 0 | |
410 | target_ulong CP0_TCHalt; | |
411 | target_ulong CP0_TCContext; | |
412 | target_ulong CP0_TCSchedule; | |
413 | target_ulong CP0_TCScheFBack; | |
414 | int32_t CP0_Debug_tcstatus; | |
415 | target_ulong CP0_UserLocal; | |
416 | ||
417 | int32_t msacsr; | |
418 | ||
419 | #define MSACSR_FS 24 | |
420 | #define MSACSR_FS_MASK (1 << MSACSR_FS) | |
421 | #define MSACSR_NX 18 | |
422 | #define MSACSR_NX_MASK (1 << MSACSR_NX) | |
423 | #define MSACSR_CEF 2 | |
424 | #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) | |
425 | #define MSACSR_RM 0 | |
426 | #define MSACSR_RM_MASK (0x3 << MSACSR_RM) | |
427 | #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ | |
428 | MSACSR_FS_MASK) | |
429 | ||
430 | float_status msa_fp_status; | |
431 | ||
a168a796 FN |
432 | /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ |
433 | uint64_t mmr[32]; | |
434 | ||
ea9c5e83 AM |
435 | #define NUMBER_OF_MXU_REGISTERS 16 |
436 | target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; | |
437 | target_ulong mxu_cr; | |
438 | #define MXU_CR_LC 31 | |
439 | #define MXU_CR_RC 30 | |
440 | #define MXU_CR_BIAS 2 | |
441 | #define MXU_CR_RD_EN 1 | |
442 | #define MXU_CR_MXU_EN 0 | |
443 | ||
444 | }; | |
445 | ||
043715d1 | 446 | struct MIPSITUState; |
ea9c5e83 AM |
447 | typedef struct CPUMIPSState CPUMIPSState; |
448 | struct CPUMIPSState { | |
449 | TCState active_tc; | |
450 | CPUMIPSFPUContext active_fpu; | |
451 | ||
452 | uint32_t current_tc; | |
453 | uint32_t current_fpu; | |
454 | ||
455 | uint32_t SEGBITS; | |
456 | uint32_t PABITS; | |
457 | #if defined(TARGET_MIPS64) | |
458 | # define PABITS_BASE 36 | |
459 | #else | |
460 | # define PABITS_BASE 32 | |
461 | #endif | |
462 | target_ulong SEGMask; | |
463 | uint64_t PAMask; | |
464 | #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) | |
465 | ||
466 | int32_t msair; | |
467 | #define MSAIR_ProcID 8 | |
468 | #define MSAIR_Rev 0 | |
469 | ||
50e7edc5 AM |
470 | /* |
471 | * CP0 Register 0 | |
a86d421e | 472 | */ |
9c2149c8 | 473 | int32_t CP0_Index; |
ead9360e | 474 | /* CP0_MVP* are per MVP registers. */ |
01bc435b YK |
475 | int32_t CP0_VPControl; |
476 | #define CP0VPCtl_DIS 0 | |
50e7edc5 AM |
477 | /* |
478 | * CP0 Register 1 | |
479 | */ | |
9c2149c8 | 480 | int32_t CP0_Random; |
ead9360e TS |
481 | int32_t CP0_VPEControl; |
482 | #define CP0VPECo_YSI 21 | |
483 | #define CP0VPECo_GSI 20 | |
484 | #define CP0VPECo_EXCPT 16 | |
485 | #define CP0VPECo_TE 15 | |
486 | #define CP0VPECo_TargTC 0 | |
487 | int32_t CP0_VPEConf0; | |
488 | #define CP0VPEC0_M 31 | |
489 | #define CP0VPEC0_XTC 21 | |
490 | #define CP0VPEC0_TCS 19 | |
491 | #define CP0VPEC0_SCS 18 | |
492 | #define CP0VPEC0_DSC 17 | |
493 | #define CP0VPEC0_ICS 16 | |
494 | #define CP0VPEC0_MVP 1 | |
495 | #define CP0VPEC0_VPA 0 | |
496 | int32_t CP0_VPEConf1; | |
497 | #define CP0VPEC1_NCX 20 | |
498 | #define CP0VPEC1_NCP2 10 | |
499 | #define CP0VPEC1_NCP1 0 | |
500 | target_ulong CP0_YQMask; | |
501 | target_ulong CP0_VPESchedule; | |
502 | target_ulong CP0_VPEScheFBack; | |
503 | int32_t CP0_VPEOpt; | |
504 | #define CP0VPEOpt_IWX7 15 | |
505 | #define CP0VPEOpt_IWX6 14 | |
506 | #define CP0VPEOpt_IWX5 13 | |
507 | #define CP0VPEOpt_IWX4 12 | |
508 | #define CP0VPEOpt_IWX3 11 | |
509 | #define CP0VPEOpt_IWX2 10 | |
510 | #define CP0VPEOpt_IWX1 9 | |
511 | #define CP0VPEOpt_IWX0 8 | |
512 | #define CP0VPEOpt_DWX7 7 | |
513 | #define CP0VPEOpt_DWX6 6 | |
514 | #define CP0VPEOpt_DWX5 5 | |
515 | #define CP0VPEOpt_DWX4 4 | |
516 | #define CP0VPEOpt_DWX3 3 | |
517 | #define CP0VPEOpt_DWX2 2 | |
518 | #define CP0VPEOpt_DWX1 1 | |
519 | #define CP0VPEOpt_DWX0 0 | |
50e7edc5 AM |
520 | /* |
521 | * CP0 Register 2 | |
522 | */ | |
284b731a | 523 | uint64_t CP0_EntryLo0; |
50e7edc5 AM |
524 | /* |
525 | * CP0 Register 3 | |
526 | */ | |
284b731a | 527 | uint64_t CP0_EntryLo1; |
2fb58b73 LA |
528 | #if defined(TARGET_MIPS64) |
529 | # define CP0EnLo_RI 63 | |
530 | # define CP0EnLo_XI 62 | |
531 | #else | |
532 | # define CP0EnLo_RI 31 | |
533 | # define CP0EnLo_XI 30 | |
534 | #endif | |
01bc435b YK |
535 | int32_t CP0_GlobalNumber; |
536 | #define CP0GN_VPId 0 | |
50e7edc5 AM |
537 | /* |
538 | * CP0 Register 4 | |
539 | */ | |
9c2149c8 | 540 | target_ulong CP0_Context; |
e98c0d17 | 541 | target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; |
3ef521ee | 542 | int32_t CP0_MemoryMapID; |
50e7edc5 AM |
543 | /* |
544 | * CP0 Register 5 | |
545 | */ | |
9c2149c8 | 546 | int32_t CP0_PageMask; |
7207c7f9 | 547 | int32_t CP0_PageGrain_rw_bitmask; |
9c2149c8 | 548 | int32_t CP0_PageGrain; |
7207c7f9 LA |
549 | #define CP0PG_RIE 31 |
550 | #define CP0PG_XIE 30 | |
e117f526 | 551 | #define CP0PG_ELPA 29 |
92ceb440 | 552 | #define CP0PG_IEC 27 |
cec56a73 JH |
553 | target_ulong CP0_SegCtl0; |
554 | target_ulong CP0_SegCtl1; | |
555 | target_ulong CP0_SegCtl2; | |
556 | #define CP0SC_PA 9 | |
557 | #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) | |
558 | #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) | |
559 | #define CP0SC_AM 4 | |
560 | #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) | |
561 | #define CP0SC_AM_UK 0ULL | |
562 | #define CP0SC_AM_MK 1ULL | |
563 | #define CP0SC_AM_MSK 2ULL | |
564 | #define CP0SC_AM_MUSK 3ULL | |
565 | #define CP0SC_AM_MUSUK 4ULL | |
566 | #define CP0SC_AM_USK 5ULL | |
567 | #define CP0SC_AM_UUSK 7ULL | |
568 | #define CP0SC_EU 3 | |
569 | #define CP0SC_EU_MASK (1ULL << CP0SC_EU) | |
570 | #define CP0SC_C 0 | |
571 | #define CP0SC_C_MASK (0x7ULL << CP0SC_C) | |
572 | #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ | |
573 | CP0SC_PA_MASK) | |
574 | #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ | |
575 | CP0SC_PA_1GMASK) | |
576 | #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) | |
577 | #define CP0SC1_XAM 59 | |
578 | #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) | |
579 | #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) | |
580 | #define CP0SC2_XR 56 | |
581 | #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) | |
582 | #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) | |
5e31fdd5 | 583 | target_ulong CP0_PWBase; |
fa75ad14 YK |
584 | target_ulong CP0_PWField; |
585 | #if defined(TARGET_MIPS64) | |
586 | #define CP0PF_BDI 32 /* 37..32 */ | |
587 | #define CP0PF_GDI 24 /* 29..24 */ | |
588 | #define CP0PF_UDI 18 /* 23..18 */ | |
589 | #define CP0PF_MDI 12 /* 17..12 */ | |
590 | #define CP0PF_PTI 6 /* 11..6 */ | |
591 | #define CP0PF_PTEI 0 /* 5..0 */ | |
592 | #else | |
593 | #define CP0PF_GDW 24 /* 29..24 */ | |
594 | #define CP0PF_UDW 18 /* 23..18 */ | |
595 | #define CP0PF_MDW 12 /* 17..12 */ | |
596 | #define CP0PF_PTW 6 /* 11..6 */ | |
597 | #define CP0PF_PTEW 0 /* 5..0 */ | |
598 | #endif | |
20b28ebc YK |
599 | target_ulong CP0_PWSize; |
600 | #if defined(TARGET_MIPS64) | |
601 | #define CP0PS_BDW 32 /* 37..32 */ | |
602 | #endif | |
603 | #define CP0PS_PS 30 | |
604 | #define CP0PS_GDW 24 /* 29..24 */ | |
605 | #define CP0PS_UDW 18 /* 23..18 */ | |
606 | #define CP0PS_MDW 12 /* 17..12 */ | |
607 | #define CP0PS_PTW 6 /* 11..6 */ | |
608 | #define CP0PS_PTEW 0 /* 5..0 */ | |
50e7edc5 AM |
609 | /* |
610 | * CP0 Register 6 | |
611 | */ | |
9c2149c8 | 612 | int32_t CP0_Wired; |
103be64c YK |
613 | int32_t CP0_PWCtl; |
614 | #define CP0PC_PWEN 31 | |
615 | #if defined(TARGET_MIPS64) | |
616 | #define CP0PC_PWDIREXT 30 | |
617 | #define CP0PC_XK 28 | |
618 | #define CP0PC_XS 27 | |
619 | #define CP0PC_XU 26 | |
620 | #endif | |
621 | #define CP0PC_DPH 7 | |
622 | #define CP0PC_HUGEPG 6 | |
623 | #define CP0PC_PSN 0 /* 5..0 */ | |
ead9360e TS |
624 | int32_t CP0_SRSConf0_rw_bitmask; |
625 | int32_t CP0_SRSConf0; | |
626 | #define CP0SRSC0_M 31 | |
627 | #define CP0SRSC0_SRS3 20 | |
628 | #define CP0SRSC0_SRS2 10 | |
629 | #define CP0SRSC0_SRS1 0 | |
630 | int32_t CP0_SRSConf1_rw_bitmask; | |
631 | int32_t CP0_SRSConf1; | |
632 | #define CP0SRSC1_M 31 | |
633 | #define CP0SRSC1_SRS6 20 | |
634 | #define CP0SRSC1_SRS5 10 | |
635 | #define CP0SRSC1_SRS4 0 | |
636 | int32_t CP0_SRSConf2_rw_bitmask; | |
637 | int32_t CP0_SRSConf2; | |
638 | #define CP0SRSC2_M 31 | |
639 | #define CP0SRSC2_SRS9 20 | |
640 | #define CP0SRSC2_SRS8 10 | |
641 | #define CP0SRSC2_SRS7 0 | |
642 | int32_t CP0_SRSConf3_rw_bitmask; | |
643 | int32_t CP0_SRSConf3; | |
644 | #define CP0SRSC3_M 31 | |
645 | #define CP0SRSC3_SRS12 20 | |
646 | #define CP0SRSC3_SRS11 10 | |
647 | #define CP0SRSC3_SRS10 0 | |
648 | int32_t CP0_SRSConf4_rw_bitmask; | |
649 | int32_t CP0_SRSConf4; | |
650 | #define CP0SRSC4_SRS15 20 | |
651 | #define CP0SRSC4_SRS14 10 | |
652 | #define CP0SRSC4_SRS13 0 | |
50e7edc5 AM |
653 | /* |
654 | * CP0 Register 7 | |
655 | */ | |
9c2149c8 | 656 | int32_t CP0_HWREna; |
50e7edc5 AM |
657 | /* |
658 | * CP0 Register 8 | |
659 | */ | |
c570fd16 | 660 | target_ulong CP0_BadVAddr; |
aea14095 LA |
661 | uint32_t CP0_BadInstr; |
662 | uint32_t CP0_BadInstrP; | |
25beba9b | 663 | uint32_t CP0_BadInstrX; |
50e7edc5 AM |
664 | /* |
665 | * CP0 Register 9 | |
666 | */ | |
9c2149c8 | 667 | int32_t CP0_Count; |
167db30e YK |
668 | uint32_t CP0_SAARI; |
669 | #define CP0SAARI_TARGET 0 /* 5..0 */ | |
670 | uint64_t CP0_SAAR[2]; | |
671 | #define CP0SAAR_BASE 12 /* 43..12 */ | |
672 | #define CP0SAAR_SIZE 1 /* 5..1 */ | |
673 | #define CP0SAAR_EN 0 | |
50e7edc5 AM |
674 | /* |
675 | * CP0 Register 10 | |
676 | */ | |
9c2149c8 | 677 | target_ulong CP0_EntryHi; |
9456c2fb | 678 | #define CP0EnHi_EHINV 10 |
6ec98bd7 | 679 | target_ulong CP0_EntryHi_ASID_mask; |
50e7edc5 AM |
680 | /* |
681 | * CP0 Register 11 | |
682 | */ | |
9c2149c8 | 683 | int32_t CP0_Compare; |
50e7edc5 AM |
684 | /* |
685 | * CP0 Register 12 | |
686 | */ | |
9c2149c8 | 687 | int32_t CP0_Status; |
6af0bf9c FB |
688 | #define CP0St_CU3 31 |
689 | #define CP0St_CU2 30 | |
690 | #define CP0St_CU1 29 | |
691 | #define CP0St_CU0 28 | |
692 | #define CP0St_RP 27 | |
6ea83fed | 693 | #define CP0St_FR 26 |
6af0bf9c | 694 | #define CP0St_RE 25 |
7a387fff TS |
695 | #define CP0St_MX 24 |
696 | #define CP0St_PX 23 | |
6af0bf9c FB |
697 | #define CP0St_BEV 22 |
698 | #define CP0St_TS 21 | |
699 | #define CP0St_SR 20 | |
700 | #define CP0St_NMI 19 | |
701 | #define CP0St_IM 8 | |
7a387fff TS |
702 | #define CP0St_KX 7 |
703 | #define CP0St_SX 6 | |
704 | #define CP0St_UX 5 | |
623a930e | 705 | #define CP0St_KSU 3 |
6af0bf9c FB |
706 | #define CP0St_ERL 2 |
707 | #define CP0St_EXL 1 | |
708 | #define CP0St_IE 0 | |
9c2149c8 | 709 | int32_t CP0_IntCtl; |
ead9360e | 710 | #define CP0IntCtl_IPTI 29 |
88991299 | 711 | #define CP0IntCtl_IPPCI 26 |
ead9360e | 712 | #define CP0IntCtl_VS 5 |
9c2149c8 | 713 | int32_t CP0_SRSCtl; |
ead9360e TS |
714 | #define CP0SRSCtl_HSS 26 |
715 | #define CP0SRSCtl_EICSS 18 | |
716 | #define CP0SRSCtl_ESS 12 | |
717 | #define CP0SRSCtl_PSS 6 | |
718 | #define CP0SRSCtl_CSS 0 | |
9c2149c8 | 719 | int32_t CP0_SRSMap; |
ead9360e TS |
720 | #define CP0SRSMap_SSV7 28 |
721 | #define CP0SRSMap_SSV6 24 | |
722 | #define CP0SRSMap_SSV5 20 | |
723 | #define CP0SRSMap_SSV4 16 | |
724 | #define CP0SRSMap_SSV3 12 | |
725 | #define CP0SRSMap_SSV2 8 | |
726 | #define CP0SRSMap_SSV1 4 | |
727 | #define CP0SRSMap_SSV0 0 | |
50e7edc5 AM |
728 | /* |
729 | * CP0 Register 13 | |
730 | */ | |
9c2149c8 | 731 | int32_t CP0_Cause; |
7a387fff TS |
732 | #define CP0Ca_BD 31 |
733 | #define CP0Ca_TI 30 | |
734 | #define CP0Ca_CE 28 | |
735 | #define CP0Ca_DC 27 | |
736 | #define CP0Ca_PCI 26 | |
6af0bf9c | 737 | #define CP0Ca_IV 23 |
7a387fff TS |
738 | #define CP0Ca_WP 22 |
739 | #define CP0Ca_IP 8 | |
4de9b249 | 740 | #define CP0Ca_IP_mask 0x0000FF00 |
7a387fff | 741 | #define CP0Ca_EC 2 |
50e7edc5 AM |
742 | /* |
743 | * CP0 Register 14 | |
744 | */ | |
c570fd16 | 745 | target_ulong CP0_EPC; |
50e7edc5 AM |
746 | /* |
747 | * CP0 Register 15 | |
748 | */ | |
9c2149c8 | 749 | int32_t CP0_PRid; |
74dbf824 JH |
750 | target_ulong CP0_EBase; |
751 | target_ulong CP0_EBaseWG_rw_bitmask; | |
752 | #define CP0EBase_WG 11 | |
c870e3f5 | 753 | target_ulong CP0_CMGCRBase; |
50e7edc5 AM |
754 | /* |
755 | * CP0 Register 16 | |
756 | */ | |
9c2149c8 | 757 | int32_t CP0_Config0; |
6af0bf9c | 758 | #define CP0C0_M 31 |
0413d7a5 AM |
759 | #define CP0C0_K23 28 /* 30..28 */ |
760 | #define CP0C0_KU 25 /* 27..25 */ | |
6af0bf9c | 761 | #define CP0C0_MDU 20 |
aff2bc6d | 762 | #define CP0C0_MM 18 |
6af0bf9c | 763 | #define CP0C0_BM 16 |
0413d7a5 | 764 | #define CP0C0_Impl 16 /* 24..16 */ |
6af0bf9c | 765 | #define CP0C0_BE 15 |
0413d7a5 AM |
766 | #define CP0C0_AT 13 /* 14..13 */ |
767 | #define CP0C0_AR 10 /* 12..10 */ | |
768 | #define CP0C0_MT 7 /* 9..7 */ | |
7a387fff | 769 | #define CP0C0_VI 3 |
0413d7a5 | 770 | #define CP0C0_K0 0 /* 2..0 */ |
9c2149c8 | 771 | int32_t CP0_Config1; |
7a387fff | 772 | #define CP0C1_M 31 |
0413d7a5 AM |
773 | #define CP0C1_MMU 25 /* 30..25 */ |
774 | #define CP0C1_IS 22 /* 24..22 */ | |
775 | #define CP0C1_IL 19 /* 21..19 */ | |
776 | #define CP0C1_IA 16 /* 18..16 */ | |
777 | #define CP0C1_DS 13 /* 15..13 */ | |
778 | #define CP0C1_DL 10 /* 12..10 */ | |
779 | #define CP0C1_DA 7 /* 9..7 */ | |
7a387fff TS |
780 | #define CP0C1_C2 6 |
781 | #define CP0C1_MD 5 | |
6af0bf9c FB |
782 | #define CP0C1_PC 4 |
783 | #define CP0C1_WR 3 | |
784 | #define CP0C1_CA 2 | |
785 | #define CP0C1_EP 1 | |
786 | #define CP0C1_FP 0 | |
9c2149c8 | 787 | int32_t CP0_Config2; |
7a387fff | 788 | #define CP0C2_M 31 |
0413d7a5 AM |
789 | #define CP0C2_TU 28 /* 30..28 */ |
790 | #define CP0C2_TS 24 /* 27..24 */ | |
791 | #define CP0C2_TL 20 /* 23..20 */ | |
792 | #define CP0C2_TA 16 /* 19..16 */ | |
793 | #define CP0C2_SU 12 /* 15..12 */ | |
794 | #define CP0C2_SS 8 /* 11..8 */ | |
795 | #define CP0C2_SL 4 /* 7..4 */ | |
796 | #define CP0C2_SA 0 /* 3..0 */ | |
9c2149c8 | 797 | int32_t CP0_Config3; |
0413d7a5 AM |
798 | #define CP0C3_M 31 |
799 | #define CP0C3_BPG 30 | |
800 | #define CP0C3_CMGCR 29 | |
801 | #define CP0C3_MSAP 28 | |
802 | #define CP0C3_BP 27 | |
803 | #define CP0C3_BI 26 | |
804 | #define CP0C3_SC 25 | |
805 | #define CP0C3_PW 24 | |
806 | #define CP0C3_VZ 23 | |
807 | #define CP0C3_IPLV 21 /* 22..21 */ | |
808 | #define CP0C3_MMAR 18 /* 20..18 */ | |
809 | #define CP0C3_MCU 17 | |
810 | #define CP0C3_ISA_ON_EXC 16 | |
811 | #define CP0C3_ISA 14 /* 15..14 */ | |
812 | #define CP0C3_ULRI 13 | |
813 | #define CP0C3_RXI 12 | |
814 | #define CP0C3_DSP2P 11 | |
815 | #define CP0C3_DSPP 10 | |
816 | #define CP0C3_CTXTC 9 | |
817 | #define CP0C3_ITL 8 | |
818 | #define CP0C3_LPA 7 | |
819 | #define CP0C3_VEIC 6 | |
820 | #define CP0C3_VInt 5 | |
821 | #define CP0C3_SP 4 | |
822 | #define CP0C3_CDMM 3 | |
823 | #define CP0C3_MT 2 | |
824 | #define CP0C3_SM 1 | |
825 | #define CP0C3_TL 0 | |
8280b12c MR |
826 | int32_t CP0_Config4; |
827 | int32_t CP0_Config4_rw_bitmask; | |
0413d7a5 AM |
828 | #define CP0C4_M 31 |
829 | #define CP0C4_IE 29 /* 30..29 */ | |
830 | #define CP0C4_AE 28 | |
831 | #define CP0C4_VTLBSizeExt 24 /* 27..24 */ | |
832 | #define CP0C4_KScrExist 16 | |
833 | #define CP0C4_MMUExtDef 14 | |
834 | #define CP0C4_FTLBPageSize 8 /* 12..8 */ | |
835 | /* bit layout if MMUExtDef=1 */ | |
836 | #define CP0C4_MMUSizeExt 0 /* 7..0 */ | |
837 | /* bit layout if MMUExtDef=2 */ | |
838 | #define CP0C4_FTLBWays 4 /* 7..4 */ | |
839 | #define CP0C4_FTLBSets 0 /* 3..0 */ | |
8280b12c MR |
840 | int32_t CP0_Config5; |
841 | int32_t CP0_Config5_rw_bitmask; | |
0413d7a5 AM |
842 | #define CP0C5_M 31 |
843 | #define CP0C5_K 30 | |
844 | #define CP0C5_CV 29 | |
845 | #define CP0C5_EVA 28 | |
846 | #define CP0C5_MSAEn 27 | |
847 | #define CP0C5_PMJ 23 /* 25..23 */ | |
848 | #define CP0C5_WR2 22 | |
849 | #define CP0C5_NMS 21 | |
850 | #define CP0C5_ULS 20 | |
851 | #define CP0C5_XPA 19 | |
852 | #define CP0C5_CRCP 18 | |
853 | #define CP0C5_MI 17 | |
854 | #define CP0C5_GI 15 /* 16..15 */ | |
855 | #define CP0C5_CA2 14 | |
856 | #define CP0C5_XNP 13 | |
857 | #define CP0C5_DEC 11 | |
858 | #define CP0C5_L2C 10 | |
859 | #define CP0C5_UFE 9 | |
860 | #define CP0C5_FRE 8 | |
861 | #define CP0C5_VP 7 | |
862 | #define CP0C5_SBRI 6 | |
863 | #define CP0C5_MVH 5 | |
864 | #define CP0C5_LLB 4 | |
865 | #define CP0C5_MRP 3 | |
866 | #define CP0C5_UFR 2 | |
867 | #define CP0C5_NFExists 0 | |
e397ee33 TS |
868 | int32_t CP0_Config6; |
869 | int32_t CP0_Config7; | |
f6d4dd81 YK |
870 | uint64_t CP0_MAAR[MIPS_MAAR_MAX]; |
871 | int32_t CP0_MAARI; | |
ead9360e | 872 | /* XXX: Maybe make LLAddr per-TC? */ |
50e7edc5 AM |
873 | /* |
874 | * CP0 Register 17 | |
875 | */ | |
284b731a | 876 | uint64_t lladdr; |
590bc601 PB |
877 | target_ulong llval; |
878 | target_ulong llnewval; | |
0b16dcd1 AR |
879 | uint64_t llval_wp; |
880 | uint32_t llnewval_wp; | |
590bc601 | 881 | target_ulong llreg; |
284b731a | 882 | uint64_t CP0_LLAddr_rw_bitmask; |
2a6e32dd | 883 | int CP0_LLAddr_shift; |
50e7edc5 AM |
884 | /* |
885 | * CP0 Register 18 | |
886 | */ | |
fd88b6ab | 887 | target_ulong CP0_WatchLo[8]; |
50e7edc5 AM |
888 | /* |
889 | * CP0 Register 19 | |
890 | */ | |
fd88b6ab | 891 | int32_t CP0_WatchHi[8]; |
6ec98bd7 | 892 | #define CP0WH_ASID 16 |
50e7edc5 AM |
893 | /* |
894 | * CP0 Register 20 | |
895 | */ | |
9c2149c8 TS |
896 | target_ulong CP0_XContext; |
897 | int32_t CP0_Framemask; | |
50e7edc5 AM |
898 | /* |
899 | * CP0 Register 23 | |
900 | */ | |
9c2149c8 | 901 | int32_t CP0_Debug; |
ead9360e | 902 | #define CP0DB_DBD 31 |
6af0bf9c FB |
903 | #define CP0DB_DM 30 |
904 | #define CP0DB_LSNM 28 | |
905 | #define CP0DB_Doze 27 | |
906 | #define CP0DB_Halt 26 | |
907 | #define CP0DB_CNT 25 | |
908 | #define CP0DB_IBEP 24 | |
909 | #define CP0DB_DBEP 21 | |
910 | #define CP0DB_IEXI 20 | |
911 | #define CP0DB_VER 15 | |
912 | #define CP0DB_DEC 10 | |
913 | #define CP0DB_SSt 8 | |
914 | #define CP0DB_DINT 5 | |
915 | #define CP0DB_DIB 4 | |
916 | #define CP0DB_DDBS 3 | |
917 | #define CP0DB_DDBL 2 | |
918 | #define CP0DB_DBp 1 | |
919 | #define CP0DB_DSS 0 | |
50e7edc5 AM |
920 | /* |
921 | * CP0 Register 24 | |
922 | */ | |
c570fd16 | 923 | target_ulong CP0_DEPC; |
50e7edc5 AM |
924 | /* |
925 | * CP0 Register 25 | |
926 | */ | |
9c2149c8 | 927 | int32_t CP0_Performance0; |
50e7edc5 AM |
928 | /* |
929 | * CP0 Register 26 | |
930 | */ | |
0d74a222 LA |
931 | int32_t CP0_ErrCtl; |
932 | #define CP0EC_WST 29 | |
933 | #define CP0EC_SPR 28 | |
934 | #define CP0EC_ITC 26 | |
50e7edc5 AM |
935 | /* |
936 | * CP0 Register 28 | |
937 | */ | |
284b731a | 938 | uint64_t CP0_TagLo; |
9c2149c8 | 939 | int32_t CP0_DataLo; |
50e7edc5 AM |
940 | /* |
941 | * CP0 Register 29 | |
942 | */ | |
9c2149c8 TS |
943 | int32_t CP0_TagHi; |
944 | int32_t CP0_DataHi; | |
50e7edc5 AM |
945 | /* |
946 | * CP0 Register 30 | |
947 | */ | |
c570fd16 | 948 | target_ulong CP0_ErrorEPC; |
50e7edc5 AM |
949 | /* |
950 | * CP0 Register 31 | |
951 | */ | |
9c2149c8 | 952 | int32_t CP0_DESAVE; |
50e7edc5 | 953 | |
b5dc7732 TS |
954 | /* We waste some space so we can handle shadow registers like TCs. */ |
955 | TCState tcs[MIPS_SHADOW_SET_MAX]; | |
f01be154 | 956 | CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; |
5cbdb3a3 | 957 | /* QEMU */ |
6af0bf9c | 958 | int error_code; |
aea14095 LA |
959 | #define EXCP_TLB_NOMATCH 0x1 |
960 | #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ | |
6af0bf9c FB |
961 | uint32_t hflags; /* CPU State */ |
962 | /* TMASK defines different execution modes */ | |
42c86612 | 963 | #define MIPS_HFLAG_TMASK 0x1F5807FF |
79ef2c4c | 964 | #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ |
623a930e TS |
965 | /* The KSU flags must be the lowest bits in hflags. The flag order |
966 | must be the same as defined for CP0 Status. This allows to use | |
967 | the bits as the value of mmu_idx. */ | |
79ef2c4c NF |
968 | #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ |
969 | #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ | |
970 | #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ | |
971 | #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ | |
972 | #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ | |
973 | #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ | |
974 | #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ | |
975 | #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ | |
976 | #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ | |
b8aa4598 TS |
977 | /* True if the MIPS IV COP1X instructions can be used. This also |
978 | controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S | |
979 | and RSQRT.D. */ | |
79ef2c4c NF |
980 | #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ |
981 | #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ | |
01f72885 | 982 | #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ |
79ef2c4c NF |
983 | #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ |
984 | #define MIPS_HFLAG_M16_SHIFT 10 | |
4ad40f36 FB |
985 | /* If translation is interrupted between the branch instruction and |
986 | * the delay slot, record what type of branch it is so that we can | |
987 | * resume translation properly. It might be possible to reduce | |
988 | * this from three bits to two. */ | |
339cd2a8 | 989 | #define MIPS_HFLAG_BMASK_BASE 0x803800 |
79ef2c4c NF |
990 | #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ |
991 | #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ | |
992 | #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ | |
993 | #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ | |
994 | /* Extra flags about the current pending branch. */ | |
b231c103 | 995 | #define MIPS_HFLAG_BMASK_EXT 0x7C000 |
79ef2c4c NF |
996 | #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ |
997 | #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ | |
998 | #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ | |
b231c103 YK |
999 | #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ |
1000 | #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ | |
79ef2c4c | 1001 | #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) |
853c3240 | 1002 | /* MIPS DSP resources access. */ |
908f6be1 SM |
1003 | #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ |
1004 | #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ | |
1005 | #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ | |
d279279e | 1006 | /* Extra flag about HWREna register. */ |
b231c103 | 1007 | #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ |
faf1f68b | 1008 | #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ |
339cd2a8 | 1009 | #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ |
e97a391d | 1010 | #define MIPS_HFLAG_MSA 0x1000000 |
7c979afd | 1011 | #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ |
e117f526 | 1012 | #define MIPS_HFLAG_ELPA 0x4000000 |
0d74a222 | 1013 | #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ |
42c86612 | 1014 | #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ |
6af0bf9c | 1015 | target_ulong btarget; /* Jump / branch target */ |
1ba74fb8 | 1016 | target_ulong bcond; /* Branch condition (if needed) */ |
a316d335 | 1017 | |
7a387fff TS |
1018 | int SYNCI_Step; /* Address step size for SYNCI */ |
1019 | int CCRes; /* Cycle count resolution/divisor */ | |
ead9360e TS |
1020 | uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ |
1021 | uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ | |
f9c9cd63 | 1022 | uint64_t insn_flags; /* Supported instruction set */ |
5fb2dcd1 | 1023 | int saarp; |
7a387fff | 1024 | |
1f5c00cf AB |
1025 | /* Fields up to this point are cleared by a CPU reset */ |
1026 | struct {} end_reset_fields; | |
1027 | ||
a316d335 | 1028 | CPU_COMMON |
6ae81775 | 1029 | |
f0c3c505 | 1030 | /* Fields from here on are preserved across CPU reset. */ |
51cc2e78 | 1031 | CPUMIPSMVPContext *mvp; |
3c7b48b7 | 1032 | #if !defined(CONFIG_USER_ONLY) |
51cc2e78 | 1033 | CPUMIPSTLBContext *tlb; |
3c7b48b7 | 1034 | #endif |
51cc2e78 | 1035 | |
c227f099 | 1036 | const mips_def_t *cpu_model; |
33ac7f16 | 1037 | void *irq[8]; |
1246b259 | 1038 | QEMUTimer *timer; /* Internal timer */ |
043715d1 | 1039 | struct MIPSITUState *itu; |
34fa7e83 | 1040 | MemoryRegion *itc_tag; /* ITC Configuration Tags */ |
89777fd1 | 1041 | target_ulong exception_base; /* ExceptionBase input to the core */ |
6af0bf9c FB |
1042 | }; |
1043 | ||
416bf936 PB |
1044 | /** |
1045 | * MIPSCPU: | |
1046 | * @env: #CPUMIPSState | |
1047 | * | |
1048 | * A MIPS CPU. | |
1049 | */ | |
1050 | struct MIPSCPU { | |
1051 | /*< private >*/ | |
1052 | CPUState parent_obj; | |
1053 | /*< public >*/ | |
1054 | ||
1055 | CPUMIPSState env; | |
1056 | }; | |
1057 | ||
1058 | static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) | |
1059 | { | |
1060 | return container_of(env, MIPSCPU, env); | |
1061 | } | |
1062 | ||
1063 | #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e)) | |
1064 | ||
1065 | #define ENV_OFFSET offsetof(MIPSCPU, env) | |
1066 | ||
9a78eead | 1067 | void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); |
647de6ca | 1068 | |
9467d44c | 1069 | #define cpu_signal_handler cpu_mips_signal_handler |
c732abe2 | 1070 | #define cpu_list mips_cpu_list |
9467d44c | 1071 | |
084d0497 RH |
1072 | extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); |
1073 | extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); | |
1074 | ||
623a930e TS |
1075 | /* MMU modes definitions. We carefully match the indices with our |
1076 | hflags layout. */ | |
6ebbf390 | 1077 | #define MMU_MODE0_SUFFIX _kernel |
623a930e TS |
1078 | #define MMU_MODE1_SUFFIX _super |
1079 | #define MMU_MODE2_SUFFIX _user | |
42c86612 | 1080 | #define MMU_MODE3_SUFFIX _error |
623a930e | 1081 | #define MMU_USER_IDX 2 |
b0fc6003 JH |
1082 | |
1083 | static inline int hflags_mmu_index(uint32_t hflags) | |
1084 | { | |
42c86612 JH |
1085 | if (hflags & MIPS_HFLAG_ERL) { |
1086 | return 3; /* ERL */ | |
1087 | } else { | |
1088 | return hflags & MIPS_HFLAG_KSU; | |
1089 | } | |
b0fc6003 JH |
1090 | } |
1091 | ||
97ed5ccd | 1092 | static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) |
6ebbf390 | 1093 | { |
b0fc6003 | 1094 | return hflags_mmu_index(env->hflags); |
6ebbf390 JM |
1095 | } |
1096 | ||
022c62cb | 1097 | #include "exec/cpu-all.h" |
6af0bf9c FB |
1098 | |
1099 | /* Memory access type : | |
1100 | * may be needed for precise access rights control and precise exceptions. | |
1101 | */ | |
1102 | enum { | |
1103 | /* 1 bit to define user level / supervisor access */ | |
1104 | ACCESS_USER = 0x00, | |
1105 | ACCESS_SUPER = 0x01, | |
1106 | /* 1 bit to indicate direction */ | |
1107 | ACCESS_STORE = 0x02, | |
1108 | /* Type of instruction that generated the access */ | |
1109 | ACCESS_CODE = 0x10, /* Code fetch access */ | |
1110 | ACCESS_INT = 0x20, /* Integer load/store access */ | |
1111 | ACCESS_FLOAT = 0x30, /* floating point load/store access */ | |
1112 | }; | |
1113 | ||
1114 | /* Exceptions */ | |
1115 | enum { | |
1116 | EXCP_NONE = -1, | |
1117 | EXCP_RESET = 0, | |
1118 | EXCP_SRESET, | |
1119 | EXCP_DSS, | |
1120 | EXCP_DINT, | |
14e51cc7 TS |
1121 | EXCP_DDBL, |
1122 | EXCP_DDBS, | |
6af0bf9c FB |
1123 | EXCP_NMI, |
1124 | EXCP_MCHECK, | |
14e51cc7 | 1125 | EXCP_EXT_INTERRUPT, /* 8 */ |
6af0bf9c | 1126 | EXCP_DFWATCH, |
14e51cc7 | 1127 | EXCP_DIB, |
6af0bf9c FB |
1128 | EXCP_IWATCH, |
1129 | EXCP_AdEL, | |
1130 | EXCP_AdES, | |
1131 | EXCP_TLBF, | |
1132 | EXCP_IBE, | |
14e51cc7 | 1133 | EXCP_DBp, /* 16 */ |
6af0bf9c | 1134 | EXCP_SYSCALL, |
14e51cc7 | 1135 | EXCP_BREAK, |
4ad40f36 | 1136 | EXCP_CpU, |
6af0bf9c FB |
1137 | EXCP_RI, |
1138 | EXCP_OVERFLOW, | |
1139 | EXCP_TRAP, | |
5a5012ec | 1140 | EXCP_FPE, |
14e51cc7 | 1141 | EXCP_DWATCH, /* 24 */ |
6af0bf9c FB |
1142 | EXCP_LTLBL, |
1143 | EXCP_TLBL, | |
1144 | EXCP_TLBS, | |
1145 | EXCP_DBE, | |
ead9360e | 1146 | EXCP_THREAD, |
14e51cc7 TS |
1147 | EXCP_MDMX, |
1148 | EXCP_C2E, | |
1149 | EXCP_CACHE, /* 32 */ | |
853c3240 | 1150 | EXCP_DSPDIS, |
e97a391d YK |
1151 | EXCP_MSADIS, |
1152 | EXCP_MSAFPE, | |
92ceb440 LA |
1153 | EXCP_TLBXI, |
1154 | EXCP_TLBRI, | |
14e51cc7 | 1155 | |
92ceb440 | 1156 | EXCP_LAST = EXCP_TLBRI, |
6af0bf9c | 1157 | }; |
590bc601 PB |
1158 | /* Dummy exception for conditional stores. */ |
1159 | #define EXCP_SC 0x100 | |
6af0bf9c | 1160 | |
f249412c | 1161 | /* |
26aa3d9a | 1162 | * This is an internally generated WAKE request line. |
f249412c EI |
1163 | * It is driven by the CPU itself. Raised when the MT |
1164 | * block wants to wake a VPE from an inactive state and | |
1165 | * cleared when VPE goes from active to inactive. | |
1166 | */ | |
1167 | #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 | |
1168 | ||
388bb21a | 1169 | int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); |
6af0bf9c | 1170 | |
a7519f2b IM |
1171 | #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU |
1172 | #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX | |
0dacec87 | 1173 | #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU |
a7519f2b IM |
1174 | |
1175 | bool cpu_supports_cps_smp(const char *cpu_type); | |
1176 | bool cpu_supports_isa(const char *cpu_type, unsigned int isa); | |
89777fd1 | 1177 | void cpu_set_exception_base(int vp_index, target_ulong address); |
30bf942d | 1178 | |
5dc5d9f0 | 1179 | /* mips_int.c */ |
7db13fae | 1180 | void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); |
5dc5d9f0 | 1181 | |
043715d1 YK |
1182 | /* mips_itu.c */ |
1183 | void itc_reconfigure(struct MIPSITUState *tag); | |
1184 | ||
f9480ffc | 1185 | /* helper.c */ |
1239b472 | 1186 | target_ulong exception_resume_pc (CPUMIPSState *env); |
f9480ffc | 1187 | |
599bc5e8 AM |
1188 | static inline void restore_snan_bit_mode(CPUMIPSState *env) |
1189 | { | |
1190 | set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, | |
1191 | &env->active_fpu.fp_status); | |
1192 | } | |
1193 | ||
7db13fae | 1194 | static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, |
89fee74a | 1195 | target_ulong *cs_base, uint32_t *flags) |
6b917547 AL |
1196 | { |
1197 | *pc = env->active_tc.PC; | |
1198 | *cs_base = 0; | |
d279279e PJ |
1199 | *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | |
1200 | MIPS_HFLAG_HWRENA_ULR); | |
6b917547 AL |
1201 | } |
1202 | ||
07f5a258 | 1203 | #endif /* MIPS_CPU_H */ |