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Commit | Line | Data |
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6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
c684822a | 19 | #include "qemu/osdep.h" |
e37e863f FB |
20 | |
21 | #include "cpu.h" | |
26aa3d9a | 22 | #include "internal.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
aea14095 | 24 | #include "exec/cpu_ldst.h" |
508127e2 | 25 | #include "exec/log.h" |
d3d93c6c | 26 | #include "hw/mips/cpudevs.h" |
535db744 | 27 | #include "qapi/qapi-commands-target.h" |
6af0bf9c | 28 | |
43057ab1 | 29 | enum { |
2fb58b73 LA |
30 | TLBRET_XI = -6, |
31 | TLBRET_RI = -5, | |
43057ab1 FB |
32 | TLBRET_DIRTY = -4, |
33 | TLBRET_INVALID = -3, | |
34 | TLBRET_NOMATCH = -2, | |
35 | TLBRET_BADADDR = -1, | |
36 | TLBRET_MATCH = 0 | |
37 | }; | |
38 | ||
3c7b48b7 PB |
39 | #if !defined(CONFIG_USER_ONLY) |
40 | ||
29929e34 | 41 | /* no MMU emulation */ |
a8170e5e | 42 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
6af0bf9c | 43 | target_ulong address, int rw, int access_type) |
29929e34 TS |
44 | { |
45 | *physical = address; | |
46 | *prot = PAGE_READ | PAGE_WRITE; | |
47 | return TLBRET_MATCH; | |
48 | } | |
49 | ||
50 | /* fixed mapping MMU emulation */ | |
a8170e5e | 51 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 TS |
52 | target_ulong address, int rw, int access_type) |
53 | { | |
54 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
55 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
56 | *physical = address + 0x40000000UL; | |
57 | else | |
58 | *physical = address; | |
59 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
60 | *physical = address & 0x1FFFFFFF; | |
61 | else | |
62 | *physical = address; | |
63 | ||
64 | *prot = PAGE_READ | PAGE_WRITE; | |
65 | return TLBRET_MATCH; | |
66 | } | |
67 | ||
68 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
a8170e5e | 69 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 70 | target_ulong address, int rw, int access_type) |
6af0bf9c | 71 | { |
2d72e7b0 | 72 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
3b1c8be4 | 73 | int i; |
6af0bf9c | 74 | |
ead9360e | 75 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
c227f099 | 76 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
3b1c8be4 | 77 | /* 1k pages are not supported. */ |
f2e9ebef | 78 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 79 | target_ulong tag = address & ~mask; |
f2e9ebef | 80 | target_ulong VPN = tlb->VPN & ~mask; |
d26bc211 | 81 | #if defined(TARGET_MIPS64) |
e034e2c3 | 82 | tag &= env->SEGMask; |
100ce988 | 83 | #endif |
3b1c8be4 | 84 | |
6af0bf9c | 85 | /* Check ASID, virtual page number & size */ |
9456c2fb | 86 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) { |
6af0bf9c | 87 | /* TLB match */ |
f2e9ebef | 88 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 89 | /* Check access rights */ |
2fb58b73 | 90 | if (!(n ? tlb->V1 : tlb->V0)) { |
43057ab1 | 91 | return TLBRET_INVALID; |
2fb58b73 LA |
92 | } |
93 | if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { | |
94 | return TLBRET_XI; | |
95 | } | |
96 | if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) { | |
97 | return TLBRET_RI; | |
98 | } | |
9f6bcedb | 99 | if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 100 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 101 | *prot = PAGE_READ; |
98c1b82b | 102 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 103 | *prot |= PAGE_WRITE; |
43057ab1 | 104 | return TLBRET_MATCH; |
6af0bf9c | 105 | } |
43057ab1 | 106 | return TLBRET_DIRTY; |
6af0bf9c FB |
107 | } |
108 | } | |
43057ab1 | 109 | return TLBRET_NOMATCH; |
6af0bf9c | 110 | } |
6af0bf9c | 111 | |
480e79ae JH |
112 | static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) |
113 | { | |
114 | /* | |
115 | * Interpret access control mode and mmu_idx. | |
116 | * AdE? TLB? | |
117 | * AM K S U E K S U E | |
118 | * UK 0 0 1 1 0 0 - - 0 | |
119 | * MK 1 0 1 1 0 1 - - !eu | |
120 | * MSK 2 0 0 1 0 1 1 - !eu | |
121 | * MUSK 3 0 0 0 0 1 1 1 !eu | |
122 | * MUSUK 4 0 0 0 0 0 1 1 0 | |
123 | * USK 5 0 0 1 0 0 0 - 0 | |
124 | * - 6 - - - - - - - - | |
125 | * UUSK 7 0 0 0 0 0 0 0 0 | |
126 | */ | |
127 | int32_t adetlb_mask; | |
128 | ||
129 | switch (mmu_idx) { | |
130 | case 3 /* ERL */: | |
131 | /* If EU is set, always unmapped */ | |
132 | if (eu) { | |
133 | return 0; | |
134 | } | |
135 | /* fall through */ | |
136 | case MIPS_HFLAG_KM: | |
137 | /* Never AdE, TLB mapped if AM={1,2,3} */ | |
138 | adetlb_mask = 0x70000000; | |
139 | goto check_tlb; | |
140 | ||
141 | case MIPS_HFLAG_SM: | |
142 | /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */ | |
143 | adetlb_mask = 0xc0380000; | |
144 | goto check_ade; | |
145 | ||
146 | case MIPS_HFLAG_UM: | |
147 | /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */ | |
148 | adetlb_mask = 0xe4180000; | |
149 | /* fall through */ | |
150 | check_ade: | |
151 | /* does this AM cause AdE in current execution mode */ | |
152 | if ((adetlb_mask << am) < 0) { | |
153 | return TLBRET_BADADDR; | |
154 | } | |
155 | adetlb_mask <<= 8; | |
156 | /* fall through */ | |
157 | check_tlb: | |
158 | /* is this AM mapped in current execution mode */ | |
159 | return ((adetlb_mask << am) < 0); | |
160 | default: | |
161 | assert(0); | |
162 | return TLBRET_BADADDR; | |
163 | }; | |
164 | } | |
165 | ||
166 | static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, | |
167 | int *prot, target_ulong real_address, | |
168 | int rw, int access_type, int mmu_idx, | |
169 | unsigned int am, bool eu, | |
170 | target_ulong segmask, | |
171 | hwaddr physical_base) | |
172 | { | |
173 | int mapped = is_seg_am_mapped(am, eu, mmu_idx); | |
174 | ||
175 | if (mapped < 0) { | |
176 | /* is_seg_am_mapped can report TLBRET_BADADDR */ | |
177 | return mapped; | |
178 | } else if (mapped) { | |
179 | /* The segment is TLB mapped */ | |
180 | return env->tlb->map_address(env, physical, prot, real_address, rw, | |
181 | access_type); | |
182 | } else { | |
183 | /* The segment is unmapped */ | |
184 | *physical = physical_base | (real_address & segmask); | |
185 | *prot = PAGE_READ | PAGE_WRITE; | |
186 | return TLBRET_MATCH; | |
187 | } | |
188 | } | |
189 | ||
190 | static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, | |
191 | int *prot, target_ulong real_address, | |
192 | int rw, int access_type, int mmu_idx, | |
193 | uint16_t segctl, target_ulong segmask) | |
194 | { | |
195 | unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM; | |
196 | bool eu = (segctl >> CP0SC_EU) & 1; | |
197 | hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20; | |
198 | ||
199 | return get_seg_physical_address(env, physical, prot, real_address, rw, | |
200 | access_type, mmu_idx, am, eu, segmask, | |
201 | pa & ~(hwaddr)segmask); | |
202 | } | |
203 | ||
a8170e5e | 204 | static int get_physical_address (CPUMIPSState *env, hwaddr *physical, |
4ef37e69 | 205 | int *prot, target_ulong real_address, |
9fbf4a58 | 206 | int rw, int access_type, int mmu_idx) |
6af0bf9c | 207 | { |
b4ab4b4e | 208 | /* User mode can only access useg/xuseg */ |
480e79ae | 209 | #if defined(TARGET_MIPS64) |
9fbf4a58 JH |
210 | int user_mode = mmu_idx == MIPS_HFLAG_UM; |
211 | int supervisor_mode = mmu_idx == MIPS_HFLAG_SM; | |
671880e6 | 212 | int kernel_mode = !user_mode && !supervisor_mode; |
b4ab4b4e TS |
213 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
214 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
215 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
216 | #endif | |
43057ab1 | 217 | int ret = TLBRET_MATCH; |
4ef37e69 JH |
218 | /* effective address (modified for KVM T&E kernel segments) */ |
219 | target_ulong address = real_address; | |
43057ab1 | 220 | |
67433345 JH |
221 | #define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) |
222 | #define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) | |
223 | #define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) | |
224 | #define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) | |
225 | #define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) | |
22010ce7 | 226 | |
67433345 JH |
227 | #define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) |
228 | #define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) | |
4ef37e69 | 229 | |
d3d93c6c | 230 | if (mips_um_ksegs_enabled()) { |
4ef37e69 JH |
231 | /* KVM T&E adds guest kernel segments in useg */ |
232 | if (real_address >= KVM_KSEG0_BASE) { | |
233 | if (real_address < KVM_KSEG2_BASE) { | |
234 | /* kseg0 */ | |
235 | address += KSEG0_BASE - KVM_KSEG0_BASE; | |
236 | } else if (real_address <= USEG_LIMIT) { | |
237 | /* kseg2/3 */ | |
238 | address += KSEG2_BASE - KVM_KSEG2_BASE; | |
239 | } | |
240 | } | |
241 | } | |
242 | ||
22010ce7 | 243 | if (address <= USEG_LIMIT) { |
b4ab4b4e | 244 | /* useg */ |
480e79ae JH |
245 | uint16_t segctl; |
246 | ||
247 | if (address >= 0x40000000UL) { | |
248 | segctl = env->CP0_SegCtl2; | |
996ba2cc | 249 | } else { |
480e79ae | 250 | segctl = env->CP0_SegCtl2 >> 16; |
6af0bf9c | 251 | } |
480e79ae JH |
252 | ret = get_segctl_physical_address(env, physical, prot, real_address, rw, |
253 | access_type, mmu_idx, segctl, | |
254 | 0x3FFFFFFF); | |
d26bc211 | 255 | #if defined(TARGET_MIPS64) |
89fc88da | 256 | } else if (address < 0x4000000000000000ULL) { |
b4ab4b4e | 257 | /* xuseg */ |
6958549d | 258 | if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
4ef37e69 | 259 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
260 | } else { |
261 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 262 | } |
89fc88da | 263 | } else if (address < 0x8000000000000000ULL) { |
b4ab4b4e | 264 | /* xsseg */ |
6958549d AJ |
265 | if ((supervisor_mode || kernel_mode) && |
266 | SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 267 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
268 | } else { |
269 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 270 | } |
89fc88da | 271 | } else if (address < 0xC000000000000000ULL) { |
b4ab4b4e | 272 | /* xkphys */ |
480e79ae JH |
273 | if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { |
274 | /* KX/SX/UX bit to check for each xkphys EVA access mode */ | |
275 | static const uint8_t am_ksux[8] = { | |
276 | [CP0SC_AM_UK] = (1u << CP0St_KX), | |
277 | [CP0SC_AM_MK] = (1u << CP0St_KX), | |
278 | [CP0SC_AM_MSK] = (1u << CP0St_SX), | |
279 | [CP0SC_AM_MUSK] = (1u << CP0St_UX), | |
280 | [CP0SC_AM_MUSUK] = (1u << CP0St_UX), | |
281 | [CP0SC_AM_USK] = (1u << CP0St_SX), | |
282 | [6] = (1u << CP0St_KX), | |
283 | [CP0SC_AM_UUSK] = (1u << CP0St_UX), | |
284 | }; | |
285 | unsigned int am = CP0SC_AM_UK; | |
286 | unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR; | |
287 | ||
288 | if (xr & (1 << ((address >> 59) & 0x7))) { | |
289 | am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; | |
290 | } | |
291 | /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ | |
292 | if (env->CP0_Status & am_ksux[am]) { | |
293 | ret = get_seg_physical_address(env, physical, prot, | |
294 | real_address, rw, access_type, | |
295 | mmu_idx, am, false, env->PAMask, | |
296 | 0); | |
297 | } else { | |
298 | ret = TLBRET_BADADDR; | |
299 | } | |
6958549d AJ |
300 | } else { |
301 | ret = TLBRET_BADADDR; | |
302 | } | |
89fc88da | 303 | } else if (address < 0xFFFFFFFF80000000ULL) { |
b4ab4b4e | 304 | /* xkseg */ |
6958549d AJ |
305 | if (kernel_mode && KX && |
306 | address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 307 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
308 | } else { |
309 | ret = TLBRET_BADADDR; | |
310 | } | |
b4ab4b4e | 311 | #endif |
67433345 | 312 | } else if (address < KSEG1_BASE) { |
6af0bf9c | 313 | /* kseg0 */ |
480e79ae JH |
314 | ret = get_segctl_physical_address(env, physical, prot, real_address, rw, |
315 | access_type, mmu_idx, | |
316 | env->CP0_SegCtl1 >> 16, 0x1FFFFFFF); | |
67433345 | 317 | } else if (address < KSEG2_BASE) { |
6af0bf9c | 318 | /* kseg1 */ |
480e79ae JH |
319 | ret = get_segctl_physical_address(env, physical, prot, real_address, rw, |
320 | access_type, mmu_idx, | |
321 | env->CP0_SegCtl1, 0x1FFFFFFF); | |
67433345 | 322 | } else if (address < KSEG3_BASE) { |
89fc88da | 323 | /* sseg (kseg2) */ |
480e79ae JH |
324 | ret = get_segctl_physical_address(env, physical, prot, real_address, rw, |
325 | access_type, mmu_idx, | |
326 | env->CP0_SegCtl0 >> 16, 0x1FFFFFFF); | |
6af0bf9c FB |
327 | } else { |
328 | /* kseg3 */ | |
6af0bf9c | 329 | /* XXX: debug segment is not emulated */ |
480e79ae JH |
330 | ret = get_segctl_physical_address(env, physical, prot, real_address, rw, |
331 | access_type, mmu_idx, | |
332 | env->CP0_SegCtl0, 0x1FFFFFFF); | |
6af0bf9c | 333 | } |
6af0bf9c FB |
334 | return ret; |
335 | } | |
e6623d88 | 336 | |
d10eb08f | 337 | void cpu_mips_tlb_flush(CPUMIPSState *env) |
e6623d88 PB |
338 | { |
339 | MIPSCPU *cpu = mips_env_get_cpu(env); | |
340 | ||
341 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
d10eb08f | 342 | tlb_flush(CPU(cpu)); |
e6623d88 PB |
343 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
344 | } | |
345 | ||
346 | /* Called for updates to CP0_Status. */ | |
347 | void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) | |
348 | { | |
349 | int32_t tcstatus, *tcst; | |
350 | uint32_t v = cpu->CP0_Status; | |
351 | uint32_t cu, mx, asid, ksu; | |
352 | uint32_t mask = ((1 << CP0TCSt_TCU3) | |
353 | | (1 << CP0TCSt_TCU2) | |
354 | | (1 << CP0TCSt_TCU1) | |
355 | | (1 << CP0TCSt_TCU0) | |
356 | | (1 << CP0TCSt_TMX) | |
357 | | (3 << CP0TCSt_TKSU) | |
358 | | (0xff << CP0TCSt_TASID)); | |
359 | ||
360 | cu = (v >> CP0St_CU0) & 0xf; | |
361 | mx = (v >> CP0St_MX) & 0x1; | |
362 | ksu = (v >> CP0St_KSU) & 0x3; | |
6ec98bd7 | 363 | asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
e6623d88 PB |
364 | |
365 | tcstatus = cu << CP0TCSt_TCU0; | |
366 | tcstatus |= mx << CP0TCSt_TMX; | |
367 | tcstatus |= ksu << CP0TCSt_TKSU; | |
368 | tcstatus |= asid; | |
369 | ||
370 | if (tc == cpu->current_tc) { | |
371 | tcst = &cpu->active_tc.CP0_TCStatus; | |
372 | } else { | |
373 | tcst = &cpu->tcs[tc].CP0_TCStatus; | |
374 | } | |
375 | ||
376 | *tcst &= ~mask; | |
377 | *tcst |= tcstatus; | |
378 | compute_hflags(cpu); | |
379 | } | |
380 | ||
381 | void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) | |
382 | { | |
383 | uint32_t mask = env->CP0_Status_rw_bitmask; | |
384 | target_ulong old = env->CP0_Status; | |
385 | ||
386 | if (env->insn_flags & ISA_MIPS32R6) { | |
387 | bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; | |
388 | #if defined(TARGET_MIPS64) | |
389 | uint32_t ksux = (1 << CP0St_KX) & val; | |
390 | ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ | |
391 | ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ | |
392 | val = (val & ~(7 << CP0St_UX)) | ksux; | |
393 | #endif | |
394 | if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { | |
395 | mask &= ~(3 << CP0St_KSU); | |
396 | } | |
397 | mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); | |
398 | } | |
399 | ||
400 | env->CP0_Status = (old & ~mask) | (val & mask); | |
401 | #if defined(TARGET_MIPS64) | |
402 | if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { | |
403 | /* Access to at least one of the 64-bit segments has been disabled */ | |
9658e4c3 | 404 | tlb_flush(CPU(mips_env_get_cpu(env))); |
e6623d88 PB |
405 | } |
406 | #endif | |
407 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { | |
408 | sync_c0_status(env, env, env->current_tc); | |
409 | } else { | |
410 | compute_hflags(env); | |
411 | } | |
412 | } | |
413 | ||
414 | void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) | |
415 | { | |
416 | uint32_t mask = 0x00C00300; | |
417 | uint32_t old = env->CP0_Cause; | |
418 | int i; | |
419 | ||
420 | if (env->insn_flags & ISA_MIPS32R2) { | |
421 | mask |= 1 << CP0Ca_DC; | |
422 | } | |
423 | if (env->insn_flags & ISA_MIPS32R6) { | |
424 | mask &= ~((1 << CP0Ca_WP) & val); | |
425 | } | |
426 | ||
427 | env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); | |
428 | ||
429 | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { | |
430 | if (env->CP0_Cause & (1 << CP0Ca_DC)) { | |
431 | cpu_mips_stop_count(env); | |
432 | } else { | |
433 | cpu_mips_start_count(env); | |
434 | } | |
435 | } | |
436 | ||
437 | /* Set/reset software interrupts */ | |
438 | for (i = 0 ; i < 2 ; i++) { | |
439 | if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { | |
440 | cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); | |
441 | } | |
442 | } | |
443 | } | |
932e71cd | 444 | #endif |
6af0bf9c | 445 | |
7db13fae | 446 | static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, |
1147e189 AJ |
447 | int rw, int tlb_error) |
448 | { | |
27103424 | 449 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
1147e189 AJ |
450 | int exception = 0, error_code = 0; |
451 | ||
aea14095 LA |
452 | if (rw == MMU_INST_FETCH) { |
453 | error_code |= EXCP_INST_NOTAVAIL; | |
454 | } | |
455 | ||
1147e189 AJ |
456 | switch (tlb_error) { |
457 | default: | |
458 | case TLBRET_BADADDR: | |
459 | /* Reference to kernel address from user mode or supervisor mode */ | |
460 | /* Reference to supervisor address from user mode */ | |
9f6bcedb | 461 | if (rw == MMU_DATA_STORE) { |
1147e189 | 462 | exception = EXCP_AdES; |
9f6bcedb | 463 | } else { |
1147e189 | 464 | exception = EXCP_AdEL; |
9f6bcedb | 465 | } |
1147e189 AJ |
466 | break; |
467 | case TLBRET_NOMATCH: | |
468 | /* No TLB match for a mapped address */ | |
9f6bcedb | 469 | if (rw == MMU_DATA_STORE) { |
1147e189 | 470 | exception = EXCP_TLBS; |
9f6bcedb | 471 | } else { |
1147e189 | 472 | exception = EXCP_TLBL; |
9f6bcedb | 473 | } |
aea14095 | 474 | error_code |= EXCP_TLB_NOMATCH; |
1147e189 AJ |
475 | break; |
476 | case TLBRET_INVALID: | |
477 | /* TLB match with no valid bit */ | |
9f6bcedb | 478 | if (rw == MMU_DATA_STORE) { |
1147e189 | 479 | exception = EXCP_TLBS; |
9f6bcedb | 480 | } else { |
1147e189 | 481 | exception = EXCP_TLBL; |
9f6bcedb | 482 | } |
1147e189 AJ |
483 | break; |
484 | case TLBRET_DIRTY: | |
485 | /* TLB match but 'D' bit is cleared */ | |
486 | exception = EXCP_LTLBL; | |
487 | break; | |
92ceb440 LA |
488 | case TLBRET_XI: |
489 | /* Execute-Inhibit Exception */ | |
490 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
491 | exception = EXCP_TLBXI; | |
492 | } else { | |
493 | exception = EXCP_TLBL; | |
494 | } | |
495 | break; | |
496 | case TLBRET_RI: | |
497 | /* Read-Inhibit Exception */ | |
498 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
499 | exception = EXCP_TLBRI; | |
500 | } else { | |
501 | exception = EXCP_TLBL; | |
502 | } | |
503 | break; | |
1147e189 AJ |
504 | } |
505 | /* Raise exception */ | |
e807bcc1 YK |
506 | if (!(env->hflags & MIPS_HFLAG_DM)) { |
507 | env->CP0_BadVAddr = address; | |
508 | } | |
1147e189 AJ |
509 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | |
510 | ((address >> 9) & 0x007ffff0); | |
6ec98bd7 | 511 | env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | |
701074a6 | 512 | (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) | |
6ec98bd7 | 513 | (address & (TARGET_PAGE_MASK << 1)); |
1147e189 AJ |
514 | #if defined(TARGET_MIPS64) |
515 | env->CP0_EntryHi &= env->SEGMask; | |
60270f85 YK |
516 | env->CP0_XContext = |
517 | /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
518 | /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | | |
519 | /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); | |
1147e189 | 520 | #endif |
27103424 | 521 | cs->exception_index = exception; |
1147e189 AJ |
522 | env->error_code = error_code; |
523 | } | |
524 | ||
4fcc562b | 525 | #if !defined(CONFIG_USER_ONLY) |
00b941e5 | 526 | hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
6af0bf9c | 527 | { |
00b941e5 | 528 | MIPSCPU *cpu = MIPS_CPU(cs); |
9fbf4a58 | 529 | CPUMIPSState *env = &cpu->env; |
a8170e5e | 530 | hwaddr phys_addr; |
932e71cd | 531 | int prot; |
6af0bf9c | 532 | |
9fbf4a58 JH |
533 | if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT, |
534 | cpu_mmu_index(env, false)) != 0) { | |
932e71cd | 535 | return -1; |
00b941e5 | 536 | } |
932e71cd | 537 | return phys_addr; |
6af0bf9c | 538 | } |
4fcc562b | 539 | #endif |
6af0bf9c | 540 | |
074cfcb4 YK |
541 | #if !defined(CONFIG_USER_ONLY) |
542 | #if !defined(TARGET_MIPS64) | |
543 | ||
544 | /* | |
545 | * Perform hardware page table walk | |
546 | * | |
547 | * Memory accesses are performed using the KERNEL privilege level. | |
548 | * Synchronous exceptions detected on memory accesses cause a silent exit | |
549 | * from page table walking, resulting in a TLB or XTLB Refill exception. | |
550 | * | |
551 | * Implementations are not required to support page table walk memory | |
552 | * accesses from mapped memory regions. When an unsupported access is | |
553 | * attempted, a silent exit is taken, resulting in a TLB or XTLB Refill | |
554 | * exception. | |
555 | * | |
556 | * Note that if an exception is caused by AddressTranslation or LoadMemory | |
557 | * functions, the exception is not taken, a silent exit is taken, | |
558 | * resulting in a TLB or XTLB Refill exception. | |
559 | */ | |
560 | ||
561 | static bool get_pte(CPUMIPSState *env, uint64_t vaddr, int entry_size, | |
562 | uint64_t *pte) | |
563 | { | |
564 | if ((vaddr & ((entry_size >> 3) - 1)) != 0) { | |
565 | return false; | |
566 | } | |
567 | if (entry_size == 64) { | |
568 | *pte = cpu_ldq_code(env, vaddr); | |
569 | } else { | |
570 | *pte = cpu_ldl_code(env, vaddr); | |
571 | } | |
572 | return true; | |
573 | } | |
574 | ||
575 | static uint64_t get_tlb_entry_layout(CPUMIPSState *env, uint64_t entry, | |
576 | int entry_size, int ptei) | |
577 | { | |
578 | uint64_t result = entry; | |
579 | uint64_t rixi; | |
580 | if (ptei > entry_size) { | |
581 | ptei -= 32; | |
582 | } | |
583 | result >>= (ptei - 2); | |
584 | rixi = result & 3; | |
585 | result >>= 2; | |
586 | result |= rixi << CP0EnLo_XI; | |
587 | return result; | |
588 | } | |
589 | ||
590 | static int walk_directory(CPUMIPSState *env, uint64_t *vaddr, | |
591 | int directory_index, bool *huge_page, bool *hgpg_directory_hit, | |
592 | uint64_t *pw_entrylo0, uint64_t *pw_entrylo1) | |
593 | { | |
594 | int dph = (env->CP0_PWCtl >> CP0PC_DPH) & 0x1; | |
595 | int psn = (env->CP0_PWCtl >> CP0PC_PSN) & 0x3F; | |
596 | int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; | |
597 | int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; | |
598 | int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F; | |
599 | int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3; | |
600 | int directory_shift = (ptew > 1) ? -1 : | |
601 | (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift; | |
602 | int leaf_shift = (ptew > 1) ? -1 : | |
603 | (ptew == 1) ? native_shift + 1 : native_shift; | |
604 | uint32_t direntry_size = 1 << (directory_shift + 3); | |
605 | uint32_t leafentry_size = 1 << (leaf_shift + 3); | |
606 | uint64_t entry; | |
607 | uint64_t paddr; | |
608 | int prot; | |
609 | uint64_t lsb = 0; | |
610 | uint64_t w = 0; | |
611 | ||
612 | if (get_physical_address(env, &paddr, &prot, *vaddr, MMU_DATA_LOAD, | |
613 | ACCESS_INT, cpu_mmu_index(env, false)) != | |
614 | TLBRET_MATCH) { | |
615 | /* wrong base address */ | |
616 | return 0; | |
617 | } | |
618 | if (!get_pte(env, *vaddr, direntry_size, &entry)) { | |
619 | return 0; | |
620 | } | |
621 | ||
622 | if ((entry & (1 << psn)) && hugepg) { | |
623 | *huge_page = true; | |
624 | *hgpg_directory_hit = true; | |
625 | entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew); | |
626 | w = directory_index - 1; | |
627 | if (directory_index & 0x1) { | |
628 | /* Generate adjacent page from same PTE for odd TLB page */ | |
629 | lsb = (1 << w) >> 6; | |
630 | *pw_entrylo0 = entry & ~lsb; /* even page */ | |
631 | *pw_entrylo1 = entry | lsb; /* odd page */ | |
632 | } else if (dph) { | |
633 | int oddpagebit = 1 << leaf_shift; | |
634 | uint64_t vaddr2 = *vaddr ^ oddpagebit; | |
635 | if (*vaddr & oddpagebit) { | |
636 | *pw_entrylo1 = entry; | |
637 | } else { | |
638 | *pw_entrylo0 = entry; | |
639 | } | |
640 | if (get_physical_address(env, &paddr, &prot, vaddr2, MMU_DATA_LOAD, | |
641 | ACCESS_INT, cpu_mmu_index(env, false)) != | |
642 | TLBRET_MATCH) { | |
643 | return 0; | |
644 | } | |
645 | if (!get_pte(env, vaddr2, leafentry_size, &entry)) { | |
646 | return 0; | |
647 | } | |
648 | entry = get_tlb_entry_layout(env, entry, leafentry_size, pf_ptew); | |
649 | if (*vaddr & oddpagebit) { | |
650 | *pw_entrylo0 = entry; | |
651 | } else { | |
652 | *pw_entrylo1 = entry; | |
653 | } | |
654 | } else { | |
655 | return 0; | |
656 | } | |
657 | return 1; | |
658 | } else { | |
659 | *vaddr = entry; | |
660 | return 2; | |
661 | } | |
662 | } | |
663 | ||
664 | static bool page_table_walk_refill(CPUMIPSState *env, vaddr address, int rw, | |
665 | int mmu_idx) | |
666 | { | |
667 | int gdw = (env->CP0_PWSize >> CP0PS_GDW) & 0x3F; | |
668 | int udw = (env->CP0_PWSize >> CP0PS_UDW) & 0x3F; | |
669 | int mdw = (env->CP0_PWSize >> CP0PS_MDW) & 0x3F; | |
670 | int ptw = (env->CP0_PWSize >> CP0PS_PTW) & 0x3F; | |
671 | int ptew = (env->CP0_PWSize >> CP0PS_PTEW) & 0x3F; | |
672 | ||
673 | /* Initial values */ | |
674 | bool huge_page = false; | |
675 | bool hgpg_bdhit = false; | |
676 | bool hgpg_gdhit = false; | |
677 | bool hgpg_udhit = false; | |
678 | bool hgpg_mdhit = false; | |
679 | ||
680 | int32_t pw_pagemask = 0; | |
681 | target_ulong pw_entryhi = 0; | |
682 | uint64_t pw_entrylo0 = 0; | |
683 | uint64_t pw_entrylo1 = 0; | |
684 | ||
685 | /* Native pointer size */ | |
686 | /*For the 32-bit architectures, this bit is fixed to 0.*/ | |
687 | int native_shift = (((env->CP0_PWSize >> CP0PS_PS) & 1) == 0) ? 2 : 3; | |
688 | ||
689 | /* Indices from PWField */ | |
690 | int pf_gdw = (env->CP0_PWField >> CP0PF_GDW) & 0x3F; | |
691 | int pf_udw = (env->CP0_PWField >> CP0PF_UDW) & 0x3F; | |
692 | int pf_mdw = (env->CP0_PWField >> CP0PF_MDW) & 0x3F; | |
693 | int pf_ptw = (env->CP0_PWField >> CP0PF_PTW) & 0x3F; | |
694 | int pf_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; | |
695 | ||
696 | /* Indices computed from faulting address */ | |
697 | int gindex = (address >> pf_gdw) & ((1 << gdw) - 1); | |
698 | int uindex = (address >> pf_udw) & ((1 << udw) - 1); | |
699 | int mindex = (address >> pf_mdw) & ((1 << mdw) - 1); | |
700 | int ptindex = (address >> pf_ptw) & ((1 << ptw) - 1); | |
701 | ||
702 | /* Other HTW configs */ | |
703 | int hugepg = (env->CP0_PWCtl >> CP0PC_HUGEPG) & 0x1; | |
704 | ||
705 | /* HTW Shift values (depend on entry size) */ | |
706 | int directory_shift = (ptew > 1) ? -1 : | |
707 | (hugepg && (ptew == 1)) ? native_shift + 1 : native_shift; | |
708 | int leaf_shift = (ptew > 1) ? -1 : | |
709 | (ptew == 1) ? native_shift + 1 : native_shift; | |
710 | ||
711 | /* Offsets into tables */ | |
712 | int goffset = gindex << directory_shift; | |
713 | int uoffset = uindex << directory_shift; | |
714 | int moffset = mindex << directory_shift; | |
715 | int ptoffset0 = (ptindex >> 1) << (leaf_shift + 1); | |
716 | int ptoffset1 = ptoffset0 | (1 << (leaf_shift)); | |
717 | ||
718 | uint32_t leafentry_size = 1 << (leaf_shift + 3); | |
719 | ||
720 | /* Starting address - Page Table Base */ | |
721 | uint64_t vaddr = env->CP0_PWBase; | |
722 | ||
723 | uint64_t dir_entry; | |
724 | uint64_t paddr; | |
725 | int prot; | |
726 | int m; | |
727 | ||
728 | if (!(env->CP0_Config3 & (1 << CP0C3_PW))) { | |
729 | /* walker is unimplemented */ | |
730 | return false; | |
731 | } | |
732 | if (!(env->CP0_PWCtl & (1 << CP0PC_PWEN))) { | |
733 | /* walker is disabled */ | |
734 | return false; | |
735 | } | |
736 | if (!(gdw > 0 || udw > 0 || mdw > 0)) { | |
737 | /* no structure to walk */ | |
738 | return false; | |
739 | } | |
740 | if ((directory_shift == -1) || (leaf_shift == -1)) { | |
741 | return false; | |
742 | } | |
743 | ||
744 | /* Global Directory */ | |
745 | if (gdw > 0) { | |
746 | vaddr |= goffset; | |
747 | switch (walk_directory(env, &vaddr, pf_gdw, &huge_page, &hgpg_gdhit, | |
748 | &pw_entrylo0, &pw_entrylo1)) | |
749 | { | |
750 | case 0: | |
751 | return false; | |
752 | case 1: | |
753 | goto refill; | |
754 | case 2: | |
755 | default: | |
756 | break; | |
757 | } | |
758 | } | |
759 | ||
760 | /* Upper directory */ | |
761 | if (udw > 0) { | |
762 | vaddr |= uoffset; | |
763 | switch (walk_directory(env, &vaddr, pf_udw, &huge_page, &hgpg_udhit, | |
764 | &pw_entrylo0, &pw_entrylo1)) | |
765 | { | |
766 | case 0: | |
767 | return false; | |
768 | case 1: | |
769 | goto refill; | |
770 | case 2: | |
771 | default: | |
772 | break; | |
773 | } | |
774 | } | |
775 | ||
776 | /* Middle directory */ | |
777 | if (mdw > 0) { | |
778 | vaddr |= moffset; | |
779 | switch (walk_directory(env, &vaddr, pf_mdw, &huge_page, &hgpg_mdhit, | |
780 | &pw_entrylo0, &pw_entrylo1)) | |
781 | { | |
782 | case 0: | |
783 | return false; | |
784 | case 1: | |
785 | goto refill; | |
786 | case 2: | |
787 | default: | |
788 | break; | |
789 | } | |
790 | } | |
791 | ||
792 | /* Leaf Level Page Table - First half of PTE pair */ | |
793 | vaddr |= ptoffset0; | |
794 | if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, | |
795 | ACCESS_INT, cpu_mmu_index(env, false)) != | |
796 | TLBRET_MATCH) { | |
797 | return false; | |
798 | } | |
799 | if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { | |
800 | return false; | |
801 | } | |
802 | dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew); | |
803 | pw_entrylo0 = dir_entry; | |
804 | ||
805 | /* Leaf Level Page Table - Second half of PTE pair */ | |
806 | vaddr |= ptoffset1; | |
807 | if (get_physical_address(env, &paddr, &prot, vaddr, MMU_DATA_LOAD, | |
808 | ACCESS_INT, cpu_mmu_index(env, false)) != | |
809 | TLBRET_MATCH) { | |
810 | return false; | |
811 | } | |
812 | if (!get_pte(env, vaddr, leafentry_size, &dir_entry)) { | |
813 | return false; | |
814 | } | |
815 | dir_entry = get_tlb_entry_layout(env, dir_entry, leafentry_size, pf_ptew); | |
816 | pw_entrylo1 = dir_entry; | |
817 | ||
818 | refill: | |
819 | ||
820 | m = (1 << pf_ptw) - 1; | |
821 | ||
822 | if (huge_page) { | |
823 | switch (hgpg_bdhit << 3 | hgpg_gdhit << 2 | hgpg_udhit << 1 | | |
824 | hgpg_mdhit) | |
825 | { | |
826 | case 4: | |
827 | m = (1 << pf_gdw) - 1; | |
828 | if (pf_gdw & 1) { | |
829 | m >>= 1; | |
830 | } | |
831 | break; | |
832 | case 2: | |
833 | m = (1 << pf_udw) - 1; | |
834 | if (pf_udw & 1) { | |
835 | m >>= 1; | |
836 | } | |
837 | break; | |
838 | case 1: | |
839 | m = (1 << pf_mdw) - 1; | |
840 | if (pf_mdw & 1) { | |
841 | m >>= 1; | |
842 | } | |
843 | break; | |
844 | } | |
845 | } | |
846 | pw_pagemask = m >> 12; | |
847 | update_pagemask(env, pw_pagemask << 13, &pw_pagemask); | |
848 | pw_entryhi = (address & ~0x1fff) | (env->CP0_EntryHi & 0xFF); | |
849 | { | |
850 | target_ulong tmp_entryhi = env->CP0_EntryHi; | |
851 | int32_t tmp_pagemask = env->CP0_PageMask; | |
852 | uint64_t tmp_entrylo0 = env->CP0_EntryLo0; | |
853 | uint64_t tmp_entrylo1 = env->CP0_EntryLo1; | |
854 | ||
855 | env->CP0_EntryHi = pw_entryhi; | |
856 | env->CP0_PageMask = pw_pagemask; | |
857 | env->CP0_EntryLo0 = pw_entrylo0; | |
858 | env->CP0_EntryLo1 = pw_entrylo1; | |
859 | ||
860 | /* | |
861 | * The hardware page walker inserts a page into the TLB in a manner | |
862 | * identical to a TLBWR instruction as executed by the software refill | |
863 | * handler. | |
864 | */ | |
865 | r4k_helper_tlbwr(env); | |
866 | ||
867 | env->CP0_EntryHi = tmp_entryhi; | |
868 | env->CP0_PageMask = tmp_pagemask; | |
869 | env->CP0_EntryLo0 = tmp_entrylo0; | |
870 | env->CP0_EntryLo1 = tmp_entrylo1; | |
871 | } | |
872 | return true; | |
873 | } | |
874 | #endif | |
875 | #endif | |
876 | ||
98670d47 | 877 | int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, |
7510454e | 878 | int mmu_idx) |
6af0bf9c | 879 | { |
7510454e AF |
880 | MIPSCPU *cpu = MIPS_CPU(cs); |
881 | CPUMIPSState *env = &cpu->env; | |
932e71cd | 882 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 883 | hwaddr physical; |
6af0bf9c | 884 | int prot; |
6af0bf9c | 885 | int access_type; |
99e43d36 | 886 | #endif |
6af0bf9c FB |
887 | int ret = 0; |
888 | ||
4ad40f36 | 889 | #if 0 |
7510454e | 890 | log_cpu_state(cs, 0); |
4ad40f36 | 891 | #endif |
339aaf5b AP |
892 | qemu_log_mask(CPU_LOG_MMU, |
893 | "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", | |
97b348e7 | 894 | __func__, env->active_tc.PC, address, rw, mmu_idx); |
4ad40f36 | 895 | |
6af0bf9c | 896 | /* data access */ |
99e43d36 | 897 | #if !defined(CONFIG_USER_ONLY) |
074cfcb4 | 898 | /* XXX: put correct access by using cpu_restore_state() correctly */ |
6af0bf9c | 899 | access_type = ACCESS_INT; |
6af0bf9c | 900 | ret = get_physical_address(env, &physical, &prot, |
9fbf4a58 | 901 | address, rw, access_type, mmu_idx); |
def74c0c PMD |
902 | switch (ret) { |
903 | case TLBRET_MATCH: | |
904 | qemu_log_mask(CPU_LOG_MMU, | |
905 | "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx | |
906 | " prot %d\n", __func__, address, physical, prot); | |
907 | break; | |
908 | default: | |
909 | qemu_log_mask(CPU_LOG_MMU, | |
910 | "%s address=%" VADDR_PRIx " ret %d\n", __func__, address, | |
911 | ret); | |
912 | break; | |
913 | } | |
43057ab1 | 914 | if (ret == TLBRET_MATCH) { |
0c591eb0 | 915 | tlb_set_page(cs, address & TARGET_PAGE_MASK, |
99e43d36 AJ |
916 | physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, |
917 | mmu_idx, TARGET_PAGE_SIZE); | |
918 | ret = 0; | |
932e71cd AJ |
919 | } else if (ret < 0) |
920 | #endif | |
921 | { | |
074cfcb4 YK |
922 | #if !defined(CONFIG_USER_ONLY) |
923 | #if !defined(TARGET_MIPS64) | |
924 | if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { | |
925 | /* | |
926 | * Memory reads during hardware page table walking are performed | |
927 | * as if they were kernel-mode load instructions. | |
928 | */ | |
929 | int mode = (env->hflags & MIPS_HFLAG_KSU); | |
930 | bool ret_walker; | |
931 | env->hflags &= ~MIPS_HFLAG_KSU; | |
932 | ret_walker = page_table_walk_refill(env, address, rw, mmu_idx); | |
933 | env->hflags |= mode; | |
934 | if (ret_walker) { | |
935 | ret = get_physical_address(env, &physical, &prot, | |
936 | address, rw, access_type, mmu_idx); | |
937 | if (ret == TLBRET_MATCH) { | |
938 | tlb_set_page(cs, address & TARGET_PAGE_MASK, | |
939 | physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, | |
940 | mmu_idx, TARGET_PAGE_SIZE); | |
941 | ret = 0; | |
942 | return ret; | |
943 | } | |
944 | } | |
945 | } | |
946 | #endif | |
947 | #endif | |
1147e189 | 948 | raise_mmu_exception(env, address, rw, ret); |
6af0bf9c FB |
949 | ret = 1; |
950 | } | |
951 | ||
952 | return ret; | |
953 | } | |
954 | ||
25b91e32 | 955 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 956 | hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) |
25b91e32 | 957 | { |
a8170e5e | 958 | hwaddr physical; |
25b91e32 AJ |
959 | int prot; |
960 | int access_type; | |
961 | int ret = 0; | |
962 | ||
25b91e32 AJ |
963 | /* data access */ |
964 | access_type = ACCESS_INT; | |
9fbf4a58 JH |
965 | ret = get_physical_address(env, &physical, &prot, address, rw, access_type, |
966 | cpu_mmu_index(env, false)); | |
25b91e32 AJ |
967 | if (ret != TLBRET_MATCH) { |
968 | raise_mmu_exception(env, address, rw, ret); | |
c36bbb28 AJ |
969 | return -1LL; |
970 | } else { | |
971 | return physical; | |
25b91e32 | 972 | } |
25b91e32 | 973 | } |
25b91e32 | 974 | |
9a5d878f TS |
975 | static const char * const excp_names[EXCP_LAST + 1] = { |
976 | [EXCP_RESET] = "reset", | |
977 | [EXCP_SRESET] = "soft reset", | |
978 | [EXCP_DSS] = "debug single step", | |
979 | [EXCP_DINT] = "debug interrupt", | |
980 | [EXCP_NMI] = "non-maskable interrupt", | |
981 | [EXCP_MCHECK] = "machine check", | |
982 | [EXCP_EXT_INTERRUPT] = "interrupt", | |
983 | [EXCP_DFWATCH] = "deferred watchpoint", | |
984 | [EXCP_DIB] = "debug instruction breakpoint", | |
985 | [EXCP_IWATCH] = "instruction fetch watchpoint", | |
986 | [EXCP_AdEL] = "address error load", | |
987 | [EXCP_AdES] = "address error store", | |
988 | [EXCP_TLBF] = "TLB refill", | |
989 | [EXCP_IBE] = "instruction bus error", | |
990 | [EXCP_DBp] = "debug breakpoint", | |
991 | [EXCP_SYSCALL] = "syscall", | |
992 | [EXCP_BREAK] = "break", | |
993 | [EXCP_CpU] = "coprocessor unusable", | |
994 | [EXCP_RI] = "reserved instruction", | |
995 | [EXCP_OVERFLOW] = "arithmetic overflow", | |
996 | [EXCP_TRAP] = "trap", | |
997 | [EXCP_FPE] = "floating point", | |
998 | [EXCP_DDBS] = "debug data break store", | |
999 | [EXCP_DWATCH] = "data watchpoint", | |
1000 | [EXCP_LTLBL] = "TLB modify", | |
1001 | [EXCP_TLBL] = "TLB load", | |
1002 | [EXCP_TLBS] = "TLB store", | |
1003 | [EXCP_DBE] = "data bus error", | |
1004 | [EXCP_DDBL] = "debug data break load", | |
1005 | [EXCP_THREAD] = "thread", | |
1006 | [EXCP_MDMX] = "MDMX", | |
1007 | [EXCP_C2E] = "precise coprocessor 2", | |
1008 | [EXCP_CACHE] = "cache error", | |
92ceb440 LA |
1009 | [EXCP_TLBXI] = "TLB execute-inhibit", |
1010 | [EXCP_TLBRI] = "TLB read-inhibit", | |
b10ac204 YK |
1011 | [EXCP_MSADIS] = "MSA disabled", |
1012 | [EXCP_MSAFPE] = "MSA floating point", | |
14e51cc7 | 1013 | }; |
d4fa5354 | 1014 | #endif |
14e51cc7 | 1015 | |
1239b472 | 1016 | target_ulong exception_resume_pc (CPUMIPSState *env) |
32188a03 NF |
1017 | { |
1018 | target_ulong bad_pc; | |
1019 | target_ulong isa_mode; | |
1020 | ||
1021 | isa_mode = !!(env->hflags & MIPS_HFLAG_M16); | |
1022 | bad_pc = env->active_tc.PC | isa_mode; | |
1023 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
1024 | /* If the exception was raised from a delay slot, come back to | |
1025 | the jump. */ | |
1026 | bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); | |
1027 | } | |
1028 | ||
1029 | return bad_pc; | |
1030 | } | |
bbfa8f72 | 1031 | |
1239b472 | 1032 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 1033 | static void set_hflags_for_handler (CPUMIPSState *env) |
bbfa8f72 NF |
1034 | { |
1035 | /* Exception handlers are entered in 32-bit mode. */ | |
1036 | env->hflags &= ~(MIPS_HFLAG_M16); | |
1037 | /* ...except that microMIPS lets you choose. */ | |
1038 | if (env->insn_flags & ASE_MICROMIPS) { | |
1039 | env->hflags |= (!!(env->CP0_Config3 | |
1040 | & (1 << CP0C3_ISA_ON_EXC)) | |
1041 | << MIPS_HFLAG_M16_SHIFT); | |
1042 | } | |
1043 | } | |
aea14095 LA |
1044 | |
1045 | static inline void set_badinstr_registers(CPUMIPSState *env) | |
1046 | { | |
7a5f784a SM |
1047 | if (env->insn_flags & ISA_NANOMIPS32) { |
1048 | if (env->CP0_Config3 & (1 << CP0C3_BI)) { | |
1049 | uint32_t instr = (cpu_lduw_code(env, env->active_tc.PC)) << 16; | |
1050 | if ((instr & 0x10000000) == 0) { | |
1051 | instr |= cpu_lduw_code(env, env->active_tc.PC + 2); | |
1052 | } | |
1053 | env->CP0_BadInstr = instr; | |
1054 | ||
1055 | if ((instr & 0xFC000000) == 0x60000000) { | |
1056 | instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16; | |
1057 | env->CP0_BadInstrX = instr; | |
1058 | } | |
1059 | } | |
1060 | return; | |
1061 | } | |
1062 | ||
aea14095 LA |
1063 | if (env->hflags & MIPS_HFLAG_M16) { |
1064 | /* TODO: add BadInstr support for microMIPS */ | |
1065 | return; | |
1066 | } | |
1067 | if (env->CP0_Config3 & (1 << CP0C3_BI)) { | |
1068 | env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); | |
1069 | } | |
1070 | if ((env->CP0_Config3 & (1 << CP0C3_BP)) && | |
1071 | (env->hflags & MIPS_HFLAG_BMASK)) { | |
1072 | env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); | |
1073 | } | |
1074 | } | |
32188a03 NF |
1075 | #endif |
1076 | ||
97a8ea5a | 1077 | void mips_cpu_do_interrupt(CPUState *cs) |
6af0bf9c | 1078 | { |
27103424 | 1079 | #if !defined(CONFIG_USER_ONLY) |
97a8ea5a AF |
1080 | MIPSCPU *cpu = MIPS_CPU(cs); |
1081 | CPUMIPSState *env = &cpu->env; | |
aea14095 | 1082 | bool update_badinstr = 0; |
932e71cd AJ |
1083 | target_ulong offset; |
1084 | int cause = -1; | |
1085 | const char *name; | |
100ce988 | 1086 | |
c8557016 RH |
1087 | if (qemu_loglevel_mask(CPU_LOG_INT) |
1088 | && cs->exception_index != EXCP_EXT_INTERRUPT) { | |
27103424 | 1089 | if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { |
932e71cd | 1090 | name = "unknown"; |
27103424 AF |
1091 | } else { |
1092 | name = excp_names[cs->exception_index]; | |
1093 | } | |
b67bfe8d | 1094 | |
c8557016 RH |
1095 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx |
1096 | " %s exception\n", | |
93fcfe39 | 1097 | __func__, env->active_tc.PC, env->CP0_EPC, name); |
932e71cd | 1098 | } |
27103424 AF |
1099 | if (cs->exception_index == EXCP_EXT_INTERRUPT && |
1100 | (env->hflags & MIPS_HFLAG_DM)) { | |
1101 | cs->exception_index = EXCP_DINT; | |
1102 | } | |
932e71cd | 1103 | offset = 0x180; |
27103424 | 1104 | switch (cs->exception_index) { |
932e71cd AJ |
1105 | case EXCP_DSS: |
1106 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
1107 | /* Debug single step cannot be raised inside a delay slot and | |
1108 | resume will always occur on the next instruction | |
1109 | (but we assume the pc has always been updated during | |
1110 | code translation). */ | |
32188a03 | 1111 | env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); |
932e71cd AJ |
1112 | goto enter_debug_mode; |
1113 | case EXCP_DINT: | |
1114 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
1115 | goto set_DEPC; | |
1116 | case EXCP_DIB: | |
1117 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
1118 | goto set_DEPC; | |
1119 | case EXCP_DBp: | |
1120 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
c6c2c0fc PD |
1121 | /* Setup DExcCode - SDBBP instruction */ |
1122 | env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC; | |
932e71cd AJ |
1123 | goto set_DEPC; |
1124 | case EXCP_DDBS: | |
1125 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
1126 | goto set_DEPC; | |
1127 | case EXCP_DDBL: | |
1128 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
1129 | set_DEPC: | |
32188a03 NF |
1130 | env->CP0_DEPC = exception_resume_pc(env); |
1131 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
0eaef5aa | 1132 | enter_debug_mode: |
d9224450 MR |
1133 | if (env->insn_flags & ISA_MIPS3) { |
1134 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
1135 | if (!(env->insn_flags & ISA_MIPS64R6) || |
1136 | env->CP0_Status & (1 << CP0St_KX)) { | |
1137 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
1138 | } | |
d9224450 MR |
1139 | } |
1140 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; | |
932e71cd AJ |
1141 | env->hflags &= ~(MIPS_HFLAG_KSU); |
1142 | /* EJTAG probe trap enable is not implemented... */ | |
1143 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 1144 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
89777fd1 | 1145 | env->active_tc.PC = env->exception_base + 0x480; |
bbfa8f72 | 1146 | set_hflags_for_handler(env); |
932e71cd AJ |
1147 | break; |
1148 | case EXCP_RESET: | |
fca1be7c | 1149 | cpu_reset(CPU(cpu)); |
932e71cd AJ |
1150 | break; |
1151 | case EXCP_SRESET: | |
1152 | env->CP0_Status |= (1 << CP0St_SR); | |
9d989c73 | 1153 | memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); |
932e71cd AJ |
1154 | goto set_error_EPC; |
1155 | case EXCP_NMI: | |
1156 | env->CP0_Status |= (1 << CP0St_NMI); | |
0eaef5aa | 1157 | set_error_EPC: |
32188a03 NF |
1158 | env->CP0_ErrorEPC = exception_resume_pc(env); |
1159 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
932e71cd | 1160 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
d9224450 MR |
1161 | if (env->insn_flags & ISA_MIPS3) { |
1162 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
1163 | if (!(env->insn_flags & ISA_MIPS64R6) || |
1164 | env->CP0_Status & (1 << CP0St_KX)) { | |
1165 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
1166 | } | |
d9224450 MR |
1167 | } |
1168 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd AJ |
1169 | env->hflags &= ~(MIPS_HFLAG_KSU); |
1170 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 1171 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
89777fd1 | 1172 | env->active_tc.PC = env->exception_base; |
bbfa8f72 | 1173 | set_hflags_for_handler(env); |
932e71cd AJ |
1174 | break; |
1175 | case EXCP_EXT_INTERRUPT: | |
1176 | cause = 0; | |
da52a4df YK |
1177 | if (env->CP0_Cause & (1 << CP0Ca_IV)) { |
1178 | uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f; | |
1179 | ||
1180 | if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) { | |
1181 | offset = 0x200; | |
1182 | } else { | |
1183 | uint32_t vector = 0; | |
1184 | uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP; | |
1185 | ||
1186 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { | |
1187 | /* For VEIC mode, the external interrupt controller feeds | |
1188 | * the vector through the CP0Cause IP lines. */ | |
1189 | vector = pending; | |
1190 | } else { | |
1191 | /* Vectored Interrupts | |
1192 | * Mask with Status.IM7-IM0 to get enabled interrupts. */ | |
1193 | pending &= (env->CP0_Status >> CP0St_IM) & 0xff; | |
1194 | /* Find the highest-priority interrupt. */ | |
1195 | while (pending >>= 1) { | |
1196 | vector++; | |
138afb02 | 1197 | } |
138afb02 | 1198 | } |
da52a4df | 1199 | offset = 0x200 + (vector * (spacing << 5)); |
138afb02 | 1200 | } |
138afb02 | 1201 | } |
932e71cd AJ |
1202 | goto set_EPC; |
1203 | case EXCP_LTLBL: | |
1204 | cause = 1; | |
aea14095 | 1205 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
1206 | goto set_EPC; |
1207 | case EXCP_TLBL: | |
1208 | cause = 2; | |
aea14095 LA |
1209 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
1210 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
1211 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 1212 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
1213 | int R = env->CP0_BadVAddr >> 62; |
1214 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
932e71cd | 1215 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
0eaef5aa | 1216 | |
480e79ae JH |
1217 | if ((R != 0 || UX) && (R != 3 || KX) && |
1218 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) { | |
932e71cd | 1219 | offset = 0x080; |
480e79ae | 1220 | } else { |
0eaef5aa | 1221 | #endif |
932e71cd | 1222 | offset = 0x000; |
480e79ae JH |
1223 | #if defined(TARGET_MIPS64) |
1224 | } | |
1225 | #endif | |
932e71cd AJ |
1226 | } |
1227 | goto set_EPC; | |
1228 | case EXCP_TLBS: | |
1229 | cause = 3; | |
aea14095 LA |
1230 | update_badinstr = 1; |
1231 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
1232 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 1233 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
1234 | int R = env->CP0_BadVAddr >> 62; |
1235 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
932e71cd | 1236 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; |
0eaef5aa | 1237 | |
480e79ae JH |
1238 | if ((R != 0 || UX) && (R != 3 || KX) && |
1239 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) { | |
932e71cd | 1240 | offset = 0x080; |
480e79ae | 1241 | } else { |
0eaef5aa | 1242 | #endif |
932e71cd | 1243 | offset = 0x000; |
480e79ae JH |
1244 | #if defined(TARGET_MIPS64) |
1245 | } | |
1246 | #endif | |
932e71cd AJ |
1247 | } |
1248 | goto set_EPC; | |
1249 | case EXCP_AdEL: | |
1250 | cause = 4; | |
aea14095 | 1251 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
1252 | goto set_EPC; |
1253 | case EXCP_AdES: | |
1254 | cause = 5; | |
aea14095 | 1255 | update_badinstr = 1; |
932e71cd AJ |
1256 | goto set_EPC; |
1257 | case EXCP_IBE: | |
1258 | cause = 6; | |
1259 | goto set_EPC; | |
1260 | case EXCP_DBE: | |
1261 | cause = 7; | |
1262 | goto set_EPC; | |
1263 | case EXCP_SYSCALL: | |
1264 | cause = 8; | |
aea14095 | 1265 | update_badinstr = 1; |
932e71cd AJ |
1266 | goto set_EPC; |
1267 | case EXCP_BREAK: | |
1268 | cause = 9; | |
aea14095 | 1269 | update_badinstr = 1; |
932e71cd AJ |
1270 | goto set_EPC; |
1271 | case EXCP_RI: | |
1272 | cause = 10; | |
aea14095 | 1273 | update_badinstr = 1; |
932e71cd AJ |
1274 | goto set_EPC; |
1275 | case EXCP_CpU: | |
1276 | cause = 11; | |
aea14095 | 1277 | update_badinstr = 1; |
932e71cd AJ |
1278 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
1279 | (env->error_code << CP0Ca_CE); | |
1280 | goto set_EPC; | |
1281 | case EXCP_OVERFLOW: | |
1282 | cause = 12; | |
aea14095 | 1283 | update_badinstr = 1; |
932e71cd AJ |
1284 | goto set_EPC; |
1285 | case EXCP_TRAP: | |
1286 | cause = 13; | |
aea14095 | 1287 | update_badinstr = 1; |
932e71cd | 1288 | goto set_EPC; |
b10ac204 YK |
1289 | case EXCP_MSAFPE: |
1290 | cause = 14; | |
1291 | update_badinstr = 1; | |
1292 | goto set_EPC; | |
932e71cd AJ |
1293 | case EXCP_FPE: |
1294 | cause = 15; | |
aea14095 | 1295 | update_badinstr = 1; |
932e71cd AJ |
1296 | goto set_EPC; |
1297 | case EXCP_C2E: | |
1298 | cause = 18; | |
1299 | goto set_EPC; | |
92ceb440 LA |
1300 | case EXCP_TLBRI: |
1301 | cause = 19; | |
aea14095 | 1302 | update_badinstr = 1; |
92ceb440 LA |
1303 | goto set_EPC; |
1304 | case EXCP_TLBXI: | |
1305 | cause = 20; | |
1306 | goto set_EPC; | |
b10ac204 YK |
1307 | case EXCP_MSADIS: |
1308 | cause = 21; | |
1309 | update_badinstr = 1; | |
1310 | goto set_EPC; | |
932e71cd AJ |
1311 | case EXCP_MDMX: |
1312 | cause = 22; | |
1313 | goto set_EPC; | |
1314 | case EXCP_DWATCH: | |
1315 | cause = 23; | |
67cc32eb | 1316 | /* XXX: TODO: manage deferred watch exceptions */ |
932e71cd AJ |
1317 | goto set_EPC; |
1318 | case EXCP_MCHECK: | |
1319 | cause = 24; | |
1320 | goto set_EPC; | |
1321 | case EXCP_THREAD: | |
1322 | cause = 25; | |
1323 | goto set_EPC; | |
853c3240 JL |
1324 | case EXCP_DSPDIS: |
1325 | cause = 26; | |
1326 | goto set_EPC; | |
932e71cd AJ |
1327 | case EXCP_CACHE: |
1328 | cause = 30; | |
74dbf824 | 1329 | offset = 0x100; |
0eaef5aa | 1330 | set_EPC: |
932e71cd | 1331 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
32188a03 | 1332 | env->CP0_EPC = exception_resume_pc(env); |
aea14095 LA |
1333 | if (update_badinstr) { |
1334 | set_badinstr_registers(env); | |
1335 | } | |
932e71cd | 1336 | if (env->hflags & MIPS_HFLAG_BMASK) { |
f45cb2f4 | 1337 | env->CP0_Cause |= (1U << CP0Ca_BD); |
0eaef5aa | 1338 | } else { |
f45cb2f4 | 1339 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
0eaef5aa | 1340 | } |
932e71cd | 1341 | env->CP0_Status |= (1 << CP0St_EXL); |
d9224450 MR |
1342 | if (env->insn_flags & ISA_MIPS3) { |
1343 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
1344 | if (!(env->insn_flags & ISA_MIPS64R6) || |
1345 | env->CP0_Status & (1 << CP0St_KX)) { | |
1346 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
1347 | } | |
d9224450 MR |
1348 | } |
1349 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd | 1350 | env->hflags &= ~(MIPS_HFLAG_KSU); |
6af0bf9c | 1351 | } |
932e71cd AJ |
1352 | env->hflags &= ~MIPS_HFLAG_BMASK; |
1353 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
89777fd1 | 1354 | env->active_tc.PC = env->exception_base + 0x200; |
74dbf824 JH |
1355 | } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) && |
1356 | env->CP0_Config5 & (1 << CP0C5_CV))) { | |
1357 | /* Force KSeg1 for cache errors */ | |
67433345 | 1358 | env->active_tc.PC = KSEG1_BASE | (env->CP0_EBase & 0x1FFFF000); |
932e71cd | 1359 | } else { |
74dbf824 | 1360 | env->active_tc.PC = env->CP0_EBase & ~0xfff; |
6af0bf9c | 1361 | } |
74dbf824 | 1362 | |
932e71cd | 1363 | env->active_tc.PC += offset; |
bbfa8f72 | 1364 | set_hflags_for_handler(env); |
932e71cd AJ |
1365 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
1366 | break; | |
1367 | default: | |
c8557016 | 1368 | abort(); |
932e71cd | 1369 | } |
c8557016 RH |
1370 | if (qemu_loglevel_mask(CPU_LOG_INT) |
1371 | && cs->exception_index != EXCP_EXT_INTERRUPT) { | |
93fcfe39 | 1372 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
c8557016 RH |
1373 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
1374 | __func__, env->active_tc.PC, env->CP0_EPC, cause, | |
1375 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
1376 | env->CP0_DEPC); | |
6af0bf9c | 1377 | } |
932e71cd | 1378 | #endif |
27103424 | 1379 | cs->exception_index = EXCP_NONE; |
6af0bf9c | 1380 | } |
2ee4aed8 | 1381 | |
fa4faba4 RH |
1382 | bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
1383 | { | |
1384 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
1385 | MIPSCPU *cpu = MIPS_CPU(cs); | |
1386 | CPUMIPSState *env = &cpu->env; | |
1387 | ||
71ca034a LA |
1388 | if (cpu_mips_hw_interrupts_enabled(env) && |
1389 | cpu_mips_hw_interrupts_pending(env)) { | |
fa4faba4 RH |
1390 | /* Raise it */ |
1391 | cs->exception_index = EXCP_EXT_INTERRUPT; | |
1392 | env->error_code = 0; | |
1393 | mips_cpu_do_interrupt(cs); | |
1394 | return true; | |
1395 | } | |
1396 | } | |
1397 | return false; | |
1398 | } | |
1399 | ||
3c7b48b7 | 1400 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 1401 | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) |
2ee4aed8 | 1402 | { |
31b030d4 AF |
1403 | MIPSCPU *cpu = mips_env_get_cpu(env); |
1404 | CPUState *cs; | |
c227f099 | 1405 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
1406 | target_ulong addr; |
1407 | target_ulong end; | |
2d72e7b0 | 1408 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
3b1c8be4 | 1409 | target_ulong mask; |
2ee4aed8 | 1410 | |
ead9360e | 1411 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 1412 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
1413 | flush these entries again. */ |
1414 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
1415 | return; | |
1416 | } | |
1417 | ||
ead9360e | 1418 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
2ee4aed8 | 1419 | /* For tlbwr, we can shadow the discarded entry into |
6958549d AJ |
1420 | a new (fake) TLB entry, as long as the guest can not |
1421 | tell that it's there. */ | |
ead9360e TS |
1422 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
1423 | env->tlb->tlb_in_use++; | |
2ee4aed8 FB |
1424 | return; |
1425 | } | |
1426 | ||
3b1c8be4 | 1427 | /* 1k pages are not supported. */ |
f2e9ebef | 1428 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 1429 | if (tlb->V0) { |
31b030d4 | 1430 | cs = CPU(cpu); |
f2e9ebef | 1431 | addr = tlb->VPN & ~mask; |
d26bc211 | 1432 | #if defined(TARGET_MIPS64) |
e034e2c3 | 1433 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
1434 | addr |= 0x3FFFFF0000000000ULL; |
1435 | } | |
1436 | #endif | |
3b1c8be4 TS |
1437 | end = addr | (mask >> 1); |
1438 | while (addr < end) { | |
31b030d4 | 1439 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
1440 | addr += TARGET_PAGE_SIZE; |
1441 | } | |
1442 | } | |
1443 | if (tlb->V1) { | |
31b030d4 | 1444 | cs = CPU(cpu); |
f2e9ebef | 1445 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
d26bc211 | 1446 | #if defined(TARGET_MIPS64) |
e034e2c3 | 1447 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
1448 | addr |= 0x3FFFFF0000000000ULL; |
1449 | } | |
1450 | #endif | |
3b1c8be4 | 1451 | end = addr | mask; |
53715e48 | 1452 | while (addr - 1 < end) { |
31b030d4 | 1453 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
1454 | addr += TARGET_PAGE_SIZE; |
1455 | } | |
1456 | } | |
2ee4aed8 | 1457 | } |
3c7b48b7 | 1458 | #endif |
33c11879 PB |
1459 | |
1460 | void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, | |
1461 | uint32_t exception, | |
1462 | int error_code, | |
1463 | uintptr_t pc) | |
1464 | { | |
1465 | CPUState *cs = CPU(mips_env_get_cpu(env)); | |
1466 | ||
33a07fa2 LA |
1467 | qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", |
1468 | __func__, exception, error_code); | |
33c11879 PB |
1469 | cs->exception_index = exception; |
1470 | env->error_code = error_code; | |
1471 | ||
1472 | cpu_loop_exit_restore(cs, pc); | |
1473 | } | |
535db744 PD |
1474 | |
1475 | static void mips_cpu_add_definition(gpointer data, gpointer user_data) | |
1476 | { | |
1477 | ObjectClass *oc = data; | |
1478 | CpuDefinitionInfoList **cpu_list = user_data; | |
1479 | CpuDefinitionInfoList *entry; | |
1480 | CpuDefinitionInfo *info; | |
1481 | const char *typename; | |
1482 | ||
1483 | typename = object_class_get_name(oc); | |
1484 | info = g_malloc0(sizeof(*info)); | |
1485 | info->name = g_strndup(typename, | |
1486 | strlen(typename) - strlen("-" TYPE_MIPS_CPU)); | |
1487 | info->q_typename = g_strdup(typename); | |
1488 | ||
1489 | entry = g_malloc0(sizeof(*entry)); | |
1490 | entry->value = info; | |
1491 | entry->next = *cpu_list; | |
1492 | *cpu_list = entry; | |
1493 | } | |
1494 | ||
1495 | CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) | |
1496 | { | |
1497 | CpuDefinitionInfoList *cpu_list = NULL; | |
1498 | GSList *list; | |
1499 | ||
1500 | list = object_class_get_list(TYPE_MIPS_CPU, false); | |
1501 | g_slist_foreach(list, mips_cpu_add_definition, &cpu_list); | |
1502 | g_slist_free(list); | |
1503 | ||
1504 | return cpu_list; | |
1505 | } |