]>
Commit | Line | Data |
---|---|---|
6af0bf9c FB |
1 | /* |
2 | * MIPS emulation helpers for qemu. | |
5fafdf24 | 3 | * |
6af0bf9c FB |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
6af0bf9c | 18 | */ |
c684822a | 19 | #include "qemu/osdep.h" |
e37e863f FB |
20 | |
21 | #include "cpu.h" | |
4ef37e69 | 22 | #include "sysemu/kvm.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
aea14095 | 24 | #include "exec/cpu_ldst.h" |
508127e2 | 25 | #include "exec/log.h" |
6af0bf9c | 26 | |
43057ab1 | 27 | enum { |
2fb58b73 LA |
28 | TLBRET_XI = -6, |
29 | TLBRET_RI = -5, | |
43057ab1 FB |
30 | TLBRET_DIRTY = -4, |
31 | TLBRET_INVALID = -3, | |
32 | TLBRET_NOMATCH = -2, | |
33 | TLBRET_BADADDR = -1, | |
34 | TLBRET_MATCH = 0 | |
35 | }; | |
36 | ||
3c7b48b7 PB |
37 | #if !defined(CONFIG_USER_ONLY) |
38 | ||
29929e34 | 39 | /* no MMU emulation */ |
a8170e5e | 40 | int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
6af0bf9c | 41 | target_ulong address, int rw, int access_type) |
29929e34 TS |
42 | { |
43 | *physical = address; | |
44 | *prot = PAGE_READ | PAGE_WRITE; | |
45 | return TLBRET_MATCH; | |
46 | } | |
47 | ||
48 | /* fixed mapping MMU emulation */ | |
a8170e5e | 49 | int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 TS |
50 | target_ulong address, int rw, int access_type) |
51 | { | |
52 | if (address <= (int32_t)0x7FFFFFFFUL) { | |
53 | if (!(env->CP0_Status & (1 << CP0St_ERL))) | |
54 | *physical = address + 0x40000000UL; | |
55 | else | |
56 | *physical = address; | |
57 | } else if (address <= (int32_t)0xBFFFFFFFUL) | |
58 | *physical = address & 0x1FFFFFFF; | |
59 | else | |
60 | *physical = address; | |
61 | ||
62 | *prot = PAGE_READ | PAGE_WRITE; | |
63 | return TLBRET_MATCH; | |
64 | } | |
65 | ||
66 | /* MIPS32/MIPS64 R4000-style MMU emulation */ | |
a8170e5e | 67 | int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, |
29929e34 | 68 | target_ulong address, int rw, int access_type) |
6af0bf9c | 69 | { |
2d72e7b0 | 70 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
3b1c8be4 | 71 | int i; |
6af0bf9c | 72 | |
ead9360e | 73 | for (i = 0; i < env->tlb->tlb_in_use; i++) { |
c227f099 | 74 | r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i]; |
3b1c8be4 | 75 | /* 1k pages are not supported. */ |
f2e9ebef | 76 | target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 77 | target_ulong tag = address & ~mask; |
f2e9ebef | 78 | target_ulong VPN = tlb->VPN & ~mask; |
d26bc211 | 79 | #if defined(TARGET_MIPS64) |
e034e2c3 | 80 | tag &= env->SEGMask; |
100ce988 | 81 | #endif |
3b1c8be4 | 82 | |
6af0bf9c | 83 | /* Check ASID, virtual page number & size */ |
9456c2fb | 84 | if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) { |
6af0bf9c | 85 | /* TLB match */ |
f2e9ebef | 86 | int n = !!(address & mask & ~(mask >> 1)); |
6af0bf9c | 87 | /* Check access rights */ |
2fb58b73 | 88 | if (!(n ? tlb->V1 : tlb->V0)) { |
43057ab1 | 89 | return TLBRET_INVALID; |
2fb58b73 LA |
90 | } |
91 | if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) { | |
92 | return TLBRET_XI; | |
93 | } | |
94 | if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) { | |
95 | return TLBRET_RI; | |
96 | } | |
9f6bcedb | 97 | if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) { |
3b1c8be4 | 98 | *physical = tlb->PFN[n] | (address & (mask >> 1)); |
9fb63ac2 | 99 | *prot = PAGE_READ; |
98c1b82b | 100 | if (n ? tlb->D1 : tlb->D0) |
9fb63ac2 | 101 | *prot |= PAGE_WRITE; |
43057ab1 | 102 | return TLBRET_MATCH; |
6af0bf9c | 103 | } |
43057ab1 | 104 | return TLBRET_DIRTY; |
6af0bf9c FB |
105 | } |
106 | } | |
43057ab1 | 107 | return TLBRET_NOMATCH; |
6af0bf9c | 108 | } |
6af0bf9c | 109 | |
a8170e5e | 110 | static int get_physical_address (CPUMIPSState *env, hwaddr *physical, |
4ef37e69 | 111 | int *prot, target_ulong real_address, |
43057ab1 | 112 | int rw, int access_type) |
6af0bf9c | 113 | { |
b4ab4b4e | 114 | /* User mode can only access useg/xuseg */ |
43057ab1 | 115 | int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM; |
671880e6 TS |
116 | int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM; |
117 | int kernel_mode = !user_mode && !supervisor_mode; | |
d26bc211 | 118 | #if defined(TARGET_MIPS64) |
b4ab4b4e TS |
119 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; |
120 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
121 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
122 | #endif | |
43057ab1 | 123 | int ret = TLBRET_MATCH; |
4ef37e69 JH |
124 | /* effective address (modified for KVM T&E kernel segments) */ |
125 | target_ulong address = real_address; | |
43057ab1 | 126 | |
22010ce7 JH |
127 | #define USEG_LIMIT 0x7FFFFFFFUL |
128 | #define KSEG0_BASE 0x80000000UL | |
129 | #define KSEG1_BASE 0xA0000000UL | |
130 | #define KSEG2_BASE 0xC0000000UL | |
131 | #define KSEG3_BASE 0xE0000000UL | |
132 | ||
4ef37e69 JH |
133 | #define KVM_KSEG0_BASE 0x40000000UL |
134 | #define KVM_KSEG2_BASE 0x60000000UL | |
135 | ||
136 | if (kvm_enabled()) { | |
137 | /* KVM T&E adds guest kernel segments in useg */ | |
138 | if (real_address >= KVM_KSEG0_BASE) { | |
139 | if (real_address < KVM_KSEG2_BASE) { | |
140 | /* kseg0 */ | |
141 | address += KSEG0_BASE - KVM_KSEG0_BASE; | |
142 | } else if (real_address <= USEG_LIMIT) { | |
143 | /* kseg2/3 */ | |
144 | address += KSEG2_BASE - KVM_KSEG2_BASE; | |
145 | } | |
146 | } | |
147 | } | |
148 | ||
22010ce7 | 149 | if (address <= USEG_LIMIT) { |
b4ab4b4e | 150 | /* useg */ |
996ba2cc | 151 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
29929e34 | 152 | *physical = address & 0xFFFFFFFF; |
6af0bf9c | 153 | *prot = PAGE_READ | PAGE_WRITE; |
996ba2cc | 154 | } else { |
4ef37e69 | 155 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6af0bf9c | 156 | } |
d26bc211 | 157 | #if defined(TARGET_MIPS64) |
89fc88da | 158 | } else if (address < 0x4000000000000000ULL) { |
b4ab4b4e | 159 | /* xuseg */ |
6958549d | 160 | if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { |
4ef37e69 | 161 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
162 | } else { |
163 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 164 | } |
89fc88da | 165 | } else if (address < 0x8000000000000000ULL) { |
b4ab4b4e | 166 | /* xsseg */ |
6958549d AJ |
167 | if ((supervisor_mode || kernel_mode) && |
168 | SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 169 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
170 | } else { |
171 | ret = TLBRET_BADADDR; | |
b4ab4b4e | 172 | } |
89fc88da | 173 | } else if (address < 0xC000000000000000ULL) { |
b4ab4b4e | 174 | /* xkphys */ |
671880e6 | 175 | if (kernel_mode && KX && |
6d35524c TS |
176 | (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { |
177 | *physical = address & env->PAMask; | |
b4ab4b4e | 178 | *prot = PAGE_READ | PAGE_WRITE; |
6958549d AJ |
179 | } else { |
180 | ret = TLBRET_BADADDR; | |
181 | } | |
89fc88da | 182 | } else if (address < 0xFFFFFFFF80000000ULL) { |
b4ab4b4e | 183 | /* xkseg */ |
6958549d AJ |
184 | if (kernel_mode && KX && |
185 | address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { | |
4ef37e69 | 186 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
6958549d AJ |
187 | } else { |
188 | ret = TLBRET_BADADDR; | |
189 | } | |
b4ab4b4e | 190 | #endif |
22010ce7 | 191 | } else if (address < (int32_t)KSEG1_BASE) { |
6af0bf9c | 192 | /* kseg0 */ |
671880e6 | 193 | if (kernel_mode) { |
22010ce7 | 194 | *physical = address - (int32_t)KSEG0_BASE; |
671880e6 TS |
195 | *prot = PAGE_READ | PAGE_WRITE; |
196 | } else { | |
197 | ret = TLBRET_BADADDR; | |
198 | } | |
22010ce7 | 199 | } else if (address < (int32_t)KSEG2_BASE) { |
6af0bf9c | 200 | /* kseg1 */ |
671880e6 | 201 | if (kernel_mode) { |
22010ce7 | 202 | *physical = address - (int32_t)KSEG1_BASE; |
671880e6 TS |
203 | *prot = PAGE_READ | PAGE_WRITE; |
204 | } else { | |
205 | ret = TLBRET_BADADDR; | |
206 | } | |
22010ce7 | 207 | } else if (address < (int32_t)KSEG3_BASE) { |
89fc88da | 208 | /* sseg (kseg2) */ |
671880e6 | 209 | if (supervisor_mode || kernel_mode) { |
4ef37e69 | 210 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
671880e6 TS |
211 | } else { |
212 | ret = TLBRET_BADADDR; | |
213 | } | |
6af0bf9c FB |
214 | } else { |
215 | /* kseg3 */ | |
6af0bf9c | 216 | /* XXX: debug segment is not emulated */ |
671880e6 | 217 | if (kernel_mode) { |
4ef37e69 | 218 | ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type); |
671880e6 TS |
219 | } else { |
220 | ret = TLBRET_BADADDR; | |
221 | } | |
6af0bf9c | 222 | } |
6af0bf9c FB |
223 | return ret; |
224 | } | |
e6623d88 | 225 | |
d10eb08f | 226 | void cpu_mips_tlb_flush(CPUMIPSState *env) |
e6623d88 PB |
227 | { |
228 | MIPSCPU *cpu = mips_env_get_cpu(env); | |
229 | ||
230 | /* Flush qemu's TLB and discard all shadowed entries. */ | |
d10eb08f | 231 | tlb_flush(CPU(cpu)); |
e6623d88 PB |
232 | env->tlb->tlb_in_use = env->tlb->nb_tlb; |
233 | } | |
234 | ||
235 | /* Called for updates to CP0_Status. */ | |
236 | void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) | |
237 | { | |
238 | int32_t tcstatus, *tcst; | |
239 | uint32_t v = cpu->CP0_Status; | |
240 | uint32_t cu, mx, asid, ksu; | |
241 | uint32_t mask = ((1 << CP0TCSt_TCU3) | |
242 | | (1 << CP0TCSt_TCU2) | |
243 | | (1 << CP0TCSt_TCU1) | |
244 | | (1 << CP0TCSt_TCU0) | |
245 | | (1 << CP0TCSt_TMX) | |
246 | | (3 << CP0TCSt_TKSU) | |
247 | | (0xff << CP0TCSt_TASID)); | |
248 | ||
249 | cu = (v >> CP0St_CU0) & 0xf; | |
250 | mx = (v >> CP0St_MX) & 0x1; | |
251 | ksu = (v >> CP0St_KSU) & 0x3; | |
6ec98bd7 | 252 | asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
e6623d88 PB |
253 | |
254 | tcstatus = cu << CP0TCSt_TCU0; | |
255 | tcstatus |= mx << CP0TCSt_TMX; | |
256 | tcstatus |= ksu << CP0TCSt_TKSU; | |
257 | tcstatus |= asid; | |
258 | ||
259 | if (tc == cpu->current_tc) { | |
260 | tcst = &cpu->active_tc.CP0_TCStatus; | |
261 | } else { | |
262 | tcst = &cpu->tcs[tc].CP0_TCStatus; | |
263 | } | |
264 | ||
265 | *tcst &= ~mask; | |
266 | *tcst |= tcstatus; | |
267 | compute_hflags(cpu); | |
268 | } | |
269 | ||
270 | void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) | |
271 | { | |
272 | uint32_t mask = env->CP0_Status_rw_bitmask; | |
273 | target_ulong old = env->CP0_Status; | |
274 | ||
275 | if (env->insn_flags & ISA_MIPS32R6) { | |
276 | bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; | |
277 | #if defined(TARGET_MIPS64) | |
278 | uint32_t ksux = (1 << CP0St_KX) & val; | |
279 | ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ | |
280 | ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ | |
281 | val = (val & ~(7 << CP0St_UX)) | ksux; | |
282 | #endif | |
283 | if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { | |
284 | mask &= ~(3 << CP0St_KSU); | |
285 | } | |
286 | mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); | |
287 | } | |
288 | ||
289 | env->CP0_Status = (old & ~mask) | (val & mask); | |
290 | #if defined(TARGET_MIPS64) | |
291 | if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { | |
292 | /* Access to at least one of the 64-bit segments has been disabled */ | |
9658e4c3 | 293 | tlb_flush(CPU(mips_env_get_cpu(env))); |
e6623d88 PB |
294 | } |
295 | #endif | |
296 | if (env->CP0_Config3 & (1 << CP0C3_MT)) { | |
297 | sync_c0_status(env, env, env->current_tc); | |
298 | } else { | |
299 | compute_hflags(env); | |
300 | } | |
301 | } | |
302 | ||
303 | void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) | |
304 | { | |
305 | uint32_t mask = 0x00C00300; | |
306 | uint32_t old = env->CP0_Cause; | |
307 | int i; | |
308 | ||
309 | if (env->insn_flags & ISA_MIPS32R2) { | |
310 | mask |= 1 << CP0Ca_DC; | |
311 | } | |
312 | if (env->insn_flags & ISA_MIPS32R6) { | |
313 | mask &= ~((1 << CP0Ca_WP) & val); | |
314 | } | |
315 | ||
316 | env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); | |
317 | ||
318 | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { | |
319 | if (env->CP0_Cause & (1 << CP0Ca_DC)) { | |
320 | cpu_mips_stop_count(env); | |
321 | } else { | |
322 | cpu_mips_start_count(env); | |
323 | } | |
324 | } | |
325 | ||
326 | /* Set/reset software interrupts */ | |
327 | for (i = 0 ; i < 2 ; i++) { | |
328 | if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { | |
329 | cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); | |
330 | } | |
331 | } | |
332 | } | |
932e71cd | 333 | #endif |
6af0bf9c | 334 | |
7db13fae | 335 | static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, |
1147e189 AJ |
336 | int rw, int tlb_error) |
337 | { | |
27103424 | 338 | CPUState *cs = CPU(mips_env_get_cpu(env)); |
1147e189 AJ |
339 | int exception = 0, error_code = 0; |
340 | ||
aea14095 LA |
341 | if (rw == MMU_INST_FETCH) { |
342 | error_code |= EXCP_INST_NOTAVAIL; | |
343 | } | |
344 | ||
1147e189 AJ |
345 | switch (tlb_error) { |
346 | default: | |
347 | case TLBRET_BADADDR: | |
348 | /* Reference to kernel address from user mode or supervisor mode */ | |
349 | /* Reference to supervisor address from user mode */ | |
9f6bcedb | 350 | if (rw == MMU_DATA_STORE) { |
1147e189 | 351 | exception = EXCP_AdES; |
9f6bcedb | 352 | } else { |
1147e189 | 353 | exception = EXCP_AdEL; |
9f6bcedb | 354 | } |
1147e189 AJ |
355 | break; |
356 | case TLBRET_NOMATCH: | |
357 | /* No TLB match for a mapped address */ | |
9f6bcedb | 358 | if (rw == MMU_DATA_STORE) { |
1147e189 | 359 | exception = EXCP_TLBS; |
9f6bcedb | 360 | } else { |
1147e189 | 361 | exception = EXCP_TLBL; |
9f6bcedb | 362 | } |
aea14095 | 363 | error_code |= EXCP_TLB_NOMATCH; |
1147e189 AJ |
364 | break; |
365 | case TLBRET_INVALID: | |
366 | /* TLB match with no valid bit */ | |
9f6bcedb | 367 | if (rw == MMU_DATA_STORE) { |
1147e189 | 368 | exception = EXCP_TLBS; |
9f6bcedb | 369 | } else { |
1147e189 | 370 | exception = EXCP_TLBL; |
9f6bcedb | 371 | } |
1147e189 AJ |
372 | break; |
373 | case TLBRET_DIRTY: | |
374 | /* TLB match but 'D' bit is cleared */ | |
375 | exception = EXCP_LTLBL; | |
376 | break; | |
92ceb440 LA |
377 | case TLBRET_XI: |
378 | /* Execute-Inhibit Exception */ | |
379 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
380 | exception = EXCP_TLBXI; | |
381 | } else { | |
382 | exception = EXCP_TLBL; | |
383 | } | |
384 | break; | |
385 | case TLBRET_RI: | |
386 | /* Read-Inhibit Exception */ | |
387 | if (env->CP0_PageGrain & (1 << CP0PG_IEC)) { | |
388 | exception = EXCP_TLBRI; | |
389 | } else { | |
390 | exception = EXCP_TLBL; | |
391 | } | |
392 | break; | |
1147e189 AJ |
393 | } |
394 | /* Raise exception */ | |
395 | env->CP0_BadVAddr = address; | |
396 | env->CP0_Context = (env->CP0_Context & ~0x007fffff) | | |
397 | ((address >> 9) & 0x007ffff0); | |
6ec98bd7 | 398 | env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | |
701074a6 | 399 | (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) | |
6ec98bd7 | 400 | (address & (TARGET_PAGE_MASK << 1)); |
1147e189 AJ |
401 | #if defined(TARGET_MIPS64) |
402 | env->CP0_EntryHi &= env->SEGMask; | |
60270f85 YK |
403 | env->CP0_XContext = |
404 | /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | | |
405 | /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | | |
406 | /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4); | |
1147e189 | 407 | #endif |
27103424 | 408 | cs->exception_index = exception; |
1147e189 AJ |
409 | env->error_code = error_code; |
410 | } | |
411 | ||
4fcc562b | 412 | #if !defined(CONFIG_USER_ONLY) |
00b941e5 | 413 | hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) |
6af0bf9c | 414 | { |
00b941e5 | 415 | MIPSCPU *cpu = MIPS_CPU(cs); |
a8170e5e | 416 | hwaddr phys_addr; |
932e71cd | 417 | int prot; |
6af0bf9c | 418 | |
00b941e5 AF |
419 | if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, |
420 | ACCESS_INT) != 0) { | |
932e71cd | 421 | return -1; |
00b941e5 | 422 | } |
932e71cd | 423 | return phys_addr; |
6af0bf9c | 424 | } |
4fcc562b | 425 | #endif |
6af0bf9c | 426 | |
7510454e AF |
427 | int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, |
428 | int mmu_idx) | |
6af0bf9c | 429 | { |
7510454e AF |
430 | MIPSCPU *cpu = MIPS_CPU(cs); |
431 | CPUMIPSState *env = &cpu->env; | |
932e71cd | 432 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 433 | hwaddr physical; |
6af0bf9c | 434 | int prot; |
6af0bf9c | 435 | int access_type; |
99e43d36 | 436 | #endif |
6af0bf9c FB |
437 | int ret = 0; |
438 | ||
4ad40f36 | 439 | #if 0 |
7510454e | 440 | log_cpu_state(cs, 0); |
4ad40f36 | 441 | #endif |
339aaf5b AP |
442 | qemu_log_mask(CPU_LOG_MMU, |
443 | "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", | |
97b348e7 | 444 | __func__, env->active_tc.PC, address, rw, mmu_idx); |
4ad40f36 | 445 | |
6af0bf9c | 446 | /* data access */ |
99e43d36 | 447 | #if !defined(CONFIG_USER_ONLY) |
6af0bf9c FB |
448 | /* XXX: put correct access by using cpu_restore_state() |
449 | correctly */ | |
450 | access_type = ACCESS_INT; | |
6af0bf9c FB |
451 | ret = get_physical_address(env, &physical, &prot, |
452 | address, rw, access_type); | |
def74c0c PMD |
453 | switch (ret) { |
454 | case TLBRET_MATCH: | |
455 | qemu_log_mask(CPU_LOG_MMU, | |
456 | "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx | |
457 | " prot %d\n", __func__, address, physical, prot); | |
458 | break; | |
459 | default: | |
460 | qemu_log_mask(CPU_LOG_MMU, | |
461 | "%s address=%" VADDR_PRIx " ret %d\n", __func__, address, | |
462 | ret); | |
463 | break; | |
464 | } | |
43057ab1 | 465 | if (ret == TLBRET_MATCH) { |
0c591eb0 | 466 | tlb_set_page(cs, address & TARGET_PAGE_MASK, |
99e43d36 AJ |
467 | physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, |
468 | mmu_idx, TARGET_PAGE_SIZE); | |
469 | ret = 0; | |
932e71cd AJ |
470 | } else if (ret < 0) |
471 | #endif | |
472 | { | |
1147e189 | 473 | raise_mmu_exception(env, address, rw, ret); |
6af0bf9c FB |
474 | ret = 1; |
475 | } | |
476 | ||
477 | return ret; | |
478 | } | |
479 | ||
25b91e32 | 480 | #if !defined(CONFIG_USER_ONLY) |
a8170e5e | 481 | hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) |
25b91e32 | 482 | { |
a8170e5e | 483 | hwaddr physical; |
25b91e32 AJ |
484 | int prot; |
485 | int access_type; | |
486 | int ret = 0; | |
487 | ||
25b91e32 AJ |
488 | /* data access */ |
489 | access_type = ACCESS_INT; | |
490 | ret = get_physical_address(env, &physical, &prot, | |
491 | address, rw, access_type); | |
492 | if (ret != TLBRET_MATCH) { | |
493 | raise_mmu_exception(env, address, rw, ret); | |
c36bbb28 AJ |
494 | return -1LL; |
495 | } else { | |
496 | return physical; | |
25b91e32 | 497 | } |
25b91e32 | 498 | } |
25b91e32 | 499 | |
9a5d878f TS |
500 | static const char * const excp_names[EXCP_LAST + 1] = { |
501 | [EXCP_RESET] = "reset", | |
502 | [EXCP_SRESET] = "soft reset", | |
503 | [EXCP_DSS] = "debug single step", | |
504 | [EXCP_DINT] = "debug interrupt", | |
505 | [EXCP_NMI] = "non-maskable interrupt", | |
506 | [EXCP_MCHECK] = "machine check", | |
507 | [EXCP_EXT_INTERRUPT] = "interrupt", | |
508 | [EXCP_DFWATCH] = "deferred watchpoint", | |
509 | [EXCP_DIB] = "debug instruction breakpoint", | |
510 | [EXCP_IWATCH] = "instruction fetch watchpoint", | |
511 | [EXCP_AdEL] = "address error load", | |
512 | [EXCP_AdES] = "address error store", | |
513 | [EXCP_TLBF] = "TLB refill", | |
514 | [EXCP_IBE] = "instruction bus error", | |
515 | [EXCP_DBp] = "debug breakpoint", | |
516 | [EXCP_SYSCALL] = "syscall", | |
517 | [EXCP_BREAK] = "break", | |
518 | [EXCP_CpU] = "coprocessor unusable", | |
519 | [EXCP_RI] = "reserved instruction", | |
520 | [EXCP_OVERFLOW] = "arithmetic overflow", | |
521 | [EXCP_TRAP] = "trap", | |
522 | [EXCP_FPE] = "floating point", | |
523 | [EXCP_DDBS] = "debug data break store", | |
524 | [EXCP_DWATCH] = "data watchpoint", | |
525 | [EXCP_LTLBL] = "TLB modify", | |
526 | [EXCP_TLBL] = "TLB load", | |
527 | [EXCP_TLBS] = "TLB store", | |
528 | [EXCP_DBE] = "data bus error", | |
529 | [EXCP_DDBL] = "debug data break load", | |
530 | [EXCP_THREAD] = "thread", | |
531 | [EXCP_MDMX] = "MDMX", | |
532 | [EXCP_C2E] = "precise coprocessor 2", | |
533 | [EXCP_CACHE] = "cache error", | |
92ceb440 LA |
534 | [EXCP_TLBXI] = "TLB execute-inhibit", |
535 | [EXCP_TLBRI] = "TLB read-inhibit", | |
b10ac204 YK |
536 | [EXCP_MSADIS] = "MSA disabled", |
537 | [EXCP_MSAFPE] = "MSA floating point", | |
14e51cc7 | 538 | }; |
d4fa5354 | 539 | #endif |
14e51cc7 | 540 | |
1239b472 | 541 | target_ulong exception_resume_pc (CPUMIPSState *env) |
32188a03 NF |
542 | { |
543 | target_ulong bad_pc; | |
544 | target_ulong isa_mode; | |
545 | ||
546 | isa_mode = !!(env->hflags & MIPS_HFLAG_M16); | |
547 | bad_pc = env->active_tc.PC | isa_mode; | |
548 | if (env->hflags & MIPS_HFLAG_BMASK) { | |
549 | /* If the exception was raised from a delay slot, come back to | |
550 | the jump. */ | |
551 | bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); | |
552 | } | |
553 | ||
554 | return bad_pc; | |
555 | } | |
bbfa8f72 | 556 | |
1239b472 | 557 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 558 | static void set_hflags_for_handler (CPUMIPSState *env) |
bbfa8f72 NF |
559 | { |
560 | /* Exception handlers are entered in 32-bit mode. */ | |
561 | env->hflags &= ~(MIPS_HFLAG_M16); | |
562 | /* ...except that microMIPS lets you choose. */ | |
563 | if (env->insn_flags & ASE_MICROMIPS) { | |
564 | env->hflags |= (!!(env->CP0_Config3 | |
565 | & (1 << CP0C3_ISA_ON_EXC)) | |
566 | << MIPS_HFLAG_M16_SHIFT); | |
567 | } | |
568 | } | |
aea14095 LA |
569 | |
570 | static inline void set_badinstr_registers(CPUMIPSState *env) | |
571 | { | |
572 | if (env->hflags & MIPS_HFLAG_M16) { | |
573 | /* TODO: add BadInstr support for microMIPS */ | |
574 | return; | |
575 | } | |
576 | if (env->CP0_Config3 & (1 << CP0C3_BI)) { | |
577 | env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC); | |
578 | } | |
579 | if ((env->CP0_Config3 & (1 << CP0C3_BP)) && | |
580 | (env->hflags & MIPS_HFLAG_BMASK)) { | |
581 | env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4); | |
582 | } | |
583 | } | |
32188a03 NF |
584 | #endif |
585 | ||
97a8ea5a | 586 | void mips_cpu_do_interrupt(CPUState *cs) |
6af0bf9c | 587 | { |
27103424 | 588 | #if !defined(CONFIG_USER_ONLY) |
97a8ea5a AF |
589 | MIPSCPU *cpu = MIPS_CPU(cs); |
590 | CPUMIPSState *env = &cpu->env; | |
aea14095 | 591 | bool update_badinstr = 0; |
932e71cd AJ |
592 | target_ulong offset; |
593 | int cause = -1; | |
594 | const char *name; | |
100ce988 | 595 | |
c8557016 RH |
596 | if (qemu_loglevel_mask(CPU_LOG_INT) |
597 | && cs->exception_index != EXCP_EXT_INTERRUPT) { | |
27103424 | 598 | if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) { |
932e71cd | 599 | name = "unknown"; |
27103424 AF |
600 | } else { |
601 | name = excp_names[cs->exception_index]; | |
602 | } | |
b67bfe8d | 603 | |
c8557016 RH |
604 | qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx |
605 | " %s exception\n", | |
93fcfe39 | 606 | __func__, env->active_tc.PC, env->CP0_EPC, name); |
932e71cd | 607 | } |
27103424 AF |
608 | if (cs->exception_index == EXCP_EXT_INTERRUPT && |
609 | (env->hflags & MIPS_HFLAG_DM)) { | |
610 | cs->exception_index = EXCP_DINT; | |
611 | } | |
932e71cd | 612 | offset = 0x180; |
27103424 | 613 | switch (cs->exception_index) { |
932e71cd AJ |
614 | case EXCP_DSS: |
615 | env->CP0_Debug |= 1 << CP0DB_DSS; | |
616 | /* Debug single step cannot be raised inside a delay slot and | |
617 | resume will always occur on the next instruction | |
618 | (but we assume the pc has always been updated during | |
619 | code translation). */ | |
32188a03 | 620 | env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16); |
932e71cd AJ |
621 | goto enter_debug_mode; |
622 | case EXCP_DINT: | |
623 | env->CP0_Debug |= 1 << CP0DB_DINT; | |
624 | goto set_DEPC; | |
625 | case EXCP_DIB: | |
626 | env->CP0_Debug |= 1 << CP0DB_DIB; | |
627 | goto set_DEPC; | |
628 | case EXCP_DBp: | |
629 | env->CP0_Debug |= 1 << CP0DB_DBp; | |
c6c2c0fc PD |
630 | /* Setup DExcCode - SDBBP instruction */ |
631 | env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC; | |
932e71cd AJ |
632 | goto set_DEPC; |
633 | case EXCP_DDBS: | |
634 | env->CP0_Debug |= 1 << CP0DB_DDBS; | |
635 | goto set_DEPC; | |
636 | case EXCP_DDBL: | |
637 | env->CP0_Debug |= 1 << CP0DB_DDBL; | |
638 | set_DEPC: | |
32188a03 NF |
639 | env->CP0_DEPC = exception_resume_pc(env); |
640 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
0eaef5aa | 641 | enter_debug_mode: |
d9224450 MR |
642 | if (env->insn_flags & ISA_MIPS3) { |
643 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
644 | if (!(env->insn_flags & ISA_MIPS64R6) || |
645 | env->CP0_Status & (1 << CP0St_KX)) { | |
646 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
647 | } | |
d9224450 MR |
648 | } |
649 | env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0; | |
932e71cd AJ |
650 | env->hflags &= ~(MIPS_HFLAG_KSU); |
651 | /* EJTAG probe trap enable is not implemented... */ | |
652 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 653 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
89777fd1 | 654 | env->active_tc.PC = env->exception_base + 0x480; |
bbfa8f72 | 655 | set_hflags_for_handler(env); |
932e71cd AJ |
656 | break; |
657 | case EXCP_RESET: | |
fca1be7c | 658 | cpu_reset(CPU(cpu)); |
932e71cd AJ |
659 | break; |
660 | case EXCP_SRESET: | |
661 | env->CP0_Status |= (1 << CP0St_SR); | |
9d989c73 | 662 | memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo)); |
932e71cd AJ |
663 | goto set_error_EPC; |
664 | case EXCP_NMI: | |
665 | env->CP0_Status |= (1 << CP0St_NMI); | |
0eaef5aa | 666 | set_error_EPC: |
32188a03 NF |
667 | env->CP0_ErrorEPC = exception_resume_pc(env); |
668 | env->hflags &= ~MIPS_HFLAG_BMASK; | |
932e71cd | 669 | env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV); |
d9224450 MR |
670 | if (env->insn_flags & ISA_MIPS3) { |
671 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
672 | if (!(env->insn_flags & ISA_MIPS64R6) || |
673 | env->CP0_Status & (1 << CP0St_KX)) { | |
674 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
675 | } | |
d9224450 MR |
676 | } |
677 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd AJ |
678 | env->hflags &= ~(MIPS_HFLAG_KSU); |
679 | if (!(env->CP0_Status & (1 << CP0St_EXL))) | |
f45cb2f4 | 680 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
89777fd1 | 681 | env->active_tc.PC = env->exception_base; |
bbfa8f72 | 682 | set_hflags_for_handler(env); |
932e71cd AJ |
683 | break; |
684 | case EXCP_EXT_INTERRUPT: | |
685 | cause = 0; | |
da52a4df YK |
686 | if (env->CP0_Cause & (1 << CP0Ca_IV)) { |
687 | uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f; | |
688 | ||
689 | if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) { | |
690 | offset = 0x200; | |
691 | } else { | |
692 | uint32_t vector = 0; | |
693 | uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP; | |
694 | ||
695 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { | |
696 | /* For VEIC mode, the external interrupt controller feeds | |
697 | * the vector through the CP0Cause IP lines. */ | |
698 | vector = pending; | |
699 | } else { | |
700 | /* Vectored Interrupts | |
701 | * Mask with Status.IM7-IM0 to get enabled interrupts. */ | |
702 | pending &= (env->CP0_Status >> CP0St_IM) & 0xff; | |
703 | /* Find the highest-priority interrupt. */ | |
704 | while (pending >>= 1) { | |
705 | vector++; | |
138afb02 | 706 | } |
138afb02 | 707 | } |
da52a4df | 708 | offset = 0x200 + (vector * (spacing << 5)); |
138afb02 | 709 | } |
138afb02 | 710 | } |
932e71cd AJ |
711 | goto set_EPC; |
712 | case EXCP_LTLBL: | |
713 | cause = 1; | |
aea14095 | 714 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
715 | goto set_EPC; |
716 | case EXCP_TLBL: | |
717 | cause = 2; | |
aea14095 LA |
718 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
719 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
720 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 721 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
722 | int R = env->CP0_BadVAddr >> 62; |
723 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
724 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
725 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 726 | |
3fc00a7b AJ |
727 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
728 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
729 | offset = 0x080; |
730 | else | |
0eaef5aa | 731 | #endif |
932e71cd AJ |
732 | offset = 0x000; |
733 | } | |
734 | goto set_EPC; | |
735 | case EXCP_TLBS: | |
736 | cause = 3; | |
aea14095 LA |
737 | update_badinstr = 1; |
738 | if ((env->error_code & EXCP_TLB_NOMATCH) && | |
739 | !(env->CP0_Status & (1 << CP0St_EXL))) { | |
0eaef5aa | 740 | #if defined(TARGET_MIPS64) |
932e71cd AJ |
741 | int R = env->CP0_BadVAddr >> 62; |
742 | int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; | |
743 | int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; | |
744 | int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; | |
0eaef5aa | 745 | |
3fc00a7b AJ |
746 | if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) && |
747 | (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) | |
932e71cd AJ |
748 | offset = 0x080; |
749 | else | |
0eaef5aa | 750 | #endif |
932e71cd AJ |
751 | offset = 0x000; |
752 | } | |
753 | goto set_EPC; | |
754 | case EXCP_AdEL: | |
755 | cause = 4; | |
aea14095 | 756 | update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL); |
932e71cd AJ |
757 | goto set_EPC; |
758 | case EXCP_AdES: | |
759 | cause = 5; | |
aea14095 | 760 | update_badinstr = 1; |
932e71cd AJ |
761 | goto set_EPC; |
762 | case EXCP_IBE: | |
763 | cause = 6; | |
764 | goto set_EPC; | |
765 | case EXCP_DBE: | |
766 | cause = 7; | |
767 | goto set_EPC; | |
768 | case EXCP_SYSCALL: | |
769 | cause = 8; | |
aea14095 | 770 | update_badinstr = 1; |
932e71cd AJ |
771 | goto set_EPC; |
772 | case EXCP_BREAK: | |
773 | cause = 9; | |
aea14095 | 774 | update_badinstr = 1; |
932e71cd AJ |
775 | goto set_EPC; |
776 | case EXCP_RI: | |
777 | cause = 10; | |
aea14095 | 778 | update_badinstr = 1; |
932e71cd AJ |
779 | goto set_EPC; |
780 | case EXCP_CpU: | |
781 | cause = 11; | |
aea14095 | 782 | update_badinstr = 1; |
932e71cd AJ |
783 | env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) | |
784 | (env->error_code << CP0Ca_CE); | |
785 | goto set_EPC; | |
786 | case EXCP_OVERFLOW: | |
787 | cause = 12; | |
aea14095 | 788 | update_badinstr = 1; |
932e71cd AJ |
789 | goto set_EPC; |
790 | case EXCP_TRAP: | |
791 | cause = 13; | |
aea14095 | 792 | update_badinstr = 1; |
932e71cd | 793 | goto set_EPC; |
b10ac204 YK |
794 | case EXCP_MSAFPE: |
795 | cause = 14; | |
796 | update_badinstr = 1; | |
797 | goto set_EPC; | |
932e71cd AJ |
798 | case EXCP_FPE: |
799 | cause = 15; | |
aea14095 | 800 | update_badinstr = 1; |
932e71cd AJ |
801 | goto set_EPC; |
802 | case EXCP_C2E: | |
803 | cause = 18; | |
804 | goto set_EPC; | |
92ceb440 LA |
805 | case EXCP_TLBRI: |
806 | cause = 19; | |
aea14095 | 807 | update_badinstr = 1; |
92ceb440 LA |
808 | goto set_EPC; |
809 | case EXCP_TLBXI: | |
810 | cause = 20; | |
811 | goto set_EPC; | |
b10ac204 YK |
812 | case EXCP_MSADIS: |
813 | cause = 21; | |
814 | update_badinstr = 1; | |
815 | goto set_EPC; | |
932e71cd AJ |
816 | case EXCP_MDMX: |
817 | cause = 22; | |
818 | goto set_EPC; | |
819 | case EXCP_DWATCH: | |
820 | cause = 23; | |
67cc32eb | 821 | /* XXX: TODO: manage deferred watch exceptions */ |
932e71cd AJ |
822 | goto set_EPC; |
823 | case EXCP_MCHECK: | |
824 | cause = 24; | |
825 | goto set_EPC; | |
826 | case EXCP_THREAD: | |
827 | cause = 25; | |
828 | goto set_EPC; | |
853c3240 JL |
829 | case EXCP_DSPDIS: |
830 | cause = 26; | |
831 | goto set_EPC; | |
932e71cd AJ |
832 | case EXCP_CACHE: |
833 | cause = 30; | |
74dbf824 | 834 | offset = 0x100; |
0eaef5aa | 835 | set_EPC: |
932e71cd | 836 | if (!(env->CP0_Status & (1 << CP0St_EXL))) { |
32188a03 | 837 | env->CP0_EPC = exception_resume_pc(env); |
aea14095 LA |
838 | if (update_badinstr) { |
839 | set_badinstr_registers(env); | |
840 | } | |
932e71cd | 841 | if (env->hflags & MIPS_HFLAG_BMASK) { |
f45cb2f4 | 842 | env->CP0_Cause |= (1U << CP0Ca_BD); |
0eaef5aa | 843 | } else { |
f45cb2f4 | 844 | env->CP0_Cause &= ~(1U << CP0Ca_BD); |
0eaef5aa | 845 | } |
932e71cd | 846 | env->CP0_Status |= (1 << CP0St_EXL); |
d9224450 MR |
847 | if (env->insn_flags & ISA_MIPS3) { |
848 | env->hflags |= MIPS_HFLAG_64; | |
7871abb9 JH |
849 | if (!(env->insn_flags & ISA_MIPS64R6) || |
850 | env->CP0_Status & (1 << CP0St_KX)) { | |
851 | env->hflags &= ~MIPS_HFLAG_AWRAP; | |
852 | } | |
d9224450 MR |
853 | } |
854 | env->hflags |= MIPS_HFLAG_CP0; | |
932e71cd | 855 | env->hflags &= ~(MIPS_HFLAG_KSU); |
6af0bf9c | 856 | } |
932e71cd AJ |
857 | env->hflags &= ~MIPS_HFLAG_BMASK; |
858 | if (env->CP0_Status & (1 << CP0St_BEV)) { | |
89777fd1 | 859 | env->active_tc.PC = env->exception_base + 0x200; |
74dbf824 JH |
860 | } else if (cause == 30 && !(env->CP0_Config3 & (1 << CP0C3_SC) && |
861 | env->CP0_Config5 & (1 << CP0C5_CV))) { | |
862 | /* Force KSeg1 for cache errors */ | |
863 | env->active_tc.PC = (int32_t)KSEG1_BASE | | |
864 | (env->CP0_EBase & 0x1FFFF000); | |
932e71cd | 865 | } else { |
74dbf824 | 866 | env->active_tc.PC = env->CP0_EBase & ~0xfff; |
6af0bf9c | 867 | } |
74dbf824 | 868 | |
932e71cd | 869 | env->active_tc.PC += offset; |
bbfa8f72 | 870 | set_hflags_for_handler(env); |
932e71cd AJ |
871 | env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC); |
872 | break; | |
873 | default: | |
c8557016 | 874 | abort(); |
932e71cd | 875 | } |
c8557016 RH |
876 | if (qemu_loglevel_mask(CPU_LOG_INT) |
877 | && cs->exception_index != EXCP_EXT_INTERRUPT) { | |
93fcfe39 | 878 | qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n" |
c8557016 RH |
879 | " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n", |
880 | __func__, env->active_tc.PC, env->CP0_EPC, cause, | |
881 | env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, | |
882 | env->CP0_DEPC); | |
6af0bf9c | 883 | } |
932e71cd | 884 | #endif |
27103424 | 885 | cs->exception_index = EXCP_NONE; |
6af0bf9c | 886 | } |
2ee4aed8 | 887 | |
fa4faba4 RH |
888 | bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
889 | { | |
890 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
891 | MIPSCPU *cpu = MIPS_CPU(cs); | |
892 | CPUMIPSState *env = &cpu->env; | |
893 | ||
71ca034a LA |
894 | if (cpu_mips_hw_interrupts_enabled(env) && |
895 | cpu_mips_hw_interrupts_pending(env)) { | |
fa4faba4 RH |
896 | /* Raise it */ |
897 | cs->exception_index = EXCP_EXT_INTERRUPT; | |
898 | env->error_code = 0; | |
899 | mips_cpu_do_interrupt(cs); | |
900 | return true; | |
901 | } | |
902 | } | |
903 | return false; | |
904 | } | |
905 | ||
3c7b48b7 | 906 | #if !defined(CONFIG_USER_ONLY) |
7db13fae | 907 | void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) |
2ee4aed8 | 908 | { |
31b030d4 AF |
909 | MIPSCPU *cpu = mips_env_get_cpu(env); |
910 | CPUState *cs; | |
c227f099 | 911 | r4k_tlb_t *tlb; |
3b1c8be4 TS |
912 | target_ulong addr; |
913 | target_ulong end; | |
2d72e7b0 | 914 | uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; |
3b1c8be4 | 915 | target_ulong mask; |
2ee4aed8 | 916 | |
ead9360e | 917 | tlb = &env->tlb->mmu.r4k.tlb[idx]; |
f2e9ebef | 918 | /* The qemu TLB is flushed when the ASID changes, so no need to |
2ee4aed8 FB |
919 | flush these entries again. */ |
920 | if (tlb->G == 0 && tlb->ASID != ASID) { | |
921 | return; | |
922 | } | |
923 | ||
ead9360e | 924 | if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) { |
2ee4aed8 | 925 | /* For tlbwr, we can shadow the discarded entry into |
6958549d AJ |
926 | a new (fake) TLB entry, as long as the guest can not |
927 | tell that it's there. */ | |
ead9360e TS |
928 | env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb; |
929 | env->tlb->tlb_in_use++; | |
2ee4aed8 FB |
930 | return; |
931 | } | |
932 | ||
3b1c8be4 | 933 | /* 1k pages are not supported. */ |
f2e9ebef | 934 | mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); |
3b1c8be4 | 935 | if (tlb->V0) { |
31b030d4 | 936 | cs = CPU(cpu); |
f2e9ebef | 937 | addr = tlb->VPN & ~mask; |
d26bc211 | 938 | #if defined(TARGET_MIPS64) |
e034e2c3 | 939 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
940 | addr |= 0x3FFFFF0000000000ULL; |
941 | } | |
942 | #endif | |
3b1c8be4 TS |
943 | end = addr | (mask >> 1); |
944 | while (addr < end) { | |
31b030d4 | 945 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
946 | addr += TARGET_PAGE_SIZE; |
947 | } | |
948 | } | |
949 | if (tlb->V1) { | |
31b030d4 | 950 | cs = CPU(cpu); |
f2e9ebef | 951 | addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1); |
d26bc211 | 952 | #if defined(TARGET_MIPS64) |
e034e2c3 | 953 | if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) { |
100ce988 TS |
954 | addr |= 0x3FFFFF0000000000ULL; |
955 | } | |
956 | #endif | |
3b1c8be4 | 957 | end = addr | mask; |
53715e48 | 958 | while (addr - 1 < end) { |
31b030d4 | 959 | tlb_flush_page(cs, addr); |
3b1c8be4 TS |
960 | addr += TARGET_PAGE_SIZE; |
961 | } | |
962 | } | |
2ee4aed8 | 963 | } |
3c7b48b7 | 964 | #endif |
33c11879 PB |
965 | |
966 | void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, | |
967 | uint32_t exception, | |
968 | int error_code, | |
969 | uintptr_t pc) | |
970 | { | |
971 | CPUState *cs = CPU(mips_env_get_cpu(env)); | |
972 | ||
973 | if (exception < EXCP_SC) { | |
974 | qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", | |
975 | __func__, exception, error_code); | |
976 | } | |
977 | cs->exception_index = exception; | |
978 | env->error_code = error_code; | |
979 | ||
980 | cpu_loop_exit_restore(cs, pc); | |
981 | } |