[mirror_qemu.git] / target / mips / internal.h

/*
 * MIPS internal definitions and helpers
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#ifndef MIPS_INTERNAL_H
#define MIPS_INTERNAL_H

#include "exec/memattrs.h"

/*
 * MMU types, the first four entries have the same layout as the
 * CP0C0_MT field.
 */
enum mips_mmu_types {
    MMU_TYPE_NONE       = 0,
    MMU_TYPE_R4000      = 1,    /* Standard TLB */
    MMU_TYPE_BAT        = 2,    /* Block Address Translation */
    MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
    MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
    MMU_TYPE_R3000,
    MMU_TYPE_R6000,
    MMU_TYPE_R8000
};

struct mips_def_t {
    const char *name;
    int32_t CP0_PRid;
    int32_t CP0_Config0;
    int32_t CP0_Config1;
    int32_t CP0_Config2;
    int32_t CP0_Config3;
    int32_t CP0_Config4;
    int32_t CP0_Config4_rw_bitmask;
    int32_t CP0_Config5;
    int32_t CP0_Config5_rw_bitmask;
    int32_t CP0_Config6;
    int32_t CP0_Config6_rw_bitmask;
    int32_t CP0_Config7;
    int32_t CP0_Config7_rw_bitmask;
    target_ulong CP0_LLAddr_rw_bitmask;
    int CP0_LLAddr_shift;
    int32_t SYNCI_Step;
    int32_t CCRes;
    int32_t CP0_Status_rw_bitmask;
    int32_t CP0_TCStatus_rw_bitmask;
    int32_t CP0_SRSCtl;
    int32_t CP1_fcr0;
    int32_t CP1_fcr31_rw_bitmask;
    int32_t CP1_fcr31;
    int32_t MSAIR;
    int32_t SEGBITS;
    int32_t PABITS;
    int32_t CP0_SRSConf0_rw_bitmask;
    int32_t CP0_SRSConf0;
    int32_t CP0_SRSConf1_rw_bitmask;
    int32_t CP0_SRSConf1;
    int32_t CP0_SRSConf2_rw_bitmask;
    int32_t CP0_SRSConf2;
    int32_t CP0_SRSConf3_rw_bitmask;
    int32_t CP0_SRSConf3;
    int32_t CP0_SRSConf4_rw_bitmask;
    int32_t CP0_SRSConf4;
    int32_t CP0_PageGrain_rw_bitmask;
    int32_t CP0_PageGrain;
    target_ulong CP0_EBaseWG_rw_bitmask;
    uint64_t insn_flags;
    enum mips_mmu_types mmu_type;
    int32_t SAARP;
};

extern const char * const regnames[32];
extern const char * const fregnames[32];

extern const struct mips_def_t mips_defs[];
extern const int mips_defs_number;

void mips_cpu_do_interrupt(CPUState *cpu);
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
                                  MMUAccessType access_type,
                                  int mmu_idx, uintptr_t retaddr);

#if !defined(CONFIG_USER_ONLY)

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint16_t ASID;
    uint32_t MMID;
    unsigned int G:1;
    unsigned int C0:3;
    unsigned int C1:3;
    unsigned int V0:1;
    unsigned int V1:1;
    unsigned int D0:1;
    unsigned int D1:1;
    unsigned int XI0:1;
    unsigned int XI1:1;
    unsigned int RI0:1;
    unsigned int RI1:1;
    unsigned int EHINV:1;
    uint64_t PFN[2];
};

struct CPUMIPSTLBContext {
    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
                       target_ulong address, MMUAccessType access_type);
    void (*helper_tlbwi)(struct CPUMIPSState *env);
    void (*helper_tlbwr)(struct CPUMIPSState *env);
    void (*helper_tlbp)(struct CPUMIPSState *env);
    void (*helper_tlbr)(struct CPUMIPSState *env);
    void (*helper_tlbinv)(struct CPUMIPSState *env);
    void (*helper_tlbinvf)(struct CPUMIPSState *env);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;
};

int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                       target_ulong address, MMUAccessType access_type);
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                          target_ulong address, MMUAccessType access_type);
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                    target_ulong address, MMUAccessType access_type);
void r4k_helper_tlbwi(CPUMIPSState *env);
void r4k_helper_tlbwr(CPUMIPSState *env);
void r4k_helper_tlbp(CPUMIPSState *env);
void r4k_helper_tlbr(CPUMIPSState *env);
void r4k_helper_tlbinv(CPUMIPSState *env);
void r4k_helper_tlbinvf(CPUMIPSState *env);
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
uint32_t cpu_mips_get_random(CPUMIPSState *env);

void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                    vaddr addr, unsigned size,
                                    MMUAccessType access_type,
                                    int mmu_idx, MemTxAttrs attrs,
                                    MemTxResult response, uintptr_t retaddr);
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
                                  MMUAccessType access_type);
#endif

#define cpu_signal_handler cpu_mips_signal_handler

#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_mips_cpu;
#endif

static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
{
    return (env->CP0_Status & (1 << CP0St_IE)) &&
        !(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM) &&
        /*
         * Note that the TCStatus IXMT field is initialized to zero,
         * and only MT capable cores can set it to one. So we don't
         * need to check for MT capabilities here.
         */
        !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
}

/* Check if there is pending and not masked out interrupt */
static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
{
    int32_t pending;
    int32_t status;
    bool r;

    pending = env->CP0_Cause & CP0Ca_IP_mask;
    status = env->CP0_Status & CP0Ca_IP_mask;

    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
        /*
         * A MIPS configured with a vectorizing external interrupt controller
         * will feed a vector into the Cause pending lines. The core treats
         * the status lines as a vector level, not as individual masks.
         */
        r = pending > status;
    } else {
        /*
         * A MIPS configured with compatibility or VInt (Vectored Interrupts)
         * treats the pending lines as individual interrupt lines, the status
         * lines are individual masks.
         */
        r = (pending & status) != 0;
    }
    return r;
}

void mips_tcg_init(void);

void msa_reset(CPUMIPSState *env);

/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);

/* helper.c */
void mmu_init(CPUMIPSState *env, const mips_def_t *def);
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);

/* op_helper.c */
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);

static inline void restore_pamask(CPUMIPSState *env)
{
    if (env->hflags & MIPS_HFLAG_ELPA) {
        env->PAMask = (1ULL << env->PABITS) - 1;
    } else {
        env->PAMask = PAMASK_BASE;
    }
}

static inline int mips_vpe_active(CPUMIPSState *env)
{
    int active = 1;

    /* Check that the VPE is enabled.  */
    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
        active = 0;
    }
    /* Check that the VPE is activated.  */
    if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
        active = 0;
    }

    /*
     * Now verify that there are active thread contexts in the VPE.
     *
     * This assumes the CPU model will internally reschedule threads
     * if the active one goes to sleep. If there are no threads available
     * the active one will be in a sleeping state, and we can turn off
     * the entire VPE.
     */
    if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
        /* TC is not activated.  */
        active = 0;
    }
    if (env->active_tc.CP0_TCHalt & 1) {
        /* TC is in halt state.  */
        active = 0;
    }

    return active;
}

static inline int mips_vp_active(CPUMIPSState *env)
{
    CPUState *other_cs = first_cpu;

    /* Check if the VP disabled other VPs (which means the VP is enabled) */
    if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
        return 1;
    }

    /* Check if the virtual processor is disabled due to a DVP */
    CPU_FOREACH(other_cs) {
        MIPSCPU *other_cpu = MIPS_CPU(other_cs);
        if ((&other_cpu->env != env) &&
            ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
            return 0;
        }
    }
    return 1;
}

static inline void compute_hflags(CPUMIPSState *env)
{
    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                     MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
    if (env->CP0_Status & (1 << CP0St_ERL)) {
        env->hflags |= MIPS_HFLAG_ERL;
    }
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM)) {
        env->hflags |= (env->CP0_Status >> CP0St_KSU) &
                       MIPS_HFLAG_KSU;
    }
#if defined(TARGET_MIPS64)
    if ((env->insn_flags & ISA_MIPS3) &&
        (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
         (env->CP0_Status & (1 << CP0St_PX)) ||
         (env->CP0_Status & (1 << CP0St_UX)))) {
        env->hflags |= MIPS_HFLAG_64;
    }

    if (!(env->insn_flags & ISA_MIPS3)) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
               !(env->CP0_Status & (1 << CP0St_UX))) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (env->insn_flags & ISA_MIPS_R6) {
        /* Address wrapping for Supervisor and Kernel is specified in R6 */
        if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
             !(env->CP0_Status & (1 << CP0St_SX))) ||
            (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
             !(env->CP0_Status & (1 << CP0St_KX)))) {
            env->hflags |= MIPS_HFLAG_AWRAP;
        }
    }
#endif
    if (((env->CP0_Status & (1 << CP0St_CU0)) &&
         !(env->insn_flags & ISA_MIPS_R6)) ||
        !(env->hflags & MIPS_HFLAG_KSU)) {
        env->hflags |= MIPS_HFLAG_CP0;
    }
    if (env->CP0_Status & (1 << CP0St_CU1)) {
        env->hflags |= MIPS_HFLAG_FPU;
    }
    if (env->CP0_Status & (1 << CP0St_FR)) {
        env->hflags |= MIPS_HFLAG_F64;
    }
    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
        (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
        env->hflags |= MIPS_HFLAG_SBRI;
    }
    if (env->insn_flags & ASE_DSP_R3) {
        /*
         * Our cpu supports DSP R3 ASE, so enable
         * access to DSP R3 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                           MIPS_HFLAG_DSP_R3;
        }
    } else if (env->insn_flags & ASE_DSP_R2) {
        /*
         * Our cpu supports DSP R2 ASE, so enable
         * access to DSP R2 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
        }

    } else if (env->insn_flags & ASE_DSP) {
        /*
         * Our cpu supports DSP ASE, so enable
         * access to DSP resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP;
        }

    }
    if (env->insn_flags & ISA_MIPS_R2) {
        if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS_R1) {
        if (env->hflags & MIPS_HFLAG_64) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS4) {
        /*
         * All supported MIPS IV CPUs use the XX (CU3) to enable
         * and disable the MIPS IV extensions to the MIPS III ISA.
         * Some other MIPS IV CPUs ignore the bit, so the check here
         * would be too restrictive for them.
         */
        if (env->CP0_Status & (1U << CP0St_CU3)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    }
    if (ase_msa_available(env)) {
        if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
            env->hflags |= MIPS_HFLAG_MSA;
        }
    }
    if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
        if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
            env->hflags |= MIPS_HFLAG_FRE;
        }
    }
    if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
        if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
            env->hflags |= MIPS_HFLAG_ELPA;
        }
    }
}

void cpu_mips_tlb_flush(CPUMIPSState *env);
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);

const char *mips_exception_name(int32_t exception);

void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
                                          int error_code, uintptr_t pc);

static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
                                                    uint32_t exception,
                                                    uintptr_t pc)
{
    do_raise_exception_err(env, exception, 0, pc);
}

#endif
Commit	Line	Data
7ba0e95b AM	1	/*
7ba0e95b AM	2	* MIPS internal definitions and helpers
26aa3d9a PMD	3	*
	4	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#ifndef MIPS_INTERNAL_H
	9	#define MIPS_INTERNAL_H
	10
34cffe96	11	#include "exec/memattrs.h"
41da212c	12
7ba0e95b AM	13	/*
	14	* MMU types, the first four entries have the same layout as the
	15	* CP0C0_MT field.
	16	*/
41da212c	17	enum mips_mmu_types {
1ab3a0de PMD	18	MMU_TYPE_NONE = 0,
	19	MMU_TYPE_R4000 = 1, /* Standard TLB */
	20	MMU_TYPE_BAT = 2, /* Block Address Translation */
	21	MMU_TYPE_FMT = 3, /* Fixed Mapping */
	22	MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */
41da212c IM	23	MMU_TYPE_R3000,
	24	MMU_TYPE_R6000,
	25	MMU_TYPE_R8000
	26	};
	27
	28	struct mips_def_t {
	29	const char *name;
	30	int32_t CP0_PRid;
	31	int32_t CP0_Config0;
	32	int32_t CP0_Config1;
	33	int32_t CP0_Config2;
	34	int32_t CP0_Config3;
	35	int32_t CP0_Config4;
	36	int32_t CP0_Config4_rw_bitmask;
	37	int32_t CP0_Config5;
	38	int32_t CP0_Config5_rw_bitmask;
	39	int32_t CP0_Config6;
af868995	40	int32_t CP0_Config6_rw_bitmask;
41da212c	41	int32_t CP0_Config7;
af868995	42	int32_t CP0_Config7_rw_bitmask;
41da212c IM	43	target_ulong CP0_LLAddr_rw_bitmask;
	44	int CP0_LLAddr_shift;
	45	int32_t SYNCI_Step;
	46	int32_t CCRes;
	47	int32_t CP0_Status_rw_bitmask;
	48	int32_t CP0_TCStatus_rw_bitmask;
	49	int32_t CP0_SRSCtl;
	50	int32_t CP1_fcr0;
	51	int32_t CP1_fcr31_rw_bitmask;
	52	int32_t CP1_fcr31;
	53	int32_t MSAIR;
	54	int32_t SEGBITS;
	55	int32_t PABITS;
	56	int32_t CP0_SRSConf0_rw_bitmask;
	57	int32_t CP0_SRSConf0;
	58	int32_t CP0_SRSConf1_rw_bitmask;
	59	int32_t CP0_SRSConf1;
	60	int32_t CP0_SRSConf2_rw_bitmask;
	61	int32_t CP0_SRSConf2;
	62	int32_t CP0_SRSConf3_rw_bitmask;
	63	int32_t CP0_SRSConf3;
	64	int32_t CP0_SRSConf4_rw_bitmask;
	65	int32_t CP0_SRSConf4;
	66	int32_t CP0_PageGrain_rw_bitmask;
	67	int32_t CP0_PageGrain;
	68	target_ulong CP0_EBaseWG_rw_bitmask;
f9c9cd63	69	uint64_t insn_flags;
41da212c	70	enum mips_mmu_types mmu_type;
5fb2dcd1	71	int32_t SAARP;
41da212c IM	72	};
41da212c IM	73
adbf1be3 PMD	74	extern const char * const regnames[32];
	75	extern const char * const fregnames[32];
	76
41da212c IM	77	extern const struct mips_def_t mips_defs[];
	78	extern const int mips_defs_number;
	79
26aa3d9a PMD	80	void mips_cpu_do_interrupt(CPUState *cpu);
26aa3d9a PMD	81	bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
90c84c56	82	void mips_cpu_dump_state(CPUState cpu, FILE f, int flags);
26aa3d9a	83	hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
a010bdbe	84	int mips_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
26aa3d9a PMD	85	int mips_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	86	void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
	87	MMUAccessType access_type,
	88	int mmu_idx, uintptr_t retaddr);
	89
	90	#if !defined(CONFIG_USER_ONLY)
	91
	92	typedef struct r4k_tlb_t r4k_tlb_t;
	93	struct r4k_tlb_t {
	94	target_ulong VPN;
	95	uint32_t PageMask;
	96	uint16_t ASID;
99029be1	97	uint32_t MMID;
26aa3d9a PMD	98	unsigned int G:1;
	99	unsigned int C0:3;
	100	unsigned int C1:3;
	101	unsigned int V0:1;
	102	unsigned int V1:1;
	103	unsigned int D0:1;
	104	unsigned int D1:1;
	105	unsigned int XI0:1;
	106	unsigned int XI1:1;
	107	unsigned int RI0:1;
	108	unsigned int RI1:1;
	109	unsigned int EHINV:1;
	110	uint64_t PFN[2];
	111	};
	112
	113	struct CPUMIPSTLBContext {
	114	uint32_t nb_tlb;
	115	uint32_t tlb_in_use;
	116	int (map_address)(struct CPUMIPSState env, hwaddr physical, int prot,
edbd4992	117	target_ulong address, MMUAccessType access_type);
26aa3d9a PMD	118	void (helper_tlbwi)(struct CPUMIPSState env);
	119	void (helper_tlbwr)(struct CPUMIPSState env);
	120	void (helper_tlbp)(struct CPUMIPSState env);
	121	void (helper_tlbr)(struct CPUMIPSState env);
	122	void (helper_tlbinv)(struct CPUMIPSState env);
	123	void (helper_tlbinvf)(struct CPUMIPSState env);
	124	union {
	125	struct {
	126	r4k_tlb_t tlb[MIPS_TLB_MAX];
	127	} r4k;
	128	} mmu;
	129	};
	130
	131	int no_mmu_map_address(CPUMIPSState env, hwaddr physical, int *prot,
edbd4992	132	target_ulong address, MMUAccessType access_type);
26aa3d9a	133	int fixed_mmu_map_address(CPUMIPSState env, hwaddr physical, int *prot,
edbd4992	134	target_ulong address, MMUAccessType access_type);
26aa3d9a	135	int r4k_map_address(CPUMIPSState env, hwaddr physical, int *prot,
edbd4992	136	target_ulong address, MMUAccessType access_type);
26aa3d9a PMD	137	void r4k_helper_tlbwi(CPUMIPSState *env);
	138	void r4k_helper_tlbwr(CPUMIPSState *env);
	139	void r4k_helper_tlbp(CPUMIPSState *env);
	140	void r4k_helper_tlbr(CPUMIPSState *env);
	141	void r4k_helper_tlbinv(CPUMIPSState *env);
	142	void r4k_helper_tlbinvf(CPUMIPSState *env);
	143	void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
2dc29222	144	uint32_t cpu_mips_get_random(CPUMIPSState *env);
26aa3d9a	145
4f02a06d PM	146	void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
	147	vaddr addr, unsigned size,
	148	MMUAccessType access_type,
	149	int mmu_idx, MemTxAttrs attrs,
	150	MemTxResult response, uintptr_t retaddr);
26aa3d9a	151	hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
48b28c6a	152	MMUAccessType access_type);
26aa3d9a PMD	153	#endif
	154
	155	#define cpu_signal_handler cpu_mips_signal_handler
	156
	157	#ifndef CONFIG_USER_ONLY
8a9358cc	158	extern const VMStateDescription vmstate_mips_cpu;
26aa3d9a PMD	159	#endif
	160
	161	static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
	162	{
	163	return (env->CP0_Status & (1 << CP0St_IE)) &&
	164	!(env->CP0_Status & (1 << CP0St_EXL)) &&
	165	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	166	!(env->hflags & MIPS_HFLAG_DM) &&
7ba0e95b AM	167	/*
	168	* Note that the TCStatus IXMT field is initialized to zero,
	169	* and only MT capable cores can set it to one. So we don't
	170	* need to check for MT capabilities here.
	171	*/
26aa3d9a PMD	172	!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
	173	}
	174
	175	/* Check if there is pending and not masked out interrupt */
	176	static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
	177	{
	178	int32_t pending;
	179	int32_t status;
	180	bool r;
	181
	182	pending = env->CP0_Cause & CP0Ca_IP_mask;
	183	status = env->CP0_Status & CP0Ca_IP_mask;
	184
	185	if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
7ba0e95b AM	186	/*
	187	* A MIPS configured with a vectorizing external interrupt controller
	188	* will feed a vector into the Cause pending lines. The core treats
8cdf8869	189	* the status lines as a vector level, not as individual masks.
7ba0e95b	190	*/
26aa3d9a PMD	191	r = pending > status;
26aa3d9a PMD	192	} else {
7ba0e95b AM	193	/*
	194	* A MIPS configured with compatibility or VInt (Vectored Interrupts)
	195	* treats the pending lines as individual interrupt lines, the status
	196	* lines are individual masks.
	197	*/
26aa3d9a PMD	198	r = (pending & status) != 0;
	199	}
	200	return r;
	201	}
	202
	203	void mips_tcg_init(void);
	204
03e4d95c PMD	205	void msa_reset(CPUMIPSState *env);
03e4d95c PMD	206
26aa3d9a	207	/* cp0_timer.c */
26aa3d9a PMD	208	uint32_t cpu_mips_get_count(CPUMIPSState *env);
	209	void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
	210	void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
	211	void cpu_mips_start_count(CPUMIPSState *env);
	212	void cpu_mips_stop_count(CPUMIPSState *env);
	213
	214	/* helper.c */
f2c5b39e	215	void mmu_init(CPUMIPSState env, const mips_def_t def);
931d019f RH	216	bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	217	MMUAccessType access_type, int mmu_idx,
	218	bool probe, uintptr_t retaddr);
26aa3d9a PMD	219
26aa3d9a PMD	220	/* op_helper.c */
074cfcb4	221	void update_pagemask(CPUMIPSState env, target_ulong arg1, int32_t pagemask);
26aa3d9a	222
26aa3d9a PMD	223	static inline void restore_pamask(CPUMIPSState *env)
	224	{
	225	if (env->hflags & MIPS_HFLAG_ELPA) {
	226	env->PAMask = (1ULL << env->PABITS) - 1;
	227	} else {
	228	env->PAMask = PAMASK_BASE;
	229	}
	230	}
	231
	232	static inline int mips_vpe_active(CPUMIPSState *env)
	233	{
	234	int active = 1;
	235
	236	/* Check that the VPE is enabled. */
	237	if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
	238	active = 0;
	239	}
	240	/* Check that the VPE is activated. */
	241	if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
	242	active = 0;
	243	}
	244
7ba0e95b AM	245	/*
	246	* Now verify that there are active thread contexts in the VPE.
	247	*
	248	* This assumes the CPU model will internally reschedule threads
	249	* if the active one goes to sleep. If there are no threads available
	250	* the active one will be in a sleeping state, and we can turn off
	251	* the entire VPE.
	252	*/
26aa3d9a PMD	253	if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
	254	/* TC is not activated. */
	255	active = 0;
	256	}
	257	if (env->active_tc.CP0_TCHalt & 1) {
	258	/* TC is in halt state. */
	259	active = 0;
	260	}
	261
	262	return active;
	263	}
	264
	265	static inline int mips_vp_active(CPUMIPSState *env)
	266	{
	267	CPUState *other_cs = first_cpu;
	268
	269	/* Check if the VP disabled other VPs (which means the VP is enabled) */
	270	if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
	271	return 1;
	272	}
	273
	274	/* Check if the virtual processor is disabled due to a DVP */
	275	CPU_FOREACH(other_cs) {
	276	MIPSCPU *other_cpu = MIPS_CPU(other_cs);
	277	if ((&other_cpu->env != env) &&
	278	((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
	279	return 0;
	280	}
	281	}
	282	return 1;
	283	}
	284
	285	static inline void compute_hflags(CPUMIPSState *env)
	286	{
	287	env->hflags &= ~(MIPS_HFLAG_COP1X \| MIPS_HFLAG_64 \| MIPS_HFLAG_CP0 \|
	288	MIPS_HFLAG_F64 \| MIPS_HFLAG_FPU \| MIPS_HFLAG_KSU \|
908f6be1 SM	289	MIPS_HFLAG_AWRAP \| MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	290	MIPS_HFLAG_DSP_R3 \| MIPS_HFLAG_SBRI \| MIPS_HFLAG_MSA \|
59e781fb	291	MIPS_HFLAG_FRE \| MIPS_HFLAG_ELPA \| MIPS_HFLAG_ERL);
26aa3d9a PMD	292	if (env->CP0_Status & (1 << CP0St_ERL)) {
	293	env->hflags \|= MIPS_HFLAG_ERL;
	294	}
	295	if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
	296	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	297	!(env->hflags & MIPS_HFLAG_DM)) {
7ba0e95b AM	298	env->hflags \|= (env->CP0_Status >> CP0St_KSU) &
7ba0e95b AM	299	MIPS_HFLAG_KSU;
26aa3d9a PMD	300	}
	301	#if defined(TARGET_MIPS64)
	302	if ((env->insn_flags & ISA_MIPS3) &&
	303	(((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) \|\|
	304	(env->CP0_Status & (1 << CP0St_PX)) \|\|
	305	(env->CP0_Status & (1 << CP0St_UX)))) {
	306	env->hflags \|= MIPS_HFLAG_64;
	307	}
	308
	309	if (!(env->insn_flags & ISA_MIPS3)) {
	310	env->hflags \|= MIPS_HFLAG_AWRAP;
	311	} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
	312	!(env->CP0_Status & (1 << CP0St_UX))) {
	313	env->hflags \|= MIPS_HFLAG_AWRAP;
2e211e0a	314	} else if (env->insn_flags & ISA_MIPS_R6) {
26aa3d9a PMD	315	/* Address wrapping for Supervisor and Kernel is specified in R6 */
	316	if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
	317	!(env->CP0_Status & (1 << CP0St_SX))) \|\|
	318	(((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
	319	!(env->CP0_Status & (1 << CP0St_KX)))) {
	320	env->hflags \|= MIPS_HFLAG_AWRAP;
	321	}
	322	}
	323	#endif
	324	if (((env->CP0_Status & (1 << CP0St_CU0)) &&
2e211e0a	325	!(env->insn_flags & ISA_MIPS_R6)) \|\|
26aa3d9a PMD	326	!(env->hflags & MIPS_HFLAG_KSU)) {
	327	env->hflags \|= MIPS_HFLAG_CP0;
	328	}
	329	if (env->CP0_Status & (1 << CP0St_CU1)) {
	330	env->hflags \|= MIPS_HFLAG_FPU;
	331	}
	332	if (env->CP0_Status & (1 << CP0St_FR)) {
	333	env->hflags \|= MIPS_HFLAG_F64;
	334	}
	335	if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
	336	(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
	337	env->hflags \|= MIPS_HFLAG_SBRI;
	338	}
908f6be1 SM	339	if (env->insn_flags & ASE_DSP_R3) {
	340	/*
	341	* Our cpu supports DSP R3 ASE, so enable
	342	* access to DSP R3 resources.
	343	*/
59e781fb	344	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1 SM	345	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	346	MIPS_HFLAG_DSP_R3;
59e781fb	347	}
908f6be1 SM	348	} else if (env->insn_flags & ASE_DSP_R2) {
	349	/*
	350	* Our cpu supports DSP R2 ASE, so enable
	351	* access to DSP R2 resources.
	352	*/
26aa3d9a	353	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1	354	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2;
26aa3d9a PMD	355	}
	356
	357	} else if (env->insn_flags & ASE_DSP) {
908f6be1 SM	358	/*
	359	* Our cpu supports DSP ASE, so enable
	360	* access to DSP resources.
	361	*/
26aa3d9a PMD	362	if (env->CP0_Status & (1 << CP0St_MX)) {
	363	env->hflags \|= MIPS_HFLAG_DSP;
	364	}
	365
	366	}
7a47bae5	367	if (env->insn_flags & ISA_MIPS_R2) {
26aa3d9a PMD	368	if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
	369	env->hflags \|= MIPS_HFLAG_COP1X;
	370	}
bbd5e4a2	371	} else if (env->insn_flags & ISA_MIPS_R1) {
26aa3d9a PMD	372	if (env->hflags & MIPS_HFLAG_64) {
	373	env->hflags \|= MIPS_HFLAG_COP1X;
	374	}
	375	} else if (env->insn_flags & ISA_MIPS4) {
7ba0e95b AM	376	/*
	377	* All supported MIPS IV CPUs use the XX (CU3) to enable
	378	* and disable the MIPS IV extensions to the MIPS III ISA.
	379	* Some other MIPS IV CPUs ignore the bit, so the check here
	380	* would be too restrictive for them.
	381	*/
26aa3d9a PMD	382	if (env->CP0_Status & (1U << CP0St_CU3)) {
	383	env->hflags \|= MIPS_HFLAG_COP1X;
	384	}
	385	}
aa314198	386	if (ase_msa_available(env)) {
26aa3d9a PMD	387	if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
	388	env->hflags \|= MIPS_HFLAG_MSA;
	389	}
	390	}
	391	if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
	392	if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
	393	env->hflags \|= MIPS_HFLAG_FRE;
	394	}
	395	}
	396	if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
	397	if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
	398	env->hflags \|= MIPS_HFLAG_ELPA;
	399	}
	400	}
	401	}
	402
	403	void cpu_mips_tlb_flush(CPUMIPSState *env);
	404	void sync_c0_status(CPUMIPSState env, CPUMIPSState cpu, int tc);
	405	void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
	406	void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
	407
e9927723 PMD	408	const char *mips_exception_name(int32_t exception);
e9927723 PMD	409
26aa3d9a PMD	410	void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
	411	int error_code, uintptr_t pc);
	412
	413	static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
	414	uint32_t exception,
	415	uintptr_t pc)
	416	{
	417	do_raise_exception_err(env, exception, 0, pc);
	418	}
	419
	420	#endif