[mirror_qemu.git] / target / mips / internal.h

/*
 * MIPS internal definitions and helpers
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#ifndef MIPS_INTERNAL_H
#define MIPS_INTERNAL_H

#include "exec/memattrs.h"
#ifdef CONFIG_TCG
#include "tcg/tcg-internal.h"
#endif

/*
 * MMU types, the first four entries have the same layout as the
 * CP0C0_MT field.
 */
enum mips_mmu_types {
    MMU_TYPE_NONE       = 0,
    MMU_TYPE_R4000      = 1,    /* Standard TLB */
    MMU_TYPE_BAT        = 2,    /* Block Address Translation */
    MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
    MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
    MMU_TYPE_R3000,
    MMU_TYPE_R6000,
    MMU_TYPE_R8000
};

struct mips_def_t {
    const char *name;
    int32_t CP0_PRid;
    int32_t CP0_Config0;
    int32_t CP0_Config1;
    int32_t CP0_Config2;
    int32_t CP0_Config3;
    int32_t CP0_Config4;
    int32_t CP0_Config4_rw_bitmask;
    int32_t CP0_Config5;
    int32_t CP0_Config5_rw_bitmask;
    int32_t CP0_Config6;
    int32_t CP0_Config6_rw_bitmask;
    int32_t CP0_Config7;
    int32_t CP0_Config7_rw_bitmask;
    target_ulong CP0_LLAddr_rw_bitmask;
    int CP0_LLAddr_shift;
    int32_t SYNCI_Step;
    int32_t CCRes;
    int32_t CP0_Status_rw_bitmask;
    int32_t CP0_TCStatus_rw_bitmask;
    int32_t CP0_SRSCtl;
    int32_t CP1_fcr0;
    int32_t CP1_fcr31_rw_bitmask;
    int32_t CP1_fcr31;
    int32_t MSAIR;
    int32_t SEGBITS;
    int32_t PABITS;
    int32_t CP0_SRSConf0_rw_bitmask;
    int32_t CP0_SRSConf0;
    int32_t CP0_SRSConf1_rw_bitmask;
    int32_t CP0_SRSConf1;
    int32_t CP0_SRSConf2_rw_bitmask;
    int32_t CP0_SRSConf2;
    int32_t CP0_SRSConf3_rw_bitmask;
    int32_t CP0_SRSConf3;
    int32_t CP0_SRSConf4_rw_bitmask;
    int32_t CP0_SRSConf4;
    int32_t CP0_PageGrain_rw_bitmask;
    int32_t CP0_PageGrain;
    target_ulong CP0_EBaseWG_rw_bitmask;
    uint64_t insn_flags;
    enum mips_mmu_types mmu_type;
    int32_t SAARP;
};

extern const char regnames[32][3];
extern const char fregnames[32][4];

extern const struct mips_def_t mips_defs[];
extern const int mips_defs_number;

int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);

#define USEG_LIMIT      ((target_ulong)(int32_t)0x7FFFFFFFUL)
#define KSEG0_BASE      ((target_ulong)(int32_t)0x80000000UL)
#define KSEG1_BASE      ((target_ulong)(int32_t)0xA0000000UL)
#define KSEG2_BASE      ((target_ulong)(int32_t)0xC0000000UL)
#define KSEG3_BASE      ((target_ulong)(int32_t)0xE0000000UL)

#define KVM_KSEG0_BASE  ((target_ulong)(int32_t)0x40000000UL)
#define KVM_KSEG2_BASE  ((target_ulong)(int32_t)0x60000000UL)

#if !defined(CONFIG_USER_ONLY)

enum {
    TLBRET_XI = -6,
    TLBRET_RI = -5,
    TLBRET_DIRTY = -4,
    TLBRET_INVALID = -3,
    TLBRET_NOMATCH = -2,
    TLBRET_BADADDR = -1,
    TLBRET_MATCH = 0
};

int get_physical_address(CPUMIPSState *env, hwaddr *physical,
                         int *prot, target_ulong real_address,
                         MMUAccessType access_type, int mmu_idx);
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint16_t ASID;
    uint32_t MMID;
    unsigned int G:1;
    unsigned int C0:3;
    unsigned int C1:3;
    unsigned int V0:1;
    unsigned int V1:1;
    unsigned int D0:1;
    unsigned int D1:1;
    unsigned int XI0:1;
    unsigned int XI1:1;
    unsigned int RI0:1;
    unsigned int RI1:1;
    unsigned int EHINV:1;
    uint64_t PFN[2];
};

struct CPUMIPSTLBContext {
    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
                       target_ulong address, MMUAccessType access_type);
    void (*helper_tlbwi)(struct CPUMIPSState *env);
    void (*helper_tlbwr)(struct CPUMIPSState *env);
    void (*helper_tlbp)(struct CPUMIPSState *env);
    void (*helper_tlbr)(struct CPUMIPSState *env);
    void (*helper_tlbinv)(struct CPUMIPSState *env);
    void (*helper_tlbinvf)(struct CPUMIPSState *env);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;
};

void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);

extern const VMStateDescription vmstate_mips_cpu;

#endif /* !CONFIG_USER_ONLY */

static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
{
    return (env->CP0_Status & (1 << CP0St_IE)) &&
        !(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM) &&
        /*
         * Note that the TCStatus IXMT field is initialized to zero,
         * and only MT capable cores can set it to one. So we don't
         * need to check for MT capabilities here.
         */
        !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
}

/* Check if there is pending and not masked out interrupt */
static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
{
    int32_t pending;
    int32_t status;
    bool r;

    pending = env->CP0_Cause & CP0Ca_IP_mask;
    status = env->CP0_Status & CP0Ca_IP_mask;

    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
        /*
         * A MIPS configured with a vectorizing external interrupt controller
         * will feed a vector into the Cause pending lines. The core treats
         * the status lines as a vector level, not as individual masks.
         */
        r = pending > status;
    } else {
        /*
         * A MIPS configured with compatibility or VInt (Vectored Interrupts)
         * treats the pending lines as individual interrupt lines, the status
         * lines are individual masks.
         */
        r = (pending & status) != 0;
    }
    return r;
}

void msa_reset(CPUMIPSState *env);

/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);

static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
{
    env->active_tc.PC = value & ~(target_ulong)1;
    if (value & 1) {
        env->hflags |= MIPS_HFLAG_M16;
    } else {
        env->hflags &= ~(MIPS_HFLAG_M16);
    }
}

static inline void restore_pamask(CPUMIPSState *env)
{
    if (env->hflags & MIPS_HFLAG_ELPA) {
        env->PAMask = (1ULL << env->PABITS) - 1;
    } else {
        env->PAMask = PAMASK_BASE;
    }
}

static inline int mips_vpe_active(CPUMIPSState *env)
{
    int active = 1;

    /* Check that the VPE is enabled.  */
    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
        active = 0;
    }
    /* Check that the VPE is activated.  */
    if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
        active = 0;
    }

    /*
     * Now verify that there are active thread contexts in the VPE.
     *
     * This assumes the CPU model will internally reschedule threads
     * if the active one goes to sleep. If there are no threads available
     * the active one will be in a sleeping state, and we can turn off
     * the entire VPE.
     */
    if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
        /* TC is not activated.  */
        active = 0;
    }
    if (env->active_tc.CP0_TCHalt & 1) {
        /* TC is in halt state.  */
        active = 0;
    }

    return active;
}

static inline int mips_vp_active(CPUMIPSState *env)
{
    CPUState *other_cs = first_cpu;

    /* Check if the VP disabled other VPs (which means the VP is enabled) */
    if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
        return 1;
    }

    /* Check if the virtual processor is disabled due to a DVP */
    CPU_FOREACH(other_cs) {
        MIPSCPU *other_cpu = MIPS_CPU(other_cs);
        if ((&other_cpu->env != env) &&
            ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
            return 0;
        }
    }
    return 1;
}

static inline void compute_hflags(CPUMIPSState *env)
{
    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                     MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
    if (env->CP0_Status & (1 << CP0St_ERL)) {
        env->hflags |= MIPS_HFLAG_ERL;
    }
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM)) {
        env->hflags |= (env->CP0_Status >> CP0St_KSU) &
                       MIPS_HFLAG_KSU;
    }
#if defined(TARGET_MIPS64)
    if ((env->insn_flags & ISA_MIPS3) &&
        (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
         (env->CP0_Status & (1 << CP0St_PX)) ||
         (env->CP0_Status & (1 << CP0St_UX)))) {
        env->hflags |= MIPS_HFLAG_64;
    }

    if (!(env->insn_flags & ISA_MIPS3)) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
               !(env->CP0_Status & (1 << CP0St_UX))) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (env->insn_flags & ISA_MIPS_R6) {
        /* Address wrapping for Supervisor and Kernel is specified in R6 */
        if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
             !(env->CP0_Status & (1 << CP0St_SX))) ||
            (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
             !(env->CP0_Status & (1 << CP0St_KX)))) {
            env->hflags |= MIPS_HFLAG_AWRAP;
        }
    }
#endif
    if (((env->CP0_Status & (1 << CP0St_CU0)) &&
         !(env->insn_flags & ISA_MIPS_R6)) ||
        !(env->hflags & MIPS_HFLAG_KSU)) {
        env->hflags |= MIPS_HFLAG_CP0;
    }
    if (env->CP0_Status & (1 << CP0St_CU1)) {
        env->hflags |= MIPS_HFLAG_FPU;
    }
    if (env->CP0_Status & (1 << CP0St_FR)) {
        env->hflags |= MIPS_HFLAG_F64;
    }
    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
        (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
        env->hflags |= MIPS_HFLAG_SBRI;
    }
    if (env->insn_flags & ASE_DSP_R3) {
        /*
         * Our cpu supports DSP R3 ASE, so enable
         * access to DSP R3 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                           MIPS_HFLAG_DSP_R3;
        }
    } else if (env->insn_flags & ASE_DSP_R2) {
        /*
         * Our cpu supports DSP R2 ASE, so enable
         * access to DSP R2 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
        }

    } else if (env->insn_flags & ASE_DSP) {
        /*
         * Our cpu supports DSP ASE, so enable
         * access to DSP resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP;
        }

    }
    if (env->insn_flags & ISA_MIPS_R2) {
        if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS_R1) {
        if (env->hflags & MIPS_HFLAG_64) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS4) {
        /*
         * All supported MIPS IV CPUs use the XX (CU3) to enable
         * and disable the MIPS IV extensions to the MIPS III ISA.
         * Some other MIPS IV CPUs ignore the bit, so the check here
         * would be too restrictive for them.
         */
        if (env->CP0_Status & (1U << CP0St_CU3)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    }
    if (ase_msa_available(env)) {
        if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
            env->hflags |= MIPS_HFLAG_MSA;
        }
    }
    if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
        if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
            env->hflags |= MIPS_HFLAG_FRE;
        }
    }
    if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
        if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
            env->hflags |= MIPS_HFLAG_ELPA;
        }
    }
}

#endif
Commit	Line	Data
7ba0e95b AM	1	/*
7ba0e95b AM	2	* MIPS internal definitions and helpers
26aa3d9a PMD	3	*
	4	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#ifndef MIPS_INTERNAL_H
	9	#define MIPS_INTERNAL_H
	10
34cffe96	11	#include "exec/memattrs.h"
6fe25ce5 PMD	12	#ifdef CONFIG_TCG
	13	#include "tcg/tcg-internal.h"
	14	#endif
41da212c	15
7ba0e95b AM	16	/*
	17	* MMU types, the first four entries have the same layout as the
	18	* CP0C0_MT field.
	19	*/
41da212c	20	enum mips_mmu_types {
1ab3a0de PMD	21	MMU_TYPE_NONE = 0,
	22	MMU_TYPE_R4000 = 1, /* Standard TLB */
	23	MMU_TYPE_BAT = 2, /* Block Address Translation */
	24	MMU_TYPE_FMT = 3, /* Fixed Mapping */
	25	MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */
41da212c IM	26	MMU_TYPE_R3000,
	27	MMU_TYPE_R6000,
	28	MMU_TYPE_R8000
	29	};
	30
	31	struct mips_def_t {
	32	const char *name;
	33	int32_t CP0_PRid;
	34	int32_t CP0_Config0;
	35	int32_t CP0_Config1;
	36	int32_t CP0_Config2;
	37	int32_t CP0_Config3;
	38	int32_t CP0_Config4;
	39	int32_t CP0_Config4_rw_bitmask;
	40	int32_t CP0_Config5;
	41	int32_t CP0_Config5_rw_bitmask;
	42	int32_t CP0_Config6;
af868995	43	int32_t CP0_Config6_rw_bitmask;
41da212c	44	int32_t CP0_Config7;
af868995	45	int32_t CP0_Config7_rw_bitmask;
41da212c IM	46	target_ulong CP0_LLAddr_rw_bitmask;
	47	int CP0_LLAddr_shift;
	48	int32_t SYNCI_Step;
	49	int32_t CCRes;
	50	int32_t CP0_Status_rw_bitmask;
	51	int32_t CP0_TCStatus_rw_bitmask;
	52	int32_t CP0_SRSCtl;
	53	int32_t CP1_fcr0;
	54	int32_t CP1_fcr31_rw_bitmask;
	55	int32_t CP1_fcr31;
	56	int32_t MSAIR;
	57	int32_t SEGBITS;
	58	int32_t PABITS;
	59	int32_t CP0_SRSConf0_rw_bitmask;
	60	int32_t CP0_SRSConf0;
	61	int32_t CP0_SRSConf1_rw_bitmask;
	62	int32_t CP0_SRSConf1;
	63	int32_t CP0_SRSConf2_rw_bitmask;
	64	int32_t CP0_SRSConf2;
	65	int32_t CP0_SRSConf3_rw_bitmask;
	66	int32_t CP0_SRSConf3;
	67	int32_t CP0_SRSConf4_rw_bitmask;
	68	int32_t CP0_SRSConf4;
	69	int32_t CP0_PageGrain_rw_bitmask;
	70	int32_t CP0_PageGrain;
	71	target_ulong CP0_EBaseWG_rw_bitmask;
f9c9cd63	72	uint64_t insn_flags;
41da212c	73	enum mips_mmu_types mmu_type;
5fb2dcd1	74	int32_t SAARP;
41da212c IM	75	};
41da212c IM	76
06106772	77	extern const char regnames[32][3];
830b87ea	78	extern const char fregnames[32][4];
adbf1be3	79
41da212c IM	80	extern const struct mips_def_t mips_defs[];
	81	extern const int mips_defs_number;
	82
a010bdbe	83	int mips_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
26aa3d9a	84	int mips_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
26aa3d9a	85
137f4d87 PMD	86	#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL)
	87	#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL)
	88	#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL)
	89	#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL)
	90	#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL)
	91
	92	#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL)
	93	#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL)
	94
26aa3d9a PMD	95	#if !defined(CONFIG_USER_ONLY)
26aa3d9a PMD	96
137f4d87 PMD	97	enum {
	98	TLBRET_XI = -6,
	99	TLBRET_RI = -5,
	100	TLBRET_DIRTY = -4,
	101	TLBRET_INVALID = -3,
	102	TLBRET_NOMATCH = -2,
	103	TLBRET_BADADDR = -1,
	104	TLBRET_MATCH = 0
	105	};
	106
	107	int get_physical_address(CPUMIPSState env, hwaddr physical,
	108	int *prot, target_ulong real_address,
	109	MMUAccessType access_type, int mmu_idx);
	110	hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
	111
26aa3d9a PMD	112	typedef struct r4k_tlb_t r4k_tlb_t;
	113	struct r4k_tlb_t {
	114	target_ulong VPN;
	115	uint32_t PageMask;
	116	uint16_t ASID;
99029be1	117	uint32_t MMID;
26aa3d9a PMD	118	unsigned int G:1;
	119	unsigned int C0:3;
	120	unsigned int C1:3;
	121	unsigned int V0:1;
	122	unsigned int V1:1;
	123	unsigned int D0:1;
	124	unsigned int D1:1;
	125	unsigned int XI0:1;
	126	unsigned int XI1:1;
	127	unsigned int RI0:1;
	128	unsigned int RI1:1;
	129	unsigned int EHINV:1;
	130	uint64_t PFN[2];
	131	};
	132
	133	struct CPUMIPSTLBContext {
	134	uint32_t nb_tlb;
	135	uint32_t tlb_in_use;
	136	int (map_address)(struct CPUMIPSState env, hwaddr physical, int prot,
edbd4992	137	target_ulong address, MMUAccessType access_type);
26aa3d9a PMD	138	void (helper_tlbwi)(struct CPUMIPSState env);
	139	void (helper_tlbwr)(struct CPUMIPSState env);
	140	void (helper_tlbp)(struct CPUMIPSState env);
	141	void (helper_tlbr)(struct CPUMIPSState env);
	142	void (helper_tlbinv)(struct CPUMIPSState env);
	143	void (helper_tlbinvf)(struct CPUMIPSState env);
	144	union {
	145	struct {
	146	r4k_tlb_t tlb[MIPS_TLB_MAX];
	147	} r4k;
	148	} mmu;
	149	};
	150
5679479b PMD	151	void sync_c0_status(CPUMIPSState env, CPUMIPSState cpu, int tc);
	152	void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
	153	void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
	154
8a9358cc	155	extern const VMStateDescription vmstate_mips_cpu;
44e3b050 PMD	156
	157	#endif /* !CONFIG_USER_ONLY */
	158
26aa3d9a PMD	159	static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
	160	{
	161	return (env->CP0_Status & (1 << CP0St_IE)) &&
	162	!(env->CP0_Status & (1 << CP0St_EXL)) &&
	163	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	164	!(env->hflags & MIPS_HFLAG_DM) &&
7ba0e95b AM	165	/*
	166	* Note that the TCStatus IXMT field is initialized to zero,
	167	* and only MT capable cores can set it to one. So we don't
	168	* need to check for MT capabilities here.
	169	*/
26aa3d9a PMD	170	!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
	171	}
	172
	173	/* Check if there is pending and not masked out interrupt */
	174	static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
	175	{
	176	int32_t pending;
	177	int32_t status;
	178	bool r;
	179
	180	pending = env->CP0_Cause & CP0Ca_IP_mask;
	181	status = env->CP0_Status & CP0Ca_IP_mask;
	182
	183	if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
7ba0e95b AM	184	/*
	185	* A MIPS configured with a vectorizing external interrupt controller
	186	* will feed a vector into the Cause pending lines. The core treats
8cdf8869	187	* the status lines as a vector level, not as individual masks.
7ba0e95b	188	*/
26aa3d9a PMD	189	r = pending > status;
26aa3d9a PMD	190	} else {
7ba0e95b AM	191	/*
	192	* A MIPS configured with compatibility or VInt (Vectored Interrupts)
	193	* treats the pending lines as individual interrupt lines, the status
	194	* lines are individual masks.
	195	*/
26aa3d9a PMD	196	r = (pending & status) != 0;
	197	}
	198	return r;
	199	}
	200
03e4d95c PMD	201	void msa_reset(CPUMIPSState *env);
03e4d95c PMD	202
26aa3d9a	203	/* cp0_timer.c */
26aa3d9a PMD	204	uint32_t cpu_mips_get_count(CPUMIPSState *env);
	205	void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
	206	void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
	207	void cpu_mips_start_count(CPUMIPSState *env);
	208	void cpu_mips_stop_count(CPUMIPSState *env);
	209
533fc64f PMD	210	static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
	211	{
	212	env->active_tc.PC = value & ~(target_ulong)1;
	213	if (value & 1) {
	214	env->hflags \|= MIPS_HFLAG_M16;
	215	} else {
	216	env->hflags &= ~(MIPS_HFLAG_M16);
	217	}
	218	}
	219
26aa3d9a PMD	220	static inline void restore_pamask(CPUMIPSState *env)
	221	{
	222	if (env->hflags & MIPS_HFLAG_ELPA) {
	223	env->PAMask = (1ULL << env->PABITS) - 1;
	224	} else {
	225	env->PAMask = PAMASK_BASE;
	226	}
	227	}
	228
	229	static inline int mips_vpe_active(CPUMIPSState *env)
	230	{
	231	int active = 1;
	232
	233	/* Check that the VPE is enabled. */
	234	if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
	235	active = 0;
	236	}
	237	/* Check that the VPE is activated. */
	238	if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
	239	active = 0;
	240	}
	241
7ba0e95b AM	242	/*
	243	* Now verify that there are active thread contexts in the VPE.
	244	*
	245	* This assumes the CPU model will internally reschedule threads
	246	* if the active one goes to sleep. If there are no threads available
	247	* the active one will be in a sleeping state, and we can turn off
	248	* the entire VPE.
	249	*/
26aa3d9a PMD	250	if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
	251	/* TC is not activated. */
	252	active = 0;
	253	}
	254	if (env->active_tc.CP0_TCHalt & 1) {
	255	/* TC is in halt state. */
	256	active = 0;
	257	}
	258
	259	return active;
	260	}
	261
	262	static inline int mips_vp_active(CPUMIPSState *env)
	263	{
	264	CPUState *other_cs = first_cpu;
	265
	266	/* Check if the VP disabled other VPs (which means the VP is enabled) */
	267	if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
	268	return 1;
	269	}
	270
	271	/* Check if the virtual processor is disabled due to a DVP */
	272	CPU_FOREACH(other_cs) {
	273	MIPSCPU *other_cpu = MIPS_CPU(other_cs);
	274	if ((&other_cpu->env != env) &&
	275	((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
	276	return 0;
	277	}
	278	}
	279	return 1;
	280	}
	281
	282	static inline void compute_hflags(CPUMIPSState *env)
	283	{
	284	env->hflags &= ~(MIPS_HFLAG_COP1X \| MIPS_HFLAG_64 \| MIPS_HFLAG_CP0 \|
	285	MIPS_HFLAG_F64 \| MIPS_HFLAG_FPU \| MIPS_HFLAG_KSU \|
908f6be1 SM	286	MIPS_HFLAG_AWRAP \| MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	287	MIPS_HFLAG_DSP_R3 \| MIPS_HFLAG_SBRI \| MIPS_HFLAG_MSA \|
59e781fb	288	MIPS_HFLAG_FRE \| MIPS_HFLAG_ELPA \| MIPS_HFLAG_ERL);
26aa3d9a PMD	289	if (env->CP0_Status & (1 << CP0St_ERL)) {
	290	env->hflags \|= MIPS_HFLAG_ERL;
	291	}
	292	if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
	293	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	294	!(env->hflags & MIPS_HFLAG_DM)) {
7ba0e95b AM	295	env->hflags \|= (env->CP0_Status >> CP0St_KSU) &
7ba0e95b AM	296	MIPS_HFLAG_KSU;
26aa3d9a PMD	297	}
	298	#if defined(TARGET_MIPS64)
	299	if ((env->insn_flags & ISA_MIPS3) &&
	300	(((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) \|\|
	301	(env->CP0_Status & (1 << CP0St_PX)) \|\|
	302	(env->CP0_Status & (1 << CP0St_UX)))) {
	303	env->hflags \|= MIPS_HFLAG_64;
	304	}
	305
	306	if (!(env->insn_flags & ISA_MIPS3)) {
	307	env->hflags \|= MIPS_HFLAG_AWRAP;
	308	} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
	309	!(env->CP0_Status & (1 << CP0St_UX))) {
	310	env->hflags \|= MIPS_HFLAG_AWRAP;
2e211e0a	311	} else if (env->insn_flags & ISA_MIPS_R6) {
26aa3d9a PMD	312	/* Address wrapping for Supervisor and Kernel is specified in R6 */
	313	if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
	314	!(env->CP0_Status & (1 << CP0St_SX))) \|\|
	315	(((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
	316	!(env->CP0_Status & (1 << CP0St_KX)))) {
	317	env->hflags \|= MIPS_HFLAG_AWRAP;
	318	}
	319	}
	320	#endif
	321	if (((env->CP0_Status & (1 << CP0St_CU0)) &&
2e211e0a	322	!(env->insn_flags & ISA_MIPS_R6)) \|\|
26aa3d9a PMD	323	!(env->hflags & MIPS_HFLAG_KSU)) {
	324	env->hflags \|= MIPS_HFLAG_CP0;
	325	}
	326	if (env->CP0_Status & (1 << CP0St_CU1)) {
	327	env->hflags \|= MIPS_HFLAG_FPU;
	328	}
	329	if (env->CP0_Status & (1 << CP0St_FR)) {
	330	env->hflags \|= MIPS_HFLAG_F64;
	331	}
	332	if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
	333	(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
	334	env->hflags \|= MIPS_HFLAG_SBRI;
	335	}
908f6be1 SM	336	if (env->insn_flags & ASE_DSP_R3) {
	337	/*
	338	* Our cpu supports DSP R3 ASE, so enable
	339	* access to DSP R3 resources.
	340	*/
59e781fb	341	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1 SM	342	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	343	MIPS_HFLAG_DSP_R3;
59e781fb	344	}
908f6be1 SM	345	} else if (env->insn_flags & ASE_DSP_R2) {
	346	/*
	347	* Our cpu supports DSP R2 ASE, so enable
	348	* access to DSP R2 resources.
	349	*/
26aa3d9a	350	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1	351	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2;
26aa3d9a PMD	352	}
	353
	354	} else if (env->insn_flags & ASE_DSP) {
908f6be1 SM	355	/*
	356	* Our cpu supports DSP ASE, so enable
	357	* access to DSP resources.
	358	*/
26aa3d9a PMD	359	if (env->CP0_Status & (1 << CP0St_MX)) {
	360	env->hflags \|= MIPS_HFLAG_DSP;
	361	}
	362
	363	}
7a47bae5	364	if (env->insn_flags & ISA_MIPS_R2) {
26aa3d9a PMD	365	if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
	366	env->hflags \|= MIPS_HFLAG_COP1X;
	367	}
bbd5e4a2	368	} else if (env->insn_flags & ISA_MIPS_R1) {
26aa3d9a PMD	369	if (env->hflags & MIPS_HFLAG_64) {
	370	env->hflags \|= MIPS_HFLAG_COP1X;
	371	}
	372	} else if (env->insn_flags & ISA_MIPS4) {
7ba0e95b AM	373	/*
	374	* All supported MIPS IV CPUs use the XX (CU3) to enable
	375	* and disable the MIPS IV extensions to the MIPS III ISA.
	376	* Some other MIPS IV CPUs ignore the bit, so the check here
	377	* would be too restrictive for them.
	378	*/
26aa3d9a PMD	379	if (env->CP0_Status & (1U << CP0St_CU3)) {
	380	env->hflags \|= MIPS_HFLAG_COP1X;
	381	}
	382	}
aa314198	383	if (ase_msa_available(env)) {
26aa3d9a PMD	384	if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
	385	env->hflags \|= MIPS_HFLAG_MSA;
	386	}
	387	}
	388	if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
	389	if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
	390	env->hflags \|= MIPS_HFLAG_FRE;
	391	}
	392	}
	393	if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
	394	if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
	395	env->hflags \|= MIPS_HFLAG_ELPA;
	396	}
	397	}
	398	}
	399
26aa3d9a	400	#endif