[mirror_qemu.git] / target / mips / internal.h

/*
 * MIPS internal definitions and helpers
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#ifndef MIPS_INTERNAL_H
#define MIPS_INTERNAL_H

#include "exec/memattrs.h"
#include "fpu/softfloat-helpers.h"

/*
 * MMU types, the first four entries have the same layout as the
 * CP0C0_MT field.
 */
enum mips_mmu_types {
    MMU_TYPE_NONE       = 0,
    MMU_TYPE_R4000      = 1,    /* Standard TLB */
    MMU_TYPE_BAT        = 2,    /* Block Address Translation */
    MMU_TYPE_FMT        = 3,    /* Fixed Mapping */
    MMU_TYPE_DVF        = 4,    /* Dual VTLB and FTLB */
    MMU_TYPE_R3000,
    MMU_TYPE_R6000,
    MMU_TYPE_R8000
};

struct mips_def_t {
    const char *name;
    int32_t CP0_PRid;
    int32_t CP0_Config0;
    int32_t CP0_Config1;
    int32_t CP0_Config2;
    int32_t CP0_Config3;
    int32_t CP0_Config4;
    int32_t CP0_Config4_rw_bitmask;
    int32_t CP0_Config5;
    int32_t CP0_Config5_rw_bitmask;
    int32_t CP0_Config6;
    int32_t CP0_Config6_rw_bitmask;
    int32_t CP0_Config7;
    int32_t CP0_Config7_rw_bitmask;
    target_ulong CP0_LLAddr_rw_bitmask;
    int CP0_LLAddr_shift;
    int32_t SYNCI_Step;
    int32_t CCRes;
    int32_t CP0_Status_rw_bitmask;
    int32_t CP0_TCStatus_rw_bitmask;
    int32_t CP0_SRSCtl;
    int32_t CP1_fcr0;
    int32_t CP1_fcr31_rw_bitmask;
    int32_t CP1_fcr31;
    int32_t MSAIR;
    int32_t SEGBITS;
    int32_t PABITS;
    int32_t CP0_SRSConf0_rw_bitmask;
    int32_t CP0_SRSConf0;
    int32_t CP0_SRSConf1_rw_bitmask;
    int32_t CP0_SRSConf1;
    int32_t CP0_SRSConf2_rw_bitmask;
    int32_t CP0_SRSConf2;
    int32_t CP0_SRSConf3_rw_bitmask;
    int32_t CP0_SRSConf3;
    int32_t CP0_SRSConf4_rw_bitmask;
    int32_t CP0_SRSConf4;
    int32_t CP0_PageGrain_rw_bitmask;
    int32_t CP0_PageGrain;
    target_ulong CP0_EBaseWG_rw_bitmask;
    uint64_t insn_flags;
    enum mips_mmu_types mmu_type;
    int32_t SAARP;
};

extern const struct mips_def_t mips_defs[];
extern const int mips_defs_number;

enum CPUMIPSMSADataFormat {
    DF_BYTE = 0,
    DF_HALF,
    DF_WORD,
    DF_DOUBLE
};

void mips_cpu_do_interrupt(CPUState *cpu);
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
                                  MMUAccessType access_type,
                                  int mmu_idx, uintptr_t retaddr);

#if !defined(CONFIG_USER_ONLY)

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint16_t ASID;
    uint32_t MMID;
    unsigned int G:1;
    unsigned int C0:3;
    unsigned int C1:3;
    unsigned int V0:1;
    unsigned int V1:1;
    unsigned int D0:1;
    unsigned int D1:1;
    unsigned int XI0:1;
    unsigned int XI1:1;
    unsigned int RI0:1;
    unsigned int RI1:1;
    unsigned int EHINV:1;
    uint64_t PFN[2];
};

struct CPUMIPSTLBContext {
    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
                       target_ulong address, int rw, int access_type);
    void (*helper_tlbwi)(struct CPUMIPSState *env);
    void (*helper_tlbwr)(struct CPUMIPSState *env);
    void (*helper_tlbp)(struct CPUMIPSState *env);
    void (*helper_tlbr)(struct CPUMIPSState *env);
    void (*helper_tlbinv)(struct CPUMIPSState *env);
    void (*helper_tlbinvf)(struct CPUMIPSState *env);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;
};

int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                       target_ulong address, int rw, int access_type);
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                          target_ulong address, int rw, int access_type);
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                    target_ulong address, int rw, int access_type);
void r4k_helper_tlbwi(CPUMIPSState *env);
void r4k_helper_tlbwr(CPUMIPSState *env);
void r4k_helper_tlbp(CPUMIPSState *env);
void r4k_helper_tlbr(CPUMIPSState *env);
void r4k_helper_tlbinv(CPUMIPSState *env);
void r4k_helper_tlbinvf(CPUMIPSState *env);
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
uint32_t cpu_mips_get_random(CPUMIPSState *env);

void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                    vaddr addr, unsigned size,
                                    MMUAccessType access_type,
                                    int mmu_idx, MemTxAttrs attrs,
                                    MemTxResult response, uintptr_t retaddr);
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
                                  int rw);
#endif

#define cpu_signal_handler cpu_mips_signal_handler

#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_mips_cpu;
#endif

static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
{
    return (env->CP0_Status & (1 << CP0St_IE)) &&
        !(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM) &&
        /*
         * Note that the TCStatus IXMT field is initialized to zero,
         * and only MT capable cores can set it to one. So we don't
         * need to check for MT capabilities here.
         */
        !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
}

/* Check if there is pending and not masked out interrupt */
static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
{
    int32_t pending;
    int32_t status;
    bool r;

    pending = env->CP0_Cause & CP0Ca_IP_mask;
    status = env->CP0_Status & CP0Ca_IP_mask;

    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
        /*
         * A MIPS configured with a vectorizing external interrupt controller
         * will feed a vector into the Cause pending lines. The core treats
         * the status lines as a vector level, not as individual masks.
         */
        r = pending > status;
    } else {
        /*
         * A MIPS configured with compatibility or VInt (Vectored Interrupts)
         * treats the pending lines as individual interrupt lines, the status
         * lines are individual masks.
         */
        r = (pending & status) != 0;
    }
    return r;
}

void mips_tcg_init(void);

/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);

/* helper.c */
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);

/* op_helper.c */
uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);

extern const FloatRoundMode ieee_rm[4];

void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);

static inline void restore_rounding_mode(CPUMIPSState *env)
{
    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
                            &env->active_fpu.fp_status);
}

static inline void restore_flush_mode(CPUMIPSState *env)
{
    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
                      &env->active_fpu.fp_status);
}

static inline void restore_snan_bit_mode(CPUMIPSState *env)
{
    set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
                        &env->active_fpu.fp_status);
}

static inline void restore_fp_status(CPUMIPSState *env)
{
    restore_rounding_mode(env);
    restore_flush_mode(env);
    restore_snan_bit_mode(env);
}

static inline void restore_msa_fp_status(CPUMIPSState *env)
{
    float_status *status = &env->active_tc.msa_fp_status;
    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;

    set_float_rounding_mode(ieee_rm[rounding_mode], status);
    set_flush_to_zero(flush_to_zero, status);
    set_flush_inputs_to_zero(flush_to_zero, status);
}

static inline void restore_pamask(CPUMIPSState *env)
{
    if (env->hflags & MIPS_HFLAG_ELPA) {
        env->PAMask = (1ULL << env->PABITS) - 1;
    } else {
        env->PAMask = PAMASK_BASE;
    }
}

static inline int mips_vpe_active(CPUMIPSState *env)
{
    int active = 1;

    /* Check that the VPE is enabled.  */
    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
        active = 0;
    }
    /* Check that the VPE is activated.  */
    if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
        active = 0;
    }

    /*
     * Now verify that there are active thread contexts in the VPE.
     *
     * This assumes the CPU model will internally reschedule threads
     * if the active one goes to sleep. If there are no threads available
     * the active one will be in a sleeping state, and we can turn off
     * the entire VPE.
     */
    if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
        /* TC is not activated.  */
        active = 0;
    }
    if (env->active_tc.CP0_TCHalt & 1) {
        /* TC is in halt state.  */
        active = 0;
    }

    return active;
}

static inline int mips_vp_active(CPUMIPSState *env)
{
    CPUState *other_cs = first_cpu;

    /* Check if the VP disabled other VPs (which means the VP is enabled) */
    if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
        return 1;
    }

    /* Check if the virtual processor is disabled due to a DVP */
    CPU_FOREACH(other_cs) {
        MIPSCPU *other_cpu = MIPS_CPU(other_cs);
        if ((&other_cpu->env != env) &&
            ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
            return 0;
        }
    }
    return 1;
}

static inline void compute_hflags(CPUMIPSState *env)
{
    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                     MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
    if (env->CP0_Status & (1 << CP0St_ERL)) {
        env->hflags |= MIPS_HFLAG_ERL;
    }
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM)) {
        env->hflags |= (env->CP0_Status >> CP0St_KSU) &
                       MIPS_HFLAG_KSU;
    }
#if defined(TARGET_MIPS64)
    if ((env->insn_flags & ISA_MIPS3) &&
        (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
         (env->CP0_Status & (1 << CP0St_PX)) ||
         (env->CP0_Status & (1 << CP0St_UX)))) {
        env->hflags |= MIPS_HFLAG_64;
    }

    if (!(env->insn_flags & ISA_MIPS3)) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
               !(env->CP0_Status & (1 << CP0St_UX))) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (env->insn_flags & ISA_MIPS64R6) {
        /* Address wrapping for Supervisor and Kernel is specified in R6 */
        if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
             !(env->CP0_Status & (1 << CP0St_SX))) ||
            (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
             !(env->CP0_Status & (1 << CP0St_KX)))) {
            env->hflags |= MIPS_HFLAG_AWRAP;
        }
    }
#endif
    if (((env->CP0_Status & (1 << CP0St_CU0)) &&
         !(env->insn_flags & ISA_MIPS32R6)) ||
        !(env->hflags & MIPS_HFLAG_KSU)) {
        env->hflags |= MIPS_HFLAG_CP0;
    }
    if (env->CP0_Status & (1 << CP0St_CU1)) {
        env->hflags |= MIPS_HFLAG_FPU;
    }
    if (env->CP0_Status & (1 << CP0St_FR)) {
        env->hflags |= MIPS_HFLAG_F64;
    }
    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
        (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
        env->hflags |= MIPS_HFLAG_SBRI;
    }
    if (env->insn_flags & ASE_DSP_R3) {
        /*
         * Our cpu supports DSP R3 ASE, so enable
         * access to DSP R3 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                           MIPS_HFLAG_DSP_R3;
        }
    } else if (env->insn_flags & ASE_DSP_R2) {
        /*
         * Our cpu supports DSP R2 ASE, so enable
         * access to DSP R2 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
        }

    } else if (env->insn_flags & ASE_DSP) {
        /*
         * Our cpu supports DSP ASE, so enable
         * access to DSP resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP;
        }

    }
    if (env->insn_flags & ISA_MIPS32R2) {
        if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS32) {
        if (env->hflags & MIPS_HFLAG_64) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS4) {
        /*
         * All supported MIPS IV CPUs use the XX (CU3) to enable
         * and disable the MIPS IV extensions to the MIPS III ISA.
         * Some other MIPS IV CPUs ignore the bit, so the check here
         * would be too restrictive for them.
         */
        if (env->CP0_Status & (1U << CP0St_CU3)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    }
    if (env->insn_flags & ASE_MSA) {
        if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
            env->hflags |= MIPS_HFLAG_MSA;
        }
    }
    if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
        if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
            env->hflags |= MIPS_HFLAG_FRE;
        }
    }
    if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
        if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
            env->hflags |= MIPS_HFLAG_ELPA;
        }
    }
}

void cpu_mips_tlb_flush(CPUMIPSState *env);
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);

void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
                                          int error_code, uintptr_t pc);

static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
                                                    uint32_t exception,
                                                    uintptr_t pc)
{
    do_raise_exception_err(env, exception, 0, pc);
}

#endif
Commit	Line	Data
7ba0e95b AM	1	/*
7ba0e95b AM	2	* MIPS internal definitions and helpers
26aa3d9a PMD	3	*
	4	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#ifndef MIPS_INTERNAL_H
	9	#define MIPS_INTERNAL_H
	10
34cffe96	11	#include "exec/memattrs.h"
502700d0	12	#include "fpu/softfloat-helpers.h"
41da212c	13
7ba0e95b AM	14	/*
	15	* MMU types, the first four entries have the same layout as the
	16	* CP0C0_MT field.
	17	*/
41da212c	18	enum mips_mmu_types {
1ab3a0de PMD	19	MMU_TYPE_NONE = 0,
	20	MMU_TYPE_R4000 = 1, /* Standard TLB */
	21	MMU_TYPE_BAT = 2, /* Block Address Translation */
	22	MMU_TYPE_FMT = 3, /* Fixed Mapping */
	23	MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */
41da212c IM	24	MMU_TYPE_R3000,
	25	MMU_TYPE_R6000,
	26	MMU_TYPE_R8000
	27	};
	28
	29	struct mips_def_t {
	30	const char *name;
	31	int32_t CP0_PRid;
	32	int32_t CP0_Config0;
	33	int32_t CP0_Config1;
	34	int32_t CP0_Config2;
	35	int32_t CP0_Config3;
	36	int32_t CP0_Config4;
	37	int32_t CP0_Config4_rw_bitmask;
	38	int32_t CP0_Config5;
	39	int32_t CP0_Config5_rw_bitmask;
	40	int32_t CP0_Config6;
af868995	41	int32_t CP0_Config6_rw_bitmask;
41da212c	42	int32_t CP0_Config7;
af868995	43	int32_t CP0_Config7_rw_bitmask;
41da212c IM	44	target_ulong CP0_LLAddr_rw_bitmask;
	45	int CP0_LLAddr_shift;
	46	int32_t SYNCI_Step;
	47	int32_t CCRes;
	48	int32_t CP0_Status_rw_bitmask;
	49	int32_t CP0_TCStatus_rw_bitmask;
	50	int32_t CP0_SRSCtl;
	51	int32_t CP1_fcr0;
	52	int32_t CP1_fcr31_rw_bitmask;
	53	int32_t CP1_fcr31;
	54	int32_t MSAIR;
	55	int32_t SEGBITS;
	56	int32_t PABITS;
	57	int32_t CP0_SRSConf0_rw_bitmask;
	58	int32_t CP0_SRSConf0;
	59	int32_t CP0_SRSConf1_rw_bitmask;
	60	int32_t CP0_SRSConf1;
	61	int32_t CP0_SRSConf2_rw_bitmask;
	62	int32_t CP0_SRSConf2;
	63	int32_t CP0_SRSConf3_rw_bitmask;
	64	int32_t CP0_SRSConf3;
	65	int32_t CP0_SRSConf4_rw_bitmask;
	66	int32_t CP0_SRSConf4;
	67	int32_t CP0_PageGrain_rw_bitmask;
	68	int32_t CP0_PageGrain;
	69	target_ulong CP0_EBaseWG_rw_bitmask;
f9c9cd63	70	uint64_t insn_flags;
41da212c	71	enum mips_mmu_types mmu_type;
5fb2dcd1	72	int32_t SAARP;
41da212c IM	73	};
	74
	75	extern const struct mips_def_t mips_defs[];
	76	extern const int mips_defs_number;
	77
26aa3d9a PMD	78	enum CPUMIPSMSADataFormat {
	79	DF_BYTE = 0,
	80	DF_HALF,
	81	DF_WORD,
	82	DF_DOUBLE
	83	};
	84
	85	void mips_cpu_do_interrupt(CPUState *cpu);
	86	bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
90c84c56	87	void mips_cpu_dump_state(CPUState cpu, FILE f, int flags);
26aa3d9a	88	hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
a010bdbe	89	int mips_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
26aa3d9a PMD	90	int mips_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	91	void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
	92	MMUAccessType access_type,
	93	int mmu_idx, uintptr_t retaddr);
	94
	95	#if !defined(CONFIG_USER_ONLY)
	96
	97	typedef struct r4k_tlb_t r4k_tlb_t;
	98	struct r4k_tlb_t {
	99	target_ulong VPN;
	100	uint32_t PageMask;
	101	uint16_t ASID;
99029be1	102	uint32_t MMID;
26aa3d9a PMD	103	unsigned int G:1;
	104	unsigned int C0:3;
	105	unsigned int C1:3;
	106	unsigned int V0:1;
	107	unsigned int V1:1;
	108	unsigned int D0:1;
	109	unsigned int D1:1;
	110	unsigned int XI0:1;
	111	unsigned int XI1:1;
	112	unsigned int RI0:1;
	113	unsigned int RI1:1;
	114	unsigned int EHINV:1;
	115	uint64_t PFN[2];
	116	};
	117
	118	struct CPUMIPSTLBContext {
	119	uint32_t nb_tlb;
	120	uint32_t tlb_in_use;
	121	int (map_address)(struct CPUMIPSState env, hwaddr physical, int prot,
	122	target_ulong address, int rw, int access_type);
	123	void (helper_tlbwi)(struct CPUMIPSState env);
	124	void (helper_tlbwr)(struct CPUMIPSState env);
	125	void (helper_tlbp)(struct CPUMIPSState env);
	126	void (helper_tlbr)(struct CPUMIPSState env);
	127	void (helper_tlbinv)(struct CPUMIPSState env);
	128	void (helper_tlbinvf)(struct CPUMIPSState env);
	129	union {
	130	struct {
	131	r4k_tlb_t tlb[MIPS_TLB_MAX];
	132	} r4k;
	133	} mmu;
	134	};
	135
	136	int no_mmu_map_address(CPUMIPSState env, hwaddr physical, int *prot,
	137	target_ulong address, int rw, int access_type);
	138	int fixed_mmu_map_address(CPUMIPSState env, hwaddr physical, int *prot,
	139	target_ulong address, int rw, int access_type);
	140	int r4k_map_address(CPUMIPSState env, hwaddr physical, int *prot,
	141	target_ulong address, int rw, int access_type);
	142	void r4k_helper_tlbwi(CPUMIPSState *env);
	143	void r4k_helper_tlbwr(CPUMIPSState *env);
	144	void r4k_helper_tlbp(CPUMIPSState *env);
	145	void r4k_helper_tlbr(CPUMIPSState *env);
	146	void r4k_helper_tlbinv(CPUMIPSState *env);
	147	void r4k_helper_tlbinvf(CPUMIPSState *env);
	148	void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
2dc29222	149	uint32_t cpu_mips_get_random(CPUMIPSState *env);
26aa3d9a	150
4f02a06d PM	151	void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
	152	vaddr addr, unsigned size,
	153	MMUAccessType access_type,
	154	int mmu_idx, MemTxAttrs attrs,
	155	MemTxResult response, uintptr_t retaddr);
26aa3d9a PMD	156	hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
	157	int rw);
	158	#endif
	159
	160	#define cpu_signal_handler cpu_mips_signal_handler
	161
	162	#ifndef CONFIG_USER_ONLY
8a9358cc	163	extern const VMStateDescription vmstate_mips_cpu;
26aa3d9a PMD	164	#endif
	165
	166	static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
	167	{
	168	return (env->CP0_Status & (1 << CP0St_IE)) &&
	169	!(env->CP0_Status & (1 << CP0St_EXL)) &&
	170	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	171	!(env->hflags & MIPS_HFLAG_DM) &&
7ba0e95b AM	172	/*
	173	* Note that the TCStatus IXMT field is initialized to zero,
	174	* and only MT capable cores can set it to one. So we don't
	175	* need to check for MT capabilities here.
	176	*/
26aa3d9a PMD	177	!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
	178	}
	179
	180	/* Check if there is pending and not masked out interrupt */
	181	static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
	182	{
	183	int32_t pending;
	184	int32_t status;
	185	bool r;
	186
	187	pending = env->CP0_Cause & CP0Ca_IP_mask;
	188	status = env->CP0_Status & CP0Ca_IP_mask;
	189
	190	if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
7ba0e95b AM	191	/*
	192	* A MIPS configured with a vectorizing external interrupt controller
	193	* will feed a vector into the Cause pending lines. The core treats
8cdf8869	194	* the status lines as a vector level, not as individual masks.
7ba0e95b	195	*/
26aa3d9a PMD	196	r = pending > status;
26aa3d9a PMD	197	} else {
7ba0e95b AM	198	/*
	199	* A MIPS configured with compatibility or VInt (Vectored Interrupts)
	200	* treats the pending lines as individual interrupt lines, the status
	201	* lines are individual masks.
	202	*/
26aa3d9a PMD	203	r = (pending & status) != 0;
	204	}
	205	return r;
	206	}
	207
	208	void mips_tcg_init(void);
	209
26aa3d9a	210	/* cp0_timer.c */
26aa3d9a PMD	211	uint32_t cpu_mips_get_count(CPUMIPSState *env);
	212	void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
	213	void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
	214	void cpu_mips_start_count(CPUMIPSState *env);
	215	void cpu_mips_stop_count(CPUMIPSState *env);
	216
	217	/* helper.c */
931d019f RH	218	bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	219	MMUAccessType access_type, int mmu_idx,
	220	bool probe, uintptr_t retaddr);
26aa3d9a PMD	221
	222	/* op_helper.c */
	223	uint32_t float_class_s(uint32_t arg, float_status *fst);
	224	uint64_t float_class_d(uint64_t arg, float_status *fst);
	225
3533ee30 PMD	226	extern const FloatRoundMode ieee_rm[4];
3533ee30 PMD	227
074cfcb4	228	void update_pagemask(CPUMIPSState env, target_ulong arg1, int32_t pagemask);
26aa3d9a PMD	229
	230	static inline void restore_rounding_mode(CPUMIPSState *env)
	231	{
	232	set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
	233	&env->active_fpu.fp_status);
	234	}
	235
	236	static inline void restore_flush_mode(CPUMIPSState *env)
	237	{
	238	set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
	239	&env->active_fpu.fp_status);
502700d0 AB	240	}
	241
	242	static inline void restore_snan_bit_mode(CPUMIPSState *env)
	243	{
	244	set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
	245	&env->active_fpu.fp_status);
26aa3d9a PMD	246	}
	247
	248	static inline void restore_fp_status(CPUMIPSState *env)
	249	{
	250	restore_rounding_mode(env);
	251	restore_flush_mode(env);
	252	restore_snan_bit_mode(env);
	253	}
	254
	255	static inline void restore_msa_fp_status(CPUMIPSState *env)
	256	{
	257	float_status *status = &env->active_tc.msa_fp_status;
	258	int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
	259	bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
	260
	261	set_float_rounding_mode(ieee_rm[rounding_mode], status);
	262	set_flush_to_zero(flush_to_zero, status);
	263	set_flush_inputs_to_zero(flush_to_zero, status);
	264	}
	265
	266	static inline void restore_pamask(CPUMIPSState *env)
	267	{
	268	if (env->hflags & MIPS_HFLAG_ELPA) {
	269	env->PAMask = (1ULL << env->PABITS) - 1;
	270	} else {
	271	env->PAMask = PAMASK_BASE;
	272	}
	273	}
	274
	275	static inline int mips_vpe_active(CPUMIPSState *env)
	276	{
	277	int active = 1;
	278
	279	/* Check that the VPE is enabled. */
	280	if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
	281	active = 0;
	282	}
	283	/* Check that the VPE is activated. */
	284	if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
	285	active = 0;
	286	}
	287
7ba0e95b AM	288	/*
	289	* Now verify that there are active thread contexts in the VPE.
	290	*
	291	* This assumes the CPU model will internally reschedule threads
	292	* if the active one goes to sleep. If there are no threads available
	293	* the active one will be in a sleeping state, and we can turn off
	294	* the entire VPE.
	295	*/
26aa3d9a PMD	296	if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
	297	/* TC is not activated. */
	298	active = 0;
	299	}
	300	if (env->active_tc.CP0_TCHalt & 1) {
	301	/* TC is in halt state. */
	302	active = 0;
	303	}
	304
	305	return active;
	306	}
	307
	308	static inline int mips_vp_active(CPUMIPSState *env)
	309	{
	310	CPUState *other_cs = first_cpu;
	311
	312	/* Check if the VP disabled other VPs (which means the VP is enabled) */
	313	if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
	314	return 1;
	315	}
	316
	317	/* Check if the virtual processor is disabled due to a DVP */
	318	CPU_FOREACH(other_cs) {
	319	MIPSCPU *other_cpu = MIPS_CPU(other_cs);
	320	if ((&other_cpu->env != env) &&
	321	((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
	322	return 0;
	323	}
	324	}
	325	return 1;
	326	}
	327
	328	static inline void compute_hflags(CPUMIPSState *env)
	329	{
	330	env->hflags &= ~(MIPS_HFLAG_COP1X \| MIPS_HFLAG_64 \| MIPS_HFLAG_CP0 \|
	331	MIPS_HFLAG_F64 \| MIPS_HFLAG_FPU \| MIPS_HFLAG_KSU \|
908f6be1 SM	332	MIPS_HFLAG_AWRAP \| MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	333	MIPS_HFLAG_DSP_R3 \| MIPS_HFLAG_SBRI \| MIPS_HFLAG_MSA \|
59e781fb	334	MIPS_HFLAG_FRE \| MIPS_HFLAG_ELPA \| MIPS_HFLAG_ERL);
26aa3d9a PMD	335	if (env->CP0_Status & (1 << CP0St_ERL)) {
	336	env->hflags \|= MIPS_HFLAG_ERL;
	337	}
	338	if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
	339	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	340	!(env->hflags & MIPS_HFLAG_DM)) {
7ba0e95b AM	341	env->hflags \|= (env->CP0_Status >> CP0St_KSU) &
7ba0e95b AM	342	MIPS_HFLAG_KSU;
26aa3d9a PMD	343	}
	344	#if defined(TARGET_MIPS64)
	345	if ((env->insn_flags & ISA_MIPS3) &&
	346	(((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) \|\|
	347	(env->CP0_Status & (1 << CP0St_PX)) \|\|
	348	(env->CP0_Status & (1 << CP0St_UX)))) {
	349	env->hflags \|= MIPS_HFLAG_64;
	350	}
	351
	352	if (!(env->insn_flags & ISA_MIPS3)) {
	353	env->hflags \|= MIPS_HFLAG_AWRAP;
	354	} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
	355	!(env->CP0_Status & (1 << CP0St_UX))) {
	356	env->hflags \|= MIPS_HFLAG_AWRAP;
	357	} else if (env->insn_flags & ISA_MIPS64R6) {
	358	/* Address wrapping for Supervisor and Kernel is specified in R6 */
	359	if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
	360	!(env->CP0_Status & (1 << CP0St_SX))) \|\|
	361	(((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
	362	!(env->CP0_Status & (1 << CP0St_KX)))) {
	363	env->hflags \|= MIPS_HFLAG_AWRAP;
	364	}
	365	}
	366	#endif
	367	if (((env->CP0_Status & (1 << CP0St_CU0)) &&
	368	!(env->insn_flags & ISA_MIPS32R6)) \|\|
	369	!(env->hflags & MIPS_HFLAG_KSU)) {
	370	env->hflags \|= MIPS_HFLAG_CP0;
	371	}
	372	if (env->CP0_Status & (1 << CP0St_CU1)) {
	373	env->hflags \|= MIPS_HFLAG_FPU;
	374	}
	375	if (env->CP0_Status & (1 << CP0St_FR)) {
	376	env->hflags \|= MIPS_HFLAG_F64;
	377	}
	378	if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
	379	(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
	380	env->hflags \|= MIPS_HFLAG_SBRI;
	381	}
908f6be1 SM	382	if (env->insn_flags & ASE_DSP_R3) {
	383	/*
	384	* Our cpu supports DSP R3 ASE, so enable
	385	* access to DSP R3 resources.
	386	*/
59e781fb	387	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1 SM	388	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	389	MIPS_HFLAG_DSP_R3;
59e781fb	390	}
908f6be1 SM	391	} else if (env->insn_flags & ASE_DSP_R2) {
	392	/*
	393	* Our cpu supports DSP R2 ASE, so enable
	394	* access to DSP R2 resources.
	395	*/
26aa3d9a	396	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1	397	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2;
26aa3d9a PMD	398	}
	399
	400	} else if (env->insn_flags & ASE_DSP) {
908f6be1 SM	401	/*
	402	* Our cpu supports DSP ASE, so enable
	403	* access to DSP resources.
	404	*/
26aa3d9a PMD	405	if (env->CP0_Status & (1 << CP0St_MX)) {
	406	env->hflags \|= MIPS_HFLAG_DSP;
	407	}
	408
	409	}
	410	if (env->insn_flags & ISA_MIPS32R2) {
	411	if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
	412	env->hflags \|= MIPS_HFLAG_COP1X;
	413	}
	414	} else if (env->insn_flags & ISA_MIPS32) {
	415	if (env->hflags & MIPS_HFLAG_64) {
	416	env->hflags \|= MIPS_HFLAG_COP1X;
	417	}
	418	} else if (env->insn_flags & ISA_MIPS4) {
7ba0e95b AM	419	/*
	420	* All supported MIPS IV CPUs use the XX (CU3) to enable
	421	* and disable the MIPS IV extensions to the MIPS III ISA.
	422	* Some other MIPS IV CPUs ignore the bit, so the check here
	423	* would be too restrictive for them.
	424	*/
26aa3d9a PMD	425	if (env->CP0_Status & (1U << CP0St_CU3)) {
	426	env->hflags \|= MIPS_HFLAG_COP1X;
	427	}
	428	}
	429	if (env->insn_flags & ASE_MSA) {
	430	if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
	431	env->hflags \|= MIPS_HFLAG_MSA;
	432	}
	433	}
	434	if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
	435	if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
	436	env->hflags \|= MIPS_HFLAG_FRE;
	437	}
	438	}
	439	if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
	440	if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
	441	env->hflags \|= MIPS_HFLAG_ELPA;
	442	}
	443	}
	444	}
	445
	446	void cpu_mips_tlb_flush(CPUMIPSState *env);
	447	void sync_c0_status(CPUMIPSState env, CPUMIPSState cpu, int tc);
	448	void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
	449	void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
	450
	451	void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
	452	int error_code, uintptr_t pc);
	453
	454	static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
	455	uint32_t exception,
	456	uintptr_t pc)
	457	{
	458	do_raise_exception_err(env, exception, 0, pc);
	459	}
	460
	461	#endif