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Commit | Line | Data |
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7ba0e95b AM |
1 | /* |
2 | * MIPS internal definitions and helpers | |
26aa3d9a PMD |
3 | * |
4 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
5 | * See the COPYING file in the top-level directory. | |
6 | */ | |
7 | ||
8 | #ifndef MIPS_INTERNAL_H | |
9 | #define MIPS_INTERNAL_H | |
10 | ||
34cffe96 | 11 | #include "exec/memattrs.h" |
41da212c | 12 | |
7ba0e95b AM |
13 | /* |
14 | * MMU types, the first four entries have the same layout as the | |
15 | * CP0C0_MT field. | |
16 | */ | |
41da212c | 17 | enum mips_mmu_types { |
1ab3a0de PMD |
18 | MMU_TYPE_NONE = 0, |
19 | MMU_TYPE_R4000 = 1, /* Standard TLB */ | |
20 | MMU_TYPE_BAT = 2, /* Block Address Translation */ | |
21 | MMU_TYPE_FMT = 3, /* Fixed Mapping */ | |
22 | MMU_TYPE_DVF = 4, /* Dual VTLB and FTLB */ | |
41da212c IM |
23 | MMU_TYPE_R3000, |
24 | MMU_TYPE_R6000, | |
25 | MMU_TYPE_R8000 | |
26 | }; | |
27 | ||
28 | struct mips_def_t { | |
29 | const char *name; | |
30 | int32_t CP0_PRid; | |
31 | int32_t CP0_Config0; | |
32 | int32_t CP0_Config1; | |
33 | int32_t CP0_Config2; | |
34 | int32_t CP0_Config3; | |
35 | int32_t CP0_Config4; | |
36 | int32_t CP0_Config4_rw_bitmask; | |
37 | int32_t CP0_Config5; | |
38 | int32_t CP0_Config5_rw_bitmask; | |
39 | int32_t CP0_Config6; | |
af868995 | 40 | int32_t CP0_Config6_rw_bitmask; |
41da212c | 41 | int32_t CP0_Config7; |
af868995 | 42 | int32_t CP0_Config7_rw_bitmask; |
41da212c IM |
43 | target_ulong CP0_LLAddr_rw_bitmask; |
44 | int CP0_LLAddr_shift; | |
45 | int32_t SYNCI_Step; | |
46 | int32_t CCRes; | |
47 | int32_t CP0_Status_rw_bitmask; | |
48 | int32_t CP0_TCStatus_rw_bitmask; | |
49 | int32_t CP0_SRSCtl; | |
50 | int32_t CP1_fcr0; | |
51 | int32_t CP1_fcr31_rw_bitmask; | |
52 | int32_t CP1_fcr31; | |
53 | int32_t MSAIR; | |
54 | int32_t SEGBITS; | |
55 | int32_t PABITS; | |
56 | int32_t CP0_SRSConf0_rw_bitmask; | |
57 | int32_t CP0_SRSConf0; | |
58 | int32_t CP0_SRSConf1_rw_bitmask; | |
59 | int32_t CP0_SRSConf1; | |
60 | int32_t CP0_SRSConf2_rw_bitmask; | |
61 | int32_t CP0_SRSConf2; | |
62 | int32_t CP0_SRSConf3_rw_bitmask; | |
63 | int32_t CP0_SRSConf3; | |
64 | int32_t CP0_SRSConf4_rw_bitmask; | |
65 | int32_t CP0_SRSConf4; | |
66 | int32_t CP0_PageGrain_rw_bitmask; | |
67 | int32_t CP0_PageGrain; | |
68 | target_ulong CP0_EBaseWG_rw_bitmask; | |
f9c9cd63 | 69 | uint64_t insn_flags; |
41da212c | 70 | enum mips_mmu_types mmu_type; |
5fb2dcd1 | 71 | int32_t SAARP; |
41da212c IM |
72 | }; |
73 | ||
74 | extern const struct mips_def_t mips_defs[]; | |
75 | extern const int mips_defs_number; | |
76 | ||
26aa3d9a PMD |
77 | void mips_cpu_do_interrupt(CPUState *cpu); |
78 | bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); | |
90c84c56 | 79 | void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
26aa3d9a | 80 | hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
a010bdbe | 81 | int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); |
26aa3d9a PMD |
82 | int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
83 | void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | |
84 | MMUAccessType access_type, | |
85 | int mmu_idx, uintptr_t retaddr); | |
86 | ||
87 | #if !defined(CONFIG_USER_ONLY) | |
88 | ||
89 | typedef struct r4k_tlb_t r4k_tlb_t; | |
90 | struct r4k_tlb_t { | |
91 | target_ulong VPN; | |
92 | uint32_t PageMask; | |
93 | uint16_t ASID; | |
99029be1 | 94 | uint32_t MMID; |
26aa3d9a PMD |
95 | unsigned int G:1; |
96 | unsigned int C0:3; | |
97 | unsigned int C1:3; | |
98 | unsigned int V0:1; | |
99 | unsigned int V1:1; | |
100 | unsigned int D0:1; | |
101 | unsigned int D1:1; | |
102 | unsigned int XI0:1; | |
103 | unsigned int XI1:1; | |
104 | unsigned int RI0:1; | |
105 | unsigned int RI1:1; | |
106 | unsigned int EHINV:1; | |
107 | uint64_t PFN[2]; | |
108 | }; | |
109 | ||
110 | struct CPUMIPSTLBContext { | |
111 | uint32_t nb_tlb; | |
112 | uint32_t tlb_in_use; | |
113 | int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot, | |
114 | target_ulong address, int rw, int access_type); | |
115 | void (*helper_tlbwi)(struct CPUMIPSState *env); | |
116 | void (*helper_tlbwr)(struct CPUMIPSState *env); | |
117 | void (*helper_tlbp)(struct CPUMIPSState *env); | |
118 | void (*helper_tlbr)(struct CPUMIPSState *env); | |
119 | void (*helper_tlbinv)(struct CPUMIPSState *env); | |
120 | void (*helper_tlbinvf)(struct CPUMIPSState *env); | |
121 | union { | |
122 | struct { | |
123 | r4k_tlb_t tlb[MIPS_TLB_MAX]; | |
124 | } r4k; | |
125 | } mmu; | |
126 | }; | |
127 | ||
128 | int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, | |
129 | target_ulong address, int rw, int access_type); | |
130 | int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, | |
131 | target_ulong address, int rw, int access_type); | |
132 | int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, | |
133 | target_ulong address, int rw, int access_type); | |
134 | void r4k_helper_tlbwi(CPUMIPSState *env); | |
135 | void r4k_helper_tlbwr(CPUMIPSState *env); | |
136 | void r4k_helper_tlbp(CPUMIPSState *env); | |
137 | void r4k_helper_tlbr(CPUMIPSState *env); | |
138 | void r4k_helper_tlbinv(CPUMIPSState *env); | |
139 | void r4k_helper_tlbinvf(CPUMIPSState *env); | |
140 | void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); | |
2dc29222 | 141 | uint32_t cpu_mips_get_random(CPUMIPSState *env); |
26aa3d9a | 142 | |
4f02a06d PM |
143 | void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, |
144 | vaddr addr, unsigned size, | |
145 | MMUAccessType access_type, | |
146 | int mmu_idx, MemTxAttrs attrs, | |
147 | MemTxResult response, uintptr_t retaddr); | |
26aa3d9a PMD |
148 | hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, |
149 | int rw); | |
150 | #endif | |
151 | ||
152 | #define cpu_signal_handler cpu_mips_signal_handler | |
153 | ||
154 | #ifndef CONFIG_USER_ONLY | |
8a9358cc | 155 | extern const VMStateDescription vmstate_mips_cpu; |
26aa3d9a PMD |
156 | #endif |
157 | ||
158 | static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) | |
159 | { | |
160 | return (env->CP0_Status & (1 << CP0St_IE)) && | |
161 | !(env->CP0_Status & (1 << CP0St_EXL)) && | |
162 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
163 | !(env->hflags & MIPS_HFLAG_DM) && | |
7ba0e95b AM |
164 | /* |
165 | * Note that the TCStatus IXMT field is initialized to zero, | |
166 | * and only MT capable cores can set it to one. So we don't | |
167 | * need to check for MT capabilities here. | |
168 | */ | |
26aa3d9a PMD |
169 | !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)); |
170 | } | |
171 | ||
172 | /* Check if there is pending and not masked out interrupt */ | |
173 | static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) | |
174 | { | |
175 | int32_t pending; | |
176 | int32_t status; | |
177 | bool r; | |
178 | ||
179 | pending = env->CP0_Cause & CP0Ca_IP_mask; | |
180 | status = env->CP0_Status & CP0Ca_IP_mask; | |
181 | ||
182 | if (env->CP0_Config3 & (1 << CP0C3_VEIC)) { | |
7ba0e95b AM |
183 | /* |
184 | * A MIPS configured with a vectorizing external interrupt controller | |
185 | * will feed a vector into the Cause pending lines. The core treats | |
8cdf8869 | 186 | * the status lines as a vector level, not as individual masks. |
7ba0e95b | 187 | */ |
26aa3d9a PMD |
188 | r = pending > status; |
189 | } else { | |
7ba0e95b AM |
190 | /* |
191 | * A MIPS configured with compatibility or VInt (Vectored Interrupts) | |
192 | * treats the pending lines as individual interrupt lines, the status | |
193 | * lines are individual masks. | |
194 | */ | |
26aa3d9a PMD |
195 | r = (pending & status) != 0; |
196 | } | |
197 | return r; | |
198 | } | |
199 | ||
200 | void mips_tcg_init(void); | |
201 | ||
26aa3d9a | 202 | /* cp0_timer.c */ |
26aa3d9a PMD |
203 | uint32_t cpu_mips_get_count(CPUMIPSState *env); |
204 | void cpu_mips_store_count(CPUMIPSState *env, uint32_t value); | |
205 | void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); | |
206 | void cpu_mips_start_count(CPUMIPSState *env); | |
207 | void cpu_mips_stop_count(CPUMIPSState *env); | |
208 | ||
209 | /* helper.c */ | |
f2c5b39e | 210 | void mmu_init(CPUMIPSState *env, const mips_def_t *def); |
931d019f RH |
211 | bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
212 | MMUAccessType access_type, int mmu_idx, | |
213 | bool probe, uintptr_t retaddr); | |
26aa3d9a PMD |
214 | |
215 | /* op_helper.c */ | |
074cfcb4 | 216 | void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); |
26aa3d9a | 217 | |
26aa3d9a PMD |
218 | static inline void restore_pamask(CPUMIPSState *env) |
219 | { | |
220 | if (env->hflags & MIPS_HFLAG_ELPA) { | |
221 | env->PAMask = (1ULL << env->PABITS) - 1; | |
222 | } else { | |
223 | env->PAMask = PAMASK_BASE; | |
224 | } | |
225 | } | |
226 | ||
227 | static inline int mips_vpe_active(CPUMIPSState *env) | |
228 | { | |
229 | int active = 1; | |
230 | ||
231 | /* Check that the VPE is enabled. */ | |
232 | if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) { | |
233 | active = 0; | |
234 | } | |
235 | /* Check that the VPE is activated. */ | |
236 | if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) { | |
237 | active = 0; | |
238 | } | |
239 | ||
7ba0e95b AM |
240 | /* |
241 | * Now verify that there are active thread contexts in the VPE. | |
242 | * | |
243 | * This assumes the CPU model will internally reschedule threads | |
244 | * if the active one goes to sleep. If there are no threads available | |
245 | * the active one will be in a sleeping state, and we can turn off | |
246 | * the entire VPE. | |
247 | */ | |
26aa3d9a PMD |
248 | if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) { |
249 | /* TC is not activated. */ | |
250 | active = 0; | |
251 | } | |
252 | if (env->active_tc.CP0_TCHalt & 1) { | |
253 | /* TC is in halt state. */ | |
254 | active = 0; | |
255 | } | |
256 | ||
257 | return active; | |
258 | } | |
259 | ||
260 | static inline int mips_vp_active(CPUMIPSState *env) | |
261 | { | |
262 | CPUState *other_cs = first_cpu; | |
263 | ||
264 | /* Check if the VP disabled other VPs (which means the VP is enabled) */ | |
265 | if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { | |
266 | return 1; | |
267 | } | |
268 | ||
269 | /* Check if the virtual processor is disabled due to a DVP */ | |
270 | CPU_FOREACH(other_cs) { | |
271 | MIPSCPU *other_cpu = MIPS_CPU(other_cs); | |
272 | if ((&other_cpu->env != env) && | |
273 | ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) { | |
274 | return 0; | |
275 | } | |
276 | } | |
277 | return 1; | |
278 | } | |
279 | ||
280 | static inline void compute_hflags(CPUMIPSState *env) | |
281 | { | |
282 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | | |
283 | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | | |
908f6be1 SM |
284 | MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | |
285 | MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | | |
59e781fb | 286 | MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL); |
26aa3d9a PMD |
287 | if (env->CP0_Status & (1 << CP0St_ERL)) { |
288 | env->hflags |= MIPS_HFLAG_ERL; | |
289 | } | |
290 | if (!(env->CP0_Status & (1 << CP0St_EXL)) && | |
291 | !(env->CP0_Status & (1 << CP0St_ERL)) && | |
292 | !(env->hflags & MIPS_HFLAG_DM)) { | |
7ba0e95b AM |
293 | env->hflags |= (env->CP0_Status >> CP0St_KSU) & |
294 | MIPS_HFLAG_KSU; | |
26aa3d9a PMD |
295 | } |
296 | #if defined(TARGET_MIPS64) | |
297 | if ((env->insn_flags & ISA_MIPS3) && | |
298 | (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) || | |
299 | (env->CP0_Status & (1 << CP0St_PX)) || | |
300 | (env->CP0_Status & (1 << CP0St_UX)))) { | |
301 | env->hflags |= MIPS_HFLAG_64; | |
302 | } | |
303 | ||
304 | if (!(env->insn_flags & ISA_MIPS3)) { | |
305 | env->hflags |= MIPS_HFLAG_AWRAP; | |
306 | } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) && | |
307 | !(env->CP0_Status & (1 << CP0St_UX))) { | |
308 | env->hflags |= MIPS_HFLAG_AWRAP; | |
2e211e0a | 309 | } else if (env->insn_flags & ISA_MIPS_R6) { |
26aa3d9a PMD |
310 | /* Address wrapping for Supervisor and Kernel is specified in R6 */ |
311 | if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) && | |
312 | !(env->CP0_Status & (1 << CP0St_SX))) || | |
313 | (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) && | |
314 | !(env->CP0_Status & (1 << CP0St_KX)))) { | |
315 | env->hflags |= MIPS_HFLAG_AWRAP; | |
316 | } | |
317 | } | |
318 | #endif | |
319 | if (((env->CP0_Status & (1 << CP0St_CU0)) && | |
2e211e0a | 320 | !(env->insn_flags & ISA_MIPS_R6)) || |
26aa3d9a PMD |
321 | !(env->hflags & MIPS_HFLAG_KSU)) { |
322 | env->hflags |= MIPS_HFLAG_CP0; | |
323 | } | |
324 | if (env->CP0_Status & (1 << CP0St_CU1)) { | |
325 | env->hflags |= MIPS_HFLAG_FPU; | |
326 | } | |
327 | if (env->CP0_Status & (1 << CP0St_FR)) { | |
328 | env->hflags |= MIPS_HFLAG_F64; | |
329 | } | |
330 | if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) && | |
331 | (env->CP0_Config5 & (1 << CP0C5_SBRI))) { | |
332 | env->hflags |= MIPS_HFLAG_SBRI; | |
333 | } | |
908f6be1 SM |
334 | if (env->insn_flags & ASE_DSP_R3) { |
335 | /* | |
336 | * Our cpu supports DSP R3 ASE, so enable | |
337 | * access to DSP R3 resources. | |
338 | */ | |
59e781fb | 339 | if (env->CP0_Status & (1 << CP0St_MX)) { |
908f6be1 SM |
340 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 | |
341 | MIPS_HFLAG_DSP_R3; | |
59e781fb | 342 | } |
908f6be1 SM |
343 | } else if (env->insn_flags & ASE_DSP_R2) { |
344 | /* | |
345 | * Our cpu supports DSP R2 ASE, so enable | |
346 | * access to DSP R2 resources. | |
347 | */ | |
26aa3d9a | 348 | if (env->CP0_Status & (1 << CP0St_MX)) { |
908f6be1 | 349 | env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2; |
26aa3d9a PMD |
350 | } |
351 | ||
352 | } else if (env->insn_flags & ASE_DSP) { | |
908f6be1 SM |
353 | /* |
354 | * Our cpu supports DSP ASE, so enable | |
355 | * access to DSP resources. | |
356 | */ | |
26aa3d9a PMD |
357 | if (env->CP0_Status & (1 << CP0St_MX)) { |
358 | env->hflags |= MIPS_HFLAG_DSP; | |
359 | } | |
360 | ||
361 | } | |
7a47bae5 | 362 | if (env->insn_flags & ISA_MIPS_R2) { |
26aa3d9a PMD |
363 | if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { |
364 | env->hflags |= MIPS_HFLAG_COP1X; | |
365 | } | |
bbd5e4a2 | 366 | } else if (env->insn_flags & ISA_MIPS_R1) { |
26aa3d9a PMD |
367 | if (env->hflags & MIPS_HFLAG_64) { |
368 | env->hflags |= MIPS_HFLAG_COP1X; | |
369 | } | |
370 | } else if (env->insn_flags & ISA_MIPS4) { | |
7ba0e95b AM |
371 | /* |
372 | * All supported MIPS IV CPUs use the XX (CU3) to enable | |
373 | * and disable the MIPS IV extensions to the MIPS III ISA. | |
374 | * Some other MIPS IV CPUs ignore the bit, so the check here | |
375 | * would be too restrictive for them. | |
376 | */ | |
26aa3d9a PMD |
377 | if (env->CP0_Status & (1U << CP0St_CU3)) { |
378 | env->hflags |= MIPS_HFLAG_COP1X; | |
379 | } | |
380 | } | |
381 | if (env->insn_flags & ASE_MSA) { | |
382 | if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) { | |
383 | env->hflags |= MIPS_HFLAG_MSA; | |
384 | } | |
385 | } | |
386 | if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { | |
387 | if (env->CP0_Config5 & (1 << CP0C5_FRE)) { | |
388 | env->hflags |= MIPS_HFLAG_FRE; | |
389 | } | |
390 | } | |
391 | if (env->CP0_Config3 & (1 << CP0C3_LPA)) { | |
392 | if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) { | |
393 | env->hflags |= MIPS_HFLAG_ELPA; | |
394 | } | |
395 | } | |
396 | } | |
397 | ||
398 | void cpu_mips_tlb_flush(CPUMIPSState *env); | |
399 | void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); | |
400 | void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); | |
401 | void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); | |
402 | ||
e9927723 PMD |
403 | const char *mips_exception_name(int32_t exception); |
404 | ||
26aa3d9a PMD |
405 | void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, |
406 | int error_code, uintptr_t pc); | |
407 | ||
408 | static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, | |
409 | uint32_t exception, | |
410 | uintptr_t pc) | |
411 | { | |
412 | do_raise_exception_err(env, exception, 0, pc); | |
413 | } | |
414 | ||
415 | #endif |