[mirror_qemu.git] / target / mips / internal.h

/*
 * MIPS internal definitions and helpers
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#ifndef MIPS_INTERNAL_H
#define MIPS_INTERNAL_H

#include "exec/memattrs.h"
#include "fpu/softfloat-helpers.h"

/*
 * MMU types, the first four entries have the same layout as the
 * CP0C0_MT field.
 */
enum mips_mmu_types {
    MMU_TYPE_NONE,
    MMU_TYPE_R4000,
    MMU_TYPE_RESERVED,
    MMU_TYPE_FMT,
    MMU_TYPE_R3000,
    MMU_TYPE_R6000,
    MMU_TYPE_R8000
};

struct mips_def_t {
    const char *name;
    int32_t CP0_PRid;
    int32_t CP0_Config0;
    int32_t CP0_Config1;
    int32_t CP0_Config2;
    int32_t CP0_Config3;
    int32_t CP0_Config4;
    int32_t CP0_Config4_rw_bitmask;
    int32_t CP0_Config5;
    int32_t CP0_Config5_rw_bitmask;
    int32_t CP0_Config6;
    int32_t CP0_Config6_rw_bitmask;
    int32_t CP0_Config7;
    int32_t CP0_Config7_rw_bitmask;
    target_ulong CP0_LLAddr_rw_bitmask;
    int CP0_LLAddr_shift;
    int32_t SYNCI_Step;
    int32_t CCRes;
    int32_t CP0_Status_rw_bitmask;
    int32_t CP0_TCStatus_rw_bitmask;
    int32_t CP0_SRSCtl;
    int32_t CP1_fcr0;
    int32_t CP1_fcr31_rw_bitmask;
    int32_t CP1_fcr31;
    int32_t MSAIR;
    int32_t SEGBITS;
    int32_t PABITS;
    int32_t CP0_SRSConf0_rw_bitmask;
    int32_t CP0_SRSConf0;
    int32_t CP0_SRSConf1_rw_bitmask;
    int32_t CP0_SRSConf1;
    int32_t CP0_SRSConf2_rw_bitmask;
    int32_t CP0_SRSConf2;
    int32_t CP0_SRSConf3_rw_bitmask;
    int32_t CP0_SRSConf3;
    int32_t CP0_SRSConf4_rw_bitmask;
    int32_t CP0_SRSConf4;
    int32_t CP0_PageGrain_rw_bitmask;
    int32_t CP0_PageGrain;
    target_ulong CP0_EBaseWG_rw_bitmask;
    uint64_t insn_flags;
    enum mips_mmu_types mmu_type;
    int32_t SAARP;
};

extern const struct mips_def_t mips_defs[];
extern const int mips_defs_number;

enum CPUMIPSMSADataFormat {
    DF_BYTE = 0,
    DF_HALF,
    DF_WORD,
    DF_DOUBLE
};

void mips_cpu_do_interrupt(CPUState *cpu);
bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
                                  MMUAccessType access_type,
                                  int mmu_idx, uintptr_t retaddr);

#if !defined(CONFIG_USER_ONLY)

typedef struct r4k_tlb_t r4k_tlb_t;
struct r4k_tlb_t {
    target_ulong VPN;
    uint32_t PageMask;
    uint16_t ASID;
    uint32_t MMID;
    unsigned int G:1;
    unsigned int C0:3;
    unsigned int C1:3;
    unsigned int V0:1;
    unsigned int V1:1;
    unsigned int D0:1;
    unsigned int D1:1;
    unsigned int XI0:1;
    unsigned int XI1:1;
    unsigned int RI0:1;
    unsigned int RI1:1;
    unsigned int EHINV:1;
    uint64_t PFN[2];
};

struct CPUMIPSTLBContext {
    uint32_t nb_tlb;
    uint32_t tlb_in_use;
    int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *prot,
                       target_ulong address, int rw, int access_type);
    void (*helper_tlbwi)(struct CPUMIPSState *env);
    void (*helper_tlbwr)(struct CPUMIPSState *env);
    void (*helper_tlbp)(struct CPUMIPSState *env);
    void (*helper_tlbr)(struct CPUMIPSState *env);
    void (*helper_tlbinv)(struct CPUMIPSState *env);
    void (*helper_tlbinvf)(struct CPUMIPSState *env);
    union {
        struct {
            r4k_tlb_t tlb[MIPS_TLB_MAX];
        } r4k;
    } mmu;
};

int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                       target_ulong address, int rw, int access_type);
int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                          target_ulong address, int rw, int access_type);
int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
                    target_ulong address, int rw, int access_type);
void r4k_helper_tlbwi(CPUMIPSState *env);
void r4k_helper_tlbwr(CPUMIPSState *env);
void r4k_helper_tlbp(CPUMIPSState *env);
void r4k_helper_tlbr(CPUMIPSState *env);
void r4k_helper_tlbinv(CPUMIPSState *env);
void r4k_helper_tlbinvf(CPUMIPSState *env);
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
uint32_t cpu_mips_get_random(CPUMIPSState *env);

void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
                                    vaddr addr, unsigned size,
                                    MMUAccessType access_type,
                                    int mmu_idx, MemTxAttrs attrs,
                                    MemTxResult response, uintptr_t retaddr);
hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
                                  int rw);
#endif

#define cpu_signal_handler cpu_mips_signal_handler

#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_mips_cpu;
#endif

static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
{
    return (env->CP0_Status & (1 << CP0St_IE)) &&
        !(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM) &&
        /*
         * Note that the TCStatus IXMT field is initialized to zero,
         * and only MT capable cores can set it to one. So we don't
         * need to check for MT capabilities here.
         */
        !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
}

/* Check if there is pending and not masked out interrupt */
static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
{
    int32_t pending;
    int32_t status;
    bool r;

    pending = env->CP0_Cause & CP0Ca_IP_mask;
    status = env->CP0_Status & CP0Ca_IP_mask;

    if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
        /*
         * A MIPS configured with a vectorizing external interrupt controller
         * will feed a vector into the Cause pending lines. The core treats
         * the status lines as a vector level, not as individual masks.
         */
        r = pending > status;
    } else {
        /*
         * A MIPS configured with compatibility or VInt (Vectored Interrupts)
         * treats the pending lines as individual interrupt lines, the status
         * lines are individual masks.
         */
        r = (pending & status) != 0;
    }
    return r;
}

void mips_tcg_init(void);

/* TODO QOM'ify CPU reset and remove */
void cpu_state_reset(CPUMIPSState *s);
void cpu_mips_realize_env(CPUMIPSState *env);

/* cp0_timer.c */
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);

/* helper.c */
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                       MMUAccessType access_type, int mmu_idx,
                       bool probe, uintptr_t retaddr);

/* op_helper.c */
uint32_t float_class_s(uint32_t arg, float_status *fst);
uint64_t float_class_d(uint64_t arg, float_status *fst);

extern unsigned int ieee_rm[];
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);

static inline void restore_rounding_mode(CPUMIPSState *env)
{
    set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
                            &env->active_fpu.fp_status);
}

static inline void restore_flush_mode(CPUMIPSState *env)
{
    set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
                      &env->active_fpu.fp_status);
}

static inline void restore_snan_bit_mode(CPUMIPSState *env)
{
    set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
                        &env->active_fpu.fp_status);
}

static inline void restore_fp_status(CPUMIPSState *env)
{
    restore_rounding_mode(env);
    restore_flush_mode(env);
    restore_snan_bit_mode(env);
}

static inline void restore_msa_fp_status(CPUMIPSState *env)
{
    float_status *status = &env->active_tc.msa_fp_status;
    int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
    bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;

    set_float_rounding_mode(ieee_rm[rounding_mode], status);
    set_flush_to_zero(flush_to_zero, status);
    set_flush_inputs_to_zero(flush_to_zero, status);
}

static inline void restore_pamask(CPUMIPSState *env)
{
    if (env->hflags & MIPS_HFLAG_ELPA) {
        env->PAMask = (1ULL << env->PABITS) - 1;
    } else {
        env->PAMask = PAMASK_BASE;
    }
}

static inline int mips_vpe_active(CPUMIPSState *env)
{
    int active = 1;

    /* Check that the VPE is enabled.  */
    if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
        active = 0;
    }
    /* Check that the VPE is activated.  */
    if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
        active = 0;
    }

    /*
     * Now verify that there are active thread contexts in the VPE.
     *
     * This assumes the CPU model will internally reschedule threads
     * if the active one goes to sleep. If there are no threads available
     * the active one will be in a sleeping state, and we can turn off
     * the entire VPE.
     */
    if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
        /* TC is not activated.  */
        active = 0;
    }
    if (env->active_tc.CP0_TCHalt & 1) {
        /* TC is in halt state.  */
        active = 0;
    }

    return active;
}

static inline int mips_vp_active(CPUMIPSState *env)
{
    CPUState *other_cs = first_cpu;

    /* Check if the VP disabled other VPs (which means the VP is enabled) */
    if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
        return 1;
    }

    /* Check if the virtual processor is disabled due to a DVP */
    CPU_FOREACH(other_cs) {
        MIPSCPU *other_cpu = MIPS_CPU(other_cs);
        if ((&other_cpu->env != env) &&
            ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
            return 0;
        }
    }
    return 1;
}

static inline void compute_hflags(CPUMIPSState *env)
{
    env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
                     MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                     MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
    if (env->CP0_Status & (1 << CP0St_ERL)) {
        env->hflags |= MIPS_HFLAG_ERL;
    }
    if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
        !(env->CP0_Status & (1 << CP0St_ERL)) &&
        !(env->hflags & MIPS_HFLAG_DM)) {
        env->hflags |= (env->CP0_Status >> CP0St_KSU) &
                       MIPS_HFLAG_KSU;
    }
#if defined(TARGET_MIPS64)
    if ((env->insn_flags & ISA_MIPS3) &&
        (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
         (env->CP0_Status & (1 << CP0St_PX)) ||
         (env->CP0_Status & (1 << CP0St_UX)))) {
        env->hflags |= MIPS_HFLAG_64;
    }

    if (!(env->insn_flags & ISA_MIPS3)) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
               !(env->CP0_Status & (1 << CP0St_UX))) {
        env->hflags |= MIPS_HFLAG_AWRAP;
    } else if (env->insn_flags & ISA_MIPS64R6) {
        /* Address wrapping for Supervisor and Kernel is specified in R6 */
        if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
             !(env->CP0_Status & (1 << CP0St_SX))) ||
            (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
             !(env->CP0_Status & (1 << CP0St_KX)))) {
            env->hflags |= MIPS_HFLAG_AWRAP;
        }
    }
#endif
    if (((env->CP0_Status & (1 << CP0St_CU0)) &&
         !(env->insn_flags & ISA_MIPS32R6)) ||
        !(env->hflags & MIPS_HFLAG_KSU)) {
        env->hflags |= MIPS_HFLAG_CP0;
    }
    if (env->CP0_Status & (1 << CP0St_CU1)) {
        env->hflags |= MIPS_HFLAG_FPU;
    }
    if (env->CP0_Status & (1 << CP0St_FR)) {
        env->hflags |= MIPS_HFLAG_F64;
    }
    if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
        (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
        env->hflags |= MIPS_HFLAG_SBRI;
    }
    if (env->insn_flags & ASE_DSP_R3) {
        /*
         * Our cpu supports DSP R3 ASE, so enable
         * access to DSP R3 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
                           MIPS_HFLAG_DSP_R3;
        }
    } else if (env->insn_flags & ASE_DSP_R2) {
        /*
         * Our cpu supports DSP R2 ASE, so enable
         * access to DSP R2 resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
        }

    } else if (env->insn_flags & ASE_DSP) {
        /*
         * Our cpu supports DSP ASE, so enable
         * access to DSP resources.
         */
        if (env->CP0_Status & (1 << CP0St_MX)) {
            env->hflags |= MIPS_HFLAG_DSP;
        }

    }
    if (env->insn_flags & ISA_MIPS32R2) {
        if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS32) {
        if (env->hflags & MIPS_HFLAG_64) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    } else if (env->insn_flags & ISA_MIPS4) {
        /*
         * All supported MIPS IV CPUs use the XX (CU3) to enable
         * and disable the MIPS IV extensions to the MIPS III ISA.
         * Some other MIPS IV CPUs ignore the bit, so the check here
         * would be too restrictive for them.
         */
        if (env->CP0_Status & (1U << CP0St_CU3)) {
            env->hflags |= MIPS_HFLAG_COP1X;
        }
    }
    if (env->insn_flags & ASE_MSA) {
        if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
            env->hflags |= MIPS_HFLAG_MSA;
        }
    }
    if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
        if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
            env->hflags |= MIPS_HFLAG_FRE;
        }
    }
    if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
        if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
            env->hflags |= MIPS_HFLAG_ELPA;
        }
    }
}

void cpu_mips_tlb_flush(CPUMIPSState *env);
void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);

void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
                                          int error_code, uintptr_t pc);

static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
                                                    uint32_t exception,
                                                    uintptr_t pc)
{
    do_raise_exception_err(env, exception, 0, pc);
}

#endif
Commit	Line	Data
7ba0e95b AM	1	/*
7ba0e95b AM	2	* MIPS internal definitions and helpers
26aa3d9a PMD	3	*
	4	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	5	* See the COPYING file in the top-level directory.
	6	*/
	7
	8	#ifndef MIPS_INTERNAL_H
	9	#define MIPS_INTERNAL_H
	10
34cffe96	11	#include "exec/memattrs.h"
502700d0	12	#include "fpu/softfloat-helpers.h"
41da212c	13
7ba0e95b AM	14	/*
	15	* MMU types, the first four entries have the same layout as the
	16	* CP0C0_MT field.
	17	*/
41da212c IM	18	enum mips_mmu_types {
	19	MMU_TYPE_NONE,
	20	MMU_TYPE_R4000,
	21	MMU_TYPE_RESERVED,
	22	MMU_TYPE_FMT,
	23	MMU_TYPE_R3000,
	24	MMU_TYPE_R6000,
	25	MMU_TYPE_R8000
	26	};
	27
	28	struct mips_def_t {
	29	const char *name;
	30	int32_t CP0_PRid;
	31	int32_t CP0_Config0;
	32	int32_t CP0_Config1;
	33	int32_t CP0_Config2;
	34	int32_t CP0_Config3;
	35	int32_t CP0_Config4;
	36	int32_t CP0_Config4_rw_bitmask;
	37	int32_t CP0_Config5;
	38	int32_t CP0_Config5_rw_bitmask;
	39	int32_t CP0_Config6;
af868995	40	int32_t CP0_Config6_rw_bitmask;
41da212c	41	int32_t CP0_Config7;
af868995	42	int32_t CP0_Config7_rw_bitmask;
41da212c IM	43	target_ulong CP0_LLAddr_rw_bitmask;
	44	int CP0_LLAddr_shift;
	45	int32_t SYNCI_Step;
	46	int32_t CCRes;
	47	int32_t CP0_Status_rw_bitmask;
	48	int32_t CP0_TCStatus_rw_bitmask;
	49	int32_t CP0_SRSCtl;
	50	int32_t CP1_fcr0;
	51	int32_t CP1_fcr31_rw_bitmask;
	52	int32_t CP1_fcr31;
	53	int32_t MSAIR;
	54	int32_t SEGBITS;
	55	int32_t PABITS;
	56	int32_t CP0_SRSConf0_rw_bitmask;
	57	int32_t CP0_SRSConf0;
	58	int32_t CP0_SRSConf1_rw_bitmask;
	59	int32_t CP0_SRSConf1;
	60	int32_t CP0_SRSConf2_rw_bitmask;
	61	int32_t CP0_SRSConf2;
	62	int32_t CP0_SRSConf3_rw_bitmask;
	63	int32_t CP0_SRSConf3;
	64	int32_t CP0_SRSConf4_rw_bitmask;
	65	int32_t CP0_SRSConf4;
	66	int32_t CP0_PageGrain_rw_bitmask;
	67	int32_t CP0_PageGrain;
	68	target_ulong CP0_EBaseWG_rw_bitmask;
f9c9cd63	69	uint64_t insn_flags;
41da212c	70	enum mips_mmu_types mmu_type;
5fb2dcd1	71	int32_t SAARP;
41da212c IM	72	};
	73
	74	extern const struct mips_def_t mips_defs[];
	75	extern const int mips_defs_number;
	76
26aa3d9a PMD	77	enum CPUMIPSMSADataFormat {
	78	DF_BYTE = 0,
	79	DF_HALF,
	80	DF_WORD,
	81	DF_DOUBLE
	82	};
	83
	84	void mips_cpu_do_interrupt(CPUState *cpu);
	85	bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
90c84c56	86	void mips_cpu_dump_state(CPUState cpu, FILE f, int flags);
26aa3d9a	87	hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
a010bdbe	88	int mips_cpu_gdb_read_register(CPUState cpu, GByteArray buf, int reg);
26aa3d9a PMD	89	int mips_cpu_gdb_write_register(CPUState cpu, uint8_t buf, int reg);
	90	void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
	91	MMUAccessType access_type,
	92	int mmu_idx, uintptr_t retaddr);
	93
	94	#if !defined(CONFIG_USER_ONLY)
	95
	96	typedef struct r4k_tlb_t r4k_tlb_t;
	97	struct r4k_tlb_t {
	98	target_ulong VPN;
	99	uint32_t PageMask;
	100	uint16_t ASID;
99029be1	101	uint32_t MMID;
26aa3d9a PMD	102	unsigned int G:1;
	103	unsigned int C0:3;
	104	unsigned int C1:3;
	105	unsigned int V0:1;
	106	unsigned int V1:1;
	107	unsigned int D0:1;
	108	unsigned int D1:1;
	109	unsigned int XI0:1;
	110	unsigned int XI1:1;
	111	unsigned int RI0:1;
	112	unsigned int RI1:1;
	113	unsigned int EHINV:1;
	114	uint64_t PFN[2];
	115	};
	116
	117	struct CPUMIPSTLBContext {
	118	uint32_t nb_tlb;
	119	uint32_t tlb_in_use;
	120	int (map_address)(struct CPUMIPSState env, hwaddr physical, int prot,
	121	target_ulong address, int rw, int access_type);
	122	void (helper_tlbwi)(struct CPUMIPSState env);
	123	void (helper_tlbwr)(struct CPUMIPSState env);
	124	void (helper_tlbp)(struct CPUMIPSState env);
	125	void (helper_tlbr)(struct CPUMIPSState env);
	126	void (helper_tlbinv)(struct CPUMIPSState env);
	127	void (helper_tlbinvf)(struct CPUMIPSState env);
	128	union {
	129	struct {
	130	r4k_tlb_t tlb[MIPS_TLB_MAX];
	131	} r4k;
	132	} mmu;
	133	};
	134
	135	int no_mmu_map_address(CPUMIPSState env, hwaddr physical, int *prot,
	136	target_ulong address, int rw, int access_type);
	137	int fixed_mmu_map_address(CPUMIPSState env, hwaddr physical, int *prot,
	138	target_ulong address, int rw, int access_type);
	139	int r4k_map_address(CPUMIPSState env, hwaddr physical, int *prot,
	140	target_ulong address, int rw, int access_type);
	141	void r4k_helper_tlbwi(CPUMIPSState *env);
	142	void r4k_helper_tlbwr(CPUMIPSState *env);
	143	void r4k_helper_tlbp(CPUMIPSState *env);
	144	void r4k_helper_tlbr(CPUMIPSState *env);
	145	void r4k_helper_tlbinv(CPUMIPSState *env);
	146	void r4k_helper_tlbinvf(CPUMIPSState *env);
	147	void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
2dc29222	148	uint32_t cpu_mips_get_random(CPUMIPSState *env);
26aa3d9a	149
4f02a06d PM	150	void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
	151	vaddr addr, unsigned size,
	152	MMUAccessType access_type,
	153	int mmu_idx, MemTxAttrs attrs,
	154	MemTxResult response, uintptr_t retaddr);
26aa3d9a PMD	155	hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
	156	int rw);
	157	#endif
	158
	159	#define cpu_signal_handler cpu_mips_signal_handler
	160
	161	#ifndef CONFIG_USER_ONLY
8a9358cc	162	extern const VMStateDescription vmstate_mips_cpu;
26aa3d9a PMD	163	#endif
	164
	165	static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
	166	{
	167	return (env->CP0_Status & (1 << CP0St_IE)) &&
	168	!(env->CP0_Status & (1 << CP0St_EXL)) &&
	169	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	170	!(env->hflags & MIPS_HFLAG_DM) &&
7ba0e95b AM	171	/*
	172	* Note that the TCStatus IXMT field is initialized to zero,
	173	* and only MT capable cores can set it to one. So we don't
	174	* need to check for MT capabilities here.
	175	*/
26aa3d9a PMD	176	!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
	177	}
	178
	179	/* Check if there is pending and not masked out interrupt */
	180	static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
	181	{
	182	int32_t pending;
	183	int32_t status;
	184	bool r;
	185
	186	pending = env->CP0_Cause & CP0Ca_IP_mask;
	187	status = env->CP0_Status & CP0Ca_IP_mask;
	188
	189	if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
7ba0e95b AM	190	/*
	191	* A MIPS configured with a vectorizing external interrupt controller
	192	* will feed a vector into the Cause pending lines. The core treats
8cdf8869	193	* the status lines as a vector level, not as individual masks.
7ba0e95b	194	*/
26aa3d9a PMD	195	r = pending > status;
26aa3d9a PMD	196	} else {
7ba0e95b AM	197	/*
	198	* A MIPS configured with compatibility or VInt (Vectored Interrupts)
	199	* treats the pending lines as individual interrupt lines, the status
	200	* lines are individual masks.
	201	*/
26aa3d9a PMD	202	r = (pending & status) != 0;
	203	}
	204	return r;
	205	}
	206
	207	void mips_tcg_init(void);
	208
	209	/* TODO QOM'ify CPU reset and remove */
	210	void cpu_state_reset(CPUMIPSState *s);
27e38392	211	void cpu_mips_realize_env(CPUMIPSState *env);
26aa3d9a PMD	212
26aa3d9a PMD	213	/* cp0_timer.c */
26aa3d9a PMD	214	uint32_t cpu_mips_get_count(CPUMIPSState *env);
	215	void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
	216	void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
	217	void cpu_mips_start_count(CPUMIPSState *env);
	218	void cpu_mips_stop_count(CPUMIPSState *env);
	219
	220	/* helper.c */
931d019f RH	221	bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	222	MMUAccessType access_type, int mmu_idx,
	223	bool probe, uintptr_t retaddr);
26aa3d9a PMD	224
	225	/* op_helper.c */
	226	uint32_t float_class_s(uint32_t arg, float_status *fst);
	227	uint64_t float_class_d(uint64_t arg, float_status *fst);
	228
	229	extern unsigned int ieee_rm[];
074cfcb4	230	void update_pagemask(CPUMIPSState env, target_ulong arg1, int32_t pagemask);
26aa3d9a PMD	231
	232	static inline void restore_rounding_mode(CPUMIPSState *env)
	233	{
	234	set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
	235	&env->active_fpu.fp_status);
	236	}
	237
	238	static inline void restore_flush_mode(CPUMIPSState *env)
	239	{
	240	set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
	241	&env->active_fpu.fp_status);
502700d0 AB	242	}
	243
	244	static inline void restore_snan_bit_mode(CPUMIPSState *env)
	245	{
	246	set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
	247	&env->active_fpu.fp_status);
26aa3d9a PMD	248	}
	249
	250	static inline void restore_fp_status(CPUMIPSState *env)
	251	{
	252	restore_rounding_mode(env);
	253	restore_flush_mode(env);
	254	restore_snan_bit_mode(env);
	255	}
	256
	257	static inline void restore_msa_fp_status(CPUMIPSState *env)
	258	{
	259	float_status *status = &env->active_tc.msa_fp_status;
	260	int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
	261	bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
	262
	263	set_float_rounding_mode(ieee_rm[rounding_mode], status);
	264	set_flush_to_zero(flush_to_zero, status);
	265	set_flush_inputs_to_zero(flush_to_zero, status);
	266	}
	267
	268	static inline void restore_pamask(CPUMIPSState *env)
	269	{
	270	if (env->hflags & MIPS_HFLAG_ELPA) {
	271	env->PAMask = (1ULL << env->PABITS) - 1;
	272	} else {
	273	env->PAMask = PAMASK_BASE;
	274	}
	275	}
	276
	277	static inline int mips_vpe_active(CPUMIPSState *env)
	278	{
	279	int active = 1;
	280
	281	/* Check that the VPE is enabled. */
	282	if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
	283	active = 0;
	284	}
	285	/* Check that the VPE is activated. */
	286	if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
	287	active = 0;
	288	}
	289
7ba0e95b AM	290	/*
	291	* Now verify that there are active thread contexts in the VPE.
	292	*
	293	* This assumes the CPU model will internally reschedule threads
	294	* if the active one goes to sleep. If there are no threads available
	295	* the active one will be in a sleeping state, and we can turn off
	296	* the entire VPE.
	297	*/
26aa3d9a PMD	298	if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
	299	/* TC is not activated. */
	300	active = 0;
	301	}
	302	if (env->active_tc.CP0_TCHalt & 1) {
	303	/* TC is in halt state. */
	304	active = 0;
	305	}
	306
	307	return active;
	308	}
	309
	310	static inline int mips_vp_active(CPUMIPSState *env)
	311	{
	312	CPUState *other_cs = first_cpu;
	313
	314	/* Check if the VP disabled other VPs (which means the VP is enabled) */
	315	if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
	316	return 1;
	317	}
	318
	319	/* Check if the virtual processor is disabled due to a DVP */
	320	CPU_FOREACH(other_cs) {
	321	MIPSCPU *other_cpu = MIPS_CPU(other_cs);
	322	if ((&other_cpu->env != env) &&
	323	((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
	324	return 0;
	325	}
	326	}
	327	return 1;
	328	}
	329
	330	static inline void compute_hflags(CPUMIPSState *env)
	331	{
	332	env->hflags &= ~(MIPS_HFLAG_COP1X \| MIPS_HFLAG_64 \| MIPS_HFLAG_CP0 \|
	333	MIPS_HFLAG_F64 \| MIPS_HFLAG_FPU \| MIPS_HFLAG_KSU \|
908f6be1 SM	334	MIPS_HFLAG_AWRAP \| MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	335	MIPS_HFLAG_DSP_R3 \| MIPS_HFLAG_SBRI \| MIPS_HFLAG_MSA \|
59e781fb	336	MIPS_HFLAG_FRE \| MIPS_HFLAG_ELPA \| MIPS_HFLAG_ERL);
26aa3d9a PMD	337	if (env->CP0_Status & (1 << CP0St_ERL)) {
	338	env->hflags \|= MIPS_HFLAG_ERL;
	339	}
	340	if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
	341	!(env->CP0_Status & (1 << CP0St_ERL)) &&
	342	!(env->hflags & MIPS_HFLAG_DM)) {
7ba0e95b AM	343	env->hflags \|= (env->CP0_Status >> CP0St_KSU) &
7ba0e95b AM	344	MIPS_HFLAG_KSU;
26aa3d9a PMD	345	}
	346	#if defined(TARGET_MIPS64)
	347	if ((env->insn_flags & ISA_MIPS3) &&
	348	(((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) \|\|
	349	(env->CP0_Status & (1 << CP0St_PX)) \|\|
	350	(env->CP0_Status & (1 << CP0St_UX)))) {
	351	env->hflags \|= MIPS_HFLAG_64;
	352	}
	353
	354	if (!(env->insn_flags & ISA_MIPS3)) {
	355	env->hflags \|= MIPS_HFLAG_AWRAP;
	356	} else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
	357	!(env->CP0_Status & (1 << CP0St_UX))) {
	358	env->hflags \|= MIPS_HFLAG_AWRAP;
	359	} else if (env->insn_flags & ISA_MIPS64R6) {
	360	/* Address wrapping for Supervisor and Kernel is specified in R6 */
	361	if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
	362	!(env->CP0_Status & (1 << CP0St_SX))) \|\|
	363	(((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
	364	!(env->CP0_Status & (1 << CP0St_KX)))) {
	365	env->hflags \|= MIPS_HFLAG_AWRAP;
	366	}
	367	}
	368	#endif
	369	if (((env->CP0_Status & (1 << CP0St_CU0)) &&
	370	!(env->insn_flags & ISA_MIPS32R6)) \|\|
	371	!(env->hflags & MIPS_HFLAG_KSU)) {
	372	env->hflags \|= MIPS_HFLAG_CP0;
	373	}
	374	if (env->CP0_Status & (1 << CP0St_CU1)) {
	375	env->hflags \|= MIPS_HFLAG_FPU;
	376	}
	377	if (env->CP0_Status & (1 << CP0St_FR)) {
	378	env->hflags \|= MIPS_HFLAG_F64;
	379	}
	380	if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
	381	(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
	382	env->hflags \|= MIPS_HFLAG_SBRI;
	383	}
908f6be1 SM	384	if (env->insn_flags & ASE_DSP_R3) {
	385	/*
	386	* Our cpu supports DSP R3 ASE, so enable
	387	* access to DSP R3 resources.
	388	*/
59e781fb	389	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1 SM	390	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2 \|
908f6be1 SM	391	MIPS_HFLAG_DSP_R3;
59e781fb	392	}
908f6be1 SM	393	} else if (env->insn_flags & ASE_DSP_R2) {
	394	/*
	395	* Our cpu supports DSP R2 ASE, so enable
	396	* access to DSP R2 resources.
	397	*/
26aa3d9a	398	if (env->CP0_Status & (1 << CP0St_MX)) {
908f6be1	399	env->hflags \|= MIPS_HFLAG_DSP \| MIPS_HFLAG_DSP_R2;
26aa3d9a PMD	400	}
	401
	402	} else if (env->insn_flags & ASE_DSP) {
908f6be1 SM	403	/*
	404	* Our cpu supports DSP ASE, so enable
	405	* access to DSP resources.
	406	*/
26aa3d9a PMD	407	if (env->CP0_Status & (1 << CP0St_MX)) {
	408	env->hflags \|= MIPS_HFLAG_DSP;
	409	}
	410
	411	}
	412	if (env->insn_flags & ISA_MIPS32R2) {
	413	if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
	414	env->hflags \|= MIPS_HFLAG_COP1X;
	415	}
	416	} else if (env->insn_flags & ISA_MIPS32) {
	417	if (env->hflags & MIPS_HFLAG_64) {
	418	env->hflags \|= MIPS_HFLAG_COP1X;
	419	}
	420	} else if (env->insn_flags & ISA_MIPS4) {
7ba0e95b AM	421	/*
	422	* All supported MIPS IV CPUs use the XX (CU3) to enable
	423	* and disable the MIPS IV extensions to the MIPS III ISA.
	424	* Some other MIPS IV CPUs ignore the bit, so the check here
	425	* would be too restrictive for them.
	426	*/
26aa3d9a PMD	427	if (env->CP0_Status & (1U << CP0St_CU3)) {
	428	env->hflags \|= MIPS_HFLAG_COP1X;
	429	}
	430	}
	431	if (env->insn_flags & ASE_MSA) {
	432	if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
	433	env->hflags \|= MIPS_HFLAG_MSA;
	434	}
	435	}
	436	if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
	437	if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
	438	env->hflags \|= MIPS_HFLAG_FRE;
	439	}
	440	}
	441	if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
	442	if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
	443	env->hflags \|= MIPS_HFLAG_ELPA;
	444	}
	445	}
	446	}
	447
	448	void cpu_mips_tlb_flush(CPUMIPSState *env);
	449	void sync_c0_status(CPUMIPSState env, CPUMIPSState cpu, int tc);
	450	void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
	451	void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
	452
	453	void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
	454	int error_code, uintptr_t pc);
	455
	456	static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
	457	uint32_t exception,
	458	uintptr_t pc)
	459	{
	460	do_raise_exception_err(env, exception, 0, pc);
	461	}
	462
	463	#endif