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Commit | Line | Data |
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c684822a | 1 | #include "qemu/osdep.h" |
33c11879 PB |
2 | #include "qemu-common.h" |
3 | #include "cpu.h" | |
8dd3dca3 | 4 | #include "hw/hw.h" |
1e00b8d5 | 5 | #include "migration/cpu.h" |
33a84765 | 6 | |
64451111 LA |
7 | static int cpu_post_load(void *opaque, int version_id) |
8 | { | |
9 | MIPSCPU *cpu = opaque; | |
10 | CPUMIPSState *env = &cpu->env; | |
11 | ||
12 | restore_fp_status(env); | |
13 | restore_msa_fp_status(env); | |
14 | compute_hflags(env); | |
e117f526 | 15 | restore_pamask(env); |
64451111 LA |
16 | |
17 | return 0; | |
18 | } | |
19 | ||
04cd7962 LA |
20 | /* FPU state */ |
21 | ||
2c21ee76 | 22 | static int get_fpr(QEMUFile *f, void *pv, size_t size, VMStateField *field) |
33a84765 | 23 | { |
64451111 | 24 | int i; |
04cd7962 | 25 | fpr_t *v = pv; |
64451111 LA |
26 | /* Restore entire MSA vector register */ |
27 | for (i = 0; i < MSA_WRLEN/64; i++) { | |
28 | qemu_get_sbe64s(f, &v->wr.d[i]); | |
29 | } | |
04cd7962 | 30 | return 0; |
33a84765 TS |
31 | } |
32 | ||
2c21ee76 JD |
33 | static int put_fpr(QEMUFile *f, void *pv, size_t size, VMStateField *field, |
34 | QJSON *vmdesc) | |
33a84765 | 35 | { |
64451111 | 36 | int i; |
04cd7962 | 37 | fpr_t *v = pv; |
64451111 LA |
38 | /* Save entire MSA vector register */ |
39 | for (i = 0; i < MSA_WRLEN/64; i++) { | |
40 | qemu_put_sbe64s(f, &v->wr.d[i]); | |
41 | } | |
2c21ee76 JD |
42 | |
43 | return 0; | |
33a84765 TS |
44 | } |
45 | ||
04cd7962 LA |
46 | const VMStateInfo vmstate_info_fpr = { |
47 | .name = "fpr", | |
48 | .get = get_fpr, | |
49 | .put = put_fpr, | |
50 | }; | |
51 | ||
52 | #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ | |
53 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t) | |
54 | ||
55 | #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ | |
56 | VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) | |
57 | ||
58 | static VMStateField vmstate_fpu_fields[] = { | |
59 | VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), | |
04cd7962 LA |
60 | VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), |
61 | VMSTATE_UINT32(fcr31, CPUMIPSFPUContext), | |
62 | VMSTATE_END_OF_LIST() | |
63 | }; | |
64 | ||
65 | const VMStateDescription vmstate_fpu = { | |
66 | .name = "cpu/fpu", | |
67 | .version_id = 1, | |
68 | .minimum_version_id = 1, | |
69 | .fields = vmstate_fpu_fields | |
70 | }; | |
71 | ||
72 | const VMStateDescription vmstate_inactive_fpu = { | |
73 | .name = "cpu/inactive_fpu", | |
74 | .version_id = 1, | |
75 | .minimum_version_id = 1, | |
76 | .fields = vmstate_fpu_fields | |
77 | }; | |
33a84765 | 78 | |
04cd7962 LA |
79 | /* TC state */ |
80 | ||
81 | static VMStateField vmstate_tc_fields[] = { | |
82 | VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), | |
83 | VMSTATE_UINTTL(PC, TCState), | |
84 | VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), | |
85 | VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), | |
86 | VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC), | |
87 | VMSTATE_UINTTL(DSPControl, TCState), | |
88 | VMSTATE_INT32(CP0_TCStatus, TCState), | |
89 | VMSTATE_INT32(CP0_TCBind, TCState), | |
90 | VMSTATE_UINTTL(CP0_TCHalt, TCState), | |
91 | VMSTATE_UINTTL(CP0_TCContext, TCState), | |
92 | VMSTATE_UINTTL(CP0_TCSchedule, TCState), | |
93 | VMSTATE_UINTTL(CP0_TCScheFBack, TCState), | |
94 | VMSTATE_INT32(CP0_Debug_tcstatus, TCState), | |
95 | VMSTATE_UINTTL(CP0_UserLocal, TCState), | |
64451111 | 96 | VMSTATE_INT32(msacsr, TCState), |
04cd7962 LA |
97 | VMSTATE_END_OF_LIST() |
98 | }; | |
99 | ||
100 | const VMStateDescription vmstate_tc = { | |
101 | .name = "cpu/tc", | |
102 | .version_id = 1, | |
103 | .minimum_version_id = 1, | |
104 | .fields = vmstate_tc_fields | |
105 | }; | |
106 | ||
107 | const VMStateDescription vmstate_inactive_tc = { | |
108 | .name = "cpu/inactive_tc", | |
109 | .version_id = 1, | |
110 | .minimum_version_id = 1, | |
111 | .fields = vmstate_tc_fields | |
112 | }; | |
113 | ||
114 | /* MVP state */ | |
115 | ||
116 | const VMStateDescription vmstate_mvp = { | |
117 | .name = "cpu/mvp", | |
118 | .version_id = 1, | |
119 | .minimum_version_id = 1, | |
120 | .fields = (VMStateField[]) { | |
121 | VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext), | |
122 | VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext), | |
123 | VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext), | |
124 | VMSTATE_END_OF_LIST() | |
460c81f1 | 125 | } |
04cd7962 | 126 | }; |
33a84765 | 127 | |
04cd7962 | 128 | /* TLB state */ |
33a84765 | 129 | |
2c21ee76 | 130 | static int get_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field) |
33a84765 | 131 | { |
04cd7962 LA |
132 | r4k_tlb_t *v = pv; |
133 | uint16_t flags; | |
134 | ||
135 | qemu_get_betls(f, &v->VPN); | |
136 | qemu_get_be32s(f, &v->PageMask); | |
2d72e7b0 | 137 | qemu_get_be16s(f, &v->ASID); |
04cd7962 LA |
138 | qemu_get_be16s(f, &flags); |
139 | v->G = (flags >> 10) & 1; | |
140 | v->C0 = (flags >> 7) & 3; | |
141 | v->C1 = (flags >> 4) & 3; | |
142 | v->V0 = (flags >> 3) & 1; | |
143 | v->V1 = (flags >> 2) & 1; | |
144 | v->D0 = (flags >> 1) & 1; | |
145 | v->D1 = (flags >> 0) & 1; | |
146 | v->EHINV = (flags >> 15) & 1; | |
147 | v->RI1 = (flags >> 14) & 1; | |
148 | v->RI0 = (flags >> 13) & 1; | |
149 | v->XI1 = (flags >> 12) & 1; | |
150 | v->XI0 = (flags >> 11) & 1; | |
284b731a LA |
151 | qemu_get_be64s(f, &v->PFN[0]); |
152 | qemu_get_be64s(f, &v->PFN[1]); | |
04cd7962 LA |
153 | |
154 | return 0; | |
33a84765 TS |
155 | } |
156 | ||
2c21ee76 JD |
157 | static int put_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field, |
158 | QJSON *vmdesc) | |
33a84765 | 159 | { |
04cd7962 LA |
160 | r4k_tlb_t *v = pv; |
161 | ||
2d72e7b0 | 162 | uint16_t asid = v->ASID; |
04cd7962 LA |
163 | uint16_t flags = ((v->EHINV << 15) | |
164 | (v->RI1 << 14) | | |
165 | (v->RI0 << 13) | | |
166 | (v->XI1 << 12) | | |
167 | (v->XI0 << 11) | | |
168 | (v->G << 10) | | |
169 | (v->C0 << 7) | | |
170 | (v->C1 << 4) | | |
171 | (v->V0 << 3) | | |
172 | (v->V1 << 2) | | |
173 | (v->D0 << 1) | | |
174 | (v->D1 << 0)); | |
175 | ||
176 | qemu_put_betls(f, &v->VPN); | |
177 | qemu_put_be32s(f, &v->PageMask); | |
2d72e7b0 | 178 | qemu_put_be16s(f, &asid); |
04cd7962 | 179 | qemu_put_be16s(f, &flags); |
284b731a LA |
180 | qemu_put_be64s(f, &v->PFN[0]); |
181 | qemu_put_be64s(f, &v->PFN[1]); | |
2c21ee76 JD |
182 | |
183 | return 0; | |
8dd3dca3 AJ |
184 | } |
185 | ||
04cd7962 LA |
186 | const VMStateInfo vmstate_info_tlb = { |
187 | .name = "tlb_entry", | |
188 | .get = get_tlb, | |
189 | .put = put_tlb, | |
190 | }; | |
33a84765 | 191 | |
04cd7962 LA |
192 | #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \ |
193 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t) | |
33a84765 | 194 | |
04cd7962 LA |
195 | #define VMSTATE_TLB_ARRAY(_f, _s, _n) \ |
196 | VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0) | |
33a84765 | 197 | |
04cd7962 LA |
198 | const VMStateDescription vmstate_tlb = { |
199 | .name = "cpu/tlb", | |
2d72e7b0 PB |
200 | .version_id = 2, |
201 | .minimum_version_id = 2, | |
04cd7962 LA |
202 | .fields = (VMStateField[]) { |
203 | VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), | |
204 | VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), | |
205 | VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX), | |
206 | VMSTATE_END_OF_LIST() | |
460c81f1 | 207 | } |
04cd7962 | 208 | }; |
33a84765 | 209 | |
04cd7962 | 210 | /* MIPS CPU state */ |
33a84765 | 211 | |
04cd7962 LA |
212 | const VMStateDescription vmstate_mips_cpu = { |
213 | .name = "cpu", | |
f6d4dd81 YK |
214 | .version_id = 8, |
215 | .minimum_version_id = 8, | |
64451111 | 216 | .post_load = cpu_post_load, |
04cd7962 LA |
217 | .fields = (VMStateField[]) { |
218 | /* Active TC */ | |
219 | VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState), | |
220 | ||
221 | /* Active FPU */ | |
222 | VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu, | |
223 | CPUMIPSFPUContext), | |
224 | ||
225 | /* MVP */ | |
226 | VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp, | |
227 | CPUMIPSMVPContext), | |
228 | ||
229 | /* TLB */ | |
230 | VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb, | |
231 | CPUMIPSTLBContext), | |
232 | ||
233 | /* CPU metastate */ | |
234 | VMSTATE_UINT32(env.current_tc, MIPSCPU), | |
235 | VMSTATE_UINT32(env.current_fpu, MIPSCPU), | |
236 | VMSTATE_INT32(env.error_code, MIPSCPU), | |
04cd7962 LA |
237 | VMSTATE_UINTTL(env.btarget, MIPSCPU), |
238 | VMSTATE_UINTTL(env.bcond, MIPSCPU), | |
239 | ||
240 | /* Remaining CP0 registers */ | |
241 | VMSTATE_INT32(env.CP0_Index, MIPSCPU), | |
242 | VMSTATE_INT32(env.CP0_Random, MIPSCPU), | |
243 | VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU), | |
244 | VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU), | |
245 | VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU), | |
246 | VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU), | |
247 | VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU), | |
248 | VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU), | |
249 | VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), | |
284b731a LA |
250 | VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), |
251 | VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), | |
04cd7962 LA |
252 | VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), |
253 | VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), | |
254 | VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU), | |
255 | VMSTATE_INT32(env.CP0_Wired, MIPSCPU), | |
256 | VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), | |
257 | VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), | |
258 | VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU), | |
259 | VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU), | |
260 | VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU), | |
261 | VMSTATE_INT32(env.CP0_HWREna, MIPSCPU), | |
262 | VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), | |
263 | VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), | |
264 | VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), | |
265 | VMSTATE_INT32(env.CP0_Count, MIPSCPU), | |
266 | VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), | |
267 | VMSTATE_INT32(env.CP0_Compare, MIPSCPU), | |
268 | VMSTATE_INT32(env.CP0_Status, MIPSCPU), | |
269 | VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU), | |
270 | VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU), | |
271 | VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU), | |
272 | VMSTATE_INT32(env.CP0_Cause, MIPSCPU), | |
273 | VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), | |
274 | VMSTATE_INT32(env.CP0_PRid, MIPSCPU), | |
275 | VMSTATE_INT32(env.CP0_EBase, MIPSCPU), | |
276 | VMSTATE_INT32(env.CP0_Config0, MIPSCPU), | |
277 | VMSTATE_INT32(env.CP0_Config1, MIPSCPU), | |
278 | VMSTATE_INT32(env.CP0_Config2, MIPSCPU), | |
279 | VMSTATE_INT32(env.CP0_Config3, MIPSCPU), | |
280 | VMSTATE_INT32(env.CP0_Config6, MIPSCPU), | |
281 | VMSTATE_INT32(env.CP0_Config7, MIPSCPU), | |
f6d4dd81 YK |
282 | VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX), |
283 | VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), | |
284b731a | 284 | VMSTATE_UINT64(env.lladdr, MIPSCPU), |
04cd7962 LA |
285 | VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), |
286 | VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), | |
287 | VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), | |
288 | VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), | |
289 | VMSTATE_INT32(env.CP0_Debug, MIPSCPU), | |
290 | VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), | |
291 | VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), | |
284b731a | 292 | VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU), |
04cd7962 LA |
293 | VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), |
294 | VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), | |
295 | VMSTATE_INT32(env.CP0_DataHi, MIPSCPU), | |
296 | VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU), | |
297 | VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU), | |
298 | VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM), | |
299 | ||
300 | /* Inactive TC */ | |
301 | VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1, | |
302 | vmstate_inactive_tc, TCState), | |
303 | VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1, | |
304 | vmstate_inactive_fpu, CPUMIPSFPUContext), | |
305 | ||
306 | VMSTATE_END_OF_LIST() | |
307 | }, | |
308 | }; |