projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 2a6a4076 MA |
1 | #ifndef QEMU_MIPS_DEFS_H |
| 2 | #define QEMU_MIPS_DEFS_H | |
| 6af0bf9c | 3 | |
| e9c71dd1 | 4 | /* Real pages are variable size... */ |
| 814b9a47 | 5 | #define MIPS_TLB_MAX 128 |
| 6af0bf9c | 6 | |
| 45ebdd24 PMD |
7 | /* |
| 8 | * bit definitions for insn_flags (ISAs/ASEs flags) | |
| 9 | * ------------------------------------------------ | |
| 10 | */ | |
| 11 | /* | |
| af868995 | 12 | * bits 0-23: MIPS base instruction sets |
| 45ebdd24 PMD |
13 | */ |
| 14 | #define ISA_MIPS1 0x0000000000000001ULL | |
| 15 | #define ISA_MIPS2 0x0000000000000002ULL | |
| b0586b38 | 16 | #define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ |
| 45ebdd24 PMD |
17 | #define ISA_MIPS4 0x0000000000000008ULL |
| 18 | #define ISA_MIPS5 0x0000000000000010ULL | |
| bbd5e4a2 | 19 | #define ISA_MIPS_R1 0x0000000000000020ULL |
| 7a47bae5 | 20 | #define ISA_MIPS_R2 0x0000000000000040ULL |
| bae4b15a | 21 | #define ISA_MIPS_R3 0x0000000000000080ULL |
| 5f89ce4f | 22 | #define ISA_MIPS_R5 0x0000000000000100ULL |
| 2e211e0a | 23 | #define ISA_MIPS_R6 0x0000000000000200ULL |
| 45ebdd24 PMD |
24 | #define ISA_NANOMIPS32 0x0000000000008000ULL |
| 25 | /* | |
| af868995 | 26 | * bits 24-39: MIPS ASEs |
| 45ebdd24 | 27 | */ |
| af868995 HC |
28 | #define ASE_MIPS16 0x0000000001000000ULL |
| 29 | #define ASE_MIPS3D 0x0000000002000000ULL | |
| 30 | #define ASE_MDMX 0x0000000004000000ULL | |
| 31 | #define ASE_DSP 0x0000000008000000ULL | |
| 32 | #define ASE_DSP_R2 0x0000000010000000ULL | |
| 33 | #define ASE_DSP_R3 0x0000000020000000ULL | |
| 34 | #define ASE_MT 0x0000000040000000ULL | |
| 35 | #define ASE_SMARTMIPS 0x0000000080000000ULL | |
| 36 | #define ASE_MICROMIPS 0x0000000100000000ULL | |
| 45ebdd24 | 37 | /* |
| af868995 | 38 | * bits 40-51: vendor-specific base instruction sets |
| 45ebdd24 | 39 | */ |
| af868995 HC |
40 | #define INSN_VR54XX 0x0000010000000000ULL |
| 41 | #define INSN_R5900 0x0000020000000000ULL | |
| 42 | #define INSN_LOONGSON2E 0x0000040000000000ULL | |
| 43 | #define INSN_LOONGSON2F 0x0000080000000000ULL | |
| 44 | #define INSN_LOONGSON3A 0x0000100000000000ULL | |
| 72d680e4 | 45 | #define INSN_OCTEON 0x0000200000000000ULL |
| 45ebdd24 | 46 | /* |
| af868995 | 47 | * bits 52-63: vendor-specific ASEs |
| 45ebdd24 | 48 | */ |
| 7f4d0651 | 49 | /* MultiMedia Instructions defined by R5900 */ |
| af868995 | 50 | #define ASE_MMI 0x0010000000000000ULL |
| 7f4d0651 | 51 | /* MIPS eXtension/enhanced Unit defined by Ingenic */ |
| af868995 | 52 | #define ASE_MXU 0x0020000000000000ULL |
| 7f4d0651 | 53 | /* Loongson MultiMedia Instructions */ |
| af868995 | 54 | #define ASE_LMMI 0x0040000000000000ULL |
| 7f4d0651 | 55 | /* Loongson EXTensions */ |
| af868995 | 56 | #define ASE_LEXT 0x0080000000000000ULL |
| e189e748 | 57 | |
| e9c71dd1 | 58 | /* MIPS CPU defines. */ |
| f823213c AM |
59 | #define CPU_MIPS1 (ISA_MIPS1) |
| 60 | #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) | |
| 61 | #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) | |
| 62 | #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) | |
| bf552377 | 63 | #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) |
| e9c71dd1 | 64 | |
| b0586b38 PMD |
65 | #define CPU_MIPS64 (ISA_MIPS3) |
| 66 | ||
| e9c71dd1 | 67 | /* MIPS Technologies "Release 1" */ |
| bbd5e4a2 | 68 | #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS_R1) |
| 08e2262f | 69 | #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1) |
| e189e748 | 70 | |
| e9c71dd1 | 71 | /* MIPS Technologies "Release 2" */ |
| 7a47bae5 | 72 | #define CPU_MIPS32R2 (CPU_MIPS32R1 | ISA_MIPS_R2) |
| f395cef7 | 73 | #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) |
| e189e748 | 74 | |
| e527526d | 75 | /* MIPS Technologies "Release 3" */ |
| bae4b15a | 76 | #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3) |
| 4d1524d2 | 77 | #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) |
| e527526d PJ |
78 | |
| 79 | /* MIPS Technologies "Release 5" */ | |
| 5f89ce4f | 80 | #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS_R5) |
| d913c399 | 81 | #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5) |
| fa0d2f69 LA |
82 | |
| 83 | /* MIPS Technologies "Release 6" */ | |
| 2e211e0a | 84 | #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6) |
| 13514fc9 | 85 | #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6) |
| e527526d | 86 | |
| f823213c AM |
87 | /* |
| 88 | * Strictly follow the architecture standard: | |
| 89 | * - Disallow "special" instruction handling for PMON/SPIM. | |
| 90 | * Note that we still maintain Count/Compare to match the host clock. | |
| 91 | * | |
| 92 | * #define MIPS_STRICT_STANDARD 1 | |
| 93 | */ | |
| b48cfdff | 94 | |
| 2a6a4076 | 95 | #endif /* QEMU_MIPS_DEFS_H */ |