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a685f7d0 PMD |
1 | /* |
2 | * Address Computation and Large Constant Instructions | |
3 | * | |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer | |
5 | * Copyright (c) 2006 Marius Groeger (FPU operations) | |
6 | * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) | |
7 | * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) | |
8 | * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) | |
9 | * Copyright (c) 2020 Philippe Mathieu-Daudé | |
10 | * | |
11 | * SPDX-License-Identifier: LGPL-2.1-or-later | |
12 | */ | |
13 | #include "qemu/osdep.h" | |
a685f7d0 PMD |
14 | #include "translate.h" |
15 | ||
16 | bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) | |
17 | { | |
18 | TCGv t0; | |
19 | TCGv t1; | |
20 | ||
21 | if (rd == 0) { | |
22 | /* Treat as NOP. */ | |
23 | return true; | |
24 | } | |
25 | t0 = tcg_temp_new(); | |
26 | t1 = tcg_temp_new(); | |
27 | gen_load_gpr(t0, rs); | |
28 | gen_load_gpr(t1, rt); | |
29 | tcg_gen_shli_tl(t0, t0, sa + 1); | |
30 | tcg_gen_add_tl(cpu_gpr[rd], t0, t1); | |
31 | tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); | |
a685f7d0 PMD |
32 | return true; |
33 | } | |
34 | ||
35 | bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa) | |
36 | { | |
37 | TCGv t0; | |
38 | TCGv t1; | |
39 | ||
40 | check_mips_64(ctx); | |
41 | ||
42 | if (rd == 0) { | |
43 | /* Treat as NOP. */ | |
44 | return true; | |
45 | } | |
46 | t0 = tcg_temp_new(); | |
47 | t1 = tcg_temp_new(); | |
48 | gen_load_gpr(t0, rs); | |
49 | gen_load_gpr(t1, rt); | |
50 | tcg_gen_shli_tl(t0, t0, sa + 1); | |
51 | tcg_gen_add_tl(cpu_gpr[rd], t0, t1); | |
a685f7d0 PMD |
52 | return true; |
53 | } |