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032c76bc CW |
1 | /* |
2 | * QEMU Nios II CPU | |
3 | * | |
4 | * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
20 | ||
21 | #include "qemu/osdep.h" | |
0b8fa32f | 22 | #include "qemu/module.h" |
032c76bc CW |
23 | #include "qapi/error.h" |
24 | #include "cpu.h" | |
25 | #include "exec/log.h" | |
4ea5fe99 | 26 | #include "gdbstub/helpers.h" |
032c76bc CW |
27 | #include "hw/qdev-properties.h" |
28 | ||
29 | static void nios2_cpu_set_pc(CPUState *cs, vaddr value) | |
30 | { | |
31 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
32 | CPUNios2State *env = &cpu->env; | |
33 | ||
17a406ee | 34 | env->pc = value; |
032c76bc CW |
35 | } |
36 | ||
e4fdf9df RH |
37 | static vaddr nios2_cpu_get_pc(CPUState *cs) |
38 | { | |
39 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
40 | CPUNios2State *env = &cpu->env; | |
41 | ||
42 | return env->pc; | |
43 | } | |
44 | ||
fbd5bd4e RH |
45 | static void nios2_restore_state_to_opc(CPUState *cs, |
46 | const TranslationBlock *tb, | |
47 | const uint64_t *data) | |
48 | { | |
49 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
50 | CPUNios2State *env = &cpu->env; | |
51 | ||
52 | env->pc = data[0]; | |
53 | } | |
54 | ||
032c76bc CW |
55 | static bool nios2_cpu_has_work(CPUState *cs) |
56 | { | |
e8d12542 | 57 | return cs->interrupt_request & CPU_INTERRUPT_HARD; |
032c76bc CW |
58 | } |
59 | ||
4245a716 | 60 | static void nios2_cpu_reset_hold(Object *obj) |
032c76bc | 61 | { |
4245a716 | 62 | CPUState *cs = CPU(obj); |
032c76bc CW |
63 | Nios2CPU *cpu = NIOS2_CPU(cs); |
64 | Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu); | |
65 | CPUNios2State *env = &cpu->env; | |
66 | ||
4245a716 PM |
67 | if (ncc->parent_phases.hold) { |
68 | ncc->parent_phases.hold(obj); | |
69 | } | |
032c76bc | 70 | |
b8f036a9 | 71 | memset(env->ctrl, 0, sizeof(env->ctrl)); |
17a406ee | 72 | env->pc = cpu->reset_addr; |
032c76bc CW |
73 | |
74 | #if defined(CONFIG_USER_ONLY) | |
75 | /* Start in user mode with interrupts enabled. */ | |
2de70d2d | 76 | env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; |
945a5bd3 | 77 | memset(env->regs, 0, sizeof(env->regs)); |
032c76bc | 78 | #else |
2de70d2d | 79 | env->ctrl[CR_STATUS] = CR_STATUS_RSIE; |
945a5bd3 RH |
80 | nios2_update_crs(env); |
81 | memset(env->shadow_regs, 0, sizeof(env->shadow_regs)); | |
032c76bc CW |
82 | #endif |
83 | } | |
84 | ||
cd2528de | 85 | #ifndef CONFIG_USER_ONLY |
a25c4eff RH |
86 | static void eic_set_irq(void *opaque, int irq, int level) |
87 | { | |
88 | Nios2CPU *cpu = opaque; | |
89 | CPUState *cs = CPU(cpu); | |
90 | ||
91 | if (level) { | |
92 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
93 | } else { | |
94 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
95 | } | |
96 | } | |
97 | ||
98 | static void iic_set_irq(void *opaque, int irq, int level) | |
cd2528de PM |
99 | { |
100 | Nios2CPU *cpu = opaque; | |
101 | CPUNios2State *env = &cpu->env; | |
102 | CPUState *cs = CPU(cpu); | |
103 | ||
b8f036a9 | 104 | env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level); |
cd2528de | 105 | |
b8f036a9 | 106 | if (env->ctrl[CR_IPENDING]) { |
cd2528de | 107 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
b72c9d59 | 108 | } else { |
cd2528de PM |
109 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
110 | } | |
111 | } | |
112 | #endif | |
113 | ||
032c76bc CW |
114 | static void nios2_cpu_initfn(Object *obj) |
115 | { | |
032c76bc | 116 | Nios2CPU *cpu = NIOS2_CPU(obj); |
032c76bc | 117 | |
7506ed90 | 118 | cpu_set_cpustate_pointers(cpu); |
032c76bc CW |
119 | |
120 | #if !defined(CONFIG_USER_ONLY) | |
7506ed90 | 121 | mmu_init(&cpu->env); |
032c76bc | 122 | #endif |
032c76bc CW |
123 | } |
124 | ||
da9cbe02 | 125 | static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model) |
032c76bc | 126 | { |
da9cbe02 | 127 | return object_class_by_name(TYPE_NIOS2_CPU); |
032c76bc CW |
128 | } |
129 | ||
796945d5 RH |
130 | static void realize_cr_status(CPUState *cs) |
131 | { | |
132 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
133 | ||
134 | /* Begin with all fields of all registers are reserved. */ | |
135 | memset(cpu->cr_state, 0, sizeof(cpu->cr_state)); | |
136 | ||
137 | /* | |
138 | * The combination of writable and readonly is the set of all | |
139 | * non-reserved fields. We apply writable as a mask to bits, | |
140 | * and merge in existing readonly bits, before storing. | |
141 | */ | |
142 | #define WR_REG(C) cpu->cr_state[C].writable = -1 | |
143 | #define RO_REG(C) cpu->cr_state[C].readonly = -1 | |
144 | #define WR_FIELD(C, F) cpu->cr_state[C].writable |= R_##C##_##F##_MASK | |
145 | #define RO_FIELD(C, F) cpu->cr_state[C].readonly |= R_##C##_##F##_MASK | |
146 | ||
147 | WR_FIELD(CR_STATUS, PIE); | |
148 | WR_REG(CR_ESTATUS); | |
149 | WR_REG(CR_BSTATUS); | |
150 | RO_REG(CR_CPUID); | |
151 | RO_REG(CR_EXCEPTION); | |
152 | WR_REG(CR_BADADDR); | |
153 | ||
a25c4eff RH |
154 | if (cpu->eic_present) { |
155 | WR_FIELD(CR_STATUS, RSIE); | |
156 | RO_FIELD(CR_STATUS, NMI); | |
157 | WR_FIELD(CR_STATUS, PRS); | |
158 | RO_FIELD(CR_STATUS, CRS); | |
159 | WR_FIELD(CR_STATUS, IL); | |
160 | WR_FIELD(CR_STATUS, IH); | |
161 | } else { | |
162 | RO_FIELD(CR_STATUS, RSIE); | |
163 | WR_REG(CR_IENABLE); | |
164 | RO_REG(CR_IPENDING); | |
165 | } | |
796945d5 RH |
166 | |
167 | if (cpu->mmu_present) { | |
168 | WR_FIELD(CR_STATUS, U); | |
169 | WR_FIELD(CR_STATUS, EH); | |
170 | ||
171 | WR_FIELD(CR_PTEADDR, VPN); | |
172 | WR_FIELD(CR_PTEADDR, PTBASE); | |
173 | ||
174 | RO_FIELD(CR_TLBMISC, D); | |
175 | RO_FIELD(CR_TLBMISC, PERM); | |
176 | RO_FIELD(CR_TLBMISC, BAD); | |
177 | RO_FIELD(CR_TLBMISC, DBL); | |
178 | WR_FIELD(CR_TLBMISC, PID); | |
179 | WR_FIELD(CR_TLBMISC, WE); | |
180 | WR_FIELD(CR_TLBMISC, RD); | |
181 | WR_FIELD(CR_TLBMISC, WAY); | |
182 | ||
183 | WR_REG(CR_TLBACC); | |
184 | } | |
185 | ||
186 | /* | |
187 | * TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are | |
188 | * unimplemented, so their corresponding control regs remain reserved. | |
189 | */ | |
190 | ||
191 | #undef WR_REG | |
192 | #undef RO_REG | |
193 | #undef WR_FIELD | |
194 | #undef RO_FIELD | |
195 | } | |
196 | ||
032c76bc CW |
197 | static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) |
198 | { | |
199 | CPUState *cs = CPU(dev); | |
b05550af | 200 | Nios2CPU *cpu = NIOS2_CPU(cs); |
032c76bc CW |
201 | Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); |
202 | Error *local_err = NULL; | |
203 | ||
a25c4eff RH |
204 | #ifndef CONFIG_USER_ONLY |
205 | if (cpu->eic_present) { | |
206 | qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); | |
207 | } else { | |
208 | qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); | |
209 | } | |
210 | #endif | |
211 | ||
032c76bc CW |
212 | cpu_exec_realizefn(cs, &local_err); |
213 | if (local_err != NULL) { | |
214 | error_propagate(errp, local_err); | |
215 | return; | |
216 | } | |
217 | ||
796945d5 | 218 | realize_cr_status(cs); |
032c76bc CW |
219 | qemu_init_vcpu(cs); |
220 | cpu_reset(cs); | |
221 | ||
b05550af RH |
222 | /* We have reserved storage for cpuid; might as well use it. */ |
223 | cpu->env.ctrl[CR_CPUID] = cs->cpu_index; | |
224 | ||
032c76bc CW |
225 | ncc->parent_realize(dev, errp); |
226 | } | |
227 | ||
dabfe133 | 228 | #ifndef CONFIG_USER_ONLY |
a25c4eff | 229 | static bool eic_take_interrupt(Nios2CPU *cpu) |
032c76bc | 230 | { |
032c76bc | 231 | CPUNios2State *env = &cpu->env; |
a25c4eff | 232 | const uint32_t status = env->ctrl[CR_STATUS]; |
032c76bc | 233 | |
a25c4eff RH |
234 | if (cpu->rnmi) { |
235 | return !(status & CR_STATUS_NMI); | |
236 | } | |
237 | if (!(status & CR_STATUS_PIE)) { | |
238 | return false; | |
239 | } | |
240 | if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) { | |
241 | return false; | |
242 | } | |
243 | if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) { | |
032c76bc CW |
244 | return true; |
245 | } | |
a25c4eff RH |
246 | return status & CR_STATUS_RSIE; |
247 | } | |
248 | ||
249 | static bool iic_take_interrupt(Nios2CPU *cpu) | |
250 | { | |
251 | CPUNios2State *env = &cpu->env; | |
252 | ||
253 | if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) { | |
254 | return false; | |
255 | } | |
256 | return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE]; | |
257 | } | |
258 | ||
259 | static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
260 | { | |
261 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
262 | ||
263 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
264 | if (cpu->eic_present | |
265 | ? eic_take_interrupt(cpu) | |
266 | : iic_take_interrupt(cpu)) { | |
267 | cs->exception_index = EXCP_IRQ; | |
268 | nios2_cpu_do_interrupt(cs); | |
269 | return true; | |
270 | } | |
271 | } | |
032c76bc CW |
272 | return false; |
273 | } | |
dabfe133 | 274 | #endif /* !CONFIG_USER_ONLY */ |
032c76bc CW |
275 | |
276 | static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) | |
277 | { | |
278 | /* NOTE: NiosII R2 is not supported yet. */ | |
279 | info->mach = bfd_arch_nios2; | |
dcc99bd8 | 280 | info->print_insn = print_insn_nios2; |
032c76bc CW |
281 | } |
282 | ||
a010bdbe | 283 | static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) |
032c76bc CW |
284 | { |
285 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
032c76bc | 286 | CPUNios2State *env = &cpu->env; |
796945d5 | 287 | uint32_t val; |
032c76bc CW |
288 | |
289 | if (n < 32) { /* GP regs */ | |
796945d5 | 290 | val = env->regs[n]; |
032c76bc | 291 | } else if (n == 32) { /* PC */ |
796945d5 | 292 | val = env->pc; |
032c76bc | 293 | } else if (n < 49) { /* Status regs */ |
796945d5 RH |
294 | unsigned cr = n - 33; |
295 | if (nios2_cr_reserved(&cpu->cr_state[cr])) { | |
296 | val = 0; | |
297 | } else { | |
298 | val = env->ctrl[n - 33]; | |
299 | } | |
300 | } else { | |
301 | /* Invalid regs */ | |
302 | return 0; | |
032c76bc CW |
303 | } |
304 | ||
796945d5 | 305 | return gdb_get_reg32(mem_buf, val); |
032c76bc CW |
306 | } |
307 | ||
308 | static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) | |
309 | { | |
310 | Nios2CPU *cpu = NIOS2_CPU(cs); | |
311 | CPUClass *cc = CPU_GET_CLASS(cs); | |
312 | CPUNios2State *env = &cpu->env; | |
796945d5 | 313 | uint32_t val; |
032c76bc CW |
314 | |
315 | if (n > cc->gdb_num_core_regs) { | |
316 | return 0; | |
317 | } | |
796945d5 | 318 | val = ldl_p(mem_buf); |
032c76bc CW |
319 | |
320 | if (n < 32) { /* GP regs */ | |
796945d5 | 321 | env->regs[n] = val; |
032c76bc | 322 | } else if (n == 32) { /* PC */ |
796945d5 | 323 | env->pc = val; |
032c76bc | 324 | } else if (n < 49) { /* Status regs */ |
796945d5 RH |
325 | unsigned cr = n - 33; |
326 | /* ??? Maybe allow the debugger to write to readonly fields. */ | |
327 | val &= cpu->cr_state[cr].writable; | |
328 | val |= cpu->cr_state[cr].readonly & env->ctrl[cr]; | |
329 | env->ctrl[cr] = val; | |
330 | } else { | |
331 | g_assert_not_reached(); | |
032c76bc CW |
332 | } |
333 | ||
334 | return 4; | |
335 | } | |
336 | ||
337 | static Property nios2_properties[] = { | |
345b7a87 | 338 | DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true), |
032c76bc CW |
339 | DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), |
340 | /* ALTR,pid-num-bits */ | |
341 | DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8), | |
342 | /* ALTR,tlb-num-ways */ | |
343 | DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16), | |
344 | /* ALTR,tlb-num-entries */ | |
345 | DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256), | |
346 | DEFINE_PROP_END_OF_LIST(), | |
347 | }; | |
348 | ||
8b80bd28 PMD |
349 | #ifndef CONFIG_USER_ONLY |
350 | #include "hw/core/sysemu-cpu-ops.h" | |
351 | ||
352 | static const struct SysemuCPUOps nios2_sysemu_ops = { | |
08928c6d | 353 | .get_phys_page_debug = nios2_cpu_get_phys_page_debug, |
8b80bd28 PMD |
354 | }; |
355 | #endif | |
356 | ||
78271684 CF |
357 | #include "hw/core/tcg-cpu-ops.h" |
358 | ||
11906557 | 359 | static const struct TCGCPUOps nios2_tcg_ops = { |
78271684 | 360 | .initialize = nios2_tcg_init, |
fbd5bd4e | 361 | .restore_state_to_opc = nios2_restore_state_to_opc, |
78271684 | 362 | |
fb4de9d2 | 363 | #ifndef CONFIG_USER_ONLY |
fac94cb3 | 364 | .tlb_fill = nios2_cpu_tlb_fill, |
dabfe133 | 365 | .cpu_exec_interrupt = nios2_cpu_exec_interrupt, |
78271684 CF |
366 | .do_interrupt = nios2_cpu_do_interrupt, |
367 | .do_unaligned_access = nios2_cpu_do_unaligned_access, | |
368 | #endif /* !CONFIG_USER_ONLY */ | |
369 | }; | |
032c76bc CW |
370 | |
371 | static void nios2_cpu_class_init(ObjectClass *oc, void *data) | |
372 | { | |
373 | DeviceClass *dc = DEVICE_CLASS(oc); | |
374 | CPUClass *cc = CPU_CLASS(oc); | |
375 | Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc); | |
4245a716 | 376 | ResettableClass *rc = RESETTABLE_CLASS(oc); |
032c76bc | 377 | |
bf853881 PMD |
378 | device_class_set_parent_realize(dc, nios2_cpu_realizefn, |
379 | &ncc->parent_realize); | |
4f67d30b | 380 | device_class_set_props(dc, nios2_properties); |
4245a716 PM |
381 | resettable_class_set_parent_phases(rc, NULL, nios2_cpu_reset_hold, NULL, |
382 | &ncc->parent_phases); | |
032c76bc | 383 | |
da9cbe02 | 384 | cc->class_by_name = nios2_cpu_class_by_name; |
032c76bc | 385 | cc->has_work = nios2_cpu_has_work; |
032c76bc CW |
386 | cc->dump_state = nios2_cpu_dump_state; |
387 | cc->set_pc = nios2_cpu_set_pc; | |
e4fdf9df | 388 | cc->get_pc = nios2_cpu_get_pc; |
032c76bc | 389 | cc->disas_set_info = nios2_cpu_disas_set_info; |
0137c93f | 390 | #ifndef CONFIG_USER_ONLY |
8b80bd28 | 391 | cc->sysemu_ops = &nios2_sysemu_ops; |
032c76bc CW |
392 | #endif |
393 | cc->gdb_read_register = nios2_cpu_gdb_read_register; | |
394 | cc->gdb_write_register = nios2_cpu_gdb_write_register; | |
395 | cc->gdb_num_core_regs = 49; | |
78271684 | 396 | cc->tcg_ops = &nios2_tcg_ops; |
032c76bc CW |
397 | } |
398 | ||
399 | static const TypeInfo nios2_cpu_type_info = { | |
400 | .name = TYPE_NIOS2_CPU, | |
401 | .parent = TYPE_CPU, | |
402 | .instance_size = sizeof(Nios2CPU), | |
f669c992 | 403 | .instance_align = __alignof(Nios2CPU), |
032c76bc CW |
404 | .instance_init = nios2_cpu_initfn, |
405 | .class_size = sizeof(Nios2CPUClass), | |
406 | .class_init = nios2_cpu_class_init, | |
407 | }; | |
408 | ||
409 | static void nios2_cpu_register_types(void) | |
410 | { | |
411 | type_register_static(&nios2_cpu_type_info); | |
412 | } | |
413 | ||
414 | type_init(nios2_cpu_register_types) |