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032c76bc CW |
1 | /* |
2 | * Altera Nios II virtual CPU header | |
3 | * | |
4 | * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2.1 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see | |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
19 | */ | |
58ea30f5 MA |
20 | |
21 | #ifndef NIOS2_CPU_H | |
22 | #define NIOS2_CPU_H | |
032c76bc | 23 | |
74433bf0 | 24 | #include "exec/cpu-defs.h" |
2e5b09fd | 25 | #include "hw/core/cpu.h" |
db1015e9 | 26 | #include "qom/object.h" |
032c76bc | 27 | |
1ea4a06a | 28 | typedef struct CPUArchState CPUNios2State; |
032c76bc CW |
29 | #if !defined(CONFIG_USER_ONLY) |
30 | #include "mmu.h" | |
31 | #endif | |
32 | ||
33 | #define TYPE_NIOS2_CPU "nios2-cpu" | |
34 | ||
9295b1aa | 35 | OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) |
032c76bc CW |
36 | |
37 | /** | |
38 | * Nios2CPUClass: | |
39 | * @parent_reset: The parent class' reset handler. | |
40 | * | |
41 | * A Nios2 CPU model. | |
42 | */ | |
db1015e9 | 43 | struct Nios2CPUClass { |
032c76bc CW |
44 | /*< private >*/ |
45 | CPUClass parent_class; | |
46 | /*< public >*/ | |
47 | ||
48 | DeviceRealize parent_realize; | |
781c67ca | 49 | DeviceReset parent_reset; |
db1015e9 | 50 | }; |
032c76bc CW |
51 | |
52 | #define TARGET_HAS_ICE 1 | |
53 | ||
54 | /* Configuration options for Nios II */ | |
55 | #define RESET_ADDRESS 0x00000000 | |
56 | #define EXCEPTION_ADDRESS 0x00000004 | |
57 | #define FAST_TLB_MISS_ADDRESS 0x00000008 | |
58 | ||
59 | ||
60 | /* GP regs + CR regs + PC */ | |
61 | #define NUM_CORE_REGS (32 + 32 + 1) | |
62 | ||
63 | /* General purpose register aliases */ | |
64 | #define R_ZERO 0 | |
65 | #define R_AT 1 | |
66 | #define R_RET0 2 | |
67 | #define R_RET1 3 | |
68 | #define R_ARG0 4 | |
69 | #define R_ARG1 5 | |
70 | #define R_ARG2 6 | |
71 | #define R_ARG3 7 | |
72 | #define R_ET 24 | |
73 | #define R_BT 25 | |
74 | #define R_GP 26 | |
75 | #define R_SP 27 | |
76 | #define R_FP 28 | |
77 | #define R_EA 29 | |
78 | #define R_BA 30 | |
79 | #define R_RA 31 | |
80 | ||
81 | /* Control register aliases */ | |
82 | #define CR_BASE 32 | |
83 | #define CR_STATUS (CR_BASE + 0) | |
84 | #define CR_STATUS_PIE (1 << 0) | |
85 | #define CR_STATUS_U (1 << 1) | |
86 | #define CR_STATUS_EH (1 << 2) | |
87 | #define CR_STATUS_IH (1 << 3) | |
88 | #define CR_STATUS_IL (63 << 4) | |
89 | #define CR_STATUS_CRS (63 << 10) | |
90 | #define CR_STATUS_PRS (63 << 16) | |
91 | #define CR_STATUS_NMI (1 << 22) | |
92 | #define CR_STATUS_RSIE (1 << 23) | |
93 | #define CR_ESTATUS (CR_BASE + 1) | |
94 | #define CR_BSTATUS (CR_BASE + 2) | |
95 | #define CR_IENABLE (CR_BASE + 3) | |
96 | #define CR_IPENDING (CR_BASE + 4) | |
97 | #define CR_CPUID (CR_BASE + 5) | |
98 | #define CR_CTL6 (CR_BASE + 6) | |
99 | #define CR_EXCEPTION (CR_BASE + 7) | |
100 | #define CR_PTEADDR (CR_BASE + 8) | |
101 | #define CR_PTEADDR_PTBASE_SHIFT 22 | |
102 | #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) | |
103 | #define CR_PTEADDR_VPN_SHIFT 2 | |
104 | #define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) | |
105 | #define CR_TLBACC (CR_BASE + 9) | |
106 | #define CR_TLBACC_IGN_SHIFT 25 | |
107 | #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) | |
108 | #define CR_TLBACC_C (1 << 24) | |
109 | #define CR_TLBACC_R (1 << 23) | |
110 | #define CR_TLBACC_W (1 << 22) | |
111 | #define CR_TLBACC_X (1 << 21) | |
112 | #define CR_TLBACC_G (1 << 20) | |
113 | #define CR_TLBACC_PFN_MASK 0x000FFFFF | |
114 | #define CR_TLBMISC (CR_BASE + 10) | |
115 | #define CR_TLBMISC_WAY_SHIFT 20 | |
116 | #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) | |
117 | #define CR_TLBMISC_RD (1 << 19) | |
118 | #define CR_TLBMISC_WR (1 << 18) | |
119 | #define CR_TLBMISC_PID_SHIFT 4 | |
120 | #define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) | |
121 | #define CR_TLBMISC_DBL (1 << 3) | |
122 | #define CR_TLBMISC_BAD (1 << 2) | |
123 | #define CR_TLBMISC_PERM (1 << 1) | |
124 | #define CR_TLBMISC_D (1 << 0) | |
125 | #define CR_ENCINJ (CR_BASE + 11) | |
126 | #define CR_BADADDR (CR_BASE + 12) | |
127 | #define CR_CONFIG (CR_BASE + 13) | |
128 | #define CR_MPUBASE (CR_BASE + 14) | |
129 | #define CR_MPUACC (CR_BASE + 15) | |
130 | ||
131 | /* Other registers */ | |
132 | #define R_PC 64 | |
133 | ||
134 | /* Exceptions */ | |
413a99a9 | 135 | #define EXCP_BREAK 0x1000 |
032c76bc CW |
136 | #define EXCP_RESET 0 |
137 | #define EXCP_PRESET 1 | |
138 | #define EXCP_IRQ 2 | |
139 | #define EXCP_TRAP 3 | |
140 | #define EXCP_UNIMPL 4 | |
141 | #define EXCP_ILLEGAL 5 | |
142 | #define EXCP_UNALIGN 6 | |
143 | #define EXCP_UNALIGND 7 | |
144 | #define EXCP_DIV 8 | |
145 | #define EXCP_SUPERA 9 | |
146 | #define EXCP_SUPERI 10 | |
147 | #define EXCP_SUPERD 11 | |
148 | #define EXCP_TLBD 12 | |
149 | #define EXCP_TLBX 13 | |
150 | #define EXCP_TLBR 14 | |
151 | #define EXCP_TLBW 15 | |
152 | #define EXCP_MPUI 16 | |
153 | #define EXCP_MPUD 17 | |
154 | ||
155 | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 | |
156 | ||
1ea4a06a | 157 | struct CPUArchState { |
032c76bc CW |
158 | uint32_t regs[NUM_CORE_REGS]; |
159 | ||
160 | #if !defined(CONFIG_USER_ONLY) | |
161 | Nios2MMU mmu; | |
032c76bc | 162 | #endif |
87d7bfdb | 163 | int error_code; |
032c76bc CW |
164 | }; |
165 | ||
166 | /** | |
167 | * Nios2CPU: | |
168 | * @env: #CPUNios2State | |
169 | * | |
170 | * A Nios2 CPU. | |
171 | */ | |
b36e239e | 172 | struct ArchCPU { |
032c76bc CW |
173 | /*< private >*/ |
174 | CPUState parent_obj; | |
175 | /*< public >*/ | |
176 | ||
5b146dc7 | 177 | CPUNegativeOffsetState neg; |
032c76bc | 178 | CPUNios2State env; |
5b146dc7 | 179 | |
032c76bc CW |
180 | bool mmu_present; |
181 | uint32_t pid_num_bits; | |
182 | uint32_t tlb_num_ways; | |
183 | uint32_t tlb_num_entries; | |
184 | ||
185 | /* Addresses that are hard-coded in the FPGA build settings */ | |
186 | uint32_t reset_addr; | |
187 | uint32_t exception_addr; | |
188 | uint32_t fast_tlb_miss_addr; | |
db1015e9 | 189 | }; |
032c76bc | 190 | |
032c76bc CW |
191 | |
192 | void nios2_tcg_init(void); | |
032c76bc | 193 | void nios2_cpu_do_interrupt(CPUState *cs); |
fad866da | 194 | void dump_mmu(CPUNios2State *env); |
90c84c56 | 195 | void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
032c76bc CW |
196 | hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); |
197 | void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, | |
fa947a66 RH |
198 | MMUAccessType access_type, int mmu_idx, |
199 | uintptr_t retaddr) QEMU_NORETURN; | |
032c76bc | 200 | |
413a99a9 SL |
201 | void do_nios2_semihosting(CPUNios2State *env); |
202 | ||
0dacec87 | 203 | #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU |
032c76bc CW |
204 | |
205 | #define cpu_gen_code cpu_nios2_gen_code | |
032c76bc CW |
206 | |
207 | #define CPU_SAVE_VERSION 1 | |
208 | ||
032c76bc | 209 | /* MMU modes definitions */ |
032c76bc CW |
210 | #define MMU_SUPERVISOR_IDX 0 |
211 | #define MMU_USER_IDX 1 | |
212 | ||
213 | static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) | |
214 | { | |
215 | return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : | |
216 | MMU_SUPERVISOR_IDX; | |
217 | } | |
218 | ||
fac94cb3 RH |
219 | #ifdef CONFIG_USER_ONLY |
220 | void nios2_cpu_record_sigsegv(CPUState *cpu, vaddr addr, | |
221 | MMUAccessType access_type, | |
222 | bool maperr, uintptr_t ra); | |
223 | #else | |
0137c93f RH |
224 | bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
225 | MMUAccessType access_type, int mmu_idx, | |
226 | bool probe, uintptr_t retaddr); | |
fac94cb3 | 227 | #endif |
032c76bc CW |
228 | |
229 | static inline int cpu_interrupts_enabled(CPUNios2State *env) | |
230 | { | |
231 | return env->regs[CR_STATUS] & CR_STATUS_PIE; | |
232 | } | |
233 | ||
4f7c64b3 | 234 | typedef CPUNios2State CPUArchState; |
2161a612 | 235 | typedef Nios2CPU ArchCPU; |
4f7c64b3 | 236 | |
032c76bc | 237 | #include "exec/cpu-all.h" |
032c76bc CW |
238 | |
239 | static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *pc, | |
240 | target_ulong *cs_base, uint32_t *flags) | |
241 | { | |
242 | *pc = env->regs[R_PC]; | |
243 | *cs_base = 0; | |
244 | *flags = (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); | |
245 | } | |
246 | ||
58ea30f5 | 247 | #endif /* NIOS2_CPU_H */ |