]>
Commit | Line | Data |
---|---|---|
e67db06e JL |
1 | /* |
2 | * QEMU OpenRISC CPU | |
3 | * | |
4 | * Copyright (c) 2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
779fc6ad | 9 | * version 2.1 of the License, or (at your option) any later version. |
e67db06e JL |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
ed2decc6 | 20 | #include "qemu/osdep.h" |
da34e65c | 21 | #include "qapi/error.h" |
0442428a | 22 | #include "qemu/qemu-print.h" |
e67db06e | 23 | #include "cpu.h" |
e67db06e | 24 | |
f45748f1 AF |
25 | static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) |
26 | { | |
27 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | |
28 | ||
29 | cpu->env.pc = value; | |
e8f29049 | 30 | cpu->env.dflag = 0; |
f45748f1 AF |
31 | } |
32 | ||
8c2e1b00 AF |
33 | static bool openrisc_cpu_has_work(CPUState *cs) |
34 | { | |
35 | return cs->interrupt_request & (CPU_INTERRUPT_HARD | | |
36 | CPU_INTERRUPT_TIMER); | |
37 | } | |
38 | ||
d5cabcce RH |
39 | static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) |
40 | { | |
41 | info->print_insn = print_insn_or1k; | |
42 | } | |
43 | ||
781c67ca | 44 | static void openrisc_cpu_reset(DeviceState *dev) |
e67db06e | 45 | { |
781c67ca | 46 | CPUState *s = CPU(dev); |
e67db06e JL |
47 | OpenRISCCPU *cpu = OPENRISC_CPU(s); |
48 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); | |
49 | ||
781c67ca | 50 | occ->parent_reset(dev); |
e67db06e | 51 | |
1f5c00cf | 52 | memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); |
e67db06e JL |
53 | |
54 | cpu->env.pc = 0x100; | |
55 | cpu->env.sr = SR_FO | SR_SM; | |
930c3d00 | 56 | cpu->env.lock_addr = -1; |
27103424 | 57 | s->exception_index = -1; |
a465772e | 58 | cpu_set_fpcsr(&cpu->env, 0); |
e67db06e | 59 | |
e67db06e JL |
60 | #ifndef CONFIG_USER_ONLY |
61 | cpu->env.picmr = 0x00000000; | |
62 | cpu->env.picsr = 0x00000000; | |
63 | ||
64 | cpu->env.ttmr = 0x00000000; | |
e67db06e JL |
65 | #endif |
66 | } | |
67 | ||
71b3254d PM |
68 | #ifndef CONFIG_USER_ONLY |
69 | static void openrisc_cpu_set_irq(void *opaque, int irq, int level) | |
70 | { | |
71 | OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; | |
72 | CPUState *cs = CPU(cpu); | |
73 | uint32_t irq_bit; | |
74 | ||
75 | if (irq > 31 || irq < 0) { | |
76 | return; | |
77 | } | |
78 | ||
79 | irq_bit = 1U << irq; | |
80 | ||
81 | if (level) { | |
82 | cpu->env.picsr |= irq_bit; | |
83 | } else { | |
84 | cpu->env.picsr &= ~irq_bit; | |
85 | } | |
86 | ||
87 | if (cpu->env.picsr & cpu->env.picmr) { | |
88 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
89 | } else { | |
90 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); | |
91 | cpu->env.picsr = 0; | |
92 | } | |
93 | } | |
94 | #endif | |
95 | ||
c296262b | 96 | static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) |
e67db06e | 97 | { |
14a10fc3 | 98 | CPUState *cs = CPU(dev); |
c296262b | 99 | OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); |
ce5b1bbf LV |
100 | Error *local_err = NULL; |
101 | ||
102 | cpu_exec_realizefn(cs, &local_err); | |
103 | if (local_err != NULL) { | |
104 | error_propagate(errp, local_err); | |
105 | return; | |
106 | } | |
e67db06e | 107 | |
14a10fc3 AF |
108 | qemu_init_vcpu(cs); |
109 | cpu_reset(cs); | |
c296262b AF |
110 | |
111 | occ->parent_realize(dev, errp); | |
e67db06e JL |
112 | } |
113 | ||
114 | static void openrisc_cpu_initfn(Object *obj) | |
115 | { | |
116 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
e67db06e | 117 | |
7506ed90 | 118 | cpu_set_cpustate_pointers(cpu); |
71b3254d PM |
119 | |
120 | #ifndef CONFIG_USER_ONLY | |
121 | qdev_init_gpio_in_named(DEVICE(cpu), openrisc_cpu_set_irq, "IRQ", NR_IRQS); | |
122 | #endif | |
e67db06e JL |
123 | } |
124 | ||
125 | /* CPU models */ | |
bd039ce0 AF |
126 | |
127 | static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) | |
128 | { | |
129 | ObjectClass *oc; | |
071b3364 | 130 | char *typename; |
bd039ce0 | 131 | |
a6772731 | 132 | typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); |
071b3364 | 133 | oc = object_class_by_name(typename); |
9b146e9a | 134 | g_free(typename); |
c432b784 AF |
135 | if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) || |
136 | object_class_is_abstract(oc))) { | |
bd039ce0 AF |
137 | return NULL; |
138 | } | |
139 | return oc; | |
140 | } | |
141 | ||
e67db06e JL |
142 | static void or1200_initfn(Object *obj) |
143 | { | |
144 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
145 | ||
c7efab4f RH |
146 | cpu->env.vr = 0x13000008; |
147 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; | |
48a1b62b SH |
148 | cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | |
149 | CPUCFGR_EVBARP; | |
c7efab4f RH |
150 | |
151 | /* 1Way, TLB_SIZE entries. */ | |
152 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | |
153 | | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); | |
154 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | |
155 | | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); | |
e67db06e JL |
156 | } |
157 | ||
158 | static void openrisc_any_initfn(Object *obj) | |
159 | { | |
160 | OpenRISCCPU *cpu = OPENRISC_CPU(obj); | |
161 | ||
8bebf7d1 RH |
162 | cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ |
163 | cpu->env.vr2 = 0; /* No version specific id */ | |
9e3bab08 | 164 | cpu->env.avr = 0x01030000; /* Architecture v1.3 */ |
8bebf7d1 | 165 | |
c7efab4f | 166 | cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; |
fe636d37 | 167 | cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | |
62f2b038 | 168 | CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; |
c7efab4f RH |
169 | |
170 | /* 1Way, TLB_SIZE entries. */ | |
171 | cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | |
172 | | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); | |
173 | cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | |
174 | | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); | |
e67db06e JL |
175 | } |
176 | ||
8b80bd28 PMD |
177 | #ifndef CONFIG_USER_ONLY |
178 | #include "hw/core/sysemu-cpu-ops.h" | |
179 | ||
180 | static const struct SysemuCPUOps openrisc_sysemu_ops = { | |
181 | }; | |
182 | #endif | |
183 | ||
78271684 CF |
184 | #include "hw/core/tcg-cpu-ops.h" |
185 | ||
186 | static struct TCGCPUOps openrisc_tcg_ops = { | |
187 | .initialize = openrisc_translate_init, | |
188 | .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, | |
189 | .tlb_fill = openrisc_cpu_tlb_fill, | |
190 | ||
191 | #ifndef CONFIG_USER_ONLY | |
192 | .do_interrupt = openrisc_cpu_do_interrupt, | |
193 | #endif /* !CONFIG_USER_ONLY */ | |
194 | }; | |
195 | ||
e67db06e JL |
196 | static void openrisc_cpu_class_init(ObjectClass *oc, void *data) |
197 | { | |
198 | OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); | |
199 | CPUClass *cc = CPU_CLASS(occ); | |
c296262b AF |
200 | DeviceClass *dc = DEVICE_CLASS(oc); |
201 | ||
bf853881 PMD |
202 | device_class_set_parent_realize(dc, openrisc_cpu_realizefn, |
203 | &occ->parent_realize); | |
781c67ca | 204 | device_class_set_parent_reset(dc, openrisc_cpu_reset, &occ->parent_reset); |
bd039ce0 AF |
205 | |
206 | cc->class_by_name = openrisc_cpu_class_by_name; | |
8c2e1b00 | 207 | cc->has_work = openrisc_cpu_has_work; |
878096ee | 208 | cc->dump_state = openrisc_cpu_dump_state; |
f45748f1 | 209 | cc->set_pc = openrisc_cpu_set_pc; |
5b50e790 AF |
210 | cc->gdb_read_register = openrisc_cpu_gdb_read_register; |
211 | cc->gdb_write_register = openrisc_cpu_gdb_write_register; | |
35e911ae | 212 | #ifndef CONFIG_USER_ONLY |
00b941e5 AF |
213 | cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; |
214 | dc->vmsd = &vmstate_openrisc_cpu; | |
8b80bd28 | 215 | cc->sysemu_ops = &openrisc_sysemu_ops; |
00b941e5 | 216 | #endif |
a0e372f0 | 217 | cc->gdb_num_core_regs = 32 + 3; |
d5cabcce | 218 | cc->disas_set_info = openrisc_disas_set_info; |
78271684 | 219 | cc->tcg_ops = &openrisc_tcg_ops; |
e67db06e JL |
220 | } |
221 | ||
e67db06e JL |
222 | /* Sort alphabetically by type name, except for "any". */ |
223 | static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b) | |
224 | { | |
225 | ObjectClass *class_a = (ObjectClass *)a; | |
226 | ObjectClass *class_b = (ObjectClass *)b; | |
227 | const char *name_a, *name_b; | |
228 | ||
229 | name_a = object_class_get_name(class_a); | |
230 | name_b = object_class_get_name(class_b); | |
478032a9 | 231 | if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e | 232 | return 1; |
478032a9 | 233 | } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) { |
e67db06e JL |
234 | return -1; |
235 | } else { | |
236 | return strcmp(name_a, name_b); | |
237 | } | |
238 | } | |
239 | ||
240 | static void openrisc_cpu_list_entry(gpointer data, gpointer user_data) | |
241 | { | |
242 | ObjectClass *oc = data; | |
478032a9 AF |
243 | const char *typename; |
244 | char *name; | |
e67db06e | 245 | |
478032a9 AF |
246 | typename = object_class_get_name(oc); |
247 | name = g_strndup(typename, | |
248 | strlen(typename) - strlen("-" TYPE_OPENRISC_CPU)); | |
0442428a | 249 | qemu_printf(" %s\n", name); |
478032a9 | 250 | g_free(name); |
e67db06e JL |
251 | } |
252 | ||
0442428a | 253 | void cpu_openrisc_list(void) |
e67db06e | 254 | { |
e67db06e JL |
255 | GSList *list; |
256 | ||
257 | list = object_class_get_list(TYPE_OPENRISC_CPU, false); | |
258 | list = g_slist_sort(list, openrisc_cpu_list_compare); | |
0442428a MA |
259 | qemu_printf("Available CPUs:\n"); |
260 | g_slist_foreach(list, openrisc_cpu_list_entry, NULL); | |
e67db06e JL |
261 | g_slist_free(list); |
262 | } | |
263 | ||
a6772731 IM |
264 | #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ |
265 | { \ | |
266 | .parent = TYPE_OPENRISC_CPU, \ | |
267 | .instance_init = initfn, \ | |
268 | .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ | |
269 | } | |
270 | ||
271 | static const TypeInfo openrisc_cpus_type_infos[] = { | |
272 | { /* base class should be registered first */ | |
273 | .name = TYPE_OPENRISC_CPU, | |
274 | .parent = TYPE_CPU, | |
275 | .instance_size = sizeof(OpenRISCCPU), | |
276 | .instance_init = openrisc_cpu_initfn, | |
277 | .abstract = true, | |
278 | .class_size = sizeof(OpenRISCCPUClass), | |
279 | .class_init = openrisc_cpu_class_init, | |
280 | }, | |
281 | DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), | |
282 | DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), | |
283 | }; | |
284 | ||
285 | DEFINE_TYPES(openrisc_cpus_type_infos) |