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e67db06e JL |
1 | /* |
2 | * OpenRISC interrupt. | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
198a2d21 | 9 | * version 2.1 of the License, or (at your option) any later version. |
e67db06e JL |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
ed2decc6 | 20 | #include "qemu/osdep.h" |
cd617484 | 21 | #include "qemu/log.h" |
e67db06e | 22 | #include "cpu.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
4ea5fe99 | 24 | #include "gdbstub/helpers.h" |
1de7afc9 | 25 | #include "qemu/host-utils.h" |
e67db06e JL |
26 | #ifndef CONFIG_USER_ONLY |
27 | #include "hw/loader.h" | |
28 | #endif | |
29 | ||
97a8ea5a | 30 | void openrisc_cpu_do_interrupt(CPUState *cs) |
e67db06e | 31 | { |
074bd799 | 32 | CPUOpenRISCState *env = cpu_env(cs); |
378cd36f | 33 | int exception = cs->exception_index; |
ae52bd96 SM |
34 | |
35 | env->epcr = env->pc; | |
765fdc1e | 36 | |
c56e3b86 SH |
37 | /* When we have an illegal instruction the error effective address |
38 | shall be set to the illegal instruction address. */ | |
378cd36f | 39 | if (exception == EXCP_ILLEGAL) { |
c56e3b86 SH |
40 | env->eear = env->pc; |
41 | } | |
b6a71ef7 | 42 | |
9f6e8afa | 43 | /* During exceptions esr is populared with the pre-exception sr. */ |
84775c43 | 44 | env->esr = cpu_get_sr(env); |
9f6e8afa SH |
45 | /* In parallel sr is updated to disable mmu, interrupts, timers and |
46 | set the delay slot exception flag. */ | |
b6a71ef7 JL |
47 | env->sr &= ~SR_DME; |
48 | env->sr &= ~SR_IME; | |
49 | env->sr |= SR_SM; | |
50 | env->sr &= ~SR_IEE; | |
51 | env->sr &= ~SR_TEE; | |
f4d1414a SH |
52 | env->pmr &= ~PMR_DME; |
53 | env->pmr &= ~PMR_SME; | |
930c3d00 | 54 | env->lock_addr = -1; |
b6a71ef7 | 55 | |
9f6e8afa SH |
56 | /* Set/clear dsx to indicate if we are in a delay slot exception. */ |
57 | if (env->dflag) { | |
58 | env->dflag = 0; | |
59 | env->sr |= SR_DSX; | |
60 | env->epcr -= 4; | |
61 | } else { | |
62 | env->sr &= ~SR_DSX; | |
765fdc1e SH |
63 | if (exception == EXCP_SYSCALL || exception == EXCP_FPE) { |
64 | env->epcr += 4; | |
65 | } | |
9f6e8afa SH |
66 | } |
67 | ||
378cd36f RH |
68 | if (exception > 0 && exception < EXCP_NR) { |
69 | static const char * const int_name[EXCP_NR] = { | |
70 | [EXCP_RESET] = "RESET", | |
71 | [EXCP_BUSERR] = "BUSERR (bus error)", | |
72 | [EXCP_DPF] = "DFP (data protection fault)", | |
73 | [EXCP_IPF] = "IPF (code protection fault)", | |
74 | [EXCP_TICK] = "TICK (timer interrupt)", | |
75 | [EXCP_ALIGN] = "ALIGN", | |
76 | [EXCP_ILLEGAL] = "ILLEGAL", | |
77 | [EXCP_INT] = "INT (device interrupt)", | |
78 | [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", | |
79 | [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", | |
80 | [EXCP_RANGE] = "RANGE", | |
81 | [EXCP_SYSCALL] = "SYSCALL", | |
82 | [EXCP_FPE] = "FPE", | |
83 | [EXCP_TRAP] = "TRAP", | |
84 | }; | |
85 | ||
bbe6855e SH |
86 | qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n", |
87 | cs->cpu_index, | |
88 | int_name[exception]); | |
378cd36f RH |
89 | |
90 | hwaddr vect_pc = exception << 8; | |
356a2db3 TA |
91 | if (env->cpucfgr & CPUCFGR_EVBARP) { |
92 | vect_pc |= env->evbar; | |
93 | } | |
3fee028d TA |
94 | if (env->sr & SR_EPH) { |
95 | vect_pc |= 0xf0000000; | |
96 | } | |
356a2db3 | 97 | env->pc = vect_pc; |
b6a71ef7 | 98 | } else { |
378cd36f | 99 | cpu_abort(cs, "Unhandled exception 0x%x\n", exception); |
b6a71ef7 | 100 | } |
b6a71ef7 | 101 | |
27103424 | 102 | cs->exception_index = -1; |
e67db06e | 103 | } |
fbb96c4b RH |
104 | |
105 | bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) | |
106 | { | |
074bd799 | 107 | CPUOpenRISCState *env = cpu_env(cs); |
fbb96c4b RH |
108 | int idx = -1; |
109 | ||
110 | if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { | |
111 | idx = EXCP_INT; | |
112 | } | |
113 | if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { | |
114 | idx = EXCP_TICK; | |
115 | } | |
116 | if (idx >= 0) { | |
117 | cs->exception_index = idx; | |
118 | openrisc_cpu_do_interrupt(cs); | |
119 | return true; | |
120 | } | |
121 | return false; | |
122 | } |