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e67db06e JL |
1 | /* |
2 | * OpenRISC Machine | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
ed2decc6 | 20 | #include "qemu/osdep.h" |
33c11879 PB |
21 | #include "qemu-common.h" |
22 | #include "cpu.h" | |
e67db06e JL |
23 | #include "hw/hw.h" |
24 | #include "hw/boards.h" | |
1e00b8d5 | 25 | #include "migration/cpu.h" |
e67db06e | 26 | |
acf57591 SH |
27 | static int env_post_load(void *opaque, int version_id) |
28 | { | |
29 | CPUOpenRISCState *env = opaque; | |
30 | ||
31 | /* Restore MMU handlers */ | |
32 | if (env->sr & SR_DME) { | |
33 | env->tlb->cpu_openrisc_map_address_data = | |
34 | &cpu_openrisc_get_phys_data; | |
35 | } else { | |
36 | env->tlb->cpu_openrisc_map_address_data = | |
37 | &cpu_openrisc_get_phys_nommu; | |
38 | } | |
39 | ||
40 | if (env->sr & SR_IME) { | |
41 | env->tlb->cpu_openrisc_map_address_code = | |
42 | &cpu_openrisc_get_phys_code; | |
43 | } else { | |
44 | env->tlb->cpu_openrisc_map_address_code = | |
45 | &cpu_openrisc_get_phys_nommu; | |
46 | } | |
47 | ||
48 | ||
49 | return 0; | |
50 | } | |
51 | ||
52 | static const VMStateDescription vmstate_tlb_entry = { | |
53 | .name = "tlb_entry", | |
54 | .version_id = 1, | |
55 | .minimum_version_id = 1, | |
56 | .minimum_version_id_old = 1, | |
57 | .fields = (VMStateField[]) { | |
58 | VMSTATE_UINTTL(mr, OpenRISCTLBEntry), | |
59 | VMSTATE_UINTTL(tr, OpenRISCTLBEntry), | |
60 | VMSTATE_END_OF_LIST() | |
61 | } | |
62 | }; | |
63 | ||
64 | static const VMStateDescription vmstate_cpu_tlb = { | |
65 | .name = "cpu_tlb", | |
66 | .version_id = 1, | |
67 | .minimum_version_id = 1, | |
68 | .minimum_version_id_old = 1, | |
69 | .fields = (VMStateField[]) { | |
70 | VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext, | |
71 | ITLB_WAYS, ITLB_SIZE, 0, | |
72 | vmstate_tlb_entry, OpenRISCTLBEntry), | |
73 | VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext, | |
74 | DTLB_WAYS, DTLB_SIZE, 0, | |
75 | vmstate_tlb_entry, OpenRISCTLBEntry), | |
76 | VMSTATE_END_OF_LIST() | |
77 | } | |
78 | }; | |
79 | ||
80 | #define VMSTATE_CPU_TLB(_f, _s) \ | |
81 | VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext) | |
82 | ||
83 | ||
84775c43 RH |
84 | static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) |
85 | { | |
86 | CPUOpenRISCState *env = opaque; | |
87 | cpu_set_sr(env, qemu_get_be32(f)); | |
88 | return 0; | |
89 | } | |
90 | ||
91 | static int put_sr(QEMUFile *f, void *opaque, size_t size, | |
92 | VMStateField *field, QJSON *vmdesc) | |
93 | { | |
94 | CPUOpenRISCState *env = opaque; | |
95 | qemu_put_be32(f, cpu_get_sr(env)); | |
96 | return 0; | |
97 | } | |
98 | ||
99 | static const VMStateInfo vmstate_sr = { | |
100 | .name = "sr", | |
101 | .get = get_sr, | |
102 | .put = put_sr, | |
103 | }; | |
104 | ||
da697214 AF |
105 | static const VMStateDescription vmstate_env = { |
106 | .name = "env", | |
acf57591 SH |
107 | .version_id = 6, |
108 | .minimum_version_id = 6, | |
109 | .post_load = env_post_load, | |
e67db06e | 110 | .fields = (VMStateField[]) { |
d89e71e8 | 111 | VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32), |
930c3d00 | 112 | VMSTATE_UINTTL(pc, CPUOpenRISCState), |
930c3d00 RH |
113 | VMSTATE_UINTTL(ppc, CPUOpenRISCState), |
114 | VMSTATE_UINTTL(jmp_pc, CPUOpenRISCState), | |
115 | VMSTATE_UINTTL(lock_addr, CPUOpenRISCState), | |
116 | VMSTATE_UINTTL(lock_value, CPUOpenRISCState), | |
117 | VMSTATE_UINTTL(epcr, CPUOpenRISCState), | |
118 | VMSTATE_UINTTL(eear, CPUOpenRISCState), | |
84775c43 RH |
119 | |
120 | /* Save the architecture value of the SR, not the internally | |
121 | expanded version. Since this architecture value does not | |
122 | exist in memory to be stored, this requires a but of hoop | |
123 | jumping. We want OFFSET=0 so that we effectively pass ENV | |
124 | to the helper functions, and we need to fill in the name by | |
125 | hand since there's no field of that name. */ | |
126 | { | |
127 | .name = "sr", | |
128 | .version_id = 0, | |
129 | .size = sizeof(uint32_t), | |
130 | .info = &vmstate_sr, | |
131 | .flags = VMS_SINGLE, | |
132 | .offset = 0 | |
133 | }, | |
134 | ||
930c3d00 RH |
135 | VMSTATE_UINT32(vr, CPUOpenRISCState), |
136 | VMSTATE_UINT32(upr, CPUOpenRISCState), | |
137 | VMSTATE_UINT32(cpucfgr, CPUOpenRISCState), | |
138 | VMSTATE_UINT32(dmmucfgr, CPUOpenRISCState), | |
139 | VMSTATE_UINT32(immucfgr, CPUOpenRISCState), | |
acf57591 | 140 | VMSTATE_UINT32(evbar, CPUOpenRISCState), |
f4d1414a | 141 | VMSTATE_UINT32(pmr, CPUOpenRISCState), |
e67db06e JL |
142 | VMSTATE_UINT32(esr, CPUOpenRISCState), |
143 | VMSTATE_UINT32(fpcsr, CPUOpenRISCState), | |
6f7332ba | 144 | VMSTATE_UINT64(mac, CPUOpenRISCState), |
acf57591 SH |
145 | |
146 | VMSTATE_CPU_TLB(tlb, CPUOpenRISCState), | |
147 | ||
148 | VMSTATE_TIMER_PTR(timer, CPUOpenRISCState), | |
149 | VMSTATE_UINT32(ttmr, CPUOpenRISCState), | |
acf57591 SH |
150 | |
151 | VMSTATE_UINT32(picmr, CPUOpenRISCState), | |
152 | VMSTATE_UINT32(picsr, CPUOpenRISCState), | |
153 | ||
e67db06e JL |
154 | VMSTATE_END_OF_LIST() |
155 | } | |
156 | }; | |
157 | ||
da697214 AF |
158 | const VMStateDescription vmstate_openrisc_cpu = { |
159 | .name = "cpu", | |
160 | .version_id = 1, | |
161 | .minimum_version_id = 1, | |
da697214 AF |
162 | .fields = (VMStateField[]) { |
163 | VMSTATE_CPU(), | |
164 | VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState), | |
165 | VMSTATE_END_OF_LIST() | |
166 | } | |
167 | }; |