[mirror_qemu.git] / target / openrisc / sys_helper.c

/*
 * OpenRISC system instructions helper routines
 *
 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
 *                         Zhizhou Zhang <etouzh@gmail.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"

#define TO_SPR(group, number) (((group) << 11) + (number))

void HELPER(mtspr)(CPUOpenRISCState *env,
                   target_ulong ra, target_ulong rb, target_ulong offset)
{
#ifndef CONFIG_USER_ONLY
    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
    CPUState *cs = CPU(cpu);
    int spr = (ra | offset);
    int idx;

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        env->vr = rb;
        break;

    case TO_SPR(0, 11): /* EVBAR */
        env->evbar = rb;
        break;

    case TO_SPR(0, 16): /* NPC */
        cpu_restore_state(cs, GETPC());
        /* ??? Mirror or1ksim in not trashing delayed branch state
           when "jumping" to the current instruction.  */
        if (env->pc != rb) {
            env->pc = rb;
            env->dflag = 0;
            cpu_loop_exit(cs);
        }
        break;

    case TO_SPR(0, 17): /* SR */
        if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
            (rb & (SR_IME | SR_DME | SR_SM))) {
            tlb_flush(cs);
        }
        cpu_set_sr(env, rb);
        if (env->sr & SR_DME) {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_data;
        } else {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_nommu;
        }

        if (env->sr & SR_IME) {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_code;
        } else {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_nommu;
        }
        break;

    case TO_SPR(0, 18): /* PPC */
        env->ppc = rb;
        break;

    case TO_SPR(0, 32): /* EPCR */
        env->epcr = rb;
        break;

    case TO_SPR(0, 48): /* EEAR */
        env->eear = rb;
        break;

    case TO_SPR(0, 64): /* ESR */
        env->esr = rb;
        break;
    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        if (!(rb & 1)) {
            tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->dtlb[0][idx].mr = rb;
        break;

    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        env->tlb->dtlb[0][idx].tr = rb;
        break;
    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;
    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        if (!(rb & 1)) {
            tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->itlb[0][idx].mr = rb;
        break;

    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        env->tlb->itlb[0][idx].tr = rb;
        break;
    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;
    case TO_SPR(5, 1):  /* MACLO */
        env->mac = deposit64(env->mac, 0, 32, rb);
        break;
    case TO_SPR(5, 2):  /* MACHI */
        env->mac = deposit64(env->mac, 32, 32, rb);
        break;
    case TO_SPR(9, 0):  /* PICMR */
        env->picmr |= rb;
        break;
    case TO_SPR(9, 2):  /* PICSR */
        env->picsr &= ~rb;
        break;
    case TO_SPR(10, 0): /* TTMR */
        {
            if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
                switch (rb & TTMR_M) {
                case TIMER_NONE:
                    cpu_openrisc_count_stop(cpu);
                    break;
                case TIMER_INTR:
                case TIMER_SHOT:
                case TIMER_CONT:
                    cpu_openrisc_count_start(cpu);
                    break;
                default:
                    break;
                }
            }

            int ip = env->ttmr & TTMR_IP;

            if (rb & TTMR_IP) {    /* Keep IP bit.  */
                env->ttmr = (rb & ~TTMR_IP) | ip;
            } else {    /* Clear IP bit.  */
                env->ttmr = rb & ~TTMR_IP;
                cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
            }

            cpu_openrisc_timer_update(cpu);
        }
        break;

    case TO_SPR(10, 1): /* TTCR */
        env->ttcr = rb;
        if (env->ttmr & TIMER_NONE) {
            return;
        }
        cpu_openrisc_timer_update(cpu);
        break;
    default:
        break;
    }
#endif
}

target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
                           target_ulong rd, target_ulong ra, uint32_t offset)
{
#ifndef CONFIG_USER_ONLY
    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
    CPUState *cs = CPU(cpu);
    int spr = (ra | offset);
    int idx;

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        return env->vr & SPR_VR;

    case TO_SPR(0, 1): /* UPR */
        return env->upr;    /* TT, DM, IM, UP present */

    case TO_SPR(0, 2): /* CPUCFGR */
        return env->cpucfgr;

    case TO_SPR(0, 3): /* DMMUCFGR */
        return env->dmmucfgr;    /* 1Way, 64 entries */

    case TO_SPR(0, 4): /* IMMUCFGR */
        return env->immucfgr;

    case TO_SPR(0, 11): /* EVBAR */
        return env->evbar;

    case TO_SPR(0, 16): /* NPC (equals PC) */
        cpu_restore_state(cs, GETPC());
        return env->pc;

    case TO_SPR(0, 17): /* SR */
        return cpu_get_sr(env);

    case TO_SPR(0, 18): /* PPC */
        cpu_restore_state(cs, GETPC());
        return env->ppc;

    case TO_SPR(0, 32): /* EPCR */
        return env->epcr;

    case TO_SPR(0, 48): /* EEAR */
        return env->eear;

    case TO_SPR(0, 64): /* ESR */
        return env->esr;

    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        return env->tlb->dtlb[0][idx].mr;

    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        return env->tlb->dtlb[0][idx].tr;

    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;

    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        return env->tlb->itlb[0][idx].mr;

    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        return env->tlb->itlb[0][idx].tr;

    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;

    case TO_SPR(5, 1):  /* MACLO */
        return (uint32_t)env->mac;
        break;
    case TO_SPR(5, 2):  /* MACHI */
        return env->mac >> 32;
        break;

    case TO_SPR(9, 0):  /* PICMR */
        return env->picmr;

    case TO_SPR(9, 2):  /* PICSR */
        return env->picsr;

    case TO_SPR(10, 0): /* TTMR */
        return env->ttmr;

    case TO_SPR(10, 1): /* TTCR */
        cpu_openrisc_count_update(cpu);
        return env->ttcr;

    default:
        break;
    }
#endif

    /* for rd is passed in, if rd unchanged, just keep it back.  */
    return rd;
}
Commit	Line	Data
4dd044c6 JL	1	/*
	2	* OpenRISC system instructions helper routines
	3	*
	4	* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
	5	* Zhizhou Zhang <etouzh@gmail.com>
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
ed2decc6	21	#include "qemu/osdep.h"
4dd044c6	22	#include "cpu.h"
63c91552	23	#include "exec/exec-all.h"
2ef6175a	24	#include "exec/helper-proto.h"
4dd044c6 JL	25
	26	#define TO_SPR(group, number) (((group) << 11) + (number))
	27
	28	void HELPER(mtspr)(CPUOpenRISCState *env,
	29	target_ulong ra, target_ulong rb, target_ulong offset)
	30	{
	31	#ifndef CONFIG_USER_ONLY
dd51dc52	32	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
259186a7	33	CPUState *cs = CPU(cpu);
24c32852 RH	34	int spr = (ra \| offset);
24c32852 RH	35	int idx;
4dd044c6 JL	36
	37	switch (spr) {
	38	case TO_SPR(0, 0): /* VR */
	39	env->vr = rb;
	40	break;
	41
356a2db3 TA	42	case TO_SPR(0, 11): /* EVBAR */
	43	env->evbar = rb;
	44	break;
	45
4dd044c6	46	case TO_SPR(0, 16): /* NPC */
24c32852 RH	47	cpu_restore_state(cs, GETPC());
	48	/* ??? Mirror or1ksim in not trashing delayed branch state
	49	when "jumping" to the current instruction. */
	50	if (env->pc != rb) {
	51	env->pc = rb;
a01deb36	52	env->dflag = 0;
24c32852 RH	53	cpu_loop_exit(cs);
24c32852 RH	54	}
4dd044c6 JL	55	break;
	56
	57	case TO_SPR(0, 17): /* SR */
	58	if ((env->sr & (SR_IME \| SR_DME \| SR_SM)) ^
	59	(rb & (SR_IME \| SR_DME \| SR_SM))) {
d10eb08f	60	tlb_flush(cs);
4dd044c6	61	}
84775c43	62	cpu_set_sr(env, rb);
4dd044c6 JL	63	if (env->sr & SR_DME) {
	64	env->tlb->cpu_openrisc_map_address_data =
	65	&cpu_openrisc_get_phys_data;
	66	} else {
	67	env->tlb->cpu_openrisc_map_address_data =
	68	&cpu_openrisc_get_phys_nommu;
	69	}
	70
	71	if (env->sr & SR_IME) {
	72	env->tlb->cpu_openrisc_map_address_code =
	73	&cpu_openrisc_get_phys_code;
	74	} else {
	75	env->tlb->cpu_openrisc_map_address_code =
	76	&cpu_openrisc_get_phys_nommu;
	77	}
	78	break;
	79
	80	case TO_SPR(0, 18): /* PPC */
	81	env->ppc = rb;
	82	break;
	83
	84	case TO_SPR(0, 32): /* EPCR */
	85	env->epcr = rb;
	86	break;
	87
	88	case TO_SPR(0, 48): /* EEAR */
	89	env->eear = rb;
	90	break;
	91
	92	case TO_SPR(0, 64): /* ESR */
	93	env->esr = rb;
	94	break;
93147a18	95	case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
4dd044c6 JL	96	idx = spr - TO_SPR(1, 512);
4dd044c6 JL	97	if (!(rb & 1)) {
31b030d4	98	tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
4dd044c6 JL	99	}
	100	env->tlb->dtlb[0][idx].mr = rb;
	101	break;
	102
93147a18	103	case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
4dd044c6 JL	104	idx = spr - TO_SPR(1, 640);
	105	env->tlb->dtlb[0][idx].tr = rb;
	106	break;
	107	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	108	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	109	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	110	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	111	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	112	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	113	break;
93147a18	114	case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
4dd044c6 JL	115	idx = spr - TO_SPR(2, 512);
4dd044c6 JL	116	if (!(rb & 1)) {
31b030d4	117	tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
4dd044c6 JL	118	}
	119	env->tlb->itlb[0][idx].mr = rb;
	120	break;
	121
93147a18	122	case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
4dd044c6 JL	123	idx = spr - TO_SPR(2, 640);
	124	env->tlb->itlb[0][idx].tr = rb;
	125	break;
	126	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	127	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	128	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	129	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	130	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	131	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	132	break;
6f7332ba RH	133	case TO_SPR(5, 1): /* MACLO */
	134	env->mac = deposit64(env->mac, 0, 32, rb);
	135	break;
	136	case TO_SPR(5, 2): /* MACHI */
	137	env->mac = deposit64(env->mac, 32, 32, rb);
	138	break;
4dd044c6 JL	139	case TO_SPR(9, 0): /* PICMR */
	140	env->picmr \|= rb;
	141	break;
	142	case TO_SPR(9, 2): /* PICSR */
	143	env->picsr &= ~rb;
	144	break;
	145	case TO_SPR(10, 0): /* TTMR */
	146	{
d5155217 SM	147	if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
	148	switch (rb & TTMR_M) {
	149	case TIMER_NONE:
	150	cpu_openrisc_count_stop(cpu);
	151	break;
	152	case TIMER_INTR:
	153	case TIMER_SHOT:
	154	case TIMER_CONT:
	155	cpu_openrisc_count_start(cpu);
	156	break;
	157	default:
	158	break;
	159	}
	160	}
	161
4dd044c6 JL	162	int ip = env->ttmr & TTMR_IP;
	163
	164	if (rb & TTMR_IP) { /* Keep IP bit. */
d5155217	165	env->ttmr = (rb & ~TTMR_IP) \| ip;
4dd044c6 JL	166	} else { /* Clear IP bit. */
4dd044c6 JL	167	env->ttmr = rb & ~TTMR_IP;
259186a7	168	cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
4dd044c6 JL	169	}
4dd044c6 JL	170
d5155217	171	cpu_openrisc_timer_update(cpu);
4dd044c6 JL	172	}
	173	break;
	174
	175	case TO_SPR(10, 1): /* TTCR */
	176	env->ttcr = rb;
	177	if (env->ttmr & TIMER_NONE) {
	178	return;
	179	}
d5155217	180	cpu_openrisc_timer_update(cpu);
4dd044c6 JL	181	break;
4dd044c6 JL	182	default:
4dd044c6 JL	183	break;
	184	}
	185	#endif
	186	}
	187
	188	target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
	189	target_ulong rd, target_ulong ra, uint32_t offset)
	190	{
	191	#ifndef CONFIG_USER_ONLY
24c32852 RH	192	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
24c32852 RH	193	CPUState *cs = CPU(cpu);
4dd044c6 JL	194	int spr = (ra \| offset);
	195	int idx;
	196
4dd044c6 JL	197	switch (spr) {
	198	case TO_SPR(0, 0): /* VR */
	199	return env->vr & SPR_VR;
	200
	201	case TO_SPR(0, 1): /* UPR */
	202	return env->upr; /* TT, DM, IM, UP present */
	203
	204	case TO_SPR(0, 2): /* CPUCFGR */
	205	return env->cpucfgr;
	206
	207	case TO_SPR(0, 3): /* DMMUCFGR */
	208	return env->dmmucfgr; /* 1Way, 64 entries */
	209
	210	case TO_SPR(0, 4): /* IMMUCFGR */
	211	return env->immucfgr;
	212
356a2db3 TA	213	case TO_SPR(0, 11): /* EVBAR */
	214	return env->evbar;
	215
24c32852 RH	216	case TO_SPR(0, 16): /* NPC (equals PC) */
	217	cpu_restore_state(cs, GETPC());
	218	return env->pc;
4dd044c6 JL	219
4dd044c6 JL	220	case TO_SPR(0, 17): /* SR */
84775c43	221	return cpu_get_sr(env);
4dd044c6 JL	222
4dd044c6 JL	223	case TO_SPR(0, 18): /* PPC */
24c32852	224	cpu_restore_state(cs, GETPC());
4dd044c6 JL	225	return env->ppc;
	226
	227	case TO_SPR(0, 32): /* EPCR */
	228	return env->epcr;
	229
	230	case TO_SPR(0, 48): /* EEAR */
	231	return env->eear;
	232
	233	case TO_SPR(0, 64): /* ESR */
	234	return env->esr;
	235
93147a18	236	case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
4dd044c6 JL	237	idx = spr - TO_SPR(1, 512);
	238	return env->tlb->dtlb[0][idx].mr;
	239
93147a18	240	case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
4dd044c6 JL	241	idx = spr - TO_SPR(1, 640);
	242	return env->tlb->dtlb[0][idx].tr;
	243
	244	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	245	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	246	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	247	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	248	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	249	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	250	break;
	251
93147a18	252	case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
4dd044c6 JL	253	idx = spr - TO_SPR(2, 512);
	254	return env->tlb->itlb[0][idx].mr;
	255
93147a18	256	case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
4dd044c6 JL	257	idx = spr - TO_SPR(2, 640);
	258	return env->tlb->itlb[0][idx].tr;
	259
	260	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	261	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	262	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	263	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	264	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	265	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	266	break;
	267
6f7332ba RH	268	case TO_SPR(5, 1): /* MACLO */
	269	return (uint32_t)env->mac;
	270	break;
	271	case TO_SPR(5, 2): /* MACHI */
	272	return env->mac >> 32;
	273	break;
	274
4dd044c6 JL	275	case TO_SPR(9, 0): /* PICMR */
	276	return env->picmr;
	277
	278	case TO_SPR(9, 2): /* PICSR */
	279	return env->picsr;
	280
	281	case TO_SPR(10, 0): /* TTMR */
	282	return env->ttmr;
	283
	284	case TO_SPR(10, 1): /* TTCR */
	285	cpu_openrisc_count_update(cpu);
	286	return env->ttcr;
	287
	288	default:
	289	break;
	290	}
	291	#endif
	292
4dd044c6 JL	293	/* for rd is passed in, if rd unchanged, just keep it back. */
	294	return rd;
	295	}