[mirror_qemu.git] / target / openrisc / sys_helper.c

/*
 * OpenRISC system instructions helper routines
 *
 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
 *                         Zhizhou Zhang <etouzh@gmail.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "exception.h"
#ifndef CONFIG_USER_ONLY
#include "hw/boards.h"
#endif

#define TO_SPR(group, number) (((group) << 11) + (number))

void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
{
#ifndef CONFIG_USER_ONLY
    OpenRISCCPU *cpu = env_archcpu(env);
    CPUState *cs = env_cpu(env);
    target_ulong mr;
    int idx;
#endif

    switch (spr) {
#ifndef CONFIG_USER_ONLY
    case TO_SPR(0, 11): /* EVBAR */
        env->evbar = rb;
        break;

    case TO_SPR(0, 16): /* NPC */
        cpu_restore_state(cs, GETPC(), true);
        /* ??? Mirror or1ksim in not trashing delayed branch state
           when "jumping" to the current instruction.  */
        if (env->pc != rb) {
            env->pc = rb;
            env->dflag = 0;
        }
        cpu_loop_exit(cs);
        break;

    case TO_SPR(0, 17): /* SR */
        cpu_set_sr(env, rb);
        break;

    case TO_SPR(0, 32): /* EPCR */
        env->epcr = rb;
        break;

    case TO_SPR(0, 48): /* EEAR */
        env->eear = rb;
        break;

    case TO_SPR(0, 64): /* ESR */
        env->esr = rb;
        break;

    case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
        idx = (spr - 1024);
        env->shadow_gpr[idx / 32][idx % 32] = rb;
        break;

    case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        mr = env->tlb.dtlb[idx].mr;
        if (mr & 1) {
            tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
        }
        if (rb & 1) {
            tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
        }
        env->tlb.dtlb[idx].mr = rb;
        break;
    case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        env->tlb.dtlb[idx].tr = rb;
        break;
    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;

    case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        mr = env->tlb.itlb[idx].mr;
        if (mr & 1) {
            tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
        }
        if (rb & 1) {
            tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
        }
        env->tlb.itlb[idx].mr = rb;
        break;
    case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        env->tlb.itlb[idx].tr = rb;
        break;
    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;

    case TO_SPR(5, 1):  /* MACLO */
        env->mac = deposit64(env->mac, 0, 32, rb);
        break;
    case TO_SPR(5, 2):  /* MACHI */
        env->mac = deposit64(env->mac, 32, 32, rb);
        break;
    case TO_SPR(8, 0):  /* PMR */
        env->pmr = rb;
        if (env->pmr & PMR_DME || env->pmr & PMR_SME) {
            cpu_restore_state(cs, GETPC(), true);
            env->pc += 4;
            cs->halted = 1;
            raise_exception(cpu, EXCP_HALTED);
        }
        break;
    case TO_SPR(9, 0):  /* PICMR */
        env->picmr = rb;
        qemu_mutex_lock_iothread();
        if (env->picsr & env->picmr) {
            cpu_interrupt(cs, CPU_INTERRUPT_HARD);
        } else {
            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
        }
        qemu_mutex_unlock_iothread();
        break;
    case TO_SPR(9, 2):  /* PICSR */
        env->picsr &= ~rb;
        break;
    case TO_SPR(10, 0): /* TTMR */
        {
            qemu_mutex_lock_iothread();
            if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
                switch (rb & TTMR_M) {
                case TIMER_NONE:
                    cpu_openrisc_count_stop(cpu);
                    break;
                case TIMER_INTR:
                case TIMER_SHOT:
                case TIMER_CONT:
                    cpu_openrisc_count_start(cpu);
                    break;
                default:
                    break;
                }
            }

            int ip = env->ttmr & TTMR_IP;

            if (rb & TTMR_IP) {    /* Keep IP bit.  */
                env->ttmr = (rb & ~TTMR_IP) | ip;
            } else {    /* Clear IP bit.  */
                env->ttmr = rb & ~TTMR_IP;
                cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
            }
            cpu_openrisc_timer_update(cpu);
            qemu_mutex_unlock_iothread();
        }
        break;

    case TO_SPR(10, 1): /* TTCR */
        qemu_mutex_lock_iothread();
        cpu_openrisc_count_set(cpu, rb);
        cpu_openrisc_timer_update(cpu);
        qemu_mutex_unlock_iothread();
        break;
#endif

    case TO_SPR(0, 20): /* FPCSR */
        cpu_set_fpcsr(env, rb);
        break;
    }
}

target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
                           target_ulong spr)
{
#ifndef CONFIG_USER_ONLY
    MachineState *ms = MACHINE(qdev_get_machine());
    OpenRISCCPU *cpu = env_archcpu(env);
    CPUState *cs = env_cpu(env);
    int idx;
#endif

    switch (spr) {
#ifndef CONFIG_USER_ONLY
    case TO_SPR(0, 0): /* VR */
        return env->vr;

    case TO_SPR(0, 1): /* UPR */
        return env->upr;

    case TO_SPR(0, 2): /* CPUCFGR */
        return env->cpucfgr;

    case TO_SPR(0, 3): /* DMMUCFGR */
        return env->dmmucfgr;

    case TO_SPR(0, 4): /* IMMUCFGR */
        return env->immucfgr;

    case TO_SPR(0, 9): /* VR2 */
        return env->vr2;

    case TO_SPR(0, 10): /* AVR */
        return env->avr;

    case TO_SPR(0, 11): /* EVBAR */
        return env->evbar;

    case TO_SPR(0, 16): /* NPC (equals PC) */
        cpu_restore_state(cs, GETPC(), false);
        return env->pc;

    case TO_SPR(0, 17): /* SR */
        return cpu_get_sr(env);

    case TO_SPR(0, 18): /* PPC */
        cpu_restore_state(cs, GETPC(), false);
        return env->ppc;

    case TO_SPR(0, 32): /* EPCR */
        return env->epcr;

    case TO_SPR(0, 48): /* EEAR */
        return env->eear;

    case TO_SPR(0, 64): /* ESR */
        return env->esr;

    case TO_SPR(0, 128): /* COREID */
        return cpu->parent_obj.cpu_index;

    case TO_SPR(0, 129): /* NUMCORES */
        return ms->smp.max_cpus;

    case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
        idx = (spr - 1024);
        return env->shadow_gpr[idx / 32][idx % 32];

    case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        return env->tlb.dtlb[idx].mr;

    case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        return env->tlb.dtlb[idx].tr;

    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;

    case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        return env->tlb.itlb[idx].mr;

    case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        return env->tlb.itlb[idx].tr;

    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;

    case TO_SPR(5, 1):  /* MACLO */
        return (uint32_t)env->mac;
        break;
    case TO_SPR(5, 2):  /* MACHI */
        return env->mac >> 32;
        break;

    case TO_SPR(8, 0):  /* PMR */
        return env->pmr;

    case TO_SPR(9, 0):  /* PICMR */
        return env->picmr;

    case TO_SPR(9, 2):  /* PICSR */
        return env->picsr;

    case TO_SPR(10, 0): /* TTMR */
        return env->ttmr;

    case TO_SPR(10, 1): /* TTCR */
        qemu_mutex_lock_iothread();
        cpu_openrisc_count_update(cpu);
        qemu_mutex_unlock_iothread();
        return cpu_openrisc_count_get(cpu);
#endif

    case TO_SPR(0, 20): /* FPCSR */
        return env->fpcsr;
    }

    /* for rd is passed in, if rd unchanged, just keep it back.  */
    return rd;
}
Commit	Line	Data
4dd044c6 JL	1	/*
	2	* OpenRISC system instructions helper routines
	3	*
	4	* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
	5	* Zhizhou Zhang <etouzh@gmail.com>
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
779fc6ad	10	* version 2.1 of the License, or (at your option) any later version.
4dd044c6 JL	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
ed2decc6	21	#include "qemu/osdep.h"
4dd044c6	22	#include "cpu.h"
63c91552	23	#include "exec/exec-all.h"
2ef6175a	24	#include "exec/helper-proto.h"
f4d1414a	25	#include "exception.h"
5cc8767d LX	26	#ifndef CONFIG_USER_ONLY
	27	#include "hw/boards.h"
	28	#endif
4dd044c6 JL	29
	30	#define TO_SPR(group, number) (((group) << 11) + (number))
	31
c28fa81f	32	void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
4dd044c6 JL	33	{
4dd044c6 JL	34	#ifndef CONFIG_USER_ONLY
5ee2b02e RH	35	OpenRISCCPU *cpu = env_archcpu(env);
5ee2b02e RH	36	CPUState *cs = env_cpu(env);
fffde669	37	target_ulong mr;
24c32852	38	int idx;
a465772e	39	#endif
4dd044c6 JL	40
4dd044c6 JL	41	switch (spr) {
a465772e	42	#ifndef CONFIG_USER_ONLY
356a2db3 TA	43	case TO_SPR(0, 11): /* EVBAR */
	44	env->evbar = rb;
	45	break;
	46
4dd044c6	47	case TO_SPR(0, 16): /* NPC */
afd46fca	48	cpu_restore_state(cs, GETPC(), true);
24c32852 RH	49	/* ??? Mirror or1ksim in not trashing delayed branch state
	50	when "jumping" to the current instruction. */
	51	if (env->pc != rb) {
	52	env->pc = rb;
a01deb36	53	env->dflag = 0;
24c32852	54	}
5813c5c7	55	cpu_loop_exit(cs);
4dd044c6 JL	56	break;
	57
	58	case TO_SPR(0, 17): /* SR */
84775c43	59	cpu_set_sr(env, rb);
4dd044c6 JL	60	break;
4dd044c6 JL	61
4dd044c6 JL	62	case TO_SPR(0, 32): /* EPCR */
	63	env->epcr = rb;
	64	break;
	65
	66	case TO_SPR(0, 48): /* EEAR */
	67	env->eear = rb;
	68	break;
	69
	70	case TO_SPR(0, 64): /* ESR */
	71	env->esr = rb;
	72	break;
d89e71e8 SH	73
	74	case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
	75	idx = (spr - 1024);
	76	env->shadow_gpr[idx / 32][idx % 32] = rb;
c3513c83	77	break;
d89e71e8	78
56c3a141	79	case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
4dd044c6	80	idx = spr - TO_SPR(1, 512);
fffde669 RH	81	mr = env->tlb.dtlb[idx].mr;
	82	if (mr & 1) {
	83	tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
	84	}
	85	if (rb & 1) {
	86	tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
4dd044c6	87	}
2acaa233	88	env->tlb.dtlb[idx].mr = rb;
4dd044c6	89	break;
56c3a141	90	case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
4dd044c6	91	idx = spr - TO_SPR(1, 640);
2acaa233	92	env->tlb.dtlb[idx].tr = rb;
4dd044c6 JL	93	break;
	94	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	95	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	96	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	97	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	98	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	99	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	100	break;
fffde669	101
56c3a141	102	case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
4dd044c6	103	idx = spr - TO_SPR(2, 512);
fffde669 RH	104	mr = env->tlb.itlb[idx].mr;
	105	if (mr & 1) {
	106	tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
	107	}
	108	if (rb & 1) {
	109	tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
4dd044c6	110	}
2acaa233	111	env->tlb.itlb[idx].mr = rb;
4dd044c6	112	break;
56c3a141	113	case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
4dd044c6	114	idx = spr - TO_SPR(2, 640);
2acaa233	115	env->tlb.itlb[idx].tr = rb;
4dd044c6 JL	116	break;
	117	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	118	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	119	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	120	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	121	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	122	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	123	break;
fffde669	124
6f7332ba RH	125	case TO_SPR(5, 1): /* MACLO */
	126	env->mac = deposit64(env->mac, 0, 32, rb);
	127	break;
	128	case TO_SPR(5, 2): /* MACHI */
	129	env->mac = deposit64(env->mac, 32, 32, rb);
	130	break;
f4d1414a SH	131	case TO_SPR(8, 0): /* PMR */
	132	env->pmr = rb;
	133	if (env->pmr & PMR_DME \|\| env->pmr & PMR_SME) {
afd46fca	134	cpu_restore_state(cs, GETPC(), true);
f4d1414a SH	135	env->pc += 4;
	136	cs->halted = 1;
	137	raise_exception(cpu, EXCP_HALTED);
	138	}
	139	break;
4dd044c6	140	case TO_SPR(9, 0): /* PICMR */
dfc84745	141	env->picmr = rb;
66564c31 SH	142	qemu_mutex_lock_iothread();
	143	if (env->picsr & env->picmr) {
	144	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
	145	} else {
	146	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
	147	}
	148	qemu_mutex_unlock_iothread();
4dd044c6 JL	149	break;
	150	case TO_SPR(9, 2): /* PICSR */
	151	env->picsr &= ~rb;
	152	break;
	153	case TO_SPR(10, 0): /* TTMR */
	154	{
6a0fc96a	155	qemu_mutex_lock_iothread();
d5155217 SM	156	if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
	157	switch (rb & TTMR_M) {
	158	case TIMER_NONE:
	159	cpu_openrisc_count_stop(cpu);
	160	break;
	161	case TIMER_INTR:
	162	case TIMER_SHOT:
	163	case TIMER_CONT:
	164	cpu_openrisc_count_start(cpu);
	165	break;
	166	default:
	167	break;
	168	}
	169	}
	170
4dd044c6 JL	171	int ip = env->ttmr & TTMR_IP;
	172
	173	if (rb & TTMR_IP) { /* Keep IP bit. */
d5155217	174	env->ttmr = (rb & ~TTMR_IP) \| ip;
4dd044c6 JL	175	} else { /* Clear IP bit. */
4dd044c6 JL	176	env->ttmr = rb & ~TTMR_IP;
259186a7	177	cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
4dd044c6	178	}
d5155217	179	cpu_openrisc_timer_update(cpu);
6a0fc96a	180	qemu_mutex_unlock_iothread();
4dd044c6 JL	181	}
	182	break;
	183
	184	case TO_SPR(10, 1): /* TTCR */
6a0fc96a	185	qemu_mutex_lock_iothread();
6b4bbd6a	186	cpu_openrisc_count_set(cpu, rb);
d5155217	187	cpu_openrisc_timer_update(cpu);
6a0fc96a	188	qemu_mutex_unlock_iothread();
4dd044c6	189	break;
a465772e RH	190	#endif
	191
	192	case TO_SPR(0, 20): /* FPCSR */
	193	cpu_set_fpcsr(env, rb);
4dd044c6 JL	194	break;
4dd044c6 JL	195	}
4dd044c6 JL	196	}
4dd044c6 JL	197
c28fa81f RH	198	target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
c28fa81f RH	199	target_ulong spr)
4dd044c6 JL	200	{
4dd044c6 JL	201	#ifndef CONFIG_USER_ONLY
5cc8767d	202	MachineState *ms = MACHINE(qdev_get_machine());
5ee2b02e RH	203	OpenRISCCPU *cpu = env_archcpu(env);
5ee2b02e RH	204	CPUState *cs = env_cpu(env);
4dd044c6	205	int idx;
a465772e	206	#endif
4dd044c6	207
4dd044c6	208	switch (spr) {
a465772e	209	#ifndef CONFIG_USER_ONLY
4dd044c6	210	case TO_SPR(0, 0): /* VR */
b72e3ff6	211	return env->vr;
4dd044c6 JL	212
4dd044c6 JL	213	case TO_SPR(0, 1): /* UPR */
c7efab4f	214	return env->upr;
4dd044c6 JL	215
	216	case TO_SPR(0, 2): /* CPUCFGR */
	217	return env->cpucfgr;
	218
	219	case TO_SPR(0, 3): /* DMMUCFGR */
c7efab4f	220	return env->dmmucfgr;
4dd044c6 JL	221
	222	case TO_SPR(0, 4): /* IMMUCFGR */
	223	return env->immucfgr;
	224
8bebf7d1 RH	225	case TO_SPR(0, 9): /* VR2 */
	226	return env->vr2;
	227
	228	case TO_SPR(0, 10): /* AVR */
	229	return env->avr;
	230
356a2db3 TA	231	case TO_SPR(0, 11): /* EVBAR */
	232	return env->evbar;
	233
24c32852	234	case TO_SPR(0, 16): /* NPC (equals PC) */
afd46fca	235	cpu_restore_state(cs, GETPC(), false);
24c32852	236	return env->pc;
4dd044c6 JL	237
4dd044c6 JL	238	case TO_SPR(0, 17): /* SR */
84775c43	239	return cpu_get_sr(env);
4dd044c6 JL	240
4dd044c6 JL	241	case TO_SPR(0, 18): /* PPC */
afd46fca	242	cpu_restore_state(cs, GETPC(), false);
4dd044c6 JL	243	return env->ppc;
	244
	245	case TO_SPR(0, 32): /* EPCR */
	246	return env->epcr;
	247
	248	case TO_SPR(0, 48): /* EEAR */
	249	return env->eear;
	250
	251	case TO_SPR(0, 64): /* ESR */
	252	return env->esr;
	253
ef3f5b9e	254	case TO_SPR(0, 128): /* COREID */
8c949951	255	return cpu->parent_obj.cpu_index;
ef3f5b9e SH	256
ef3f5b9e SH	257	case TO_SPR(0, 129): /* NUMCORES */
5cc8767d	258	return ms->smp.max_cpus;
ef3f5b9e	259
d89e71e8 SH	260	case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
	261	idx = (spr - 1024);
	262	return env->shadow_gpr[idx / 32][idx % 32];
	263
56c3a141	264	case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
4dd044c6	265	idx = spr - TO_SPR(1, 512);
2acaa233	266	return env->tlb.dtlb[idx].mr;
4dd044c6	267
56c3a141	268	case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
4dd044c6	269	idx = spr - TO_SPR(1, 640);
2acaa233	270	return env->tlb.dtlb[idx].tr;
4dd044c6 JL	271
	272	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	273	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	274	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	275	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	276	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	277	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	278	break;
	279
56c3a141	280	case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
4dd044c6	281	idx = spr - TO_SPR(2, 512);
2acaa233	282	return env->tlb.itlb[idx].mr;
4dd044c6	283
56c3a141	284	case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
4dd044c6	285	idx = spr - TO_SPR(2, 640);
2acaa233	286	return env->tlb.itlb[idx].tr;
4dd044c6 JL	287
	288	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	289	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	290	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	291	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	292	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
	293	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
	294	break;
	295
6f7332ba RH	296	case TO_SPR(5, 1): /* MACLO */
	297	return (uint32_t)env->mac;
	298	break;
	299	case TO_SPR(5, 2): /* MACHI */
	300	return env->mac >> 32;
	301	break;
	302
f4d1414a SH	303	case TO_SPR(8, 0): /* PMR */
	304	return env->pmr;
	305
4dd044c6 JL	306	case TO_SPR(9, 0): /* PICMR */
	307	return env->picmr;
	308
	309	case TO_SPR(9, 2): /* PICSR */
	310	return env->picsr;
	311
	312	case TO_SPR(10, 0): /* TTMR */
	313	return env->ttmr;
	314
	315	case TO_SPR(10, 1): /* TTCR */
6a0fc96a	316	qemu_mutex_lock_iothread();
4dd044c6	317	cpu_openrisc_count_update(cpu);
6a0fc96a	318	qemu_mutex_unlock_iothread();
6b4bbd6a	319	return cpu_openrisc_count_get(cpu);
a465772e	320	#endif
4dd044c6	321
a465772e RH	322	case TO_SPR(0, 20): /* FPCSR */
a465772e RH	323	return env->fpcsr;
4dd044c6	324	}
4dd044c6	325
4dd044c6 JL	326	/* for rd is passed in, if rd unchanged, just keep it back. */
	327	return rd;
	328	}