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e67db06e JL |
1 | /* |
2 | * OpenRISC translation | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Feng Gao <gf91597@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
779fc6ad | 10 | * version 2.1 of the License, or (at your option) any later version. |
e67db06e JL |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
e67db06e | 22 | #include "cpu.h" |
022c62cb | 23 | #include "exec/exec-all.h" |
76cad711 | 24 | #include "disas/disas.h" |
e67db06e | 25 | #include "tcg-op.h" |
1de7afc9 | 26 | #include "qemu/log.h" |
1de7afc9 | 27 | #include "qemu/bitops.h" |
90c84c56 | 28 | #include "qemu/qemu-print.h" |
f08b6170 | 29 | #include "exec/cpu_ldst.h" |
77fc6f5e | 30 | #include "exec/translator.h" |
bbe418f2 | 31 | |
2ef6175a RH |
32 | #include "exec/helper-proto.h" |
33 | #include "exec/helper-gen.h" | |
7de9729f | 34 | #include "exec/gen-icount.h" |
e67db06e | 35 | |
a7e30d84 | 36 | #include "trace-tcg.h" |
508127e2 | 37 | #include "exec/log.h" |
a7e30d84 | 38 | |
77fc6f5e | 39 | /* is_jmp field values */ |
64e46c95 | 40 | #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ |
8000ba56 | 41 | #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ |
77fc6f5e | 42 | |
bbe418f2 | 43 | typedef struct DisasContext { |
1ffa4bce | 44 | DisasContextBase base; |
bbe418f2 | 45 | uint32_t mem_idx; |
a01deb36 | 46 | uint32_t tb_flags; |
bbe418f2 | 47 | uint32_t delayed_branch; |
fe636d37 | 48 | uint32_t cpucfgr; |
2b13b4b9 | 49 | uint32_t avr; |
8000ba56 RH |
50 | |
51 | /* If not -1, jmp_pc contains this value and so is a direct jump. */ | |
52 | target_ulong jmp_pc_imm; | |
d29f4368 RH |
53 | |
54 | /* The temporary corresponding to register 0 for this compilation. */ | |
55 | TCGv R0; | |
bbe418f2 JL |
56 | } DisasContext; |
57 | ||
2ba65417 RH |
58 | static inline bool is_user(DisasContext *dc) |
59 | { | |
60 | #ifdef CONFIG_USER_ONLY | |
61 | return true; | |
62 | #else | |
b9bed1b9 | 63 | return !(dc->tb_flags & TB_FLAGS_SM); |
2ba65417 RH |
64 | #endif |
65 | } | |
66 | ||
7de9729f RH |
67 | /* Include the auto-generated decoder. */ |
68 | #include "decode.inc.c" | |
69 | ||
bbe418f2 | 70 | static TCGv cpu_sr; |
8bba7619 | 71 | static TCGv cpu_regs[32]; |
bbe418f2 JL |
72 | static TCGv cpu_pc; |
73 | static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ | |
bbe418f2 | 74 | static TCGv cpu_ppc; |
84775c43 | 75 | static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ |
97458071 RH |
76 | static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ |
77 | static TCGv cpu_sr_ov; /* signed overflow */ | |
930c3d00 RH |
78 | static TCGv cpu_lock_addr; |
79 | static TCGv cpu_lock_value; | |
bbe418f2 | 80 | static TCGv_i32 fpcsr; |
6f7332ba | 81 | static TCGv_i64 cpu_mac; /* MACHI:MACLO */ |
a01deb36 | 82 | static TCGv_i32 cpu_dflag; |
bbe418f2 | 83 | |
e67db06e JL |
84 | void openrisc_translate_init(void) |
85 | { | |
bbe418f2 JL |
86 | static const char * const regnames[] = { |
87 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
88 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
89 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
90 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
91 | }; | |
92 | int i; | |
93 | ||
e1ccc054 | 94 | cpu_sr = tcg_global_mem_new(cpu_env, |
bbe418f2 | 95 | offsetof(CPUOpenRISCState, sr), "sr"); |
a01deb36 RH |
96 | cpu_dflag = tcg_global_mem_new_i32(cpu_env, |
97 | offsetof(CPUOpenRISCState, dflag), | |
98 | "dflag"); | |
e1ccc054 | 99 | cpu_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 100 | offsetof(CPUOpenRISCState, pc), "pc"); |
e1ccc054 | 101 | cpu_ppc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 102 | offsetof(CPUOpenRISCState, ppc), "ppc"); |
e1ccc054 | 103 | jmp_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 104 | offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); |
84775c43 RH |
105 | cpu_sr_f = tcg_global_mem_new(cpu_env, |
106 | offsetof(CPUOpenRISCState, sr_f), "sr_f"); | |
97458071 RH |
107 | cpu_sr_cy = tcg_global_mem_new(cpu_env, |
108 | offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); | |
109 | cpu_sr_ov = tcg_global_mem_new(cpu_env, | |
110 | offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); | |
930c3d00 RH |
111 | cpu_lock_addr = tcg_global_mem_new(cpu_env, |
112 | offsetof(CPUOpenRISCState, lock_addr), | |
113 | "lock_addr"); | |
114 | cpu_lock_value = tcg_global_mem_new(cpu_env, | |
115 | offsetof(CPUOpenRISCState, lock_value), | |
116 | "lock_value"); | |
e1ccc054 | 117 | fpcsr = tcg_global_mem_new_i32(cpu_env, |
bbe418f2 JL |
118 | offsetof(CPUOpenRISCState, fpcsr), |
119 | "fpcsr"); | |
6f7332ba RH |
120 | cpu_mac = tcg_global_mem_new_i64(cpu_env, |
121 | offsetof(CPUOpenRISCState, mac), | |
122 | "mac"); | |
bbe418f2 | 123 | for (i = 0; i < 32; i++) { |
8bba7619 RH |
124 | cpu_regs[i] = tcg_global_mem_new(cpu_env, |
125 | offsetof(CPUOpenRISCState, | |
126 | shadow_gpr[0][i]), | |
127 | regnames[i]); | |
bbe418f2 | 128 | } |
bbe418f2 JL |
129 | } |
130 | ||
bbe418f2 JL |
131 | static void gen_exception(DisasContext *dc, unsigned int excp) |
132 | { | |
133 | TCGv_i32 tmp = tcg_const_i32(excp); | |
134 | gen_helper_exception(cpu_env, tmp); | |
135 | tcg_temp_free_i32(tmp); | |
136 | } | |
137 | ||
138 | static void gen_illegal_exception(DisasContext *dc) | |
139 | { | |
1ffa4bce | 140 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); |
bbe418f2 | 141 | gen_exception(dc, EXCP_ILLEGAL); |
1ffa4bce | 142 | dc->base.is_jmp = DISAS_NORETURN; |
bbe418f2 JL |
143 | } |
144 | ||
2b13b4b9 RH |
145 | static bool check_v1_3(DisasContext *dc) |
146 | { | |
147 | return dc->avr >= 0x01030000; | |
148 | } | |
149 | ||
fe636d37 | 150 | static bool check_of32s(DisasContext *dc) |
bbe418f2 | 151 | { |
fe636d37 | 152 | return dc->cpucfgr & CPUCFGR_OF32S; |
bbe418f2 | 153 | } |
bbe418f2 | 154 | |
62f2b038 RH |
155 | static bool check_of64a32s(DisasContext *dc) |
156 | { | |
157 | return dc->cpucfgr & CPUCFGR_OF64A32S; | |
158 | } | |
159 | ||
8bba7619 RH |
160 | static TCGv cpu_R(DisasContext *dc, int reg) |
161 | { | |
d29f4368 RH |
162 | if (reg == 0) { |
163 | return dc->R0; | |
164 | } else { | |
165 | return cpu_regs[reg]; | |
166 | } | |
8bba7619 RH |
167 | } |
168 | ||
cdd0f459 RH |
169 | /* |
170 | * We're about to write to REG. On the off-chance that the user is | |
171 | * writing to R0, re-instate the architectural register. | |
172 | */ | |
173 | static void check_r0_write(DisasContext *dc, int reg) | |
174 | { | |
175 | if (unlikely(reg == 0)) { | |
d29f4368 | 176 | dc->R0 = cpu_regs[0]; |
cdd0f459 RH |
177 | } |
178 | } | |
6597c28d | 179 | |
97458071 | 180 | static void gen_ove_cy(DisasContext *dc) |
9ecaa27e | 181 | { |
0c53d734 | 182 | if (dc->tb_flags & SR_OVE) { |
97458071 | 183 | gen_helper_ove_cy(cpu_env); |
0c53d734 | 184 | } |
9ecaa27e RH |
185 | } |
186 | ||
97458071 | 187 | static void gen_ove_ov(DisasContext *dc) |
9ecaa27e | 188 | { |
0c53d734 | 189 | if (dc->tb_flags & SR_OVE) { |
97458071 | 190 | gen_helper_ove_ov(cpu_env); |
0c53d734 | 191 | } |
9ecaa27e RH |
192 | } |
193 | ||
97458071 | 194 | static void gen_ove_cyov(DisasContext *dc) |
9ecaa27e | 195 | { |
0c53d734 | 196 | if (dc->tb_flags & SR_OVE) { |
97458071 | 197 | gen_helper_ove_cyov(cpu_env); |
0c53d734 | 198 | } |
9ecaa27e RH |
199 | } |
200 | ||
201 | static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
202 | { | |
203 | TCGv t0 = tcg_const_tl(0); | |
204 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 205 | |
97458071 RH |
206 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); |
207 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 208 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 209 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
210 | tcg_temp_free(t0); |
211 | ||
212 | tcg_gen_mov_tl(dest, res); | |
213 | tcg_temp_free(res); | |
214 | ||
97458071 | 215 | gen_ove_cyov(dc); |
9ecaa27e RH |
216 | } |
217 | ||
218 | static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
219 | { | |
220 | TCGv t0 = tcg_const_tl(0); | |
221 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 222 | |
97458071 RH |
223 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); |
224 | tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); | |
225 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 226 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 227 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
228 | tcg_temp_free(t0); |
229 | ||
230 | tcg_gen_mov_tl(dest, res); | |
231 | tcg_temp_free(res); | |
232 | ||
97458071 | 233 | gen_ove_cyov(dc); |
9ecaa27e RH |
234 | } |
235 | ||
236 | static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
237 | { | |
238 | TCGv res = tcg_temp_new(); | |
9ecaa27e RH |
239 | |
240 | tcg_gen_sub_tl(res, srca, srcb); | |
97458071 RH |
241 | tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); |
242 | tcg_gen_xor_tl(cpu_sr_ov, res, srcb); | |
243 | tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); | |
244 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); | |
9ecaa27e RH |
245 | |
246 | tcg_gen_mov_tl(dest, res); | |
247 | tcg_temp_free(res); | |
248 | ||
97458071 | 249 | gen_ove_cyov(dc); |
9ecaa27e RH |
250 | } |
251 | ||
252 | static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
253 | { | |
9ecaa27e RH |
254 | TCGv t0 = tcg_temp_new(); |
255 | ||
97458071 | 256 | tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); |
9ecaa27e | 257 | tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); |
97458071 | 258 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); |
9ecaa27e RH |
259 | tcg_temp_free(t0); |
260 | ||
97458071 RH |
261 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
262 | gen_ove_ov(dc); | |
9ecaa27e RH |
263 | } |
264 | ||
265 | static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
266 | { | |
97458071 RH |
267 | tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); |
268 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); | |
9ecaa27e | 269 | |
97458071 | 270 | gen_ove_cy(dc); |
9ecaa27e RH |
271 | } |
272 | ||
273 | static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
274 | { | |
9ecaa27e RH |
275 | TCGv t0 = tcg_temp_new(); |
276 | ||
97458071 | 277 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); |
9ecaa27e RH |
278 | /* The result of divide-by-zero is undefined. |
279 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 280 | tcg_gen_or_tl(t0, srcb, cpu_sr_ov); |
9ecaa27e RH |
281 | tcg_gen_div_tl(dest, srca, t0); |
282 | tcg_temp_free(t0); | |
283 | ||
97458071 RH |
284 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
285 | gen_ove_ov(dc); | |
9ecaa27e RH |
286 | } |
287 | ||
288 | static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
289 | { | |
9ecaa27e RH |
290 | TCGv t0 = tcg_temp_new(); |
291 | ||
97458071 | 292 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); |
9ecaa27e RH |
293 | /* The result of divide-by-zero is undefined. |
294 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 295 | tcg_gen_or_tl(t0, srcb, cpu_sr_cy); |
9ecaa27e RH |
296 | tcg_gen_divu_tl(dest, srca, t0); |
297 | tcg_temp_free(t0); | |
298 | ||
97458071 | 299 | gen_ove_cy(dc); |
9ecaa27e | 300 | } |
da1d7759 | 301 | |
cc5de49e RH |
302 | static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) |
303 | { | |
304 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
305 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
306 | ||
307 | tcg_gen_ext_tl_i64(t1, srca); | |
308 | tcg_gen_ext_tl_i64(t2, srcb); | |
309 | if (TARGET_LONG_BITS == 32) { | |
310 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
311 | tcg_gen_movi_tl(cpu_sr_ov, 0); | |
312 | } else { | |
313 | TCGv_i64 high = tcg_temp_new_i64(); | |
314 | ||
315 | tcg_gen_muls2_i64(cpu_mac, high, t1, t2); | |
316 | tcg_gen_sari_i64(t1, cpu_mac, 63); | |
317 | tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high); | |
318 | tcg_temp_free_i64(high); | |
319 | tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); | |
320 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); | |
321 | ||
322 | gen_ove_ov(dc); | |
323 | } | |
324 | tcg_temp_free_i64(t1); | |
325 | tcg_temp_free_i64(t2); | |
326 | } | |
327 | ||
328 | static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) | |
329 | { | |
330 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
331 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
332 | ||
333 | tcg_gen_extu_tl_i64(t1, srca); | |
334 | tcg_gen_extu_tl_i64(t2, srcb); | |
335 | if (TARGET_LONG_BITS == 32) { | |
336 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
337 | tcg_gen_movi_tl(cpu_sr_cy, 0); | |
338 | } else { | |
339 | TCGv_i64 high = tcg_temp_new_i64(); | |
340 | ||
341 | tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); | |
342 | tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); | |
343 | tcg_gen_trunc_i64_tl(cpu_sr_cy, high); | |
344 | tcg_temp_free_i64(high); | |
345 | ||
346 | gen_ove_cy(dc); | |
347 | } | |
348 | tcg_temp_free_i64(t1); | |
349 | tcg_temp_free_i64(t2); | |
350 | } | |
351 | ||
6f7332ba RH |
352 | static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) |
353 | { | |
354 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
355 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
356 | ||
357 | tcg_gen_ext_tl_i64(t1, srca); | |
358 | tcg_gen_ext_tl_i64(t2, srcb); | |
359 | tcg_gen_mul_i64(t1, t1, t2); | |
360 | ||
361 | /* Note that overflow is only computed during addition stage. */ | |
362 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
363 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
364 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
365 | tcg_gen_andc_i64(t1, t1, t2); | |
366 | tcg_temp_free_i64(t2); | |
367 | ||
368 | #if TARGET_LONG_BITS == 32 | |
369 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
370 | #else | |
371 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
372 | #endif | |
373 | tcg_temp_free_i64(t1); | |
374 | ||
375 | gen_ove_ov(dc); | |
376 | } | |
377 | ||
cc5de49e RH |
378 | static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb) |
379 | { | |
380 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
381 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
382 | ||
383 | tcg_gen_extu_tl_i64(t1, srca); | |
384 | tcg_gen_extu_tl_i64(t2, srcb); | |
385 | tcg_gen_mul_i64(t1, t1, t2); | |
386 | tcg_temp_free_i64(t2); | |
387 | ||
388 | /* Note that overflow is only computed during addition stage. */ | |
389 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
390 | tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); | |
391 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); | |
392 | tcg_temp_free_i64(t1); | |
393 | ||
394 | gen_ove_cy(dc); | |
395 | } | |
396 | ||
6f7332ba RH |
397 | static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb) |
398 | { | |
399 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
400 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
401 | ||
402 | tcg_gen_ext_tl_i64(t1, srca); | |
403 | tcg_gen_ext_tl_i64(t2, srcb); | |
404 | tcg_gen_mul_i64(t1, t1, t2); | |
405 | ||
406 | /* Note that overflow is only computed during subtraction stage. */ | |
407 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
408 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
409 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
410 | tcg_gen_and_i64(t1, t1, t2); | |
411 | tcg_temp_free_i64(t2); | |
412 | ||
413 | #if TARGET_LONG_BITS == 32 | |
414 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
415 | #else | |
416 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
417 | #endif | |
418 | tcg_temp_free_i64(t1); | |
419 | ||
420 | gen_ove_ov(dc); | |
421 | } | |
422 | ||
cc5de49e RH |
423 | static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) |
424 | { | |
425 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
426 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
427 | ||
428 | tcg_gen_extu_tl_i64(t1, srca); | |
429 | tcg_gen_extu_tl_i64(t2, srcb); | |
430 | tcg_gen_mul_i64(t1, t1, t2); | |
431 | ||
432 | /* Note that overflow is only computed during subtraction stage. */ | |
433 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); | |
434 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
435 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); | |
436 | tcg_temp_free_i64(t2); | |
437 | tcg_temp_free_i64(t1); | |
438 | ||
439 | gen_ove_cy(dc); | |
440 | } | |
441 | ||
3a7be554 | 442 | static bool trans_l_add(DisasContext *dc, arg_dab *a) |
bbe418f2 | 443 | { |
cdd0f459 | 444 | check_r0_write(dc, a->d); |
8bba7619 | 445 | gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
446 | return true; |
447 | } | |
bbe418f2 | 448 | |
3a7be554 | 449 | static bool trans_l_addc(DisasContext *dc, arg_dab *a) |
6ad216ab | 450 | { |
cdd0f459 | 451 | check_r0_write(dc, a->d); |
8bba7619 | 452 | gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
453 | return true; |
454 | } | |
cf2ae442 | 455 | |
3a7be554 | 456 | static bool trans_l_sub(DisasContext *dc, arg_dab *a) |
6ad216ab | 457 | { |
cdd0f459 | 458 | check_r0_write(dc, a->d); |
8bba7619 | 459 | gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
460 | return true; |
461 | } | |
bbe418f2 | 462 | |
3a7be554 | 463 | static bool trans_l_and(DisasContext *dc, arg_dab *a) |
6ad216ab | 464 | { |
cdd0f459 | 465 | check_r0_write(dc, a->d); |
8bba7619 | 466 | tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
467 | return true; |
468 | } | |
469 | ||
3a7be554 | 470 | static bool trans_l_or(DisasContext *dc, arg_dab *a) |
6ad216ab | 471 | { |
cdd0f459 | 472 | check_r0_write(dc, a->d); |
8bba7619 | 473 | tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
474 | return true; |
475 | } | |
476 | ||
3a7be554 | 477 | static bool trans_l_xor(DisasContext *dc, arg_dab *a) |
6ad216ab | 478 | { |
cdd0f459 | 479 | check_r0_write(dc, a->d); |
8bba7619 | 480 | tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
481 | return true; |
482 | } | |
bbe418f2 | 483 | |
3a7be554 | 484 | static bool trans_l_sll(DisasContext *dc, arg_dab *a) |
6ad216ab | 485 | { |
cdd0f459 | 486 | check_r0_write(dc, a->d); |
8bba7619 | 487 | tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
488 | return true; |
489 | } | |
bbe418f2 | 490 | |
3a7be554 | 491 | static bool trans_l_srl(DisasContext *dc, arg_dab *a) |
6ad216ab | 492 | { |
cdd0f459 | 493 | check_r0_write(dc, a->d); |
8bba7619 | 494 | tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
495 | return true; |
496 | } | |
cc5de49e | 497 | |
3a7be554 | 498 | static bool trans_l_sra(DisasContext *dc, arg_dab *a) |
6ad216ab | 499 | { |
cdd0f459 | 500 | check_r0_write(dc, a->d); |
8bba7619 | 501 | tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
502 | return true; |
503 | } | |
bbe418f2 | 504 | |
3a7be554 | 505 | static bool trans_l_ror(DisasContext *dc, arg_dab *a) |
6ad216ab | 506 | { |
cdd0f459 | 507 | check_r0_write(dc, a->d); |
8bba7619 | 508 | tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
509 | return true; |
510 | } | |
bbe418f2 | 511 | |
3a7be554 | 512 | static bool trans_l_exths(DisasContext *dc, arg_da *a) |
6ad216ab | 513 | { |
cdd0f459 | 514 | check_r0_write(dc, a->d); |
8bba7619 | 515 | tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
516 | return true; |
517 | } | |
cc5de49e | 518 | |
3a7be554 | 519 | static bool trans_l_extbs(DisasContext *dc, arg_da *a) |
6ad216ab | 520 | { |
cdd0f459 | 521 | check_r0_write(dc, a->d); |
8bba7619 | 522 | tcg_gen_ext8s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
523 | return true; |
524 | } | |
525 | ||
3a7be554 | 526 | static bool trans_l_exthz(DisasContext *dc, arg_da *a) |
6ad216ab | 527 | { |
cdd0f459 | 528 | check_r0_write(dc, a->d); |
8bba7619 | 529 | tcg_gen_ext16u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
530 | return true; |
531 | } | |
532 | ||
3a7be554 | 533 | static bool trans_l_extbz(DisasContext *dc, arg_da *a) |
6ad216ab | 534 | { |
cdd0f459 | 535 | check_r0_write(dc, a->d); |
8bba7619 | 536 | tcg_gen_ext8u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
537 | return true; |
538 | } | |
539 | ||
3a7be554 | 540 | static bool trans_l_cmov(DisasContext *dc, arg_dab *a) |
6ad216ab RH |
541 | { |
542 | TCGv zero; | |
6ad216ab | 543 | |
cdd0f459 | 544 | check_r0_write(dc, a->d); |
6ad216ab | 545 | zero = tcg_const_tl(0); |
8bba7619 RH |
546 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, zero, |
547 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
6ad216ab RH |
548 | tcg_temp_free(zero); |
549 | return true; | |
550 | } | |
551 | ||
3a7be554 | 552 | static bool trans_l_ff1(DisasContext *dc, arg_da *a) |
6ad216ab | 553 | { |
cdd0f459 | 554 | check_r0_write(dc, a->d); |
8bba7619 RH |
555 | tcg_gen_ctzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), -1); |
556 | tcg_gen_addi_tl(cpu_R(dc, a->d), cpu_R(dc, a->d), 1); | |
6ad216ab RH |
557 | return true; |
558 | } | |
559 | ||
3a7be554 | 560 | static bool trans_l_fl1(DisasContext *dc, arg_da *a) |
6ad216ab | 561 | { |
cdd0f459 | 562 | check_r0_write(dc, a->d); |
8bba7619 RH |
563 | tcg_gen_clzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS); |
564 | tcg_gen_subfi_tl(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d)); | |
6ad216ab RH |
565 | return true; |
566 | } | |
567 | ||
3a7be554 | 568 | static bool trans_l_mul(DisasContext *dc, arg_dab *a) |
6ad216ab | 569 | { |
cdd0f459 | 570 | check_r0_write(dc, a->d); |
8bba7619 | 571 | gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
572 | return true; |
573 | } | |
574 | ||
3a7be554 | 575 | static bool trans_l_mulu(DisasContext *dc, arg_dab *a) |
6ad216ab | 576 | { |
cdd0f459 | 577 | check_r0_write(dc, a->d); |
8bba7619 | 578 | gen_mulu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
579 | return true; |
580 | } | |
581 | ||
3a7be554 | 582 | static bool trans_l_div(DisasContext *dc, arg_dab *a) |
6ad216ab | 583 | { |
cdd0f459 | 584 | check_r0_write(dc, a->d); |
8bba7619 | 585 | gen_div(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
586 | return true; |
587 | } | |
588 | ||
3a7be554 | 589 | static bool trans_l_divu(DisasContext *dc, arg_dab *a) |
6ad216ab | 590 | { |
cdd0f459 | 591 | check_r0_write(dc, a->d); |
8bba7619 | 592 | gen_divu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
593 | return true; |
594 | } | |
595 | ||
3a7be554 | 596 | static bool trans_l_muld(DisasContext *dc, arg_ab *a) |
6ad216ab | 597 | { |
8bba7619 | 598 | gen_muld(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
599 | return true; |
600 | } | |
601 | ||
3a7be554 | 602 | static bool trans_l_muldu(DisasContext *dc, arg_ab *a) |
6ad216ab | 603 | { |
8bba7619 | 604 | gen_muldu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab | 605 | return true; |
bbe418f2 JL |
606 | } |
607 | ||
3a7be554 | 608 | static bool trans_l_j(DisasContext *dc, arg_l_j *a) |
136e13ae RH |
609 | { |
610 | target_ulong tmp_pc = dc->base.pc_next + a->n * 4; | |
611 | ||
136e13ae | 612 | tcg_gen_movi_tl(jmp_pc, tmp_pc); |
8000ba56 | 613 | dc->jmp_pc_imm = tmp_pc; |
136e13ae RH |
614 | dc->delayed_branch = 2; |
615 | return true; | |
616 | } | |
617 | ||
3a7be554 | 618 | static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) |
136e13ae RH |
619 | { |
620 | target_ulong tmp_pc = dc->base.pc_next + a->n * 4; | |
621 | target_ulong ret_pc = dc->base.pc_next + 8; | |
622 | ||
8bba7619 | 623 | tcg_gen_movi_tl(cpu_regs[9], ret_pc); |
136e13ae RH |
624 | /* Optimize jal being used to load the PC for PIC. */ |
625 | if (tmp_pc != ret_pc) { | |
626 | tcg_gen_movi_tl(jmp_pc, tmp_pc); | |
8000ba56 | 627 | dc->jmp_pc_imm = tmp_pc; |
136e13ae RH |
628 | dc->delayed_branch = 2; |
629 | } | |
630 | return true; | |
631 | } | |
632 | ||
633 | static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) | |
634 | { | |
635 | target_ulong tmp_pc = dc->base.pc_next + a->n * 4; | |
636 | TCGv t_next = tcg_const_tl(dc->base.pc_next + 8); | |
637 | TCGv t_true = tcg_const_tl(tmp_pc); | |
638 | TCGv t_zero = tcg_const_tl(0); | |
639 | ||
640 | tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next); | |
641 | ||
642 | tcg_temp_free(t_next); | |
643 | tcg_temp_free(t_true); | |
644 | tcg_temp_free(t_zero); | |
645 | dc->delayed_branch = 2; | |
646 | } | |
647 | ||
3a7be554 | 648 | static bool trans_l_bf(DisasContext *dc, arg_l_bf *a) |
136e13ae | 649 | { |
136e13ae RH |
650 | do_bf(dc, a, TCG_COND_NE); |
651 | return true; | |
652 | } | |
653 | ||
3a7be554 | 654 | static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a) |
136e13ae | 655 | { |
136e13ae RH |
656 | do_bf(dc, a, TCG_COND_EQ); |
657 | return true; | |
658 | } | |
659 | ||
3a7be554 | 660 | static bool trans_l_jr(DisasContext *dc, arg_l_jr *a) |
136e13ae | 661 | { |
8bba7619 | 662 | tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); |
136e13ae RH |
663 | dc->delayed_branch = 2; |
664 | return true; | |
665 | } | |
666 | ||
3a7be554 | 667 | static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a) |
136e13ae | 668 | { |
8bba7619 RH |
669 | tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); |
670 | tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8); | |
136e13ae RH |
671 | dc->delayed_branch = 2; |
672 | return true; | |
673 | } | |
674 | ||
3a7be554 | 675 | static bool trans_l_lwa(DisasContext *dc, arg_load *a) |
d80bff19 RH |
676 | { |
677 | TCGv ea; | |
678 | ||
cdd0f459 | 679 | check_r0_write(dc, a->d); |
d80bff19 | 680 | ea = tcg_temp_new(); |
8bba7619 RH |
681 | tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); |
682 | tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); | |
d80bff19 | 683 | tcg_gen_mov_tl(cpu_lock_addr, ea); |
8bba7619 | 684 | tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); |
d80bff19 RH |
685 | tcg_temp_free(ea); |
686 | return true; | |
687 | } | |
688 | ||
14776ab5 | 689 | static void do_load(DisasContext *dc, arg_load *a, MemOp mop) |
d80bff19 RH |
690 | { |
691 | TCGv ea; | |
692 | ||
cdd0f459 | 693 | check_r0_write(dc, a->d); |
d80bff19 | 694 | ea = tcg_temp_new(); |
8bba7619 RH |
695 | tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); |
696 | tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); | |
d80bff19 RH |
697 | tcg_temp_free(ea); |
698 | } | |
699 | ||
3a7be554 | 700 | static bool trans_l_lwz(DisasContext *dc, arg_load *a) |
d80bff19 | 701 | { |
d80bff19 RH |
702 | do_load(dc, a, MO_TEUL); |
703 | return true; | |
704 | } | |
705 | ||
3a7be554 | 706 | static bool trans_l_lws(DisasContext *dc, arg_load *a) |
d80bff19 | 707 | { |
d80bff19 RH |
708 | do_load(dc, a, MO_TESL); |
709 | return true; | |
710 | } | |
711 | ||
3a7be554 | 712 | static bool trans_l_lbz(DisasContext *dc, arg_load *a) |
d80bff19 | 713 | { |
d80bff19 RH |
714 | do_load(dc, a, MO_UB); |
715 | return true; | |
716 | } | |
717 | ||
3a7be554 | 718 | static bool trans_l_lbs(DisasContext *dc, arg_load *a) |
d80bff19 | 719 | { |
d80bff19 RH |
720 | do_load(dc, a, MO_SB); |
721 | return true; | |
722 | } | |
723 | ||
3a7be554 | 724 | static bool trans_l_lhz(DisasContext *dc, arg_load *a) |
d80bff19 | 725 | { |
d80bff19 RH |
726 | do_load(dc, a, MO_TEUW); |
727 | return true; | |
728 | } | |
729 | ||
3a7be554 | 730 | static bool trans_l_lhs(DisasContext *dc, arg_load *a) |
d80bff19 | 731 | { |
d80bff19 RH |
732 | do_load(dc, a, MO_TESW); |
733 | return true; | |
734 | } | |
735 | ||
3a7be554 | 736 | static bool trans_l_swa(DisasContext *dc, arg_store *a) |
d80bff19 RH |
737 | { |
738 | TCGv ea, val; | |
739 | TCGLabel *lab_fail, *lab_done; | |
740 | ||
d80bff19 | 741 | ea = tcg_temp_new(); |
8bba7619 | 742 | tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); |
d80bff19 RH |
743 | |
744 | /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned | |
8bba7619 | 745 | to cpu_regs[0]. Since l.swa is quite often immediately followed by a |
d80bff19 RH |
746 | branch, don't bother reallocating; finish the TB using the "real" R0. |
747 | This also takes care of RB input across the branch. */ | |
d29f4368 | 748 | dc->R0 = cpu_regs[0]; |
d80bff19 RH |
749 | |
750 | lab_fail = gen_new_label(); | |
751 | lab_done = gen_new_label(); | |
752 | tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); | |
753 | tcg_temp_free(ea); | |
754 | ||
755 | val = tcg_temp_new(); | |
756 | tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, | |
8bba7619 | 757 | cpu_regs[a->b], dc->mem_idx, MO_TEUL); |
d80bff19 RH |
758 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); |
759 | tcg_temp_free(val); | |
760 | ||
761 | tcg_gen_br(lab_done); | |
762 | ||
763 | gen_set_label(lab_fail); | |
764 | tcg_gen_movi_tl(cpu_sr_f, 0); | |
765 | ||
766 | gen_set_label(lab_done); | |
767 | tcg_gen_movi_tl(cpu_lock_addr, -1); | |
768 | return true; | |
769 | } | |
770 | ||
14776ab5 | 771 | static void do_store(DisasContext *dc, arg_store *a, MemOp mop) |
d80bff19 RH |
772 | { |
773 | TCGv t0 = tcg_temp_new(); | |
8bba7619 RH |
774 | tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); |
775 | tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); | |
d80bff19 RH |
776 | tcg_temp_free(t0); |
777 | } | |
778 | ||
3a7be554 | 779 | static bool trans_l_sw(DisasContext *dc, arg_store *a) |
d80bff19 | 780 | { |
d80bff19 RH |
781 | do_store(dc, a, MO_TEUL); |
782 | return true; | |
783 | } | |
784 | ||
3a7be554 | 785 | static bool trans_l_sb(DisasContext *dc, arg_store *a) |
d80bff19 | 786 | { |
d80bff19 RH |
787 | do_store(dc, a, MO_UB); |
788 | return true; | |
789 | } | |
790 | ||
3a7be554 | 791 | static bool trans_l_sh(DisasContext *dc, arg_store *a) |
d80bff19 | 792 | { |
d80bff19 RH |
793 | do_store(dc, a, MO_TEUW); |
794 | return true; | |
795 | } | |
796 | ||
3a7be554 | 797 | static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) |
bbe418f2 | 798 | { |
8816f70b RH |
799 | return true; |
800 | } | |
bbe418f2 | 801 | |
3a7be554 | 802 | static bool trans_l_addi(DisasContext *dc, arg_rri *a) |
8816f70b RH |
803 | { |
804 | TCGv t0; | |
bbe418f2 | 805 | |
cdd0f459 | 806 | check_r0_write(dc, a->d); |
8816f70b | 807 | t0 = tcg_const_tl(a->i); |
8bba7619 | 808 | gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); |
8816f70b RH |
809 | tcg_temp_free(t0); |
810 | return true; | |
811 | } | |
bbe418f2 | 812 | |
3a7be554 | 813 | static bool trans_l_addic(DisasContext *dc, arg_rri *a) |
8816f70b RH |
814 | { |
815 | TCGv t0; | |
bbe418f2 | 816 | |
cdd0f459 | 817 | check_r0_write(dc, a->d); |
8816f70b | 818 | t0 = tcg_const_tl(a->i); |
8bba7619 | 819 | gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); |
8816f70b RH |
820 | tcg_temp_free(t0); |
821 | return true; | |
822 | } | |
bbe418f2 | 823 | |
3a7be554 | 824 | static bool trans_l_muli(DisasContext *dc, arg_rri *a) |
8816f70b RH |
825 | { |
826 | TCGv t0; | |
bbe418f2 | 827 | |
cdd0f459 | 828 | check_r0_write(dc, a->d); |
8816f70b | 829 | t0 = tcg_const_tl(a->i); |
8bba7619 | 830 | gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), t0); |
8816f70b RH |
831 | tcg_temp_free(t0); |
832 | return true; | |
833 | } | |
bbe418f2 | 834 | |
3a7be554 | 835 | static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) |
8816f70b RH |
836 | { |
837 | TCGv t0; | |
bbe418f2 | 838 | |
8816f70b | 839 | t0 = tcg_const_tl(a->i); |
8bba7619 | 840 | gen_mac(dc, cpu_R(dc, a->a), t0); |
8816f70b RH |
841 | tcg_temp_free(t0); |
842 | return true; | |
843 | } | |
bbe418f2 | 844 | |
3a7be554 | 845 | static bool trans_l_andi(DisasContext *dc, arg_rrk *a) |
8816f70b | 846 | { |
cdd0f459 | 847 | check_r0_write(dc, a->d); |
8bba7619 | 848 | tcg_gen_andi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); |
8816f70b RH |
849 | return true; |
850 | } | |
bbe418f2 | 851 | |
3a7be554 | 852 | static bool trans_l_ori(DisasContext *dc, arg_rrk *a) |
8816f70b | 853 | { |
cdd0f459 | 854 | check_r0_write(dc, a->d); |
8bba7619 | 855 | tcg_gen_ori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); |
8816f70b RH |
856 | return true; |
857 | } | |
bbe418f2 | 858 | |
3a7be554 | 859 | static bool trans_l_xori(DisasContext *dc, arg_rri *a) |
8816f70b | 860 | { |
cdd0f459 | 861 | check_r0_write(dc, a->d); |
8bba7619 | 862 | tcg_gen_xori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i); |
8816f70b RH |
863 | return true; |
864 | } | |
bbe418f2 | 865 | |
3a7be554 | 866 | static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) |
8816f70b | 867 | { |
cdd0f459 | 868 | check_r0_write(dc, a->d); |
bbe418f2 | 869 | |
2ba65417 | 870 | if (is_user(dc)) { |
8816f70b RH |
871 | gen_illegal_exception(dc); |
872 | } else { | |
c28fa81f | 873 | TCGv spr = tcg_temp_new(); |
8bba7619 RH |
874 | tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); |
875 | gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); | |
c28fa81f | 876 | tcg_temp_free(spr); |
8816f70b | 877 | } |
8816f70b RH |
878 | return true; |
879 | } | |
bbe418f2 | 880 | |
3a7be554 | 881 | static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) |
8816f70b | 882 | { |
2ba65417 | 883 | if (is_user(dc)) { |
bbe418f2 | 884 | gen_illegal_exception(dc); |
8816f70b | 885 | } else { |
c28fa81f | 886 | TCGv spr; |
01ec3ec9 RH |
887 | |
888 | /* For SR, we will need to exit the TB to recognize the new | |
889 | * exception state. For NPC, in theory this counts as a branch | |
890 | * (although the SPR only exists for use by an ICE). Save all | |
891 | * of the cpu state first, allowing it to be overwritten. | |
892 | */ | |
893 | if (dc->delayed_branch) { | |
894 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
895 | tcg_gen_discard_tl(jmp_pc); | |
896 | } else { | |
897 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); | |
898 | } | |
899 | dc->base.is_jmp = DISAS_EXIT; | |
900 | ||
c28fa81f | 901 | spr = tcg_temp_new(); |
8bba7619 RH |
902 | tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); |
903 | gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); | |
c28fa81f | 904 | tcg_temp_free(spr); |
bbe418f2 | 905 | } |
8816f70b | 906 | return true; |
bbe418f2 JL |
907 | } |
908 | ||
3a7be554 | 909 | static bool trans_l_mac(DisasContext *dc, arg_ab *a) |
bbe418f2 | 910 | { |
8bba7619 | 911 | gen_mac(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 RH |
912 | return true; |
913 | } | |
bbe418f2 | 914 | |
3a7be554 | 915 | static bool trans_l_msb(DisasContext *dc, arg_ab *a) |
99d863d6 | 916 | { |
8bba7619 | 917 | gen_msb(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 RH |
918 | return true; |
919 | } | |
cc5de49e | 920 | |
3a7be554 | 921 | static bool trans_l_macu(DisasContext *dc, arg_ab *a) |
99d863d6 | 922 | { |
8bba7619 | 923 | gen_macu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 RH |
924 | return true; |
925 | } | |
cc5de49e | 926 | |
3a7be554 | 927 | static bool trans_l_msbu(DisasContext *dc, arg_ab *a) |
99d863d6 | 928 | { |
8bba7619 | 929 | gen_msbu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 | 930 | return true; |
bbe418f2 JL |
931 | } |
932 | ||
3a7be554 | 933 | static bool trans_l_slli(DisasContext *dc, arg_dal *a) |
bbe418f2 | 934 | { |
cdd0f459 | 935 | check_r0_write(dc, a->d); |
8bba7619 RH |
936 | tcg_gen_shli_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
937 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 RH |
938 | return true; |
939 | } | |
bbe418f2 | 940 | |
3a7be554 | 941 | static bool trans_l_srli(DisasContext *dc, arg_dal *a) |
e20c2592 | 942 | { |
cdd0f459 | 943 | check_r0_write(dc, a->d); |
8bba7619 RH |
944 | tcg_gen_shri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
945 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 RH |
946 | return true; |
947 | } | |
bbe418f2 | 948 | |
3a7be554 | 949 | static bool trans_l_srai(DisasContext *dc, arg_dal *a) |
e20c2592 | 950 | { |
cdd0f459 | 951 | check_r0_write(dc, a->d); |
8bba7619 RH |
952 | tcg_gen_sari_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
953 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 RH |
954 | return true; |
955 | } | |
bbe418f2 | 956 | |
3a7be554 | 957 | static bool trans_l_rori(DisasContext *dc, arg_dal *a) |
e20c2592 | 958 | { |
cdd0f459 | 959 | check_r0_write(dc, a->d); |
8bba7619 RH |
960 | tcg_gen_rotri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
961 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 | 962 | return true; |
bbe418f2 JL |
963 | } |
964 | ||
3a7be554 | 965 | static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) |
bbe418f2 | 966 | { |
cdd0f459 | 967 | check_r0_write(dc, a->d); |
8bba7619 | 968 | tcg_gen_movi_tl(cpu_R(dc, a->d), a->k << 16); |
e720a571 RH |
969 | return true; |
970 | } | |
bbe418f2 | 971 | |
3a7be554 | 972 | static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) |
e720a571 | 973 | { |
cdd0f459 | 974 | check_r0_write(dc, a->d); |
8bba7619 | 975 | tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac); |
e720a571 RH |
976 | tcg_gen_movi_i64(cpu_mac, 0); |
977 | return true; | |
bbe418f2 JL |
978 | } |
979 | ||
3a7be554 | 980 | static bool trans_l_sfeq(DisasContext *dc, arg_ab *a) |
bbe418f2 | 981 | { |
8bba7619 RH |
982 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, |
983 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
984 | return true; |
985 | } | |
bbe418f2 | 986 | |
3a7be554 | 987 | static bool trans_l_sfne(DisasContext *dc, arg_ab *a) |
fbb3e29a | 988 | { |
8bba7619 RH |
989 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, |
990 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
991 | return true; |
992 | } | |
bbe418f2 | 993 | |
3a7be554 | 994 | static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 995 | { |
8bba7619 RH |
996 | tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, |
997 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
998 | return true; |
999 | } | |
bbe418f2 | 1000 | |
3a7be554 | 1001 | static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1002 | { |
8bba7619 RH |
1003 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, |
1004 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
1005 | return true; |
1006 | } | |
bbe418f2 | 1007 | |
3a7be554 | 1008 | static bool trans_l_sfltu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1009 | { |
8bba7619 RH |
1010 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, |
1011 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
1012 | return true; |
1013 | } | |
bbe418f2 | 1014 | |
3a7be554 | 1015 | static bool trans_l_sfleu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1016 | { |
8bba7619 RH |
1017 | tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, |
1018 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
1019 | return true; |
1020 | } | |
bbe418f2 | 1021 | |
3a7be554 | 1022 | static bool trans_l_sfgts(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1023 | { |
8bba7619 RH |
1024 | tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, |
1025 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
1026 | return true; |
1027 | } | |
bbe418f2 | 1028 | |
3a7be554 | 1029 | static bool trans_l_sfges(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1030 | { |
8bba7619 RH |
1031 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, |
1032 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
1033 | return true; |
1034 | } | |
bbe418f2 | 1035 | |
3a7be554 | 1036 | static bool trans_l_sflts(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1037 | { |
8bba7619 RH |
1038 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, |
1039 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
1040 | return true; |
1041 | } | |
bbe418f2 | 1042 | |
3a7be554 | 1043 | static bool trans_l_sfles(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1044 | { |
8bba7619 RH |
1045 | tcg_gen_setcond_tl(TCG_COND_LE, |
1046 | cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a | 1047 | return true; |
bbe418f2 JL |
1048 | } |
1049 | ||
3a7be554 | 1050 | static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a) |
bbe418f2 | 1051 | { |
8bba7619 | 1052 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1053 | return true; |
1054 | } | |
bbe418f2 | 1055 | |
3a7be554 | 1056 | static bool trans_l_sfnei(DisasContext *dc, arg_ai *a) |
032de4fc | 1057 | { |
8bba7619 | 1058 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1059 | return true; |
1060 | } | |
bbe418f2 | 1061 | |
3a7be554 | 1062 | static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a) |
032de4fc | 1063 | { |
8bba7619 | 1064 | tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1065 | return true; |
1066 | } | |
bbe418f2 | 1067 | |
3a7be554 | 1068 | static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a) |
032de4fc | 1069 | { |
8bba7619 | 1070 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1071 | return true; |
1072 | } | |
bbe418f2 | 1073 | |
3a7be554 | 1074 | static bool trans_l_sfltui(DisasContext *dc, arg_ai *a) |
032de4fc | 1075 | { |
8bba7619 | 1076 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1077 | return true; |
1078 | } | |
bbe418f2 | 1079 | |
3a7be554 | 1080 | static bool trans_l_sfleui(DisasContext *dc, arg_ai *a) |
032de4fc | 1081 | { |
8bba7619 | 1082 | tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1083 | return true; |
1084 | } | |
bbe418f2 | 1085 | |
3a7be554 | 1086 | static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a) |
032de4fc | 1087 | { |
8bba7619 | 1088 | tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1089 | return true; |
1090 | } | |
bbe418f2 | 1091 | |
3a7be554 | 1092 | static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a) |
032de4fc | 1093 | { |
8bba7619 | 1094 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1095 | return true; |
1096 | } | |
bbe418f2 | 1097 | |
3a7be554 | 1098 | static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a) |
032de4fc | 1099 | { |
8bba7619 | 1100 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1101 | return true; |
1102 | } | |
bbe418f2 | 1103 | |
3a7be554 | 1104 | static bool trans_l_sflesi(DisasContext *dc, arg_ai *a) |
032de4fc | 1105 | { |
8bba7619 | 1106 | tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc | 1107 | return true; |
bbe418f2 JL |
1108 | } |
1109 | ||
3a7be554 | 1110 | static bool trans_l_sys(DisasContext *dc, arg_l_sys *a) |
bbe418f2 | 1111 | { |
7de9729f RH |
1112 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); |
1113 | gen_exception(dc, EXCP_SYSCALL); | |
1114 | dc->base.is_jmp = DISAS_NORETURN; | |
1115 | return true; | |
1116 | } | |
bbe418f2 | 1117 | |
3a7be554 | 1118 | static bool trans_l_trap(DisasContext *dc, arg_l_trap *a) |
7de9729f | 1119 | { |
7de9729f RH |
1120 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); |
1121 | gen_exception(dc, EXCP_TRAP); | |
1122 | dc->base.is_jmp = DISAS_NORETURN; | |
1123 | return true; | |
1124 | } | |
bbe418f2 | 1125 | |
3a7be554 | 1126 | static bool trans_l_msync(DisasContext *dc, arg_l_msync *a) |
7de9729f | 1127 | { |
7de9729f RH |
1128 | tcg_gen_mb(TCG_MO_ALL); |
1129 | return true; | |
1130 | } | |
bbe418f2 | 1131 | |
3a7be554 | 1132 | static bool trans_l_psync(DisasContext *dc, arg_l_psync *a) |
7de9729f | 1133 | { |
7de9729f RH |
1134 | return true; |
1135 | } | |
bbe418f2 | 1136 | |
3a7be554 | 1137 | static bool trans_l_csync(DisasContext *dc, arg_l_csync *a) |
7de9729f | 1138 | { |
7de9729f | 1139 | return true; |
bbe418f2 JL |
1140 | } |
1141 | ||
3a7be554 | 1142 | static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a) |
8816f70b | 1143 | { |
2ba65417 | 1144 | if (is_user(dc)) { |
8816f70b RH |
1145 | gen_illegal_exception(dc); |
1146 | } else { | |
1147 | gen_helper_rfe(cpu_env); | |
64e46c95 | 1148 | dc->base.is_jmp = DISAS_EXIT; |
8816f70b | 1149 | } |
8816f70b RH |
1150 | return true; |
1151 | } | |
1152 | ||
fe636d37 | 1153 | static bool do_fp2(DisasContext *dc, arg_da *a, |
6fd204a2 RH |
1154 | void (*fn)(TCGv, TCGv_env, TCGv)) |
1155 | { | |
fe636d37 RH |
1156 | if (!check_of32s(dc)) { |
1157 | return false; | |
1158 | } | |
cdd0f459 | 1159 | check_r0_write(dc, a->d); |
8bba7619 | 1160 | fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a)); |
6fd204a2 | 1161 | gen_helper_update_fpcsr(cpu_env); |
fe636d37 | 1162 | return true; |
6fd204a2 | 1163 | } |
bbe418f2 | 1164 | |
fe636d37 | 1165 | static bool do_fp3(DisasContext *dc, arg_dab *a, |
6fd204a2 RH |
1166 | void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) |
1167 | { | |
fe636d37 RH |
1168 | if (!check_of32s(dc)) { |
1169 | return false; | |
1170 | } | |
cdd0f459 | 1171 | check_r0_write(dc, a->d); |
8bba7619 | 1172 | fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6fd204a2 | 1173 | gen_helper_update_fpcsr(cpu_env); |
fe636d37 | 1174 | return true; |
6fd204a2 RH |
1175 | } |
1176 | ||
fe636d37 | 1177 | static bool do_fpcmp(DisasContext *dc, arg_ab *a, |
6fd204a2 RH |
1178 | void (*fn)(TCGv, TCGv_env, TCGv, TCGv), |
1179 | bool inv, bool swap) | |
1180 | { | |
fe636d37 RH |
1181 | if (!check_of32s(dc)) { |
1182 | return false; | |
1183 | } | |
6fd204a2 | 1184 | if (swap) { |
8bba7619 | 1185 | fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); |
6fd204a2 | 1186 | } else { |
8bba7619 | 1187 | fn(cpu_sr_f, cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6fd204a2 RH |
1188 | } |
1189 | if (inv) { | |
1190 | tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); | |
bbe418f2 | 1191 | } |
6fd204a2 | 1192 | gen_helper_update_fpcsr(cpu_env); |
fe636d37 | 1193 | return true; |
bbe418f2 JL |
1194 | } |
1195 | ||
3a7be554 | 1196 | static bool trans_lf_add_s(DisasContext *dc, arg_dab *a) |
bbe418f2 | 1197 | { |
fe636d37 | 1198 | return do_fp3(dc, a, gen_helper_float_add_s); |
6fd204a2 | 1199 | } |
bbe418f2 | 1200 | |
3a7be554 | 1201 | static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1202 | { |
fe636d37 | 1203 | return do_fp3(dc, a, gen_helper_float_sub_s); |
6fd204a2 RH |
1204 | } |
1205 | ||
3a7be554 | 1206 | static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1207 | { |
fe636d37 | 1208 | return do_fp3(dc, a, gen_helper_float_mul_s); |
6fd204a2 RH |
1209 | } |
1210 | ||
3a7be554 | 1211 | static bool trans_lf_div_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1212 | { |
fe636d37 | 1213 | return do_fp3(dc, a, gen_helper_float_div_s); |
6fd204a2 RH |
1214 | } |
1215 | ||
3a7be554 | 1216 | static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1217 | { |
fe636d37 | 1218 | return do_fp3(dc, a, gen_helper_float_rem_s); |
6fd204a2 RH |
1219 | return true; |
1220 | } | |
1221 | ||
3a7be554 | 1222 | static bool trans_lf_itof_s(DisasContext *dc, arg_da *a) |
6fd204a2 | 1223 | { |
fe636d37 | 1224 | return do_fp2(dc, a, gen_helper_itofs); |
6fd204a2 RH |
1225 | } |
1226 | ||
3a7be554 | 1227 | static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a) |
6fd204a2 | 1228 | { |
fe636d37 | 1229 | return do_fp2(dc, a, gen_helper_ftois); |
6fd204a2 | 1230 | } |
7de9729f | 1231 | |
3a7be554 | 1232 | static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1233 | { |
fe636d37 RH |
1234 | if (!check_of32s(dc)) { |
1235 | return false; | |
1236 | } | |
cdd0f459 | 1237 | check_r0_write(dc, a->d); |
8bba7619 RH |
1238 | gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), |
1239 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
6fd204a2 RH |
1240 | gen_helper_update_fpcsr(cpu_env); |
1241 | return true; | |
1242 | } | |
bbe418f2 | 1243 | |
3a7be554 | 1244 | static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1245 | { |
fe636d37 | 1246 | return do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); |
6fd204a2 RH |
1247 | } |
1248 | ||
3a7be554 | 1249 | static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1250 | { |
fe636d37 | 1251 | return do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); |
6fd204a2 RH |
1252 | } |
1253 | ||
3a7be554 | 1254 | static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1255 | { |
fe636d37 | 1256 | return do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); |
6fd204a2 RH |
1257 | } |
1258 | ||
3a7be554 | 1259 | static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1260 | { |
fe636d37 | 1261 | return do_fpcmp(dc, a, gen_helper_float_le_s, false, true); |
6fd204a2 RH |
1262 | } |
1263 | ||
3a7be554 | 1264 | static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1265 | { |
fe636d37 | 1266 | return do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); |
6fd204a2 RH |
1267 | } |
1268 | ||
3a7be554 | 1269 | static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1270 | { |
fe636d37 | 1271 | return do_fpcmp(dc, a, gen_helper_float_le_s, false, false); |
6fd204a2 RH |
1272 | } |
1273 | ||
2b13b4b9 RH |
1274 | static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a) |
1275 | { | |
1276 | if (!check_v1_3(dc)) { | |
1277 | return false; | |
1278 | } | |
1279 | return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false); | |
1280 | } | |
1281 | ||
1282 | static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a) | |
1283 | { | |
1284 | if (!check_v1_3(dc)) { | |
1285 | return false; | |
1286 | } | |
1287 | return do_fpcmp(dc, a, gen_helper_float_ult_s, false, false); | |
1288 | } | |
1289 | ||
1290 | static bool trans_lf_sfugt_s(DisasContext *dc, arg_ab *a) | |
1291 | { | |
1292 | if (!check_v1_3(dc)) { | |
1293 | return false; | |
1294 | } | |
1295 | return do_fpcmp(dc, a, gen_helper_float_ult_s, false, true); | |
1296 | } | |
1297 | ||
1298 | static bool trans_lf_sfule_s(DisasContext *dc, arg_ab *a) | |
1299 | { | |
1300 | if (!check_v1_3(dc)) { | |
1301 | return false; | |
1302 | } | |
1303 | return do_fpcmp(dc, a, gen_helper_float_ule_s, false, false); | |
1304 | } | |
1305 | ||
1306 | static bool trans_lf_sfuge_s(DisasContext *dc, arg_ab *a) | |
1307 | { | |
1308 | if (!check_v1_3(dc)) { | |
1309 | return false; | |
1310 | } | |
1311 | return do_fpcmp(dc, a, gen_helper_float_ule_s, false, true); | |
1312 | } | |
1313 | ||
1314 | static bool trans_lf_sfun_s(DisasContext *dc, arg_ab *a) | |
1315 | { | |
1316 | if (!check_v1_3(dc)) { | |
1317 | return false; | |
1318 | } | |
1319 | return do_fpcmp(dc, a, gen_helper_float_un_s, false, false); | |
1320 | } | |
1321 | ||
62f2b038 RH |
1322 | static bool check_pair(DisasContext *dc, int r, int p) |
1323 | { | |
1324 | return r + 1 + p < 32; | |
1325 | } | |
1326 | ||
1327 | static void load_pair(DisasContext *dc, TCGv_i64 t, int r, int p) | |
1328 | { | |
1329 | tcg_gen_concat_i32_i64(t, cpu_R(dc, r + 1 + p), cpu_R(dc, r)); | |
1330 | } | |
1331 | ||
1332 | static void save_pair(DisasContext *dc, TCGv_i64 t, int r, int p) | |
1333 | { | |
1334 | tcg_gen_extr_i64_i32(cpu_R(dc, r + 1 + p), cpu_R(dc, r), t); | |
1335 | } | |
1336 | ||
1337 | static bool do_dp3(DisasContext *dc, arg_dab_pair *a, | |
1338 | void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) | |
1339 | { | |
1340 | TCGv_i64 t0, t1; | |
1341 | ||
1342 | if (!check_of64a32s(dc) || | |
1343 | !check_pair(dc, a->a, a->ap) || | |
1344 | !check_pair(dc, a->b, a->bp) || | |
1345 | !check_pair(dc, a->d, a->dp)) { | |
1346 | return false; | |
1347 | } | |
1348 | check_r0_write(dc, a->d); | |
1349 | ||
1350 | t0 = tcg_temp_new_i64(); | |
1351 | t1 = tcg_temp_new_i64(); | |
1352 | load_pair(dc, t0, a->a, a->ap); | |
1353 | load_pair(dc, t1, a->b, a->bp); | |
1354 | fn(t0, cpu_env, t0, t1); | |
1355 | save_pair(dc, t0, a->d, a->dp); | |
1356 | tcg_temp_free_i64(t0); | |
1357 | tcg_temp_free_i64(t1); | |
1358 | ||
1359 | gen_helper_update_fpcsr(cpu_env); | |
1360 | return true; | |
1361 | } | |
1362 | ||
1363 | static bool do_dp2(DisasContext *dc, arg_da_pair *a, | |
1364 | void (*fn)(TCGv_i64, TCGv_env, TCGv_i64)) | |
1365 | { | |
1366 | TCGv_i64 t0; | |
1367 | ||
1368 | if (!check_of64a32s(dc) || | |
1369 | !check_pair(dc, a->a, a->ap) || | |
1370 | !check_pair(dc, a->d, a->dp)) { | |
1371 | return false; | |
1372 | } | |
1373 | check_r0_write(dc, a->d); | |
1374 | ||
1375 | t0 = tcg_temp_new_i64(); | |
1376 | load_pair(dc, t0, a->a, a->ap); | |
1377 | fn(t0, cpu_env, t0); | |
1378 | save_pair(dc, t0, a->d, a->dp); | |
1379 | tcg_temp_free_i64(t0); | |
1380 | ||
1381 | gen_helper_update_fpcsr(cpu_env); | |
1382 | return true; | |
1383 | } | |
1384 | ||
1385 | static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, | |
1386 | void (*fn)(TCGv, TCGv_env, TCGv_i64, TCGv_i64), | |
1387 | bool inv, bool swap) | |
1388 | { | |
1389 | TCGv_i64 t0, t1; | |
1390 | ||
1391 | if (!check_of64a32s(dc) || | |
1392 | !check_pair(dc, a->a, a->ap) || | |
1393 | !check_pair(dc, a->b, a->bp)) { | |
1394 | return false; | |
1395 | } | |
1396 | ||
1397 | t0 = tcg_temp_new_i64(); | |
1398 | t1 = tcg_temp_new_i64(); | |
1399 | load_pair(dc, t0, a->a, a->ap); | |
1400 | load_pair(dc, t1, a->b, a->bp); | |
1401 | if (swap) { | |
1402 | fn(cpu_sr_f, cpu_env, t1, t0); | |
1403 | } else { | |
1404 | fn(cpu_sr_f, cpu_env, t0, t1); | |
1405 | } | |
1406 | tcg_temp_free_i64(t0); | |
1407 | tcg_temp_free_i64(t1); | |
1408 | ||
1409 | if (inv) { | |
1410 | tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); | |
1411 | } | |
1412 | gen_helper_update_fpcsr(cpu_env); | |
1413 | return true; | |
1414 | } | |
1415 | ||
1416 | static bool trans_lf_add_d(DisasContext *dc, arg_dab_pair *a) | |
1417 | { | |
1418 | return do_dp3(dc, a, gen_helper_float_add_d); | |
1419 | } | |
1420 | ||
1421 | static bool trans_lf_sub_d(DisasContext *dc, arg_dab_pair *a) | |
1422 | { | |
1423 | return do_dp3(dc, a, gen_helper_float_sub_d); | |
1424 | } | |
1425 | ||
1426 | static bool trans_lf_mul_d(DisasContext *dc, arg_dab_pair *a) | |
1427 | { | |
1428 | return do_dp3(dc, a, gen_helper_float_mul_d); | |
1429 | } | |
1430 | ||
1431 | static bool trans_lf_div_d(DisasContext *dc, arg_dab_pair *a) | |
1432 | { | |
1433 | return do_dp3(dc, a, gen_helper_float_div_d); | |
1434 | } | |
1435 | ||
1436 | static bool trans_lf_rem_d(DisasContext *dc, arg_dab_pair *a) | |
1437 | { | |
1438 | return do_dp3(dc, a, gen_helper_float_rem_d); | |
1439 | } | |
1440 | ||
1441 | static bool trans_lf_itof_d(DisasContext *dc, arg_da_pair *a) | |
1442 | { | |
1443 | return do_dp2(dc, a, gen_helper_itofd); | |
1444 | } | |
1445 | ||
1446 | static bool trans_lf_ftoi_d(DisasContext *dc, arg_da_pair *a) | |
1447 | { | |
1448 | return do_dp2(dc, a, gen_helper_ftoid); | |
1449 | } | |
1450 | ||
1451 | static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a) | |
1452 | { | |
1453 | TCGv_i64 t0; | |
1454 | ||
1455 | if (!check_of64a32s(dc) || | |
1456 | !check_pair(dc, a->d, a->dp)) { | |
1457 | return false; | |
1458 | } | |
1459 | check_r0_write(dc, a->d); | |
1460 | ||
1461 | t0 = tcg_temp_new_i64(); | |
1462 | gen_helper_stod(t0, cpu_env, cpu_R(dc, a->a)); | |
1463 | save_pair(dc, t0, a->d, a->dp); | |
1464 | tcg_temp_free_i64(t0); | |
1465 | ||
1466 | gen_helper_update_fpcsr(cpu_env); | |
1467 | return true; | |
1468 | } | |
1469 | ||
1470 | static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a) | |
1471 | { | |
1472 | TCGv_i64 t0; | |
1473 | ||
1474 | if (!check_of64a32s(dc) || | |
1475 | !check_pair(dc, a->a, a->ap)) { | |
1476 | return false; | |
1477 | } | |
1478 | check_r0_write(dc, a->d); | |
1479 | ||
1480 | t0 = tcg_temp_new_i64(); | |
1481 | load_pair(dc, t0, a->a, a->ap); | |
1482 | gen_helper_dtos(cpu_R(dc, a->d), cpu_env, t0); | |
1483 | tcg_temp_free_i64(t0); | |
1484 | ||
1485 | gen_helper_update_fpcsr(cpu_env); | |
1486 | return true; | |
1487 | } | |
1488 | ||
1489 | static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a) | |
1490 | { | |
1491 | TCGv_i64 t0, t1, t2; | |
1492 | ||
1493 | if (!check_of64a32s(dc) || | |
1494 | !check_pair(dc, a->a, a->ap) || | |
1495 | !check_pair(dc, a->b, a->bp) || | |
1496 | !check_pair(dc, a->d, a->dp)) { | |
1497 | return false; | |
1498 | } | |
1499 | check_r0_write(dc, a->d); | |
1500 | ||
1501 | t0 = tcg_temp_new_i64(); | |
1502 | t1 = tcg_temp_new_i64(); | |
1503 | t2 = tcg_temp_new_i64(); | |
1504 | load_pair(dc, t0, a->d, a->dp); | |
1505 | load_pair(dc, t1, a->a, a->ap); | |
1506 | load_pair(dc, t2, a->b, a->bp); | |
1507 | gen_helper_float_madd_d(t0, cpu_env, t0, t1, t2); | |
1508 | save_pair(dc, t0, a->d, a->dp); | |
1509 | tcg_temp_free_i64(t0); | |
1510 | tcg_temp_free_i64(t1); | |
1511 | tcg_temp_free_i64(t2); | |
1512 | ||
1513 | gen_helper_update_fpcsr(cpu_env); | |
1514 | return true; | |
1515 | } | |
1516 | ||
1517 | static bool trans_lf_sfeq_d(DisasContext *dc, arg_ab_pair *a) | |
1518 | { | |
1519 | return do_dpcmp(dc, a, gen_helper_float_eq_d, false, false); | |
1520 | } | |
1521 | ||
1522 | static bool trans_lf_sfne_d(DisasContext *dc, arg_ab_pair *a) | |
1523 | { | |
1524 | return do_dpcmp(dc, a, gen_helper_float_eq_d, true, false); | |
1525 | } | |
1526 | ||
1527 | static bool trans_lf_sfgt_d(DisasContext *dc, arg_ab_pair *a) | |
1528 | { | |
1529 | return do_dpcmp(dc, a, gen_helper_float_lt_d, false, true); | |
1530 | } | |
1531 | ||
1532 | static bool trans_lf_sfge_d(DisasContext *dc, arg_ab_pair *a) | |
1533 | { | |
1534 | return do_dpcmp(dc, a, gen_helper_float_le_d, false, true); | |
1535 | } | |
1536 | ||
1537 | static bool trans_lf_sflt_d(DisasContext *dc, arg_ab_pair *a) | |
1538 | { | |
1539 | return do_dpcmp(dc, a, gen_helper_float_lt_d, false, false); | |
1540 | } | |
1541 | ||
1542 | static bool trans_lf_sfle_d(DisasContext *dc, arg_ab_pair *a) | |
1543 | { | |
1544 | return do_dpcmp(dc, a, gen_helper_float_le_d, false, false); | |
1545 | } | |
1546 | ||
2b13b4b9 RH |
1547 | static bool trans_lf_sfueq_d(DisasContext *dc, arg_ab_pair *a) |
1548 | { | |
1549 | return do_dpcmp(dc, a, gen_helper_float_ueq_d, false, false); | |
1550 | } | |
1551 | ||
1552 | static bool trans_lf_sfule_d(DisasContext *dc, arg_ab_pair *a) | |
1553 | { | |
1554 | return do_dpcmp(dc, a, gen_helper_float_ule_d, false, false); | |
1555 | } | |
1556 | ||
1557 | static bool trans_lf_sfuge_d(DisasContext *dc, arg_ab_pair *a) | |
1558 | { | |
1559 | return do_dpcmp(dc, a, gen_helper_float_ule_d, false, true); | |
1560 | } | |
1561 | ||
1562 | static bool trans_lf_sfult_d(DisasContext *dc, arg_ab_pair *a) | |
1563 | { | |
1564 | return do_dpcmp(dc, a, gen_helper_float_ult_d, false, false); | |
1565 | } | |
1566 | ||
1567 | static bool trans_lf_sfugt_d(DisasContext *dc, arg_ab_pair *a) | |
1568 | { | |
1569 | return do_dpcmp(dc, a, gen_helper_float_ult_d, false, true); | |
1570 | } | |
1571 | ||
1572 | static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_pair *a) | |
1573 | { | |
1574 | return do_dpcmp(dc, a, gen_helper_float_un_d, false, false); | |
1575 | } | |
1576 | ||
a4fd3ec3 | 1577 | static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) |
e67db06e | 1578 | { |
a4fd3ec3 | 1579 | DisasContext *dc = container_of(dcb, DisasContext, base); |
9c489ea6 | 1580 | CPUOpenRISCState *env = cs->env_ptr; |
a4fd3ec3 | 1581 | int bound; |
1ffa4bce | 1582 | |
a4fd3ec3 | 1583 | dc->mem_idx = cpu_mmu_index(env, false); |
1ffa4bce | 1584 | dc->tb_flags = dc->base.tb->flags; |
a01deb36 | 1585 | dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; |
fe636d37 | 1586 | dc->cpucfgr = env->cpucfgr; |
2b13b4b9 | 1587 | dc->avr = env->avr; |
8000ba56 RH |
1588 | dc->jmp_pc_imm = -1; |
1589 | ||
a4fd3ec3 EC |
1590 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; |
1591 | dc->base.max_insns = MIN(dc->base.max_insns, bound); | |
1592 | } | |
bbe418f2 | 1593 | |
a4fd3ec3 EC |
1594 | static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) |
1595 | { | |
1596 | DisasContext *dc = container_of(db, DisasContext, base); | |
bbe418f2 | 1597 | |
6597c28d RH |
1598 | /* Allow the TCG optimizer to see that R0 == 0, |
1599 | when it's true, which is the common case. */ | |
1600 | if (dc->tb_flags & TB_FLAGS_R0_0) { | |
d29f4368 | 1601 | dc->R0 = tcg_const_tl(0); |
6597c28d | 1602 | } else { |
d29f4368 | 1603 | dc->R0 = cpu_regs[0]; |
6597c28d | 1604 | } |
a4fd3ec3 | 1605 | } |
6597c28d | 1606 | |
a4fd3ec3 EC |
1607 | static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
1608 | { | |
1609 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
bbe418f2 | 1610 | |
a4fd3ec3 EC |
1611 | tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) |
1612 | | (dc->base.num_insns > 1 ? 2 : 0)); | |
1613 | } | |
b933066a | 1614 | |
a4fd3ec3 EC |
1615 | static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, |
1616 | const CPUBreakpoint *bp) | |
1617 | { | |
1618 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
1619 | ||
1620 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); | |
1621 | gen_exception(dc, EXCP_DEBUG); | |
1622 | dc->base.is_jmp = DISAS_NORETURN; | |
1623 | /* The address covered by the breakpoint must be included in | |
1624 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
1625 | properly cleared -- thus we increment the PC here so that | |
1626 | the logic setting tb->size below does the right thing. */ | |
1627 | dc->base.pc_next += 4; | |
1628 | return true; | |
1629 | } | |
1630 | ||
1631 | static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | |
1632 | { | |
1633 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
1634 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | |
c7b6f54b | 1635 | uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); |
a4fd3ec3 | 1636 | |
c7b6f54b RH |
1637 | if (!decode(dc, insn)) { |
1638 | gen_illegal_exception(dc); | |
1639 | } | |
a4fd3ec3 EC |
1640 | dc->base.pc_next += 4; |
1641 | ||
8000ba56 RH |
1642 | /* When exiting the delay slot normally, exit via jmp_pc. |
1643 | * For DISAS_NORETURN, we have raised an exception and already exited. | |
1644 | * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing | |
1645 | * in the manual saying this is illegal, but it surely it should. | |
1646 | * At least or1ksim overrides pcnext and ignores the branch. | |
1647 | */ | |
1648 | if (dc->delayed_branch | |
1649 | && --dc->delayed_branch == 0 | |
1650 | && dc->base.is_jmp == DISAS_NEXT) { | |
1651 | dc->base.is_jmp = DISAS_JUMP; | |
bbe418f2 | 1652 | } |
a4fd3ec3 EC |
1653 | } |
1654 | ||
1655 | static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
1656 | { | |
1657 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
8000ba56 | 1658 | target_ulong jmp_dest; |
24c32852 | 1659 | |
e0a369cf RH |
1660 | /* If we have already exited the TB, nothing following has effect. */ |
1661 | if (dc->base.is_jmp == DISAS_NORETURN) { | |
1662 | return; | |
1663 | } | |
1664 | ||
8000ba56 | 1665 | /* Adjust the delayed branch state for the next TB. */ |
a01deb36 RH |
1666 | if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { |
1667 | tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); | |
1668 | } | |
1669 | ||
8000ba56 RH |
1670 | /* For DISAS_TOO_MANY, jump to the next insn. */ |
1671 | jmp_dest = dc->base.pc_next; | |
1672 | tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); | |
1673 | ||
e0a369cf | 1674 | switch (dc->base.is_jmp) { |
8000ba56 RH |
1675 | case DISAS_JUMP: |
1676 | jmp_dest = dc->jmp_pc_imm; | |
1677 | if (jmp_dest == -1) { | |
1678 | /* The jump destination is indirect/computed; use jmp_pc. */ | |
1679 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
1680 | tcg_gen_discard_tl(jmp_pc); | |
1681 | if (unlikely(dc->base.singlestep_enabled)) { | |
1682 | gen_exception(dc, EXCP_DEBUG); | |
1683 | } else { | |
1684 | tcg_gen_lookup_and_goto_ptr(); | |
1685 | } | |
1686 | break; | |
1687 | } | |
1688 | /* The jump destination is direct; use jmp_pc_imm. | |
1689 | However, we will have stored into jmp_pc as well; | |
1690 | we know now that it wasn't needed. */ | |
1691 | tcg_gen_discard_tl(jmp_pc); | |
1692 | /* fallthru */ | |
1693 | ||
e0a369cf | 1694 | case DISAS_TOO_MANY: |
8000ba56 RH |
1695 | if (unlikely(dc->base.singlestep_enabled)) { |
1696 | tcg_gen_movi_tl(cpu_pc, jmp_dest); | |
1697 | gen_exception(dc, EXCP_DEBUG); | |
1698 | } else if ((dc->base.pc_first ^ jmp_dest) & TARGET_PAGE_MASK) { | |
1699 | tcg_gen_movi_tl(cpu_pc, jmp_dest); | |
1700 | tcg_gen_lookup_and_goto_ptr(); | |
1701 | } else { | |
1702 | tcg_gen_goto_tb(0); | |
1703 | tcg_gen_movi_tl(cpu_pc, jmp_dest); | |
1704 | tcg_gen_exit_tb(dc->base.tb, 0); | |
1705 | } | |
e0a369cf | 1706 | break; |
8000ba56 | 1707 | |
e0a369cf RH |
1708 | case DISAS_EXIT: |
1709 | if (unlikely(dc->base.singlestep_enabled)) { | |
1710 | gen_exception(dc, EXCP_DEBUG); | |
1711 | } else { | |
07ea28b4 | 1712 | tcg_gen_exit_tb(NULL, 0); |
bbe418f2 | 1713 | } |
e0a369cf RH |
1714 | break; |
1715 | default: | |
1716 | g_assert_not_reached(); | |
bbe418f2 | 1717 | } |
a4fd3ec3 | 1718 | } |
bbe418f2 | 1719 | |
a4fd3ec3 EC |
1720 | static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) |
1721 | { | |
1722 | DisasContext *s = container_of(dcbase, DisasContext, base); | |
0a7df5da | 1723 | |
a4fd3ec3 EC |
1724 | qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first)); |
1725 | log_target_disas(cs, s->base.pc_first, s->base.tb->size); | |
1726 | } | |
bbe418f2 | 1727 | |
a4fd3ec3 EC |
1728 | static const TranslatorOps openrisc_tr_ops = { |
1729 | .init_disas_context = openrisc_tr_init_disas_context, | |
1730 | .tb_start = openrisc_tr_tb_start, | |
1731 | .insn_start = openrisc_tr_insn_start, | |
1732 | .breakpoint_check = openrisc_tr_breakpoint_check, | |
1733 | .translate_insn = openrisc_tr_translate_insn, | |
1734 | .tb_stop = openrisc_tr_tb_stop, | |
1735 | .disas_log = openrisc_tr_disas_log, | |
1736 | }; | |
1737 | ||
8b86d6d2 | 1738 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
a4fd3ec3 EC |
1739 | { |
1740 | DisasContext ctx; | |
1741 | ||
8b86d6d2 | 1742 | translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns); |
e67db06e JL |
1743 | } |
1744 | ||
90c84c56 | 1745 | void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
e67db06e | 1746 | { |
878096ee AF |
1747 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
1748 | CPUOpenRISCState *env = &cpu->env; | |
e67db06e | 1749 | int i; |
878096ee | 1750 | |
90c84c56 | 1751 | qemu_fprintf(f, "PC=%08x\n", env->pc); |
e67db06e | 1752 | for (i = 0; i < 32; ++i) { |
90c84c56 MA |
1753 | qemu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i), |
1754 | (i % 4) == 3 ? '\n' : ' '); | |
e67db06e JL |
1755 | } |
1756 | } | |
1757 | ||
1758 | void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, | |
bad729e2 | 1759 | target_ulong *data) |
e67db06e | 1760 | { |
bad729e2 | 1761 | env->pc = data[0]; |
a01deb36 RH |
1762 | env->dflag = data[1] & 1; |
1763 | if (data[1] & 2) { | |
24c32852 RH |
1764 | env->ppc = env->pc - 4; |
1765 | } | |
e67db06e | 1766 | } |