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e67db06e JL |
1 | /* |
2 | * OpenRISC translation | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Feng Gao <gf91597@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
e67db06e | 22 | #include "cpu.h" |
022c62cb | 23 | #include "exec/exec-all.h" |
76cad711 | 24 | #include "disas/disas.h" |
e67db06e JL |
25 | #include "tcg-op.h" |
26 | #include "qemu-common.h" | |
1de7afc9 | 27 | #include "qemu/log.h" |
1de7afc9 | 28 | #include "qemu/bitops.h" |
f08b6170 | 29 | #include "exec/cpu_ldst.h" |
bbe418f2 | 30 | |
2ef6175a RH |
31 | #include "exec/helper-proto.h" |
32 | #include "exec/helper-gen.h" | |
e67db06e | 33 | |
a7e30d84 | 34 | #include "trace-tcg.h" |
508127e2 | 35 | #include "exec/log.h" |
a7e30d84 | 36 | |
111ece51 RH |
37 | #define LOG_DIS(str, ...) \ |
38 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) | |
e67db06e | 39 | |
bbe418f2 JL |
40 | typedef struct DisasContext { |
41 | TranslationBlock *tb; | |
42 | target_ulong pc, ppc, npc; | |
43 | uint32_t tb_flags, synced_flags, flags; | |
44 | uint32_t is_jmp; | |
45 | uint32_t mem_idx; | |
46 | int singlestep_enabled; | |
47 | uint32_t delayed_branch; | |
48 | } DisasContext; | |
49 | ||
1bcea73e | 50 | static TCGv_env cpu_env; |
bbe418f2 JL |
51 | static TCGv cpu_sr; |
52 | static TCGv cpu_R[32]; | |
53 | static TCGv cpu_pc; | |
54 | static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ | |
55 | static TCGv cpu_npc; | |
56 | static TCGv cpu_ppc; | |
84775c43 | 57 | static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ |
97458071 RH |
58 | static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ |
59 | static TCGv cpu_sr_ov; /* signed overflow */ | |
930c3d00 RH |
60 | static TCGv cpu_lock_addr; |
61 | static TCGv cpu_lock_value; | |
bbe418f2 JL |
62 | static TCGv_i32 fpcsr; |
63 | static TCGv machi, maclo; | |
64 | static TCGv fpmaddhi, fpmaddlo; | |
65 | static TCGv_i32 env_flags; | |
022c62cb | 66 | #include "exec/gen-icount.h" |
bbe418f2 | 67 | |
e67db06e JL |
68 | void openrisc_translate_init(void) |
69 | { | |
bbe418f2 JL |
70 | static const char * const regnames[] = { |
71 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
72 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
73 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
74 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
75 | }; | |
76 | int i; | |
77 | ||
78 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
7c255043 | 79 | tcg_ctx.tcg_env = cpu_env; |
e1ccc054 | 80 | cpu_sr = tcg_global_mem_new(cpu_env, |
bbe418f2 | 81 | offsetof(CPUOpenRISCState, sr), "sr"); |
e1ccc054 | 82 | env_flags = tcg_global_mem_new_i32(cpu_env, |
bbe418f2 JL |
83 | offsetof(CPUOpenRISCState, flags), |
84 | "flags"); | |
e1ccc054 | 85 | cpu_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 86 | offsetof(CPUOpenRISCState, pc), "pc"); |
e1ccc054 | 87 | cpu_npc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 88 | offsetof(CPUOpenRISCState, npc), "npc"); |
e1ccc054 | 89 | cpu_ppc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 90 | offsetof(CPUOpenRISCState, ppc), "ppc"); |
e1ccc054 | 91 | jmp_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 92 | offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); |
84775c43 RH |
93 | cpu_sr_f = tcg_global_mem_new(cpu_env, |
94 | offsetof(CPUOpenRISCState, sr_f), "sr_f"); | |
97458071 RH |
95 | cpu_sr_cy = tcg_global_mem_new(cpu_env, |
96 | offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); | |
97 | cpu_sr_ov = tcg_global_mem_new(cpu_env, | |
98 | offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); | |
930c3d00 RH |
99 | cpu_lock_addr = tcg_global_mem_new(cpu_env, |
100 | offsetof(CPUOpenRISCState, lock_addr), | |
101 | "lock_addr"); | |
102 | cpu_lock_value = tcg_global_mem_new(cpu_env, | |
103 | offsetof(CPUOpenRISCState, lock_value), | |
104 | "lock_value"); | |
e1ccc054 | 105 | fpcsr = tcg_global_mem_new_i32(cpu_env, |
bbe418f2 JL |
106 | offsetof(CPUOpenRISCState, fpcsr), |
107 | "fpcsr"); | |
e1ccc054 | 108 | machi = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
109 | offsetof(CPUOpenRISCState, machi), |
110 | "machi"); | |
e1ccc054 | 111 | maclo = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
112 | offsetof(CPUOpenRISCState, maclo), |
113 | "maclo"); | |
e1ccc054 | 114 | fpmaddhi = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
115 | offsetof(CPUOpenRISCState, fpmaddhi), |
116 | "fpmaddhi"); | |
e1ccc054 | 117 | fpmaddlo = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
118 | offsetof(CPUOpenRISCState, fpmaddlo), |
119 | "fpmaddlo"); | |
120 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 121 | cpu_R[i] = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
122 | offsetof(CPUOpenRISCState, gpr[i]), |
123 | regnames[i]); | |
124 | } | |
bbe418f2 JL |
125 | } |
126 | ||
bbe418f2 JL |
127 | static inline void gen_sync_flags(DisasContext *dc) |
128 | { | |
129 | /* Sync the tb dependent flag between translate and runtime. */ | |
0c53d734 RH |
130 | if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) { |
131 | tcg_gen_movi_tl(env_flags, dc->tb_flags & D_FLAG); | |
bbe418f2 JL |
132 | dc->synced_flags = dc->tb_flags; |
133 | } | |
134 | } | |
135 | ||
136 | static void gen_exception(DisasContext *dc, unsigned int excp) | |
137 | { | |
138 | TCGv_i32 tmp = tcg_const_i32(excp); | |
139 | gen_helper_exception(cpu_env, tmp); | |
140 | tcg_temp_free_i32(tmp); | |
141 | } | |
142 | ||
143 | static void gen_illegal_exception(DisasContext *dc) | |
144 | { | |
145 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
146 | gen_exception(dc, EXCP_ILLEGAL); | |
147 | dc->is_jmp = DISAS_UPDATE; | |
148 | } | |
149 | ||
150 | /* not used yet, open it when we need or64. */ | |
151 | /*#ifdef TARGET_OPENRISC64 | |
152 | static void check_ob64s(DisasContext *dc) | |
153 | { | |
154 | if (!(dc->flags & CPUCFGR_OB64S)) { | |
155 | gen_illegal_exception(dc); | |
156 | } | |
157 | } | |
158 | ||
159 | static void check_of64s(DisasContext *dc) | |
160 | { | |
161 | if (!(dc->flags & CPUCFGR_OF64S)) { | |
162 | gen_illegal_exception(dc); | |
163 | } | |
164 | } | |
165 | ||
166 | static void check_ov64s(DisasContext *dc) | |
167 | { | |
168 | if (!(dc->flags & CPUCFGR_OV64S)) { | |
169 | gen_illegal_exception(dc); | |
170 | } | |
171 | } | |
172 | #endif*/ | |
173 | ||
90aa39a1 SF |
174 | static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) |
175 | { | |
176 | if (unlikely(dc->singlestep_enabled)) { | |
177 | return false; | |
178 | } | |
179 | ||
180 | #ifndef CONFIG_USER_ONLY | |
181 | return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
182 | #else | |
183 | return true; | |
184 | #endif | |
185 | } | |
186 | ||
bbe418f2 JL |
187 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
188 | { | |
90aa39a1 | 189 | if (use_goto_tb(dc, dest)) { |
bbe418f2 JL |
190 | tcg_gen_movi_tl(cpu_pc, dest); |
191 | tcg_gen_goto_tb(n); | |
90aa39a1 | 192 | tcg_gen_exit_tb((uintptr_t)dc->tb + n); |
bbe418f2 JL |
193 | } else { |
194 | tcg_gen_movi_tl(cpu_pc, dest); | |
195 | if (dc->singlestep_enabled) { | |
196 | gen_exception(dc, EXCP_DEBUG); | |
197 | } | |
198 | tcg_gen_exit_tb(0); | |
199 | } | |
200 | } | |
201 | ||
6da544a6 | 202 | static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0) |
bbe418f2 | 203 | { |
6da544a6 | 204 | target_ulong tmp_pc = dc->pc + n26 * 4; |
bbe418f2 | 205 | |
da1d7759 SM |
206 | switch (op0) { |
207 | case 0x00: /* l.j */ | |
bbe418f2 | 208 | tcg_gen_movi_tl(jmp_pc, tmp_pc); |
da1d7759 SM |
209 | break; |
210 | case 0x01: /* l.jal */ | |
bbe418f2 JL |
211 | tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8)); |
212 | tcg_gen_movi_tl(jmp_pc, tmp_pc); | |
da1d7759 SM |
213 | break; |
214 | case 0x03: /* l.bnf */ | |
215 | case 0x04: /* l.bf */ | |
216 | { | |
784696d1 RH |
217 | TCGv t_next = tcg_const_tl(dc->pc + 8); |
218 | TCGv t_true = tcg_const_tl(tmp_pc); | |
219 | TCGv t_zero = tcg_const_tl(0); | |
220 | ||
221 | tcg_gen_movcond_tl(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE, | |
222 | jmp_pc, cpu_sr_f, t_zero, t_true, t_next); | |
223 | ||
224 | tcg_temp_free(t_next); | |
225 | tcg_temp_free(t_true); | |
226 | tcg_temp_free(t_zero); | |
da1d7759 SM |
227 | } |
228 | break; | |
229 | case 0x11: /* l.jr */ | |
bbe418f2 | 230 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); |
da1d7759 SM |
231 | break; |
232 | case 0x12: /* l.jalr */ | |
bbe418f2 JL |
233 | tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8)); |
234 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); | |
da1d7759 SM |
235 | break; |
236 | default: | |
bbe418f2 | 237 | gen_illegal_exception(dc); |
da1d7759 | 238 | break; |
bbe418f2 JL |
239 | } |
240 | ||
bbe418f2 JL |
241 | dc->delayed_branch = 2; |
242 | dc->tb_flags |= D_FLAG; | |
243 | gen_sync_flags(dc); | |
244 | } | |
245 | ||
97458071 | 246 | static void gen_ove_cy(DisasContext *dc) |
9ecaa27e | 247 | { |
0c53d734 | 248 | if (dc->tb_flags & SR_OVE) { |
97458071 | 249 | gen_helper_ove_cy(cpu_env); |
0c53d734 | 250 | } |
9ecaa27e RH |
251 | } |
252 | ||
97458071 | 253 | static void gen_ove_ov(DisasContext *dc) |
9ecaa27e | 254 | { |
0c53d734 | 255 | if (dc->tb_flags & SR_OVE) { |
97458071 | 256 | gen_helper_ove_ov(cpu_env); |
0c53d734 | 257 | } |
9ecaa27e RH |
258 | } |
259 | ||
97458071 | 260 | static void gen_ove_cyov(DisasContext *dc) |
9ecaa27e | 261 | { |
0c53d734 | 262 | if (dc->tb_flags & SR_OVE) { |
97458071 | 263 | gen_helper_ove_cyov(cpu_env); |
0c53d734 | 264 | } |
9ecaa27e RH |
265 | } |
266 | ||
267 | static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
268 | { | |
269 | TCGv t0 = tcg_const_tl(0); | |
270 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 271 | |
97458071 RH |
272 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); |
273 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 274 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 275 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
276 | tcg_temp_free(t0); |
277 | ||
278 | tcg_gen_mov_tl(dest, res); | |
279 | tcg_temp_free(res); | |
280 | ||
97458071 | 281 | gen_ove_cyov(dc); |
9ecaa27e RH |
282 | } |
283 | ||
284 | static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
285 | { | |
286 | TCGv t0 = tcg_const_tl(0); | |
287 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 288 | |
97458071 RH |
289 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); |
290 | tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); | |
291 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 292 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 293 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
294 | tcg_temp_free(t0); |
295 | ||
296 | tcg_gen_mov_tl(dest, res); | |
297 | tcg_temp_free(res); | |
298 | ||
97458071 | 299 | gen_ove_cyov(dc); |
9ecaa27e RH |
300 | } |
301 | ||
302 | static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
303 | { | |
304 | TCGv res = tcg_temp_new(); | |
9ecaa27e RH |
305 | |
306 | tcg_gen_sub_tl(res, srca, srcb); | |
97458071 RH |
307 | tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); |
308 | tcg_gen_xor_tl(cpu_sr_ov, res, srcb); | |
309 | tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); | |
310 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); | |
9ecaa27e RH |
311 | |
312 | tcg_gen_mov_tl(dest, res); | |
313 | tcg_temp_free(res); | |
314 | ||
97458071 | 315 | gen_ove_cyov(dc); |
9ecaa27e RH |
316 | } |
317 | ||
318 | static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
319 | { | |
9ecaa27e RH |
320 | TCGv t0 = tcg_temp_new(); |
321 | ||
97458071 | 322 | tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); |
9ecaa27e | 323 | tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); |
97458071 | 324 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); |
9ecaa27e RH |
325 | tcg_temp_free(t0); |
326 | ||
97458071 RH |
327 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
328 | gen_ove_ov(dc); | |
9ecaa27e RH |
329 | } |
330 | ||
331 | static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
332 | { | |
97458071 RH |
333 | tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); |
334 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); | |
9ecaa27e | 335 | |
97458071 | 336 | gen_ove_cy(dc); |
9ecaa27e RH |
337 | } |
338 | ||
339 | static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
340 | { | |
9ecaa27e RH |
341 | TCGv t0 = tcg_temp_new(); |
342 | ||
97458071 | 343 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); |
9ecaa27e RH |
344 | /* The result of divide-by-zero is undefined. |
345 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 346 | tcg_gen_or_tl(t0, srcb, cpu_sr_ov); |
9ecaa27e RH |
347 | tcg_gen_div_tl(dest, srca, t0); |
348 | tcg_temp_free(t0); | |
349 | ||
97458071 RH |
350 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
351 | gen_ove_ov(dc); | |
9ecaa27e RH |
352 | } |
353 | ||
354 | static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
355 | { | |
9ecaa27e RH |
356 | TCGv t0 = tcg_temp_new(); |
357 | ||
97458071 | 358 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); |
9ecaa27e RH |
359 | /* The result of divide-by-zero is undefined. |
360 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 361 | tcg_gen_or_tl(t0, srcb, cpu_sr_cy); |
9ecaa27e RH |
362 | tcg_gen_divu_tl(dest, srca, t0); |
363 | tcg_temp_free(t0); | |
364 | ||
97458071 | 365 | gen_ove_cy(dc); |
9ecaa27e | 366 | } |
da1d7759 | 367 | |
930c3d00 RH |
368 | static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) |
369 | { | |
370 | TCGv ea = tcg_temp_new(); | |
371 | ||
372 | tcg_gen_addi_tl(ea, ra, ofs); | |
373 | tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL); | |
374 | tcg_gen_mov_tl(cpu_lock_addr, ea); | |
375 | tcg_gen_mov_tl(cpu_lock_value, rd); | |
376 | tcg_temp_free(ea); | |
377 | } | |
378 | ||
379 | static void gen_swa(DisasContext *dc, TCGv rb, TCGv ra, int32_t ofs) | |
380 | { | |
381 | TCGv ea, val; | |
382 | TCGLabel *lab_fail, *lab_done; | |
383 | ||
384 | ea = tcg_temp_new(); | |
385 | tcg_gen_addi_tl(ea, ra, ofs); | |
386 | ||
387 | lab_fail = gen_new_label(); | |
388 | lab_done = gen_new_label(); | |
389 | tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); | |
390 | tcg_temp_free(ea); | |
391 | ||
392 | val = tcg_temp_new(); | |
393 | tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, | |
394 | rb, dc->mem_idx, MO_TEUL); | |
84775c43 | 395 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); |
930c3d00 RH |
396 | tcg_temp_free(val); |
397 | ||
398 | tcg_gen_br(lab_done); | |
399 | ||
400 | gen_set_label(lab_fail); | |
84775c43 | 401 | tcg_gen_movi_tl(cpu_sr_f, 0); |
930c3d00 RH |
402 | |
403 | gen_set_label(lab_done); | |
404 | tcg_gen_movi_tl(cpu_lock_addr, -1); | |
930c3d00 RH |
405 | } |
406 | ||
bbe418f2 JL |
407 | static void dec_calc(DisasContext *dc, uint32_t insn) |
408 | { | |
409 | uint32_t op0, op1, op2; | |
410 | uint32_t ra, rb, rd; | |
411 | op0 = extract32(insn, 0, 4); | |
412 | op1 = extract32(insn, 8, 2); | |
413 | op2 = extract32(insn, 6, 2); | |
414 | ra = extract32(insn, 16, 5); | |
415 | rb = extract32(insn, 11, 5); | |
416 | rd = extract32(insn, 21, 5); | |
417 | ||
cf2ae442 RH |
418 | switch (op1) { |
419 | case 0: | |
420 | switch (op0) { | |
421 | case 0x0: /* l.add */ | |
bbe418f2 | 422 | LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 423 | gen_add(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 424 | return; |
bbe418f2 | 425 | |
cf2ae442 | 426 | case 0x1: /* l.addc */ |
bbe418f2 | 427 | LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 428 | gen_addc(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 429 | return; |
bbe418f2 | 430 | |
cf2ae442 | 431 | case 0x2: /* l.sub */ |
bbe418f2 | 432 | LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 433 | gen_sub(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 434 | return; |
bbe418f2 | 435 | |
cf2ae442 | 436 | case 0x3: /* l.and */ |
bbe418f2 JL |
437 | LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb); |
438 | tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 439 | return; |
bbe418f2 | 440 | |
cf2ae442 | 441 | case 0x4: /* l.or */ |
bbe418f2 JL |
442 | LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb); |
443 | tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 444 | return; |
bbe418f2 | 445 | |
cf2ae442 | 446 | case 0x5: /* l.xor */ |
bbe418f2 JL |
447 | LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb); |
448 | tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 449 | return; |
bbe418f2 | 450 | |
cf2ae442 RH |
451 | case 0x8: |
452 | switch (op2) { | |
453 | case 0: /* l.sll */ | |
454 | LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb); | |
455 | tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
456 | return; | |
457 | case 1: /* l.srl */ | |
458 | LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb); | |
459 | tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
460 | return; | |
461 | case 2: /* l.sra */ | |
462 | LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb); | |
463 | tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
464 | return; | |
465 | case 3: /* l.ror */ | |
466 | LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb); | |
467 | tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
468 | return; | |
469 | } | |
bbe418f2 | 470 | break; |
bbe418f2 | 471 | |
cf2ae442 RH |
472 | case 0xc: |
473 | switch (op2) { | |
474 | case 0: /* l.exths */ | |
475 | LOG_DIS("l.exths r%d, r%d\n", rd, ra); | |
476 | tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]); | |
477 | return; | |
478 | case 1: /* l.extbs */ | |
479 | LOG_DIS("l.extbs r%d, r%d\n", rd, ra); | |
480 | tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]); | |
481 | return; | |
482 | case 2: /* l.exthz */ | |
483 | LOG_DIS("l.exthz r%d, r%d\n", rd, ra); | |
484 | tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]); | |
485 | return; | |
486 | case 3: /* l.extbz */ | |
487 | LOG_DIS("l.extbz r%d, r%d\n", rd, ra); | |
488 | tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]); | |
489 | return; | |
490 | } | |
bbe418f2 JL |
491 | break; |
492 | ||
cf2ae442 RH |
493 | case 0xd: |
494 | switch (op2) { | |
495 | case 0: /* l.extws */ | |
496 | LOG_DIS("l.extws r%d, r%d\n", rd, ra); | |
497 | tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]); | |
498 | return; | |
499 | case 1: /* l.extwz */ | |
500 | LOG_DIS("l.extwz r%d, r%d\n", rd, ra); | |
501 | tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]); | |
502 | return; | |
503 | } | |
bbe418f2 | 504 | break; |
bbe418f2 | 505 | |
cf2ae442 | 506 | case 0xe: /* l.cmov */ |
bbe418f2 JL |
507 | LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb); |
508 | { | |
784696d1 RH |
509 | TCGv zero = tcg_const_tl(0); |
510 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[rd], cpu_sr_f, zero, | |
511 | cpu_R[ra], cpu_R[rb]); | |
512 | tcg_temp_free(zero); | |
bbe418f2 | 513 | } |
cf2ae442 | 514 | return; |
bbe418f2 | 515 | |
cf2ae442 | 516 | case 0xf: /* l.ff1 */ |
bbe418f2 | 517 | LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); |
555baef8 RH |
518 | tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1); |
519 | tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1); | |
cf2ae442 RH |
520 | return; |
521 | } | |
522 | break; | |
523 | ||
524 | case 1: | |
525 | switch (op0) { | |
526 | case 0xf: /* l.fl1 */ | |
bbe418f2 | 527 | LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); |
555baef8 RH |
528 | tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS); |
529 | tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]); | |
cf2ae442 | 530 | return; |
bbe418f2 JL |
531 | } |
532 | break; | |
533 | ||
cf2ae442 | 534 | case 2: |
bbe418f2 JL |
535 | break; |
536 | ||
cf2ae442 RH |
537 | case 3: |
538 | switch (op0) { | |
539 | case 0x6: /* l.mul */ | |
540 | LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb); | |
541 | gen_mul(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
542 | return; | |
bbe418f2 | 543 | |
cf2ae442 RH |
544 | case 0x9: /* l.div */ |
545 | LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb); | |
546 | gen_div(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
547 | return; | |
bbe418f2 | 548 | |
cf2ae442 RH |
549 | case 0xa: /* l.divu */ |
550 | LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb); | |
551 | gen_divu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
552 | return; | |
bbe418f2 | 553 | |
cf2ae442 RH |
554 | case 0xb: /* l.mulu */ |
555 | LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb); | |
556 | gen_mulu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
557 | return; | |
bbe418f2 JL |
558 | } |
559 | break; | |
bbe418f2 | 560 | } |
cf2ae442 | 561 | gen_illegal_exception(dc); |
bbe418f2 JL |
562 | } |
563 | ||
564 | static void dec_misc(DisasContext *dc, uint32_t insn) | |
565 | { | |
566 | uint32_t op0, op1; | |
567 | uint32_t ra, rb, rd; | |
6da544a6 RH |
568 | uint32_t L6, K5, K16, K5_11; |
569 | int32_t I16, I5_11, N26; | |
5631e69c | 570 | TCGMemOp mop; |
9ecaa27e | 571 | TCGv t0; |
5631e69c | 572 | |
bbe418f2 JL |
573 | op0 = extract32(insn, 26, 6); |
574 | op1 = extract32(insn, 24, 2); | |
575 | ra = extract32(insn, 16, 5); | |
576 | rb = extract32(insn, 11, 5); | |
577 | rd = extract32(insn, 21, 5); | |
bbe418f2 JL |
578 | L6 = extract32(insn, 5, 6); |
579 | K5 = extract32(insn, 0, 5); | |
6da544a6 RH |
580 | K16 = extract32(insn, 0, 16); |
581 | I16 = (int16_t)K16; | |
582 | N26 = sextract32(insn, 0, 26); | |
583 | K5_11 = (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); | |
584 | I5_11 = (int16_t)K5_11; | |
bbe418f2 JL |
585 | |
586 | switch (op0) { | |
587 | case 0x00: /* l.j */ | |
588 | LOG_DIS("l.j %d\n", N26); | |
589 | gen_jump(dc, N26, 0, op0); | |
590 | break; | |
591 | ||
592 | case 0x01: /* l.jal */ | |
593 | LOG_DIS("l.jal %d\n", N26); | |
594 | gen_jump(dc, N26, 0, op0); | |
595 | break; | |
596 | ||
597 | case 0x03: /* l.bnf */ | |
598 | LOG_DIS("l.bnf %d\n", N26); | |
599 | gen_jump(dc, N26, 0, op0); | |
600 | break; | |
601 | ||
602 | case 0x04: /* l.bf */ | |
603 | LOG_DIS("l.bf %d\n", N26); | |
604 | gen_jump(dc, N26, 0, op0); | |
605 | break; | |
606 | ||
607 | case 0x05: | |
608 | switch (op1) { | |
609 | case 0x01: /* l.nop */ | |
610 | LOG_DIS("l.nop %d\n", I16); | |
611 | break; | |
612 | ||
613 | default: | |
614 | gen_illegal_exception(dc); | |
615 | break; | |
616 | } | |
617 | break; | |
618 | ||
619 | case 0x11: /* l.jr */ | |
620 | LOG_DIS("l.jr r%d\n", rb); | |
621 | gen_jump(dc, 0, rb, op0); | |
622 | break; | |
623 | ||
624 | case 0x12: /* l.jalr */ | |
625 | LOG_DIS("l.jalr r%d\n", rb); | |
626 | gen_jump(dc, 0, rb, op0); | |
627 | break; | |
628 | ||
629 | case 0x13: /* l.maci */ | |
6da544a6 | 630 | LOG_DIS("l.maci r%d, %d\n", ra, I16); |
bbe418f2 JL |
631 | { |
632 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
633 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
634 | TCGv_i32 dst = tcg_temp_new_i32(); | |
6da544a6 | 635 | TCGv ttmp = tcg_const_tl(I16); |
bbe418f2 JL |
636 | tcg_gen_mul_tl(dst, cpu_R[ra], ttmp); |
637 | tcg_gen_ext_i32_i64(t1, dst); | |
638 | tcg_gen_concat_i32_i64(t2, maclo, machi); | |
639 | tcg_gen_add_i64(t2, t2, t1); | |
ecc7b3aa | 640 | tcg_gen_extrl_i64_i32(maclo, t2); |
bbe418f2 | 641 | tcg_gen_shri_i64(t2, t2, 32); |
ecc7b3aa | 642 | tcg_gen_extrl_i64_i32(machi, t2); |
bbe418f2 JL |
643 | tcg_temp_free_i32(dst); |
644 | tcg_temp_free(ttmp); | |
645 | tcg_temp_free_i64(t1); | |
646 | tcg_temp_free_i64(t2); | |
647 | } | |
648 | break; | |
649 | ||
650 | case 0x09: /* l.rfe */ | |
651 | LOG_DIS("l.rfe\n"); | |
652 | { | |
653 | #if defined(CONFIG_USER_ONLY) | |
654 | return; | |
655 | #else | |
656 | if (dc->mem_idx == MMU_USER_IDX) { | |
657 | gen_illegal_exception(dc); | |
658 | return; | |
659 | } | |
660 | gen_helper_rfe(cpu_env); | |
661 | dc->is_jmp = DISAS_UPDATE; | |
662 | #endif | |
663 | } | |
664 | break; | |
665 | ||
930c3d00 RH |
666 | case 0x1b: /* l.lwa */ |
667 | LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16); | |
668 | gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16); | |
669 | break; | |
670 | ||
bbe418f2 JL |
671 | case 0x1c: /* l.cust1 */ |
672 | LOG_DIS("l.cust1\n"); | |
673 | break; | |
674 | ||
675 | case 0x1d: /* l.cust2 */ | |
676 | LOG_DIS("l.cust2\n"); | |
677 | break; | |
678 | ||
679 | case 0x1e: /* l.cust3 */ | |
680 | LOG_DIS("l.cust3\n"); | |
681 | break; | |
682 | ||
683 | case 0x1f: /* l.cust4 */ | |
684 | LOG_DIS("l.cust4\n"); | |
685 | break; | |
686 | ||
687 | case 0x3c: /* l.cust5 */ | |
688 | LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5); | |
689 | break; | |
690 | ||
691 | case 0x3d: /* l.cust6 */ | |
692 | LOG_DIS("l.cust6\n"); | |
693 | break; | |
694 | ||
695 | case 0x3e: /* l.cust7 */ | |
696 | LOG_DIS("l.cust7\n"); | |
697 | break; | |
698 | ||
699 | case 0x3f: /* l.cust8 */ | |
700 | LOG_DIS("l.cust8\n"); | |
701 | break; | |
702 | ||
703 | /* not used yet, open it when we need or64. */ | |
704 | /*#ifdef TARGET_OPENRISC64 | |
705 | case 0x20: l.ld | |
706 | LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
707 | check_ob64s(dc); |
708 | mop = MO_TEQ; | |
709 | goto do_load; | |
bbe418f2 JL |
710 | #endif*/ |
711 | ||
712 | case 0x21: /* l.lwz */ | |
713 | LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
714 | mop = MO_TEUL; |
715 | goto do_load; | |
bbe418f2 JL |
716 | |
717 | case 0x22: /* l.lws */ | |
718 | LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
719 | mop = MO_TESL; |
720 | goto do_load; | |
bbe418f2 JL |
721 | |
722 | case 0x23: /* l.lbz */ | |
723 | LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
724 | mop = MO_UB; |
725 | goto do_load; | |
bbe418f2 JL |
726 | |
727 | case 0x24: /* l.lbs */ | |
728 | LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
729 | mop = MO_SB; |
730 | goto do_load; | |
bbe418f2 JL |
731 | |
732 | case 0x25: /* l.lhz */ | |
733 | LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
734 | mop = MO_TEUW; |
735 | goto do_load; | |
bbe418f2 JL |
736 | |
737 | case 0x26: /* l.lhs */ | |
738 | LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
739 | mop = MO_TESW; |
740 | goto do_load; | |
741 | ||
742 | do_load: | |
bbe418f2 JL |
743 | { |
744 | TCGv t0 = tcg_temp_new(); | |
6da544a6 | 745 | tcg_gen_addi_tl(t0, cpu_R[ra], I16); |
5631e69c | 746 | tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); |
bbe418f2 JL |
747 | tcg_temp_free(t0); |
748 | } | |
749 | break; | |
750 | ||
751 | case 0x27: /* l.addi */ | |
752 | LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); | |
9ecaa27e RH |
753 | t0 = tcg_const_tl(I16); |
754 | gen_add(dc, cpu_R[rd], cpu_R[ra], t0); | |
755 | tcg_temp_free(t0); | |
bbe418f2 JL |
756 | break; |
757 | ||
758 | case 0x28: /* l.addic */ | |
759 | LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16); | |
9ecaa27e RH |
760 | t0 = tcg_const_tl(I16); |
761 | gen_addc(dc, cpu_R[rd], cpu_R[ra], t0); | |
762 | tcg_temp_free(t0); | |
bbe418f2 JL |
763 | break; |
764 | ||
765 | case 0x29: /* l.andi */ | |
6da544a6 RH |
766 | LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, K16); |
767 | tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], K16); | |
bbe418f2 JL |
768 | break; |
769 | ||
770 | case 0x2a: /* l.ori */ | |
6da544a6 RH |
771 | LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, K16); |
772 | tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], K16); | |
bbe418f2 JL |
773 | break; |
774 | ||
775 | case 0x2b: /* l.xori */ | |
776 | LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); | |
6da544a6 | 777 | tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], I16); |
bbe418f2 JL |
778 | break; |
779 | ||
780 | case 0x2c: /* l.muli */ | |
781 | LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16); | |
9ecaa27e RH |
782 | t0 = tcg_const_tl(I16); |
783 | gen_mul(dc, cpu_R[rd], cpu_R[ra], t0); | |
784 | tcg_temp_free(t0); | |
bbe418f2 JL |
785 | break; |
786 | ||
787 | case 0x2d: /* l.mfspr */ | |
6da544a6 | 788 | LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, K16); |
4dd044c6 JL |
789 | { |
790 | #if defined(CONFIG_USER_ONLY) | |
791 | return; | |
792 | #else | |
6da544a6 | 793 | TCGv_i32 ti = tcg_const_i32(K16); |
4dd044c6 JL |
794 | if (dc->mem_idx == MMU_USER_IDX) { |
795 | gen_illegal_exception(dc); | |
796 | return; | |
797 | } | |
798 | gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); | |
799 | tcg_temp_free_i32(ti); | |
800 | #endif | |
801 | } | |
bbe418f2 JL |
802 | break; |
803 | ||
804 | case 0x30: /* l.mtspr */ | |
6da544a6 | 805 | LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11); |
4dd044c6 JL |
806 | { |
807 | #if defined(CONFIG_USER_ONLY) | |
808 | return; | |
809 | #else | |
6da544a6 | 810 | TCGv_i32 im = tcg_const_i32(K5_11); |
4dd044c6 JL |
811 | if (dc->mem_idx == MMU_USER_IDX) { |
812 | gen_illegal_exception(dc); | |
813 | return; | |
814 | } | |
815 | gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); | |
816 | tcg_temp_free_i32(im); | |
817 | #endif | |
818 | } | |
bbe418f2 JL |
819 | break; |
820 | ||
930c3d00 | 821 | case 0x33: /* l.swa */ |
6da544a6 RH |
822 | LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); |
823 | gen_swa(dc, cpu_R[rb], cpu_R[ra], I5_11); | |
930c3d00 RH |
824 | break; |
825 | ||
bbe418f2 JL |
826 | /* not used yet, open it when we need or64. */ |
827 | /*#ifdef TARGET_OPENRISC64 | |
828 | case 0x34: l.sd | |
6da544a6 | 829 | LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
830 | check_ob64s(dc); |
831 | mop = MO_TEQ; | |
832 | goto do_store; | |
bbe418f2 JL |
833 | #endif*/ |
834 | ||
835 | case 0x35: /* l.sw */ | |
6da544a6 | 836 | LOG_DIS("l.sw r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
837 | mop = MO_TEUL; |
838 | goto do_store; | |
bbe418f2 JL |
839 | |
840 | case 0x36: /* l.sb */ | |
6da544a6 | 841 | LOG_DIS("l.sb r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
842 | mop = MO_UB; |
843 | goto do_store; | |
bbe418f2 JL |
844 | |
845 | case 0x37: /* l.sh */ | |
6da544a6 | 846 | LOG_DIS("l.sh r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
847 | mop = MO_TEUW; |
848 | goto do_store; | |
849 | ||
850 | do_store: | |
bbe418f2 JL |
851 | { |
852 | TCGv t0 = tcg_temp_new(); | |
6da544a6 | 853 | tcg_gen_addi_tl(t0, cpu_R[ra], I5_11); |
5631e69c | 854 | tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); |
bbe418f2 JL |
855 | tcg_temp_free(t0); |
856 | } | |
857 | break; | |
858 | ||
859 | default: | |
860 | gen_illegal_exception(dc); | |
861 | break; | |
862 | } | |
863 | } | |
864 | ||
865 | static void dec_mac(DisasContext *dc, uint32_t insn) | |
866 | { | |
867 | uint32_t op0; | |
868 | uint32_t ra, rb; | |
869 | op0 = extract32(insn, 0, 4); | |
870 | ra = extract32(insn, 16, 5); | |
871 | rb = extract32(insn, 11, 5); | |
872 | ||
873 | switch (op0) { | |
874 | case 0x0001: /* l.mac */ | |
875 | LOG_DIS("l.mac r%d, r%d\n", ra, rb); | |
876 | { | |
877 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
878 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
879 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
880 | tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]); | |
881 | tcg_gen_ext_i32_i64(t1, t0); | |
882 | tcg_gen_concat_i32_i64(t2, maclo, machi); | |
883 | tcg_gen_add_i64(t2, t2, t1); | |
ecc7b3aa | 884 | tcg_gen_extrl_i64_i32(maclo, t2); |
bbe418f2 | 885 | tcg_gen_shri_i64(t2, t2, 32); |
ecc7b3aa | 886 | tcg_gen_extrl_i64_i32(machi, t2); |
bbe418f2 JL |
887 | tcg_temp_free_i32(t0); |
888 | tcg_temp_free_i64(t1); | |
889 | tcg_temp_free_i64(t2); | |
890 | } | |
891 | break; | |
892 | ||
893 | case 0x0002: /* l.msb */ | |
894 | LOG_DIS("l.msb r%d, r%d\n", ra, rb); | |
895 | { | |
896 | TCGv_i32 t0 = tcg_temp_new_i32(); | |
897 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
898 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
899 | tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]); | |
900 | tcg_gen_ext_i32_i64(t1, t0); | |
901 | tcg_gen_concat_i32_i64(t2, maclo, machi); | |
902 | tcg_gen_sub_i64(t2, t2, t1); | |
ecc7b3aa | 903 | tcg_gen_extrl_i64_i32(maclo, t2); |
bbe418f2 | 904 | tcg_gen_shri_i64(t2, t2, 32); |
ecc7b3aa | 905 | tcg_gen_extrl_i64_i32(machi, t2); |
bbe418f2 JL |
906 | tcg_temp_free_i32(t0); |
907 | tcg_temp_free_i64(t1); | |
908 | tcg_temp_free_i64(t2); | |
909 | } | |
910 | break; | |
911 | ||
912 | default: | |
913 | gen_illegal_exception(dc); | |
914 | break; | |
915 | } | |
916 | } | |
917 | ||
918 | static void dec_logic(DisasContext *dc, uint32_t insn) | |
919 | { | |
920 | uint32_t op0; | |
6da544a6 | 921 | uint32_t rd, ra, L6, S6; |
bbe418f2 JL |
922 | op0 = extract32(insn, 6, 2); |
923 | rd = extract32(insn, 21, 5); | |
924 | ra = extract32(insn, 16, 5); | |
925 | L6 = extract32(insn, 0, 6); | |
6da544a6 | 926 | S6 = L6 & (TARGET_LONG_BITS - 1); |
bbe418f2 JL |
927 | |
928 | switch (op0) { | |
929 | case 0x00: /* l.slli */ | |
930 | LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 931 | tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
932 | break; |
933 | ||
934 | case 0x01: /* l.srli */ | |
935 | LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 936 | tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
937 | break; |
938 | ||
939 | case 0x02: /* l.srai */ | |
940 | LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 RH |
941 | tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6); |
942 | break; | |
bbe418f2 JL |
943 | |
944 | case 0x03: /* l.rori */ | |
945 | LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 946 | tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
947 | break; |
948 | ||
949 | default: | |
950 | gen_illegal_exception(dc); | |
951 | break; | |
952 | } | |
953 | } | |
954 | ||
955 | static void dec_M(DisasContext *dc, uint32_t insn) | |
956 | { | |
957 | uint32_t op0; | |
958 | uint32_t rd; | |
959 | uint32_t K16; | |
960 | op0 = extract32(insn, 16, 1); | |
961 | rd = extract32(insn, 21, 5); | |
962 | K16 = extract32(insn, 0, 16); | |
963 | ||
964 | switch (op0) { | |
965 | case 0x0: /* l.movhi */ | |
966 | LOG_DIS("l.movhi r%d, %d\n", rd, K16); | |
967 | tcg_gen_movi_tl(cpu_R[rd], (K16 << 16)); | |
968 | break; | |
969 | ||
970 | case 0x1: /* l.macrc */ | |
971 | LOG_DIS("l.macrc r%d\n", rd); | |
972 | tcg_gen_mov_tl(cpu_R[rd], maclo); | |
973 | tcg_gen_movi_tl(maclo, 0x0); | |
974 | tcg_gen_movi_tl(machi, 0x0); | |
975 | break; | |
976 | ||
977 | default: | |
978 | gen_illegal_exception(dc); | |
979 | break; | |
980 | } | |
981 | } | |
982 | ||
983 | static void dec_comp(DisasContext *dc, uint32_t insn) | |
984 | { | |
985 | uint32_t op0; | |
986 | uint32_t ra, rb; | |
987 | ||
988 | op0 = extract32(insn, 21, 5); | |
989 | ra = extract32(insn, 16, 5); | |
990 | rb = extract32(insn, 11, 5); | |
991 | ||
bbe418f2 JL |
992 | /* unsigned integers */ |
993 | tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]); | |
994 | tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]); | |
995 | ||
996 | switch (op0) { | |
997 | case 0x0: /* l.sfeq */ | |
998 | LOG_DIS("l.sfeq r%d, r%d\n", ra, rb); | |
84775c43 | 999 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1000 | break; |
1001 | ||
1002 | case 0x1: /* l.sfne */ | |
1003 | LOG_DIS("l.sfne r%d, r%d\n", ra, rb); | |
84775c43 | 1004 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1005 | break; |
1006 | ||
1007 | case 0x2: /* l.sfgtu */ | |
1008 | LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb); | |
84775c43 | 1009 | tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1010 | break; |
1011 | ||
1012 | case 0x3: /* l.sfgeu */ | |
1013 | LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb); | |
84775c43 | 1014 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1015 | break; |
1016 | ||
1017 | case 0x4: /* l.sfltu */ | |
1018 | LOG_DIS("l.sfltu r%d, r%d\n", ra, rb); | |
84775c43 | 1019 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1020 | break; |
1021 | ||
1022 | case 0x5: /* l.sfleu */ | |
1023 | LOG_DIS("l.sfleu r%d, r%d\n", ra, rb); | |
84775c43 | 1024 | tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1025 | break; |
1026 | ||
1027 | case 0xa: /* l.sfgts */ | |
1028 | LOG_DIS("l.sfgts r%d, r%d\n", ra, rb); | |
84775c43 | 1029 | tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1030 | break; |
1031 | ||
1032 | case 0xb: /* l.sfges */ | |
1033 | LOG_DIS("l.sfges r%d, r%d\n", ra, rb); | |
84775c43 | 1034 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1035 | break; |
1036 | ||
1037 | case 0xc: /* l.sflts */ | |
1038 | LOG_DIS("l.sflts r%d, r%d\n", ra, rb); | |
84775c43 | 1039 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1040 | break; |
1041 | ||
1042 | case 0xd: /* l.sfles */ | |
1043 | LOG_DIS("l.sfles r%d, r%d\n", ra, rb); | |
84775c43 | 1044 | tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1045 | break; |
1046 | ||
1047 | default: | |
1048 | gen_illegal_exception(dc); | |
1049 | break; | |
1050 | } | |
bbe418f2 JL |
1051 | } |
1052 | ||
1053 | static void dec_compi(DisasContext *dc, uint32_t insn) | |
1054 | { | |
6da544a6 RH |
1055 | uint32_t op0, ra; |
1056 | int32_t I16; | |
bbe418f2 JL |
1057 | |
1058 | op0 = extract32(insn, 21, 5); | |
1059 | ra = extract32(insn, 16, 5); | |
6da544a6 | 1060 | I16 = sextract32(insn, 0, 16); |
bbe418f2 | 1061 | |
bbe418f2 JL |
1062 | switch (op0) { |
1063 | case 0x0: /* l.sfeqi */ | |
1064 | LOG_DIS("l.sfeqi r%d, %d\n", ra, I16); | |
84775c43 | 1065 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1066 | break; |
1067 | ||
1068 | case 0x1: /* l.sfnei */ | |
1069 | LOG_DIS("l.sfnei r%d, %d\n", ra, I16); | |
84775c43 | 1070 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1071 | break; |
1072 | ||
1073 | case 0x2: /* l.sfgtui */ | |
1074 | LOG_DIS("l.sfgtui r%d, %d\n", ra, I16); | |
84775c43 | 1075 | tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1076 | break; |
1077 | ||
1078 | case 0x3: /* l.sfgeui */ | |
1079 | LOG_DIS("l.sfgeui r%d, %d\n", ra, I16); | |
84775c43 | 1080 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1081 | break; |
1082 | ||
1083 | case 0x4: /* l.sfltui */ | |
1084 | LOG_DIS("l.sfltui r%d, %d\n", ra, I16); | |
84775c43 | 1085 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1086 | break; |
1087 | ||
1088 | case 0x5: /* l.sfleui */ | |
1089 | LOG_DIS("l.sfleui r%d, %d\n", ra, I16); | |
84775c43 | 1090 | tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1091 | break; |
1092 | ||
1093 | case 0xa: /* l.sfgtsi */ | |
1094 | LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16); | |
84775c43 | 1095 | tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1096 | break; |
1097 | ||
1098 | case 0xb: /* l.sfgesi */ | |
1099 | LOG_DIS("l.sfgesi r%d, %d\n", ra, I16); | |
84775c43 | 1100 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1101 | break; |
1102 | ||
1103 | case 0xc: /* l.sfltsi */ | |
1104 | LOG_DIS("l.sfltsi r%d, %d\n", ra, I16); | |
84775c43 | 1105 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1106 | break; |
1107 | ||
1108 | case 0xd: /* l.sflesi */ | |
1109 | LOG_DIS("l.sflesi r%d, %d\n", ra, I16); | |
84775c43 | 1110 | tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1111 | break; |
1112 | ||
1113 | default: | |
1114 | gen_illegal_exception(dc); | |
1115 | break; | |
1116 | } | |
bbe418f2 JL |
1117 | } |
1118 | ||
1119 | static void dec_sys(DisasContext *dc, uint32_t insn) | |
1120 | { | |
1121 | uint32_t op0; | |
bbe418f2 | 1122 | uint32_t K16; |
111ece51 | 1123 | |
3d59b680 | 1124 | op0 = extract32(insn, 16, 10); |
bbe418f2 | 1125 | K16 = extract32(insn, 0, 16); |
bbe418f2 JL |
1126 | |
1127 | switch (op0) { | |
1128 | case 0x000: /* l.sys */ | |
1129 | LOG_DIS("l.sys %d\n", K16); | |
1130 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1131 | gen_exception(dc, EXCP_SYSCALL); | |
1132 | dc->is_jmp = DISAS_UPDATE; | |
1133 | break; | |
1134 | ||
1135 | case 0x100: /* l.trap */ | |
1136 | LOG_DIS("l.trap %d\n", K16); | |
1137 | #if defined(CONFIG_USER_ONLY) | |
1138 | return; | |
1139 | #else | |
1140 | if (dc->mem_idx == MMU_USER_IDX) { | |
1141 | gen_illegal_exception(dc); | |
1142 | return; | |
1143 | } | |
1144 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1145 | gen_exception(dc, EXCP_TRAP); | |
1146 | #endif | |
1147 | break; | |
1148 | ||
1149 | case 0x300: /* l.csync */ | |
1150 | LOG_DIS("l.csync\n"); | |
1151 | #if defined(CONFIG_USER_ONLY) | |
1152 | return; | |
1153 | #else | |
1154 | if (dc->mem_idx == MMU_USER_IDX) { | |
1155 | gen_illegal_exception(dc); | |
1156 | return; | |
1157 | } | |
1158 | #endif | |
1159 | break; | |
1160 | ||
1161 | case 0x200: /* l.msync */ | |
1162 | LOG_DIS("l.msync\n"); | |
1163 | #if defined(CONFIG_USER_ONLY) | |
1164 | return; | |
1165 | #else | |
1166 | if (dc->mem_idx == MMU_USER_IDX) { | |
1167 | gen_illegal_exception(dc); | |
1168 | return; | |
1169 | } | |
1170 | #endif | |
1171 | break; | |
1172 | ||
1173 | case 0x270: /* l.psync */ | |
1174 | LOG_DIS("l.psync\n"); | |
1175 | #if defined(CONFIG_USER_ONLY) | |
1176 | return; | |
1177 | #else | |
1178 | if (dc->mem_idx == MMU_USER_IDX) { | |
1179 | gen_illegal_exception(dc); | |
1180 | return; | |
1181 | } | |
1182 | #endif | |
1183 | break; | |
1184 | ||
1185 | default: | |
1186 | gen_illegal_exception(dc); | |
1187 | break; | |
1188 | } | |
1189 | } | |
1190 | ||
1191 | static void dec_float(DisasContext *dc, uint32_t insn) | |
1192 | { | |
1193 | uint32_t op0; | |
1194 | uint32_t ra, rb, rd; | |
1195 | op0 = extract32(insn, 0, 8); | |
1196 | ra = extract32(insn, 16, 5); | |
1197 | rb = extract32(insn, 11, 5); | |
1198 | rd = extract32(insn, 21, 5); | |
1199 | ||
1200 | switch (op0) { | |
1201 | case 0x00: /* lf.add.s */ | |
1202 | LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb); | |
1203 | gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1204 | break; | |
1205 | ||
1206 | case 0x01: /* lf.sub.s */ | |
1207 | LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb); | |
1208 | gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1209 | break; | |
1210 | ||
1211 | ||
1212 | case 0x02: /* lf.mul.s */ | |
1213 | LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb); | |
1214 | if (ra != 0 && rb != 0) { | |
1215 | gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1216 | } else { | |
1217 | tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF); | |
1218 | tcg_gen_movi_i32(cpu_R[rd], 0x0); | |
1219 | } | |
1220 | break; | |
1221 | ||
1222 | case 0x03: /* lf.div.s */ | |
1223 | LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb); | |
1224 | gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1225 | break; | |
1226 | ||
1227 | case 0x04: /* lf.itof.s */ | |
1228 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); | |
1229 | gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1230 | break; | |
1231 | ||
1232 | case 0x05: /* lf.ftoi.s */ | |
1233 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); | |
1234 | gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1235 | break; | |
1236 | ||
1237 | case 0x06: /* lf.rem.s */ | |
1238 | LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb); | |
1239 | gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1240 | break; | |
1241 | ||
1242 | case 0x07: /* lf.madd.s */ | |
1243 | LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); | |
1244 | gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1245 | break; | |
1246 | ||
1247 | case 0x08: /* lf.sfeq.s */ | |
1248 | LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); | |
84775c43 | 1249 | gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1250 | break; |
1251 | ||
1252 | case 0x09: /* lf.sfne.s */ | |
1253 | LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); | |
84775c43 | 1254 | gen_helper_float_ne_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1255 | break; |
1256 | ||
1257 | case 0x0a: /* lf.sfgt.s */ | |
1258 | LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); | |
84775c43 | 1259 | gen_helper_float_gt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1260 | break; |
1261 | ||
1262 | case 0x0b: /* lf.sfge.s */ | |
1263 | LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); | |
84775c43 | 1264 | gen_helper_float_ge_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1265 | break; |
1266 | ||
1267 | case 0x0c: /* lf.sflt.s */ | |
1268 | LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); | |
84775c43 | 1269 | gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1270 | break; |
1271 | ||
1272 | case 0x0d: /* lf.sfle.s */ | |
1273 | LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); | |
84775c43 | 1274 | gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1275 | break; |
1276 | ||
1277 | /* not used yet, open it when we need or64. */ | |
1278 | /*#ifdef TARGET_OPENRISC64 | |
1279 | case 0x10: lf.add.d | |
1280 | LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb); | |
1281 | check_of64s(dc); | |
1282 | gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1283 | break; | |
1284 | ||
1285 | case 0x11: lf.sub.d | |
1286 | LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb); | |
1287 | check_of64s(dc); | |
1288 | gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1289 | break; | |
1290 | ||
1291 | case 0x12: lf.mul.d | |
1292 | LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb); | |
1293 | check_of64s(dc); | |
1294 | if (ra != 0 && rb != 0) { | |
1295 | gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1296 | } else { | |
1297 | tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF); | |
1298 | tcg_gen_movi_i64(cpu_R[rd], 0x0); | |
1299 | } | |
1300 | break; | |
1301 | ||
1302 | case 0x13: lf.div.d | |
1303 | LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb); | |
1304 | check_of64s(dc); | |
1305 | gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1306 | break; | |
1307 | ||
1308 | case 0x14: lf.itof.d | |
1309 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); | |
1310 | check_of64s(dc); | |
1311 | gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1312 | break; | |
1313 | ||
1314 | case 0x15: lf.ftoi.d | |
1315 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); | |
1316 | check_of64s(dc); | |
1317 | gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1318 | break; | |
1319 | ||
1320 | case 0x16: lf.rem.d | |
1321 | LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb); | |
1322 | check_of64s(dc); | |
1323 | gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1324 | break; | |
1325 | ||
1326 | case 0x17: lf.madd.d | |
1327 | LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); | |
1328 | check_of64s(dc); | |
1329 | gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1330 | break; | |
1331 | ||
1332 | case 0x18: lf.sfeq.d | |
1333 | LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); | |
1334 | check_of64s(dc); | |
84775c43 | 1335 | gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1336 | break; |
1337 | ||
1338 | case 0x1a: lf.sfgt.d | |
1339 | LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); | |
1340 | check_of64s(dc); | |
84775c43 | 1341 | gen_helper_float_gt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1342 | break; |
1343 | ||
1344 | case 0x1b: lf.sfge.d | |
1345 | LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); | |
1346 | check_of64s(dc); | |
84775c43 | 1347 | gen_helper_float_ge_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1348 | break; |
1349 | ||
1350 | case 0x19: lf.sfne.d | |
1351 | LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); | |
1352 | check_of64s(dc); | |
84775c43 | 1353 | gen_helper_float_ne_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1354 | break; |
1355 | ||
1356 | case 0x1c: lf.sflt.d | |
1357 | LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); | |
1358 | check_of64s(dc); | |
84775c43 | 1359 | gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1360 | break; |
1361 | ||
1362 | case 0x1d: lf.sfle.d | |
1363 | LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); | |
1364 | check_of64s(dc); | |
84775c43 | 1365 | gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1366 | break; |
1367 | #endif*/ | |
1368 | ||
1369 | default: | |
1370 | gen_illegal_exception(dc); | |
1371 | break; | |
1372 | } | |
bbe418f2 JL |
1373 | } |
1374 | ||
1375 | static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) | |
1376 | { | |
1377 | uint32_t op0; | |
1378 | uint32_t insn; | |
1379 | insn = cpu_ldl_code(&cpu->env, dc->pc); | |
1380 | op0 = extract32(insn, 26, 6); | |
1381 | ||
1382 | switch (op0) { | |
1383 | case 0x06: | |
1384 | dec_M(dc, insn); | |
1385 | break; | |
1386 | ||
1387 | case 0x08: | |
1388 | dec_sys(dc, insn); | |
1389 | break; | |
1390 | ||
1391 | case 0x2e: | |
1392 | dec_logic(dc, insn); | |
1393 | break; | |
1394 | ||
1395 | case 0x2f: | |
1396 | dec_compi(dc, insn); | |
1397 | break; | |
1398 | ||
1399 | case 0x31: | |
1400 | dec_mac(dc, insn); | |
1401 | break; | |
1402 | ||
1403 | case 0x32: | |
1404 | dec_float(dc, insn); | |
1405 | break; | |
1406 | ||
1407 | case 0x38: | |
1408 | dec_calc(dc, insn); | |
1409 | break; | |
1410 | ||
1411 | case 0x39: | |
1412 | dec_comp(dc, insn); | |
1413 | break; | |
1414 | ||
1415 | default: | |
1416 | dec_misc(dc, insn); | |
1417 | break; | |
1418 | } | |
1419 | } | |
1420 | ||
4e5e1215 | 1421 | void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) |
e67db06e | 1422 | { |
4e5e1215 | 1423 | OpenRISCCPU *cpu = openrisc_env_get_cpu(env); |
ed2803da | 1424 | CPUState *cs = CPU(cpu); |
bbe418f2 | 1425 | struct DisasContext ctx, *dc = &ctx; |
bbe418f2 | 1426 | uint32_t pc_start; |
bbe418f2 JL |
1427 | uint32_t next_page_start; |
1428 | int num_insns; | |
1429 | int max_insns; | |
1430 | ||
bbe418f2 JL |
1431 | pc_start = tb->pc; |
1432 | dc->tb = tb; | |
1433 | ||
bbe418f2 JL |
1434 | dc->is_jmp = DISAS_NEXT; |
1435 | dc->ppc = pc_start; | |
1436 | dc->pc = pc_start; | |
1437 | dc->flags = cpu->env.cpucfgr; | |
97ed5ccd | 1438 | dc->mem_idx = cpu_mmu_index(&cpu->env, false); |
bbe418f2 | 1439 | dc->synced_flags = dc->tb_flags = tb->flags; |
0c53d734 | 1440 | dc->delayed_branch = (dc->tb_flags & D_FLAG) != 0; |
ed2803da | 1441 | dc->singlestep_enabled = cs->singlestep_enabled; |
bbe418f2 JL |
1442 | |
1443 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
bbe418f2 JL |
1444 | num_insns = 0; |
1445 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1446 | ||
1447 | if (max_insns == 0) { | |
1448 | max_insns = CF_COUNT_MASK; | |
1449 | } | |
190ce7fb RH |
1450 | if (max_insns > TCG_MAX_INSNS) { |
1451 | max_insns = TCG_MAX_INSNS; | |
1452 | } | |
bbe418f2 | 1453 | |
111ece51 RH |
1454 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
1455 | && qemu_log_in_addr_range(pc_start)) { | |
1456 | qemu_log_lock(); | |
1457 | qemu_log("----------------\n"); | |
1458 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
1459 | } | |
1460 | ||
cd42d5b2 | 1461 | gen_tb_start(tb); |
bbe418f2 JL |
1462 | |
1463 | do { | |
667b8e29 | 1464 | tcg_gen_insn_start(dc->pc); |
959082fc | 1465 | num_insns++; |
bbe418f2 | 1466 | |
b933066a RH |
1467 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
1468 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1469 | gen_exception(dc, EXCP_DEBUG); | |
1470 | dc->is_jmp = DISAS_UPDATE; | |
522a0d4e RH |
1471 | /* The address covered by the breakpoint must be included in |
1472 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
1473 | properly cleared -- thus we increment the PC here so that | |
1474 | the logic setting tb->size below does the right thing. */ | |
1475 | dc->pc += 4; | |
b933066a RH |
1476 | break; |
1477 | } | |
1478 | ||
959082fc | 1479 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
bbe418f2 JL |
1480 | gen_io_start(); |
1481 | } | |
1482 | dc->ppc = dc->pc - 4; | |
1483 | dc->npc = dc->pc + 4; | |
1484 | tcg_gen_movi_tl(cpu_ppc, dc->ppc); | |
1485 | tcg_gen_movi_tl(cpu_npc, dc->npc); | |
1486 | disas_openrisc_insn(dc, cpu); | |
1487 | dc->pc = dc->npc; | |
bbe418f2 JL |
1488 | /* delay slot */ |
1489 | if (dc->delayed_branch) { | |
1490 | dc->delayed_branch--; | |
1491 | if (!dc->delayed_branch) { | |
1492 | dc->tb_flags &= ~D_FLAG; | |
1493 | gen_sync_flags(dc); | |
1494 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
1495 | tcg_gen_mov_tl(cpu_npc, jmp_pc); | |
1496 | tcg_gen_movi_tl(jmp_pc, 0); | |
1497 | tcg_gen_exit_tb(0); | |
1498 | dc->is_jmp = DISAS_JUMP; | |
1499 | break; | |
1500 | } | |
1501 | } | |
1502 | } while (!dc->is_jmp | |
fe700adb | 1503 | && !tcg_op_buf_full() |
ed2803da | 1504 | && !cs->singlestep_enabled |
bbe418f2 JL |
1505 | && !singlestep |
1506 | && (dc->pc < next_page_start) | |
1507 | && num_insns < max_insns); | |
1508 | ||
1509 | if (tb->cflags & CF_LAST_IO) { | |
1510 | gen_io_end(); | |
1511 | } | |
1512 | if (dc->is_jmp == DISAS_NEXT) { | |
1513 | dc->is_jmp = DISAS_UPDATE; | |
1514 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1515 | } | |
ed2803da | 1516 | if (unlikely(cs->singlestep_enabled)) { |
bbe418f2 JL |
1517 | if (dc->is_jmp == DISAS_NEXT) { |
1518 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1519 | } | |
1520 | gen_exception(dc, EXCP_DEBUG); | |
1521 | } else { | |
1522 | switch (dc->is_jmp) { | |
1523 | case DISAS_NEXT: | |
1524 | gen_goto_tb(dc, 0, dc->pc); | |
1525 | break; | |
1526 | default: | |
1527 | case DISAS_JUMP: | |
1528 | break; | |
1529 | case DISAS_UPDATE: | |
1530 | /* indicate that the hash table must be used | |
1531 | to find the next TB */ | |
1532 | tcg_gen_exit_tb(0); | |
1533 | break; | |
1534 | case DISAS_TB_JUMP: | |
1535 | /* nothing more to generate */ | |
1536 | break; | |
1537 | } | |
1538 | } | |
1539 | ||
806f352d | 1540 | gen_tb_end(tb, num_insns); |
0a7df5da | 1541 | |
4e5e1215 RH |
1542 | tb->size = dc->pc - pc_start; |
1543 | tb->icount = num_insns; | |
bbe418f2 | 1544 | |
4910e6e4 RH |
1545 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
1546 | && qemu_log_in_addr_range(pc_start)) { | |
111ece51 RH |
1547 | log_target_disas(cs, pc_start, tb->size, 0); |
1548 | qemu_log("\n"); | |
1ee73216 | 1549 | qemu_log_unlock(); |
bbe418f2 | 1550 | } |
e67db06e JL |
1551 | } |
1552 | ||
878096ee AF |
1553 | void openrisc_cpu_dump_state(CPUState *cs, FILE *f, |
1554 | fprintf_function cpu_fprintf, | |
1555 | int flags) | |
e67db06e | 1556 | { |
878096ee AF |
1557 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
1558 | CPUOpenRISCState *env = &cpu->env; | |
e67db06e | 1559 | int i; |
878096ee | 1560 | |
e67db06e JL |
1561 | cpu_fprintf(f, "PC=%08x\n", env->pc); |
1562 | for (i = 0; i < 32; ++i) { | |
878096ee | 1563 | cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i], |
e67db06e JL |
1564 | (i % 4) == 3 ? '\n' : ' '); |
1565 | } | |
1566 | } | |
1567 | ||
1568 | void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, | |
bad729e2 | 1569 | target_ulong *data) |
e67db06e | 1570 | { |
bad729e2 | 1571 | env->pc = data[0]; |
e67db06e | 1572 | } |