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e67db06e JL |
1 | /* |
2 | * OpenRISC translation | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Feng Gao <gf91597@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
e67db06e | 22 | #include "cpu.h" |
022c62cb | 23 | #include "exec/exec-all.h" |
76cad711 | 24 | #include "disas/disas.h" |
e67db06e JL |
25 | #include "tcg-op.h" |
26 | #include "qemu-common.h" | |
1de7afc9 | 27 | #include "qemu/log.h" |
1de7afc9 | 28 | #include "qemu/bitops.h" |
f08b6170 | 29 | #include "exec/cpu_ldst.h" |
77fc6f5e | 30 | #include "exec/translator.h" |
bbe418f2 | 31 | |
2ef6175a RH |
32 | #include "exec/helper-proto.h" |
33 | #include "exec/helper-gen.h" | |
7de9729f | 34 | #include "exec/gen-icount.h" |
e67db06e | 35 | |
a7e30d84 | 36 | #include "trace-tcg.h" |
508127e2 | 37 | #include "exec/log.h" |
a7e30d84 | 38 | |
111ece51 | 39 | #define LOG_DIS(str, ...) \ |
1ffa4bce EC |
40 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \ |
41 | ## __VA_ARGS__) | |
e67db06e | 42 | |
77fc6f5e LV |
43 | /* is_jmp field values */ |
44 | #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ | |
45 | #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ | |
46 | #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ | |
47 | ||
bbe418f2 | 48 | typedef struct DisasContext { |
1ffa4bce | 49 | DisasContextBase base; |
bbe418f2 | 50 | uint32_t mem_idx; |
a01deb36 | 51 | uint32_t tb_flags; |
bbe418f2 JL |
52 | uint32_t delayed_branch; |
53 | } DisasContext; | |
54 | ||
7de9729f RH |
55 | /* Include the auto-generated decoder. */ |
56 | #include "decode.inc.c" | |
57 | ||
bbe418f2 JL |
58 | static TCGv cpu_sr; |
59 | static TCGv cpu_R[32]; | |
6597c28d | 60 | static TCGv cpu_R0; |
bbe418f2 JL |
61 | static TCGv cpu_pc; |
62 | static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ | |
bbe418f2 | 63 | static TCGv cpu_ppc; |
84775c43 | 64 | static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ |
97458071 RH |
65 | static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ |
66 | static TCGv cpu_sr_ov; /* signed overflow */ | |
930c3d00 RH |
67 | static TCGv cpu_lock_addr; |
68 | static TCGv cpu_lock_value; | |
bbe418f2 | 69 | static TCGv_i32 fpcsr; |
6f7332ba | 70 | static TCGv_i64 cpu_mac; /* MACHI:MACLO */ |
a01deb36 | 71 | static TCGv_i32 cpu_dflag; |
bbe418f2 | 72 | |
e67db06e JL |
73 | void openrisc_translate_init(void) |
74 | { | |
bbe418f2 JL |
75 | static const char * const regnames[] = { |
76 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
77 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
78 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
79 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
80 | }; | |
81 | int i; | |
82 | ||
e1ccc054 | 83 | cpu_sr = tcg_global_mem_new(cpu_env, |
bbe418f2 | 84 | offsetof(CPUOpenRISCState, sr), "sr"); |
a01deb36 RH |
85 | cpu_dflag = tcg_global_mem_new_i32(cpu_env, |
86 | offsetof(CPUOpenRISCState, dflag), | |
87 | "dflag"); | |
e1ccc054 | 88 | cpu_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 89 | offsetof(CPUOpenRISCState, pc), "pc"); |
e1ccc054 | 90 | cpu_ppc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 91 | offsetof(CPUOpenRISCState, ppc), "ppc"); |
e1ccc054 | 92 | jmp_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 93 | offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); |
84775c43 RH |
94 | cpu_sr_f = tcg_global_mem_new(cpu_env, |
95 | offsetof(CPUOpenRISCState, sr_f), "sr_f"); | |
97458071 RH |
96 | cpu_sr_cy = tcg_global_mem_new(cpu_env, |
97 | offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); | |
98 | cpu_sr_ov = tcg_global_mem_new(cpu_env, | |
99 | offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); | |
930c3d00 RH |
100 | cpu_lock_addr = tcg_global_mem_new(cpu_env, |
101 | offsetof(CPUOpenRISCState, lock_addr), | |
102 | "lock_addr"); | |
103 | cpu_lock_value = tcg_global_mem_new(cpu_env, | |
104 | offsetof(CPUOpenRISCState, lock_value), | |
105 | "lock_value"); | |
e1ccc054 | 106 | fpcsr = tcg_global_mem_new_i32(cpu_env, |
bbe418f2 JL |
107 | offsetof(CPUOpenRISCState, fpcsr), |
108 | "fpcsr"); | |
6f7332ba RH |
109 | cpu_mac = tcg_global_mem_new_i64(cpu_env, |
110 | offsetof(CPUOpenRISCState, mac), | |
111 | "mac"); | |
bbe418f2 | 112 | for (i = 0; i < 32; i++) { |
e1ccc054 | 113 | cpu_R[i] = tcg_global_mem_new(cpu_env, |
d89e71e8 SH |
114 | offsetof(CPUOpenRISCState, |
115 | shadow_gpr[0][i]), | |
bbe418f2 JL |
116 | regnames[i]); |
117 | } | |
6597c28d | 118 | cpu_R0 = cpu_R[0]; |
bbe418f2 JL |
119 | } |
120 | ||
bbe418f2 JL |
121 | static void gen_exception(DisasContext *dc, unsigned int excp) |
122 | { | |
123 | TCGv_i32 tmp = tcg_const_i32(excp); | |
124 | gen_helper_exception(cpu_env, tmp); | |
125 | tcg_temp_free_i32(tmp); | |
126 | } | |
127 | ||
128 | static void gen_illegal_exception(DisasContext *dc) | |
129 | { | |
1ffa4bce | 130 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); |
bbe418f2 | 131 | gen_exception(dc, EXCP_ILLEGAL); |
1ffa4bce | 132 | dc->base.is_jmp = DISAS_NORETURN; |
bbe418f2 JL |
133 | } |
134 | ||
135 | /* not used yet, open it when we need or64. */ | |
136 | /*#ifdef TARGET_OPENRISC64 | |
137 | static void check_ob64s(DisasContext *dc) | |
138 | { | |
139 | if (!(dc->flags & CPUCFGR_OB64S)) { | |
140 | gen_illegal_exception(dc); | |
141 | } | |
142 | } | |
143 | ||
144 | static void check_of64s(DisasContext *dc) | |
145 | { | |
146 | if (!(dc->flags & CPUCFGR_OF64S)) { | |
147 | gen_illegal_exception(dc); | |
148 | } | |
149 | } | |
150 | ||
151 | static void check_ov64s(DisasContext *dc) | |
152 | { | |
153 | if (!(dc->flags & CPUCFGR_OV64S)) { | |
154 | gen_illegal_exception(dc); | |
155 | } | |
156 | } | |
157 | #endif*/ | |
158 | ||
6597c28d RH |
159 | /* We're about to write to REG. On the off-chance that the user is |
160 | writing to R0, re-instate the architectural register. */ | |
161 | #define check_r0_write(reg) \ | |
162 | do { \ | |
163 | if (unlikely(reg == 0)) { \ | |
164 | cpu_R[0] = cpu_R0; \ | |
165 | } \ | |
166 | } while (0) | |
167 | ||
90aa39a1 SF |
168 | static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) |
169 | { | |
1ffa4bce | 170 | if (unlikely(dc->base.singlestep_enabled)) { |
90aa39a1 SF |
171 | return false; |
172 | } | |
173 | ||
174 | #ifndef CONFIG_USER_ONLY | |
1ffa4bce | 175 | return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
90aa39a1 SF |
176 | #else |
177 | return true; | |
178 | #endif | |
179 | } | |
180 | ||
bbe418f2 JL |
181 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
182 | { | |
90aa39a1 | 183 | if (use_goto_tb(dc, dest)) { |
bbe418f2 JL |
184 | tcg_gen_movi_tl(cpu_pc, dest); |
185 | tcg_gen_goto_tb(n); | |
1ffa4bce | 186 | tcg_gen_exit_tb((uintptr_t)dc->base.tb + n); |
bbe418f2 JL |
187 | } else { |
188 | tcg_gen_movi_tl(cpu_pc, dest); | |
1ffa4bce | 189 | if (dc->base.singlestep_enabled) { |
bbe418f2 JL |
190 | gen_exception(dc, EXCP_DEBUG); |
191 | } | |
192 | tcg_gen_exit_tb(0); | |
193 | } | |
194 | } | |
195 | ||
6da544a6 | 196 | static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0) |
bbe418f2 | 197 | { |
1ffa4bce | 198 | target_ulong tmp_pc = dc->base.pc_next + n26 * 4; |
bbe418f2 | 199 | |
da1d7759 SM |
200 | switch (op0) { |
201 | case 0x00: /* l.j */ | |
bbe418f2 | 202 | tcg_gen_movi_tl(jmp_pc, tmp_pc); |
da1d7759 SM |
203 | break; |
204 | case 0x01: /* l.jal */ | |
1ffa4bce | 205 | tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8); |
a8000cb4 | 206 | /* Optimize jal being used to load the PC for PIC. */ |
1ffa4bce | 207 | if (tmp_pc == dc->base.pc_next + 8) { |
a8000cb4 RH |
208 | return; |
209 | } | |
bbe418f2 | 210 | tcg_gen_movi_tl(jmp_pc, tmp_pc); |
da1d7759 SM |
211 | break; |
212 | case 0x03: /* l.bnf */ | |
213 | case 0x04: /* l.bf */ | |
214 | { | |
1ffa4bce | 215 | TCGv t_next = tcg_const_tl(dc->base.pc_next + 8); |
784696d1 RH |
216 | TCGv t_true = tcg_const_tl(tmp_pc); |
217 | TCGv t_zero = tcg_const_tl(0); | |
218 | ||
219 | tcg_gen_movcond_tl(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE, | |
220 | jmp_pc, cpu_sr_f, t_zero, t_true, t_next); | |
221 | ||
222 | tcg_temp_free(t_next); | |
223 | tcg_temp_free(t_true); | |
224 | tcg_temp_free(t_zero); | |
da1d7759 SM |
225 | } |
226 | break; | |
227 | case 0x11: /* l.jr */ | |
bbe418f2 | 228 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); |
da1d7759 SM |
229 | break; |
230 | case 0x12: /* l.jalr */ | |
1ffa4bce | 231 | tcg_gen_movi_tl(cpu_R[9], (dc->base.pc_next + 8)); |
bbe418f2 | 232 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); |
da1d7759 SM |
233 | break; |
234 | default: | |
bbe418f2 | 235 | gen_illegal_exception(dc); |
da1d7759 | 236 | break; |
bbe418f2 JL |
237 | } |
238 | ||
bbe418f2 | 239 | dc->delayed_branch = 2; |
bbe418f2 JL |
240 | } |
241 | ||
97458071 | 242 | static void gen_ove_cy(DisasContext *dc) |
9ecaa27e | 243 | { |
0c53d734 | 244 | if (dc->tb_flags & SR_OVE) { |
97458071 | 245 | gen_helper_ove_cy(cpu_env); |
0c53d734 | 246 | } |
9ecaa27e RH |
247 | } |
248 | ||
97458071 | 249 | static void gen_ove_ov(DisasContext *dc) |
9ecaa27e | 250 | { |
0c53d734 | 251 | if (dc->tb_flags & SR_OVE) { |
97458071 | 252 | gen_helper_ove_ov(cpu_env); |
0c53d734 | 253 | } |
9ecaa27e RH |
254 | } |
255 | ||
97458071 | 256 | static void gen_ove_cyov(DisasContext *dc) |
9ecaa27e | 257 | { |
0c53d734 | 258 | if (dc->tb_flags & SR_OVE) { |
97458071 | 259 | gen_helper_ove_cyov(cpu_env); |
0c53d734 | 260 | } |
9ecaa27e RH |
261 | } |
262 | ||
263 | static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
264 | { | |
265 | TCGv t0 = tcg_const_tl(0); | |
266 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 267 | |
97458071 RH |
268 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); |
269 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 270 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 271 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
272 | tcg_temp_free(t0); |
273 | ||
274 | tcg_gen_mov_tl(dest, res); | |
275 | tcg_temp_free(res); | |
276 | ||
97458071 | 277 | gen_ove_cyov(dc); |
9ecaa27e RH |
278 | } |
279 | ||
280 | static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
281 | { | |
282 | TCGv t0 = tcg_const_tl(0); | |
283 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 284 | |
97458071 RH |
285 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); |
286 | tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); | |
287 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 288 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 289 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
290 | tcg_temp_free(t0); |
291 | ||
292 | tcg_gen_mov_tl(dest, res); | |
293 | tcg_temp_free(res); | |
294 | ||
97458071 | 295 | gen_ove_cyov(dc); |
9ecaa27e RH |
296 | } |
297 | ||
298 | static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
299 | { | |
300 | TCGv res = tcg_temp_new(); | |
9ecaa27e RH |
301 | |
302 | tcg_gen_sub_tl(res, srca, srcb); | |
97458071 RH |
303 | tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); |
304 | tcg_gen_xor_tl(cpu_sr_ov, res, srcb); | |
305 | tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); | |
306 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); | |
9ecaa27e RH |
307 | |
308 | tcg_gen_mov_tl(dest, res); | |
309 | tcg_temp_free(res); | |
310 | ||
97458071 | 311 | gen_ove_cyov(dc); |
9ecaa27e RH |
312 | } |
313 | ||
314 | static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
315 | { | |
9ecaa27e RH |
316 | TCGv t0 = tcg_temp_new(); |
317 | ||
97458071 | 318 | tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); |
9ecaa27e | 319 | tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); |
97458071 | 320 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); |
9ecaa27e RH |
321 | tcg_temp_free(t0); |
322 | ||
97458071 RH |
323 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
324 | gen_ove_ov(dc); | |
9ecaa27e RH |
325 | } |
326 | ||
327 | static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
328 | { | |
97458071 RH |
329 | tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); |
330 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); | |
9ecaa27e | 331 | |
97458071 | 332 | gen_ove_cy(dc); |
9ecaa27e RH |
333 | } |
334 | ||
335 | static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
336 | { | |
9ecaa27e RH |
337 | TCGv t0 = tcg_temp_new(); |
338 | ||
97458071 | 339 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); |
9ecaa27e RH |
340 | /* The result of divide-by-zero is undefined. |
341 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 342 | tcg_gen_or_tl(t0, srcb, cpu_sr_ov); |
9ecaa27e RH |
343 | tcg_gen_div_tl(dest, srca, t0); |
344 | tcg_temp_free(t0); | |
345 | ||
97458071 RH |
346 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
347 | gen_ove_ov(dc); | |
9ecaa27e RH |
348 | } |
349 | ||
350 | static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
351 | { | |
9ecaa27e RH |
352 | TCGv t0 = tcg_temp_new(); |
353 | ||
97458071 | 354 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); |
9ecaa27e RH |
355 | /* The result of divide-by-zero is undefined. |
356 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 357 | tcg_gen_or_tl(t0, srcb, cpu_sr_cy); |
9ecaa27e RH |
358 | tcg_gen_divu_tl(dest, srca, t0); |
359 | tcg_temp_free(t0); | |
360 | ||
97458071 | 361 | gen_ove_cy(dc); |
9ecaa27e | 362 | } |
da1d7759 | 363 | |
cc5de49e RH |
364 | static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) |
365 | { | |
366 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
367 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
368 | ||
369 | tcg_gen_ext_tl_i64(t1, srca); | |
370 | tcg_gen_ext_tl_i64(t2, srcb); | |
371 | if (TARGET_LONG_BITS == 32) { | |
372 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
373 | tcg_gen_movi_tl(cpu_sr_ov, 0); | |
374 | } else { | |
375 | TCGv_i64 high = tcg_temp_new_i64(); | |
376 | ||
377 | tcg_gen_muls2_i64(cpu_mac, high, t1, t2); | |
378 | tcg_gen_sari_i64(t1, cpu_mac, 63); | |
379 | tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high); | |
380 | tcg_temp_free_i64(high); | |
381 | tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); | |
382 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); | |
383 | ||
384 | gen_ove_ov(dc); | |
385 | } | |
386 | tcg_temp_free_i64(t1); | |
387 | tcg_temp_free_i64(t2); | |
388 | } | |
389 | ||
390 | static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) | |
391 | { | |
392 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
393 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
394 | ||
395 | tcg_gen_extu_tl_i64(t1, srca); | |
396 | tcg_gen_extu_tl_i64(t2, srcb); | |
397 | if (TARGET_LONG_BITS == 32) { | |
398 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
399 | tcg_gen_movi_tl(cpu_sr_cy, 0); | |
400 | } else { | |
401 | TCGv_i64 high = tcg_temp_new_i64(); | |
402 | ||
403 | tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); | |
404 | tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); | |
405 | tcg_gen_trunc_i64_tl(cpu_sr_cy, high); | |
406 | tcg_temp_free_i64(high); | |
407 | ||
408 | gen_ove_cy(dc); | |
409 | } | |
410 | tcg_temp_free_i64(t1); | |
411 | tcg_temp_free_i64(t2); | |
412 | } | |
413 | ||
6f7332ba RH |
414 | static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) |
415 | { | |
416 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
417 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
418 | ||
419 | tcg_gen_ext_tl_i64(t1, srca); | |
420 | tcg_gen_ext_tl_i64(t2, srcb); | |
421 | tcg_gen_mul_i64(t1, t1, t2); | |
422 | ||
423 | /* Note that overflow is only computed during addition stage. */ | |
424 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
425 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
426 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
427 | tcg_gen_andc_i64(t1, t1, t2); | |
428 | tcg_temp_free_i64(t2); | |
429 | ||
430 | #if TARGET_LONG_BITS == 32 | |
431 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
432 | #else | |
433 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
434 | #endif | |
435 | tcg_temp_free_i64(t1); | |
436 | ||
437 | gen_ove_ov(dc); | |
438 | } | |
439 | ||
cc5de49e RH |
440 | static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb) |
441 | { | |
442 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
443 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
444 | ||
445 | tcg_gen_extu_tl_i64(t1, srca); | |
446 | tcg_gen_extu_tl_i64(t2, srcb); | |
447 | tcg_gen_mul_i64(t1, t1, t2); | |
448 | tcg_temp_free_i64(t2); | |
449 | ||
450 | /* Note that overflow is only computed during addition stage. */ | |
451 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
452 | tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); | |
453 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); | |
454 | tcg_temp_free_i64(t1); | |
455 | ||
456 | gen_ove_cy(dc); | |
457 | } | |
458 | ||
6f7332ba RH |
459 | static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb) |
460 | { | |
461 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
462 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
463 | ||
464 | tcg_gen_ext_tl_i64(t1, srca); | |
465 | tcg_gen_ext_tl_i64(t2, srcb); | |
466 | tcg_gen_mul_i64(t1, t1, t2); | |
467 | ||
468 | /* Note that overflow is only computed during subtraction stage. */ | |
469 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
470 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
471 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
472 | tcg_gen_and_i64(t1, t1, t2); | |
473 | tcg_temp_free_i64(t2); | |
474 | ||
475 | #if TARGET_LONG_BITS == 32 | |
476 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
477 | #else | |
478 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
479 | #endif | |
480 | tcg_temp_free_i64(t1); | |
481 | ||
482 | gen_ove_ov(dc); | |
483 | } | |
484 | ||
cc5de49e RH |
485 | static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) |
486 | { | |
487 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
488 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
489 | ||
490 | tcg_gen_extu_tl_i64(t1, srca); | |
491 | tcg_gen_extu_tl_i64(t2, srcb); | |
492 | tcg_gen_mul_i64(t1, t1, t2); | |
493 | ||
494 | /* Note that overflow is only computed during subtraction stage. */ | |
495 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); | |
496 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
497 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); | |
498 | tcg_temp_free_i64(t2); | |
499 | tcg_temp_free_i64(t1); | |
500 | ||
501 | gen_ove_cy(dc); | |
502 | } | |
503 | ||
930c3d00 RH |
504 | static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) |
505 | { | |
506 | TCGv ea = tcg_temp_new(); | |
507 | ||
508 | tcg_gen_addi_tl(ea, ra, ofs); | |
509 | tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL); | |
510 | tcg_gen_mov_tl(cpu_lock_addr, ea); | |
511 | tcg_gen_mov_tl(cpu_lock_value, rd); | |
512 | tcg_temp_free(ea); | |
513 | } | |
514 | ||
6597c28d | 515 | static void gen_swa(DisasContext *dc, int b, TCGv ra, int32_t ofs) |
930c3d00 RH |
516 | { |
517 | TCGv ea, val; | |
518 | TCGLabel *lab_fail, *lab_done; | |
519 | ||
520 | ea = tcg_temp_new(); | |
521 | tcg_gen_addi_tl(ea, ra, ofs); | |
522 | ||
6597c28d RH |
523 | /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned |
524 | to cpu_R[0]. Since l.swa is quite often immediately followed by a | |
525 | branch, don't bother reallocating; finish the TB using the "real" R0. | |
526 | This also takes care of RB input across the branch. */ | |
527 | cpu_R[0] = cpu_R0; | |
528 | ||
930c3d00 RH |
529 | lab_fail = gen_new_label(); |
530 | lab_done = gen_new_label(); | |
531 | tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); | |
532 | tcg_temp_free(ea); | |
533 | ||
534 | val = tcg_temp_new(); | |
535 | tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, | |
6597c28d | 536 | cpu_R[b], dc->mem_idx, MO_TEUL); |
84775c43 | 537 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); |
930c3d00 RH |
538 | tcg_temp_free(val); |
539 | ||
540 | tcg_gen_br(lab_done); | |
541 | ||
542 | gen_set_label(lab_fail); | |
84775c43 | 543 | tcg_gen_movi_tl(cpu_sr_f, 0); |
930c3d00 RH |
544 | |
545 | gen_set_label(lab_done); | |
546 | tcg_gen_movi_tl(cpu_lock_addr, -1); | |
930c3d00 RH |
547 | } |
548 | ||
bbe418f2 JL |
549 | static void dec_calc(DisasContext *dc, uint32_t insn) |
550 | { | |
551 | uint32_t op0, op1, op2; | |
552 | uint32_t ra, rb, rd; | |
553 | op0 = extract32(insn, 0, 4); | |
554 | op1 = extract32(insn, 8, 2); | |
555 | op2 = extract32(insn, 6, 2); | |
556 | ra = extract32(insn, 16, 5); | |
557 | rb = extract32(insn, 11, 5); | |
558 | rd = extract32(insn, 21, 5); | |
559 | ||
cf2ae442 RH |
560 | switch (op1) { |
561 | case 0: | |
562 | switch (op0) { | |
563 | case 0x0: /* l.add */ | |
bbe418f2 | 564 | LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 565 | gen_add(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 566 | return; |
bbe418f2 | 567 | |
cf2ae442 | 568 | case 0x1: /* l.addc */ |
bbe418f2 | 569 | LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 570 | gen_addc(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 571 | return; |
bbe418f2 | 572 | |
cf2ae442 | 573 | case 0x2: /* l.sub */ |
bbe418f2 | 574 | LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 575 | gen_sub(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 576 | return; |
bbe418f2 | 577 | |
cf2ae442 | 578 | case 0x3: /* l.and */ |
bbe418f2 JL |
579 | LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb); |
580 | tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 581 | return; |
bbe418f2 | 582 | |
cf2ae442 | 583 | case 0x4: /* l.or */ |
bbe418f2 JL |
584 | LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb); |
585 | tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 586 | return; |
bbe418f2 | 587 | |
cf2ae442 | 588 | case 0x5: /* l.xor */ |
bbe418f2 JL |
589 | LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb); |
590 | tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 591 | return; |
bbe418f2 | 592 | |
cf2ae442 RH |
593 | case 0x8: |
594 | switch (op2) { | |
595 | case 0: /* l.sll */ | |
596 | LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb); | |
597 | tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
598 | return; | |
599 | case 1: /* l.srl */ | |
600 | LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb); | |
601 | tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
602 | return; | |
603 | case 2: /* l.sra */ | |
604 | LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb); | |
605 | tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
606 | return; | |
607 | case 3: /* l.ror */ | |
608 | LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb); | |
609 | tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
610 | return; | |
611 | } | |
bbe418f2 | 612 | break; |
bbe418f2 | 613 | |
cf2ae442 RH |
614 | case 0xc: |
615 | switch (op2) { | |
616 | case 0: /* l.exths */ | |
617 | LOG_DIS("l.exths r%d, r%d\n", rd, ra); | |
618 | tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]); | |
619 | return; | |
620 | case 1: /* l.extbs */ | |
621 | LOG_DIS("l.extbs r%d, r%d\n", rd, ra); | |
622 | tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]); | |
623 | return; | |
624 | case 2: /* l.exthz */ | |
625 | LOG_DIS("l.exthz r%d, r%d\n", rd, ra); | |
626 | tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]); | |
627 | return; | |
628 | case 3: /* l.extbz */ | |
629 | LOG_DIS("l.extbz r%d, r%d\n", rd, ra); | |
630 | tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]); | |
631 | return; | |
632 | } | |
bbe418f2 JL |
633 | break; |
634 | ||
cf2ae442 RH |
635 | case 0xd: |
636 | switch (op2) { | |
637 | case 0: /* l.extws */ | |
638 | LOG_DIS("l.extws r%d, r%d\n", rd, ra); | |
639 | tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]); | |
640 | return; | |
641 | case 1: /* l.extwz */ | |
642 | LOG_DIS("l.extwz r%d, r%d\n", rd, ra); | |
643 | tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]); | |
644 | return; | |
645 | } | |
bbe418f2 | 646 | break; |
bbe418f2 | 647 | |
cf2ae442 | 648 | case 0xe: /* l.cmov */ |
bbe418f2 JL |
649 | LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb); |
650 | { | |
784696d1 RH |
651 | TCGv zero = tcg_const_tl(0); |
652 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[rd], cpu_sr_f, zero, | |
653 | cpu_R[ra], cpu_R[rb]); | |
654 | tcg_temp_free(zero); | |
bbe418f2 | 655 | } |
cf2ae442 | 656 | return; |
bbe418f2 | 657 | |
cf2ae442 | 658 | case 0xf: /* l.ff1 */ |
bbe418f2 | 659 | LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); |
555baef8 RH |
660 | tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1); |
661 | tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1); | |
cf2ae442 RH |
662 | return; |
663 | } | |
664 | break; | |
665 | ||
666 | case 1: | |
667 | switch (op0) { | |
668 | case 0xf: /* l.fl1 */ | |
bbe418f2 | 669 | LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); |
555baef8 RH |
670 | tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS); |
671 | tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]); | |
cf2ae442 | 672 | return; |
bbe418f2 JL |
673 | } |
674 | break; | |
675 | ||
cf2ae442 | 676 | case 2: |
bbe418f2 JL |
677 | break; |
678 | ||
cf2ae442 RH |
679 | case 3: |
680 | switch (op0) { | |
681 | case 0x6: /* l.mul */ | |
682 | LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb); | |
683 | gen_mul(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
684 | return; | |
bbe418f2 | 685 | |
cc5de49e RH |
686 | case 0x7: /* l.muld */ |
687 | LOG_DIS("l.muld r%d, r%d\n", ra, rb); | |
688 | gen_muld(dc, cpu_R[ra], cpu_R[rb]); | |
689 | break; | |
690 | ||
cf2ae442 RH |
691 | case 0x9: /* l.div */ |
692 | LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb); | |
693 | gen_div(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
694 | return; | |
bbe418f2 | 695 | |
cf2ae442 RH |
696 | case 0xa: /* l.divu */ |
697 | LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb); | |
698 | gen_divu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
699 | return; | |
bbe418f2 | 700 | |
cf2ae442 RH |
701 | case 0xb: /* l.mulu */ |
702 | LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb); | |
703 | gen_mulu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
704 | return; | |
cc5de49e RH |
705 | |
706 | case 0xc: /* l.muldu */ | |
707 | LOG_DIS("l.muldu r%d, r%d\n", ra, rb); | |
708 | gen_muldu(dc, cpu_R[ra], cpu_R[rb]); | |
709 | return; | |
bbe418f2 JL |
710 | } |
711 | break; | |
bbe418f2 | 712 | } |
cf2ae442 | 713 | gen_illegal_exception(dc); |
bbe418f2 JL |
714 | } |
715 | ||
716 | static void dec_misc(DisasContext *dc, uint32_t insn) | |
717 | { | |
718 | uint32_t op0, op1; | |
719 | uint32_t ra, rb, rd; | |
6da544a6 RH |
720 | uint32_t L6, K5, K16, K5_11; |
721 | int32_t I16, I5_11, N26; | |
5631e69c | 722 | TCGMemOp mop; |
9ecaa27e | 723 | TCGv t0; |
5631e69c | 724 | |
bbe418f2 JL |
725 | op0 = extract32(insn, 26, 6); |
726 | op1 = extract32(insn, 24, 2); | |
727 | ra = extract32(insn, 16, 5); | |
728 | rb = extract32(insn, 11, 5); | |
729 | rd = extract32(insn, 21, 5); | |
bbe418f2 JL |
730 | L6 = extract32(insn, 5, 6); |
731 | K5 = extract32(insn, 0, 5); | |
6da544a6 RH |
732 | K16 = extract32(insn, 0, 16); |
733 | I16 = (int16_t)K16; | |
734 | N26 = sextract32(insn, 0, 26); | |
735 | K5_11 = (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); | |
736 | I5_11 = (int16_t)K5_11; | |
bbe418f2 JL |
737 | |
738 | switch (op0) { | |
739 | case 0x00: /* l.j */ | |
740 | LOG_DIS("l.j %d\n", N26); | |
741 | gen_jump(dc, N26, 0, op0); | |
742 | break; | |
743 | ||
744 | case 0x01: /* l.jal */ | |
745 | LOG_DIS("l.jal %d\n", N26); | |
746 | gen_jump(dc, N26, 0, op0); | |
747 | break; | |
748 | ||
749 | case 0x03: /* l.bnf */ | |
750 | LOG_DIS("l.bnf %d\n", N26); | |
751 | gen_jump(dc, N26, 0, op0); | |
752 | break; | |
753 | ||
754 | case 0x04: /* l.bf */ | |
755 | LOG_DIS("l.bf %d\n", N26); | |
756 | gen_jump(dc, N26, 0, op0); | |
757 | break; | |
758 | ||
759 | case 0x05: | |
760 | switch (op1) { | |
761 | case 0x01: /* l.nop */ | |
762 | LOG_DIS("l.nop %d\n", I16); | |
763 | break; | |
764 | ||
765 | default: | |
766 | gen_illegal_exception(dc); | |
767 | break; | |
768 | } | |
769 | break; | |
770 | ||
771 | case 0x11: /* l.jr */ | |
772 | LOG_DIS("l.jr r%d\n", rb); | |
773 | gen_jump(dc, 0, rb, op0); | |
774 | break; | |
775 | ||
776 | case 0x12: /* l.jalr */ | |
777 | LOG_DIS("l.jalr r%d\n", rb); | |
778 | gen_jump(dc, 0, rb, op0); | |
779 | break; | |
780 | ||
781 | case 0x13: /* l.maci */ | |
6da544a6 | 782 | LOG_DIS("l.maci r%d, %d\n", ra, I16); |
6f7332ba RH |
783 | t0 = tcg_const_tl(I16); |
784 | gen_mac(dc, cpu_R[ra], t0); | |
785 | tcg_temp_free(t0); | |
bbe418f2 JL |
786 | break; |
787 | ||
788 | case 0x09: /* l.rfe */ | |
789 | LOG_DIS("l.rfe\n"); | |
790 | { | |
791 | #if defined(CONFIG_USER_ONLY) | |
792 | return; | |
793 | #else | |
794 | if (dc->mem_idx == MMU_USER_IDX) { | |
795 | gen_illegal_exception(dc); | |
796 | return; | |
797 | } | |
798 | gen_helper_rfe(cpu_env); | |
1ffa4bce | 799 | dc->base.is_jmp = DISAS_UPDATE; |
bbe418f2 JL |
800 | #endif |
801 | } | |
802 | break; | |
803 | ||
930c3d00 RH |
804 | case 0x1b: /* l.lwa */ |
805 | LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16); | |
6597c28d | 806 | check_r0_write(rd); |
930c3d00 RH |
807 | gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16); |
808 | break; | |
809 | ||
bbe418f2 JL |
810 | case 0x1c: /* l.cust1 */ |
811 | LOG_DIS("l.cust1\n"); | |
812 | break; | |
813 | ||
814 | case 0x1d: /* l.cust2 */ | |
815 | LOG_DIS("l.cust2\n"); | |
816 | break; | |
817 | ||
818 | case 0x1e: /* l.cust3 */ | |
819 | LOG_DIS("l.cust3\n"); | |
820 | break; | |
821 | ||
822 | case 0x1f: /* l.cust4 */ | |
823 | LOG_DIS("l.cust4\n"); | |
824 | break; | |
825 | ||
826 | case 0x3c: /* l.cust5 */ | |
827 | LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5); | |
828 | break; | |
829 | ||
830 | case 0x3d: /* l.cust6 */ | |
831 | LOG_DIS("l.cust6\n"); | |
832 | break; | |
833 | ||
834 | case 0x3e: /* l.cust7 */ | |
835 | LOG_DIS("l.cust7\n"); | |
836 | break; | |
837 | ||
838 | case 0x3f: /* l.cust8 */ | |
839 | LOG_DIS("l.cust8\n"); | |
840 | break; | |
841 | ||
842 | /* not used yet, open it when we need or64. */ | |
843 | /*#ifdef TARGET_OPENRISC64 | |
844 | case 0x20: l.ld | |
845 | LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
846 | check_ob64s(dc); |
847 | mop = MO_TEQ; | |
848 | goto do_load; | |
bbe418f2 JL |
849 | #endif*/ |
850 | ||
851 | case 0x21: /* l.lwz */ | |
852 | LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
853 | mop = MO_TEUL; |
854 | goto do_load; | |
bbe418f2 JL |
855 | |
856 | case 0x22: /* l.lws */ | |
857 | LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
858 | mop = MO_TESL; |
859 | goto do_load; | |
bbe418f2 JL |
860 | |
861 | case 0x23: /* l.lbz */ | |
862 | LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
863 | mop = MO_UB; |
864 | goto do_load; | |
bbe418f2 JL |
865 | |
866 | case 0x24: /* l.lbs */ | |
867 | LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
868 | mop = MO_SB; |
869 | goto do_load; | |
bbe418f2 JL |
870 | |
871 | case 0x25: /* l.lhz */ | |
872 | LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
873 | mop = MO_TEUW; |
874 | goto do_load; | |
bbe418f2 JL |
875 | |
876 | case 0x26: /* l.lhs */ | |
877 | LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
878 | mop = MO_TESW; |
879 | goto do_load; | |
880 | ||
881 | do_load: | |
6597c28d RH |
882 | check_r0_write(rd); |
883 | t0 = tcg_temp_new(); | |
884 | tcg_gen_addi_tl(t0, cpu_R[ra], I16); | |
885 | tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); | |
886 | tcg_temp_free(t0); | |
bbe418f2 JL |
887 | break; |
888 | ||
889 | case 0x27: /* l.addi */ | |
890 | LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); | |
6597c28d | 891 | check_r0_write(rd); |
9ecaa27e RH |
892 | t0 = tcg_const_tl(I16); |
893 | gen_add(dc, cpu_R[rd], cpu_R[ra], t0); | |
894 | tcg_temp_free(t0); | |
bbe418f2 JL |
895 | break; |
896 | ||
897 | case 0x28: /* l.addic */ | |
898 | LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16); | |
6597c28d | 899 | check_r0_write(rd); |
9ecaa27e RH |
900 | t0 = tcg_const_tl(I16); |
901 | gen_addc(dc, cpu_R[rd], cpu_R[ra], t0); | |
902 | tcg_temp_free(t0); | |
bbe418f2 JL |
903 | break; |
904 | ||
905 | case 0x29: /* l.andi */ | |
6da544a6 | 906 | LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, K16); |
6597c28d | 907 | check_r0_write(rd); |
6da544a6 | 908 | tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], K16); |
bbe418f2 JL |
909 | break; |
910 | ||
911 | case 0x2a: /* l.ori */ | |
6da544a6 | 912 | LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, K16); |
6597c28d | 913 | check_r0_write(rd); |
6da544a6 | 914 | tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], K16); |
bbe418f2 JL |
915 | break; |
916 | ||
917 | case 0x2b: /* l.xori */ | |
918 | LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); | |
6597c28d | 919 | check_r0_write(rd); |
6da544a6 | 920 | tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], I16); |
bbe418f2 JL |
921 | break; |
922 | ||
923 | case 0x2c: /* l.muli */ | |
924 | LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16); | |
6597c28d | 925 | check_r0_write(rd); |
9ecaa27e RH |
926 | t0 = tcg_const_tl(I16); |
927 | gen_mul(dc, cpu_R[rd], cpu_R[ra], t0); | |
928 | tcg_temp_free(t0); | |
bbe418f2 JL |
929 | break; |
930 | ||
931 | case 0x2d: /* l.mfspr */ | |
6da544a6 | 932 | LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, K16); |
6597c28d | 933 | check_r0_write(rd); |
4dd044c6 JL |
934 | { |
935 | #if defined(CONFIG_USER_ONLY) | |
936 | return; | |
937 | #else | |
6da544a6 | 938 | TCGv_i32 ti = tcg_const_i32(K16); |
4dd044c6 JL |
939 | if (dc->mem_idx == MMU_USER_IDX) { |
940 | gen_illegal_exception(dc); | |
941 | return; | |
942 | } | |
943 | gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); | |
944 | tcg_temp_free_i32(ti); | |
945 | #endif | |
946 | } | |
bbe418f2 JL |
947 | break; |
948 | ||
949 | case 0x30: /* l.mtspr */ | |
6da544a6 | 950 | LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11); |
4dd044c6 JL |
951 | { |
952 | #if defined(CONFIG_USER_ONLY) | |
953 | return; | |
954 | #else | |
6da544a6 | 955 | TCGv_i32 im = tcg_const_i32(K5_11); |
4dd044c6 JL |
956 | if (dc->mem_idx == MMU_USER_IDX) { |
957 | gen_illegal_exception(dc); | |
958 | return; | |
959 | } | |
960 | gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); | |
961 | tcg_temp_free_i32(im); | |
962 | #endif | |
963 | } | |
bbe418f2 JL |
964 | break; |
965 | ||
930c3d00 | 966 | case 0x33: /* l.swa */ |
6da544a6 | 967 | LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); |
6597c28d | 968 | gen_swa(dc, rb, cpu_R[ra], I5_11); |
930c3d00 RH |
969 | break; |
970 | ||
bbe418f2 JL |
971 | /* not used yet, open it when we need or64. */ |
972 | /*#ifdef TARGET_OPENRISC64 | |
973 | case 0x34: l.sd | |
6da544a6 | 974 | LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
975 | check_ob64s(dc); |
976 | mop = MO_TEQ; | |
977 | goto do_store; | |
bbe418f2 JL |
978 | #endif*/ |
979 | ||
980 | case 0x35: /* l.sw */ | |
6da544a6 | 981 | LOG_DIS("l.sw r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
982 | mop = MO_TEUL; |
983 | goto do_store; | |
bbe418f2 JL |
984 | |
985 | case 0x36: /* l.sb */ | |
6da544a6 | 986 | LOG_DIS("l.sb r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
987 | mop = MO_UB; |
988 | goto do_store; | |
bbe418f2 JL |
989 | |
990 | case 0x37: /* l.sh */ | |
6da544a6 | 991 | LOG_DIS("l.sh r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
992 | mop = MO_TEUW; |
993 | goto do_store; | |
994 | ||
995 | do_store: | |
bbe418f2 JL |
996 | { |
997 | TCGv t0 = tcg_temp_new(); | |
6da544a6 | 998 | tcg_gen_addi_tl(t0, cpu_R[ra], I5_11); |
5631e69c | 999 | tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); |
bbe418f2 JL |
1000 | tcg_temp_free(t0); |
1001 | } | |
1002 | break; | |
1003 | ||
1004 | default: | |
1005 | gen_illegal_exception(dc); | |
1006 | break; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | static void dec_mac(DisasContext *dc, uint32_t insn) | |
1011 | { | |
1012 | uint32_t op0; | |
1013 | uint32_t ra, rb; | |
1014 | op0 = extract32(insn, 0, 4); | |
1015 | ra = extract32(insn, 16, 5); | |
1016 | rb = extract32(insn, 11, 5); | |
1017 | ||
1018 | switch (op0) { | |
1019 | case 0x0001: /* l.mac */ | |
1020 | LOG_DIS("l.mac r%d, r%d\n", ra, rb); | |
6f7332ba | 1021 | gen_mac(dc, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1022 | break; |
1023 | ||
1024 | case 0x0002: /* l.msb */ | |
1025 | LOG_DIS("l.msb r%d, r%d\n", ra, rb); | |
6f7332ba | 1026 | gen_msb(dc, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1027 | break; |
1028 | ||
cc5de49e RH |
1029 | case 0x0003: /* l.macu */ |
1030 | LOG_DIS("l.macu r%d, r%d\n", ra, rb); | |
1031 | gen_macu(dc, cpu_R[ra], cpu_R[rb]); | |
1032 | break; | |
1033 | ||
1034 | case 0x0004: /* l.msbu */ | |
1035 | LOG_DIS("l.msbu r%d, r%d\n", ra, rb); | |
1036 | gen_msbu(dc, cpu_R[ra], cpu_R[rb]); | |
1037 | break; | |
1038 | ||
bbe418f2 JL |
1039 | default: |
1040 | gen_illegal_exception(dc); | |
1041 | break; | |
1042 | } | |
1043 | } | |
1044 | ||
1045 | static void dec_logic(DisasContext *dc, uint32_t insn) | |
1046 | { | |
1047 | uint32_t op0; | |
6da544a6 | 1048 | uint32_t rd, ra, L6, S6; |
bbe418f2 JL |
1049 | op0 = extract32(insn, 6, 2); |
1050 | rd = extract32(insn, 21, 5); | |
1051 | ra = extract32(insn, 16, 5); | |
1052 | L6 = extract32(insn, 0, 6); | |
6da544a6 | 1053 | S6 = L6 & (TARGET_LONG_BITS - 1); |
bbe418f2 | 1054 | |
6597c28d | 1055 | check_r0_write(rd); |
bbe418f2 JL |
1056 | switch (op0) { |
1057 | case 0x00: /* l.slli */ | |
1058 | LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 1059 | tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
1060 | break; |
1061 | ||
1062 | case 0x01: /* l.srli */ | |
1063 | LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 1064 | tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
1065 | break; |
1066 | ||
1067 | case 0x02: /* l.srai */ | |
1068 | LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 RH |
1069 | tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6); |
1070 | break; | |
bbe418f2 JL |
1071 | |
1072 | case 0x03: /* l.rori */ | |
1073 | LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 1074 | tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
1075 | break; |
1076 | ||
1077 | default: | |
1078 | gen_illegal_exception(dc); | |
1079 | break; | |
1080 | } | |
1081 | } | |
1082 | ||
1083 | static void dec_M(DisasContext *dc, uint32_t insn) | |
1084 | { | |
1085 | uint32_t op0; | |
1086 | uint32_t rd; | |
1087 | uint32_t K16; | |
1088 | op0 = extract32(insn, 16, 1); | |
1089 | rd = extract32(insn, 21, 5); | |
1090 | K16 = extract32(insn, 0, 16); | |
1091 | ||
6597c28d | 1092 | check_r0_write(rd); |
bbe418f2 JL |
1093 | switch (op0) { |
1094 | case 0x0: /* l.movhi */ | |
1095 | LOG_DIS("l.movhi r%d, %d\n", rd, K16); | |
1096 | tcg_gen_movi_tl(cpu_R[rd], (K16 << 16)); | |
1097 | break; | |
1098 | ||
1099 | case 0x1: /* l.macrc */ | |
1100 | LOG_DIS("l.macrc r%d\n", rd); | |
6f7332ba RH |
1101 | tcg_gen_trunc_i64_tl(cpu_R[rd], cpu_mac); |
1102 | tcg_gen_movi_i64(cpu_mac, 0); | |
bbe418f2 JL |
1103 | break; |
1104 | ||
1105 | default: | |
1106 | gen_illegal_exception(dc); | |
1107 | break; | |
1108 | } | |
1109 | } | |
1110 | ||
1111 | static void dec_comp(DisasContext *dc, uint32_t insn) | |
1112 | { | |
1113 | uint32_t op0; | |
1114 | uint32_t ra, rb; | |
1115 | ||
1116 | op0 = extract32(insn, 21, 5); | |
1117 | ra = extract32(insn, 16, 5); | |
1118 | rb = extract32(insn, 11, 5); | |
1119 | ||
bbe418f2 JL |
1120 | /* unsigned integers */ |
1121 | tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]); | |
1122 | tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]); | |
1123 | ||
1124 | switch (op0) { | |
1125 | case 0x0: /* l.sfeq */ | |
1126 | LOG_DIS("l.sfeq r%d, r%d\n", ra, rb); | |
84775c43 | 1127 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1128 | break; |
1129 | ||
1130 | case 0x1: /* l.sfne */ | |
1131 | LOG_DIS("l.sfne r%d, r%d\n", ra, rb); | |
84775c43 | 1132 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1133 | break; |
1134 | ||
1135 | case 0x2: /* l.sfgtu */ | |
1136 | LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb); | |
84775c43 | 1137 | tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1138 | break; |
1139 | ||
1140 | case 0x3: /* l.sfgeu */ | |
1141 | LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb); | |
84775c43 | 1142 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1143 | break; |
1144 | ||
1145 | case 0x4: /* l.sfltu */ | |
1146 | LOG_DIS("l.sfltu r%d, r%d\n", ra, rb); | |
84775c43 | 1147 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1148 | break; |
1149 | ||
1150 | case 0x5: /* l.sfleu */ | |
1151 | LOG_DIS("l.sfleu r%d, r%d\n", ra, rb); | |
84775c43 | 1152 | tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1153 | break; |
1154 | ||
1155 | case 0xa: /* l.sfgts */ | |
1156 | LOG_DIS("l.sfgts r%d, r%d\n", ra, rb); | |
84775c43 | 1157 | tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1158 | break; |
1159 | ||
1160 | case 0xb: /* l.sfges */ | |
1161 | LOG_DIS("l.sfges r%d, r%d\n", ra, rb); | |
84775c43 | 1162 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1163 | break; |
1164 | ||
1165 | case 0xc: /* l.sflts */ | |
1166 | LOG_DIS("l.sflts r%d, r%d\n", ra, rb); | |
84775c43 | 1167 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1168 | break; |
1169 | ||
1170 | case 0xd: /* l.sfles */ | |
1171 | LOG_DIS("l.sfles r%d, r%d\n", ra, rb); | |
84775c43 | 1172 | tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1173 | break; |
1174 | ||
1175 | default: | |
1176 | gen_illegal_exception(dc); | |
1177 | break; | |
1178 | } | |
bbe418f2 JL |
1179 | } |
1180 | ||
1181 | static void dec_compi(DisasContext *dc, uint32_t insn) | |
1182 | { | |
6da544a6 RH |
1183 | uint32_t op0, ra; |
1184 | int32_t I16; | |
bbe418f2 JL |
1185 | |
1186 | op0 = extract32(insn, 21, 5); | |
1187 | ra = extract32(insn, 16, 5); | |
6da544a6 | 1188 | I16 = sextract32(insn, 0, 16); |
bbe418f2 | 1189 | |
bbe418f2 JL |
1190 | switch (op0) { |
1191 | case 0x0: /* l.sfeqi */ | |
1192 | LOG_DIS("l.sfeqi r%d, %d\n", ra, I16); | |
84775c43 | 1193 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1194 | break; |
1195 | ||
1196 | case 0x1: /* l.sfnei */ | |
1197 | LOG_DIS("l.sfnei r%d, %d\n", ra, I16); | |
84775c43 | 1198 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1199 | break; |
1200 | ||
1201 | case 0x2: /* l.sfgtui */ | |
1202 | LOG_DIS("l.sfgtui r%d, %d\n", ra, I16); | |
84775c43 | 1203 | tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1204 | break; |
1205 | ||
1206 | case 0x3: /* l.sfgeui */ | |
1207 | LOG_DIS("l.sfgeui r%d, %d\n", ra, I16); | |
84775c43 | 1208 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1209 | break; |
1210 | ||
1211 | case 0x4: /* l.sfltui */ | |
1212 | LOG_DIS("l.sfltui r%d, %d\n", ra, I16); | |
84775c43 | 1213 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1214 | break; |
1215 | ||
1216 | case 0x5: /* l.sfleui */ | |
1217 | LOG_DIS("l.sfleui r%d, %d\n", ra, I16); | |
84775c43 | 1218 | tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1219 | break; |
1220 | ||
1221 | case 0xa: /* l.sfgtsi */ | |
1222 | LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16); | |
84775c43 | 1223 | tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1224 | break; |
1225 | ||
1226 | case 0xb: /* l.sfgesi */ | |
1227 | LOG_DIS("l.sfgesi r%d, %d\n", ra, I16); | |
84775c43 | 1228 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1229 | break; |
1230 | ||
1231 | case 0xc: /* l.sfltsi */ | |
1232 | LOG_DIS("l.sfltsi r%d, %d\n", ra, I16); | |
84775c43 | 1233 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1234 | break; |
1235 | ||
1236 | case 0xd: /* l.sflesi */ | |
1237 | LOG_DIS("l.sflesi r%d, %d\n", ra, I16); | |
84775c43 | 1238 | tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1239 | break; |
1240 | ||
1241 | default: | |
1242 | gen_illegal_exception(dc); | |
1243 | break; | |
1244 | } | |
bbe418f2 JL |
1245 | } |
1246 | ||
7de9729f | 1247 | static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn) |
bbe418f2 | 1248 | { |
7de9729f RH |
1249 | LOG_DIS("l.sys %d\n", a->k); |
1250 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); | |
1251 | gen_exception(dc, EXCP_SYSCALL); | |
1252 | dc->base.is_jmp = DISAS_NORETURN; | |
1253 | return true; | |
1254 | } | |
bbe418f2 | 1255 | |
7de9729f RH |
1256 | static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn) |
1257 | { | |
1258 | LOG_DIS("l.trap %d\n", a->k); | |
1259 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); | |
1260 | gen_exception(dc, EXCP_TRAP); | |
1261 | dc->base.is_jmp = DISAS_NORETURN; | |
1262 | return true; | |
1263 | } | |
bbe418f2 | 1264 | |
7de9729f RH |
1265 | static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn) |
1266 | { | |
1267 | LOG_DIS("l.msync\n"); | |
1268 | tcg_gen_mb(TCG_MO_ALL); | |
1269 | return true; | |
1270 | } | |
bbe418f2 | 1271 | |
7de9729f RH |
1272 | static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn) |
1273 | { | |
1274 | LOG_DIS("l.psync\n"); | |
1275 | return true; | |
1276 | } | |
bbe418f2 | 1277 | |
7de9729f RH |
1278 | static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn) |
1279 | { | |
1280 | LOG_DIS("l.csync\n"); | |
1281 | return true; | |
bbe418f2 JL |
1282 | } |
1283 | ||
1284 | static void dec_float(DisasContext *dc, uint32_t insn) | |
1285 | { | |
1286 | uint32_t op0; | |
1287 | uint32_t ra, rb, rd; | |
1288 | op0 = extract32(insn, 0, 8); | |
1289 | ra = extract32(insn, 16, 5); | |
1290 | rb = extract32(insn, 11, 5); | |
1291 | rd = extract32(insn, 21, 5); | |
1292 | ||
1293 | switch (op0) { | |
4e2d3007 | 1294 | case 0x00: /* lf.add.s */ |
bbe418f2 | 1295 | LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb); |
6597c28d | 1296 | check_r0_write(rd); |
bbe418f2 | 1297 | gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1298 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1299 | break; |
1300 | ||
4e2d3007 | 1301 | case 0x01: /* lf.sub.s */ |
bbe418f2 | 1302 | LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb); |
6597c28d | 1303 | check_r0_write(rd); |
bbe418f2 | 1304 | gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1305 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1306 | break; |
1307 | ||
bbe418f2 JL |
1308 | case 0x02: /* lf.mul.s */ |
1309 | LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb); | |
6597c28d RH |
1310 | check_r0_write(rd); |
1311 | gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
4e2d3007 | 1312 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1313 | break; |
1314 | ||
4e2d3007 | 1315 | case 0x03: /* lf.div.s */ |
bbe418f2 | 1316 | LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb); |
6597c28d | 1317 | check_r0_write(rd); |
bbe418f2 | 1318 | gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1319 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1320 | break; |
1321 | ||
4e2d3007 | 1322 | case 0x04: /* lf.itof.s */ |
bbe418f2 | 1323 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); |
6597c28d | 1324 | check_r0_write(rd); |
bbe418f2 | 1325 | gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]); |
4e2d3007 | 1326 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1327 | break; |
1328 | ||
4e2d3007 | 1329 | case 0x05: /* lf.ftoi.s */ |
bbe418f2 | 1330 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); |
6597c28d | 1331 | check_r0_write(rd); |
bbe418f2 | 1332 | gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]); |
4e2d3007 | 1333 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1334 | break; |
1335 | ||
4e2d3007 | 1336 | case 0x06: /* lf.rem.s */ |
bbe418f2 | 1337 | LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb); |
6597c28d | 1338 | check_r0_write(rd); |
bbe418f2 | 1339 | gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1340 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1341 | break; |
1342 | ||
4e2d3007 | 1343 | case 0x07: /* lf.madd.s */ |
bbe418f2 | 1344 | LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); |
6597c28d | 1345 | check_r0_write(rd); |
762e22ed RH |
1346 | gen_helper_float_madd_s(cpu_R[rd], cpu_env, cpu_R[rd], |
1347 | cpu_R[ra], cpu_R[rb]); | |
4e2d3007 | 1348 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1349 | break; |
1350 | ||
4e2d3007 | 1351 | case 0x08: /* lf.sfeq.s */ |
bbe418f2 | 1352 | LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); |
84775c43 | 1353 | gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1354 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1355 | break; |
1356 | ||
4e2d3007 | 1357 | case 0x09: /* lf.sfne.s */ |
bbe418f2 | 1358 | LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); |
4e2d3007 RH |
1359 | gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
1360 | tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); | |
1361 | gen_helper_update_fpcsr(cpu_env); | |
bbe418f2 JL |
1362 | break; |
1363 | ||
4e2d3007 | 1364 | case 0x0a: /* lf.sfgt.s */ |
bbe418f2 | 1365 | LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); |
4e2d3007 RH |
1366 | gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); |
1367 | gen_helper_update_fpcsr(cpu_env); | |
bbe418f2 JL |
1368 | break; |
1369 | ||
4e2d3007 | 1370 | case 0x0b: /* lf.sfge.s */ |
bbe418f2 | 1371 | LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); |
4e2d3007 RH |
1372 | gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); |
1373 | gen_helper_update_fpcsr(cpu_env); | |
bbe418f2 JL |
1374 | break; |
1375 | ||
4e2d3007 | 1376 | case 0x0c: /* lf.sflt.s */ |
bbe418f2 | 1377 | LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); |
84775c43 | 1378 | gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1379 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1380 | break; |
1381 | ||
4e2d3007 | 1382 | case 0x0d: /* lf.sfle.s */ |
bbe418f2 | 1383 | LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); |
84775c43 | 1384 | gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1385 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1386 | break; |
1387 | ||
4e2d3007 RH |
1388 | #ifdef TARGET_OPENRISC64 |
1389 | case 0x10: /* lf.add.d */ | |
bbe418f2 JL |
1390 | LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb); |
1391 | check_of64s(dc); | |
6597c28d | 1392 | check_r0_write(rd); |
bbe418f2 | 1393 | gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1394 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1395 | break; |
1396 | ||
4e2d3007 | 1397 | case 0x11: /* lf.sub.d */ |
bbe418f2 JL |
1398 | LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb); |
1399 | check_of64s(dc); | |
6597c28d | 1400 | check_r0_write(rd); |
bbe418f2 | 1401 | gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1402 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1403 | break; |
1404 | ||
4e2d3007 | 1405 | case 0x12: /* lf.mul.d */ |
bbe418f2 JL |
1406 | LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb); |
1407 | check_of64s(dc); | |
6597c28d RH |
1408 | check_r0_write(rd); |
1409 | gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
4e2d3007 | 1410 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1411 | break; |
1412 | ||
4e2d3007 | 1413 | case 0x13: /* lf.div.d */ |
bbe418f2 JL |
1414 | LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb); |
1415 | check_of64s(dc); | |
6597c28d | 1416 | check_r0_write(rd); |
bbe418f2 | 1417 | gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1418 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1419 | break; |
1420 | ||
4e2d3007 | 1421 | case 0x14: /* lf.itof.d */ |
bbe418f2 JL |
1422 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); |
1423 | check_of64s(dc); | |
6597c28d | 1424 | check_r0_write(rd); |
bbe418f2 | 1425 | gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]); |
4e2d3007 | 1426 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1427 | break; |
1428 | ||
4e2d3007 | 1429 | case 0x15: /* lf.ftoi.d */ |
bbe418f2 JL |
1430 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); |
1431 | check_of64s(dc); | |
6597c28d | 1432 | check_r0_write(rd); |
bbe418f2 | 1433 | gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]); |
4e2d3007 | 1434 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1435 | break; |
1436 | ||
4e2d3007 | 1437 | case 0x16: /* lf.rem.d */ |
bbe418f2 JL |
1438 | LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb); |
1439 | check_of64s(dc); | |
6597c28d | 1440 | check_r0_write(rd); |
bbe418f2 | 1441 | gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1442 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1443 | break; |
1444 | ||
4e2d3007 | 1445 | case 0x17: /* lf.madd.d */ |
bbe418f2 JL |
1446 | LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); |
1447 | check_of64s(dc); | |
6597c28d | 1448 | check_r0_write(rd); |
762e22ed RH |
1449 | gen_helper_float_madd_d(cpu_R[rd], cpu_env, cpu_R[rd], |
1450 | cpu_R[ra], cpu_R[rb]); | |
4e2d3007 | 1451 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1452 | break; |
1453 | ||
4e2d3007 | 1454 | case 0x18: /* lf.sfeq.d */ |
bbe418f2 JL |
1455 | LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); |
1456 | check_of64s(dc); | |
84775c43 | 1457 | gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1458 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1459 | break; |
1460 | ||
4e2d3007 | 1461 | case 0x1a: /* lf.sfgt.d */ |
bbe418f2 JL |
1462 | LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); |
1463 | check_of64s(dc); | |
4e2d3007 RH |
1464 | gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); |
1465 | gen_helper_update_fpcsr(cpu_env); | |
bbe418f2 JL |
1466 | break; |
1467 | ||
4e2d3007 | 1468 | case 0x1b: /* lf.sfge.d */ |
bbe418f2 JL |
1469 | LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); |
1470 | check_of64s(dc); | |
4e2d3007 RH |
1471 | gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[rb], cpu_R[ra]); |
1472 | gen_helper_update_fpcsr(cpu_env); | |
bbe418f2 JL |
1473 | break; |
1474 | ||
4e2d3007 | 1475 | case 0x19: /* lf.sfne.d */ |
bbe418f2 JL |
1476 | LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); |
1477 | check_of64s(dc); | |
4e2d3007 RH |
1478 | gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
1479 | tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); | |
1480 | gen_helper_update_fpcsr(cpu_env); | |
bbe418f2 JL |
1481 | break; |
1482 | ||
4e2d3007 | 1483 | case 0x1c: /* lf.sflt.d */ |
bbe418f2 JL |
1484 | LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); |
1485 | check_of64s(dc); | |
84775c43 | 1486 | gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1487 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 JL |
1488 | break; |
1489 | ||
4e2d3007 | 1490 | case 0x1d: /* lf.sfle.d */ |
bbe418f2 JL |
1491 | LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); |
1492 | check_of64s(dc); | |
84775c43 | 1493 | gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
4e2d3007 | 1494 | gen_helper_update_fpcsr(cpu_env); |
bbe418f2 | 1495 | break; |
4e2d3007 | 1496 | #endif |
bbe418f2 JL |
1497 | |
1498 | default: | |
1499 | gen_illegal_exception(dc); | |
1500 | break; | |
1501 | } | |
bbe418f2 JL |
1502 | } |
1503 | ||
1504 | static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) | |
1505 | { | |
1506 | uint32_t op0; | |
7de9729f | 1507 | uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next); |
bbe418f2 | 1508 | |
7de9729f RH |
1509 | /* Transition to the auto-generated decoder. */ |
1510 | if (decode(dc, insn)) { | |
1511 | return; | |
1512 | } | |
1513 | ||
1514 | op0 = extract32(insn, 26, 6); | |
bbe418f2 JL |
1515 | switch (op0) { |
1516 | case 0x06: | |
1517 | dec_M(dc, insn); | |
1518 | break; | |
1519 | ||
bbe418f2 JL |
1520 | case 0x2e: |
1521 | dec_logic(dc, insn); | |
1522 | break; | |
1523 | ||
1524 | case 0x2f: | |
1525 | dec_compi(dc, insn); | |
1526 | break; | |
1527 | ||
1528 | case 0x31: | |
1529 | dec_mac(dc, insn); | |
1530 | break; | |
1531 | ||
1532 | case 0x32: | |
1533 | dec_float(dc, insn); | |
1534 | break; | |
1535 | ||
1536 | case 0x38: | |
1537 | dec_calc(dc, insn); | |
1538 | break; | |
1539 | ||
1540 | case 0x39: | |
1541 | dec_comp(dc, insn); | |
1542 | break; | |
1543 | ||
1544 | default: | |
1545 | dec_misc(dc, insn); | |
1546 | break; | |
1547 | } | |
1548 | } | |
1549 | ||
a4fd3ec3 | 1550 | static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) |
e67db06e | 1551 | { |
a4fd3ec3 | 1552 | DisasContext *dc = container_of(dcb, DisasContext, base); |
9c489ea6 | 1553 | CPUOpenRISCState *env = cs->env_ptr; |
a4fd3ec3 | 1554 | int bound; |
1ffa4bce | 1555 | |
a4fd3ec3 | 1556 | dc->mem_idx = cpu_mmu_index(env, false); |
1ffa4bce | 1557 | dc->tb_flags = dc->base.tb->flags; |
a01deb36 | 1558 | dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; |
a4fd3ec3 EC |
1559 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; |
1560 | dc->base.max_insns = MIN(dc->base.max_insns, bound); | |
1561 | } | |
bbe418f2 | 1562 | |
a4fd3ec3 EC |
1563 | static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) |
1564 | { | |
1565 | DisasContext *dc = container_of(db, DisasContext, base); | |
bbe418f2 | 1566 | |
6597c28d RH |
1567 | /* Allow the TCG optimizer to see that R0 == 0, |
1568 | when it's true, which is the common case. */ | |
1569 | if (dc->tb_flags & TB_FLAGS_R0_0) { | |
1570 | cpu_R[0] = tcg_const_tl(0); | |
1571 | } else { | |
1572 | cpu_R[0] = cpu_R0; | |
1573 | } | |
a4fd3ec3 | 1574 | } |
6597c28d | 1575 | |
a4fd3ec3 EC |
1576 | static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
1577 | { | |
1578 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
bbe418f2 | 1579 | |
a4fd3ec3 EC |
1580 | tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) |
1581 | | (dc->base.num_insns > 1 ? 2 : 0)); | |
1582 | } | |
b933066a | 1583 | |
a4fd3ec3 EC |
1584 | static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, |
1585 | const CPUBreakpoint *bp) | |
1586 | { | |
1587 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
1588 | ||
1589 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); | |
1590 | gen_exception(dc, EXCP_DEBUG); | |
1591 | dc->base.is_jmp = DISAS_NORETURN; | |
1592 | /* The address covered by the breakpoint must be included in | |
1593 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
1594 | properly cleared -- thus we increment the PC here so that | |
1595 | the logic setting tb->size below does the right thing. */ | |
1596 | dc->base.pc_next += 4; | |
1597 | return true; | |
1598 | } | |
1599 | ||
1600 | static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) | |
1601 | { | |
1602 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
1603 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | |
1604 | ||
1605 | disas_openrisc_insn(dc, cpu); | |
1606 | dc->base.pc_next += 4; | |
1607 | ||
1608 | /* delay slot */ | |
1609 | if (dc->delayed_branch) { | |
1610 | dc->delayed_branch--; | |
1611 | if (!dc->delayed_branch) { | |
1612 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
1613 | tcg_gen_discard_tl(jmp_pc); | |
1614 | dc->base.is_jmp = DISAS_UPDATE; | |
1615 | return; | |
bbe418f2 | 1616 | } |
bbe418f2 | 1617 | } |
a4fd3ec3 EC |
1618 | } |
1619 | ||
1620 | static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
1621 | { | |
1622 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
24c32852 | 1623 | |
a01deb36 RH |
1624 | if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { |
1625 | tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); | |
1626 | } | |
1627 | ||
1ffa4bce EC |
1628 | tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4); |
1629 | if (dc->base.is_jmp == DISAS_NEXT) { | |
1630 | dc->base.is_jmp = DISAS_UPDATE; | |
1631 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); | |
bbe418f2 | 1632 | } |
1ffa4bce | 1633 | if (unlikely(dc->base.singlestep_enabled)) { |
bbe418f2 JL |
1634 | gen_exception(dc, EXCP_DEBUG); |
1635 | } else { | |
1ffa4bce | 1636 | switch (dc->base.is_jmp) { |
a4fd3ec3 | 1637 | case DISAS_TOO_MANY: |
1ffa4bce | 1638 | gen_goto_tb(dc, 0, dc->base.pc_next); |
bbe418f2 | 1639 | break; |
1ffa4bce | 1640 | case DISAS_NORETURN: |
bbe418f2 | 1641 | case DISAS_JUMP: |
1ffa4bce | 1642 | case DISAS_TB_JUMP: |
bbe418f2 JL |
1643 | break; |
1644 | case DISAS_UPDATE: | |
1645 | /* indicate that the hash table must be used | |
1646 | to find the next TB */ | |
1647 | tcg_gen_exit_tb(0); | |
1648 | break; | |
a4fd3ec3 EC |
1649 | default: |
1650 | g_assert_not_reached(); | |
bbe418f2 JL |
1651 | } |
1652 | } | |
a4fd3ec3 | 1653 | } |
bbe418f2 | 1654 | |
a4fd3ec3 EC |
1655 | static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) |
1656 | { | |
1657 | DisasContext *s = container_of(dcbase, DisasContext, base); | |
0a7df5da | 1658 | |
a4fd3ec3 EC |
1659 | qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first)); |
1660 | log_target_disas(cs, s->base.pc_first, s->base.tb->size); | |
1661 | } | |
bbe418f2 | 1662 | |
a4fd3ec3 EC |
1663 | static const TranslatorOps openrisc_tr_ops = { |
1664 | .init_disas_context = openrisc_tr_init_disas_context, | |
1665 | .tb_start = openrisc_tr_tb_start, | |
1666 | .insn_start = openrisc_tr_insn_start, | |
1667 | .breakpoint_check = openrisc_tr_breakpoint_check, | |
1668 | .translate_insn = openrisc_tr_translate_insn, | |
1669 | .tb_stop = openrisc_tr_tb_stop, | |
1670 | .disas_log = openrisc_tr_disas_log, | |
1671 | }; | |
1672 | ||
1673 | void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) | |
1674 | { | |
1675 | DisasContext ctx; | |
1676 | ||
1677 | translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb); | |
e67db06e JL |
1678 | } |
1679 | ||
878096ee AF |
1680 | void openrisc_cpu_dump_state(CPUState *cs, FILE *f, |
1681 | fprintf_function cpu_fprintf, | |
1682 | int flags) | |
e67db06e | 1683 | { |
878096ee AF |
1684 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
1685 | CPUOpenRISCState *env = &cpu->env; | |
e67db06e | 1686 | int i; |
878096ee | 1687 | |
e67db06e JL |
1688 | cpu_fprintf(f, "PC=%08x\n", env->pc); |
1689 | for (i = 0; i < 32; ++i) { | |
d89e71e8 | 1690 | cpu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i), |
e67db06e JL |
1691 | (i % 4) == 3 ? '\n' : ' '); |
1692 | } | |
1693 | } | |
1694 | ||
1695 | void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, | |
bad729e2 | 1696 | target_ulong *data) |
e67db06e | 1697 | { |
bad729e2 | 1698 | env->pc = data[0]; |
a01deb36 RH |
1699 | env->dflag = data[1] & 1; |
1700 | if (data[1] & 2) { | |
24c32852 RH |
1701 | env->ppc = env->pc - 4; |
1702 | } | |
e67db06e | 1703 | } |