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e67db06e JL |
1 | /* |
2 | * OpenRISC translation | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Feng Gao <gf91597@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
779fc6ad | 10 | * version 2.1 of the License, or (at your option) any later version. |
e67db06e JL |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
e67db06e | 22 | #include "cpu.h" |
022c62cb | 23 | #include "exec/exec-all.h" |
76cad711 | 24 | #include "disas/disas.h" |
dcb32f1d | 25 | #include "tcg/tcg-op.h" |
1de7afc9 | 26 | #include "qemu/log.h" |
1de7afc9 | 27 | #include "qemu/bitops.h" |
90c84c56 | 28 | #include "qemu/qemu-print.h" |
77fc6f5e | 29 | #include "exec/translator.h" |
bbe418f2 | 30 | |
2ef6175a RH |
31 | #include "exec/helper-proto.h" |
32 | #include "exec/helper-gen.h" | |
e67db06e | 33 | |
508127e2 | 34 | #include "exec/log.h" |
a7e30d84 | 35 | |
d53106c9 RH |
36 | #define HELPER_H "helper.h" |
37 | #include "exec/helper-info.c.inc" | |
38 | #undef HELPER_H | |
39 | ||
40 | ||
77fc6f5e | 41 | /* is_jmp field values */ |
64e46c95 | 42 | #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ |
8000ba56 | 43 | #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ |
77fc6f5e | 44 | |
bbe418f2 | 45 | typedef struct DisasContext { |
1ffa4bce | 46 | DisasContextBase base; |
bbe418f2 | 47 | uint32_t mem_idx; |
a01deb36 | 48 | uint32_t tb_flags; |
bbe418f2 | 49 | uint32_t delayed_branch; |
fe636d37 | 50 | uint32_t cpucfgr; |
2b13b4b9 | 51 | uint32_t avr; |
8000ba56 RH |
52 | |
53 | /* If not -1, jmp_pc contains this value and so is a direct jump. */ | |
54 | target_ulong jmp_pc_imm; | |
d29f4368 RH |
55 | |
56 | /* The temporary corresponding to register 0 for this compilation. */ | |
57 | TCGv R0; | |
118671f0 RH |
58 | /* The constant zero. */ |
59 | TCGv zero; | |
bbe418f2 JL |
60 | } DisasContext; |
61 | ||
2ba65417 RH |
62 | static inline bool is_user(DisasContext *dc) |
63 | { | |
64 | #ifdef CONFIG_USER_ONLY | |
65 | return true; | |
66 | #else | |
b9bed1b9 | 67 | return !(dc->tb_flags & TB_FLAGS_SM); |
2ba65417 RH |
68 | #endif |
69 | } | |
70 | ||
7de9729f | 71 | /* Include the auto-generated decoder. */ |
abff1abf | 72 | #include "decode-insns.c.inc" |
7de9729f | 73 | |
bbe418f2 | 74 | static TCGv cpu_sr; |
8bba7619 | 75 | static TCGv cpu_regs[32]; |
bbe418f2 JL |
76 | static TCGv cpu_pc; |
77 | static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ | |
bbe418f2 | 78 | static TCGv cpu_ppc; |
84775c43 | 79 | static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ |
97458071 RH |
80 | static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ |
81 | static TCGv cpu_sr_ov; /* signed overflow */ | |
930c3d00 RH |
82 | static TCGv cpu_lock_addr; |
83 | static TCGv cpu_lock_value; | |
bbe418f2 | 84 | static TCGv_i32 fpcsr; |
6f7332ba | 85 | static TCGv_i64 cpu_mac; /* MACHI:MACLO */ |
a01deb36 | 86 | static TCGv_i32 cpu_dflag; |
bbe418f2 | 87 | |
e67db06e JL |
88 | void openrisc_translate_init(void) |
89 | { | |
bbe418f2 JL |
90 | static const char * const regnames[] = { |
91 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
92 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
93 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
94 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
95 | }; | |
96 | int i; | |
97 | ||
ad75a51e | 98 | cpu_sr = tcg_global_mem_new(tcg_env, |
bbe418f2 | 99 | offsetof(CPUOpenRISCState, sr), "sr"); |
ad75a51e | 100 | cpu_dflag = tcg_global_mem_new_i32(tcg_env, |
a01deb36 RH |
101 | offsetof(CPUOpenRISCState, dflag), |
102 | "dflag"); | |
ad75a51e | 103 | cpu_pc = tcg_global_mem_new(tcg_env, |
bbe418f2 | 104 | offsetof(CPUOpenRISCState, pc), "pc"); |
ad75a51e | 105 | cpu_ppc = tcg_global_mem_new(tcg_env, |
bbe418f2 | 106 | offsetof(CPUOpenRISCState, ppc), "ppc"); |
ad75a51e | 107 | jmp_pc = tcg_global_mem_new(tcg_env, |
bbe418f2 | 108 | offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); |
ad75a51e | 109 | cpu_sr_f = tcg_global_mem_new(tcg_env, |
84775c43 | 110 | offsetof(CPUOpenRISCState, sr_f), "sr_f"); |
ad75a51e | 111 | cpu_sr_cy = tcg_global_mem_new(tcg_env, |
97458071 | 112 | offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); |
ad75a51e | 113 | cpu_sr_ov = tcg_global_mem_new(tcg_env, |
97458071 | 114 | offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); |
ad75a51e | 115 | cpu_lock_addr = tcg_global_mem_new(tcg_env, |
930c3d00 RH |
116 | offsetof(CPUOpenRISCState, lock_addr), |
117 | "lock_addr"); | |
ad75a51e | 118 | cpu_lock_value = tcg_global_mem_new(tcg_env, |
930c3d00 RH |
119 | offsetof(CPUOpenRISCState, lock_value), |
120 | "lock_value"); | |
ad75a51e | 121 | fpcsr = tcg_global_mem_new_i32(tcg_env, |
bbe418f2 JL |
122 | offsetof(CPUOpenRISCState, fpcsr), |
123 | "fpcsr"); | |
ad75a51e | 124 | cpu_mac = tcg_global_mem_new_i64(tcg_env, |
6f7332ba RH |
125 | offsetof(CPUOpenRISCState, mac), |
126 | "mac"); | |
bbe418f2 | 127 | for (i = 0; i < 32; i++) { |
ad75a51e | 128 | cpu_regs[i] = tcg_global_mem_new(tcg_env, |
8bba7619 RH |
129 | offsetof(CPUOpenRISCState, |
130 | shadow_gpr[0][i]), | |
131 | regnames[i]); | |
bbe418f2 | 132 | } |
bbe418f2 JL |
133 | } |
134 | ||
bbe418f2 JL |
135 | static void gen_exception(DisasContext *dc, unsigned int excp) |
136 | { | |
ad75a51e | 137 | gen_helper_exception(tcg_env, tcg_constant_i32(excp)); |
bbe418f2 JL |
138 | } |
139 | ||
140 | static void gen_illegal_exception(DisasContext *dc) | |
141 | { | |
1ffa4bce | 142 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); |
bbe418f2 | 143 | gen_exception(dc, EXCP_ILLEGAL); |
1ffa4bce | 144 | dc->base.is_jmp = DISAS_NORETURN; |
bbe418f2 JL |
145 | } |
146 | ||
2b13b4b9 RH |
147 | static bool check_v1_3(DisasContext *dc) |
148 | { | |
149 | return dc->avr >= 0x01030000; | |
150 | } | |
151 | ||
fe636d37 | 152 | static bool check_of32s(DisasContext *dc) |
bbe418f2 | 153 | { |
fe636d37 | 154 | return dc->cpucfgr & CPUCFGR_OF32S; |
bbe418f2 | 155 | } |
bbe418f2 | 156 | |
62f2b038 RH |
157 | static bool check_of64a32s(DisasContext *dc) |
158 | { | |
159 | return dc->cpucfgr & CPUCFGR_OF64A32S; | |
160 | } | |
161 | ||
8bba7619 RH |
162 | static TCGv cpu_R(DisasContext *dc, int reg) |
163 | { | |
d29f4368 RH |
164 | if (reg == 0) { |
165 | return dc->R0; | |
166 | } else { | |
167 | return cpu_regs[reg]; | |
168 | } | |
8bba7619 RH |
169 | } |
170 | ||
cdd0f459 RH |
171 | /* |
172 | * We're about to write to REG. On the off-chance that the user is | |
173 | * writing to R0, re-instate the architectural register. | |
174 | */ | |
175 | static void check_r0_write(DisasContext *dc, int reg) | |
176 | { | |
177 | if (unlikely(reg == 0)) { | |
d29f4368 | 178 | dc->R0 = cpu_regs[0]; |
cdd0f459 RH |
179 | } |
180 | } | |
6597c28d | 181 | |
97458071 | 182 | static void gen_ove_cy(DisasContext *dc) |
9ecaa27e | 183 | { |
0c53d734 | 184 | if (dc->tb_flags & SR_OVE) { |
ad75a51e | 185 | gen_helper_ove_cy(tcg_env); |
0c53d734 | 186 | } |
9ecaa27e RH |
187 | } |
188 | ||
97458071 | 189 | static void gen_ove_ov(DisasContext *dc) |
9ecaa27e | 190 | { |
0c53d734 | 191 | if (dc->tb_flags & SR_OVE) { |
ad75a51e | 192 | gen_helper_ove_ov(tcg_env); |
0c53d734 | 193 | } |
9ecaa27e RH |
194 | } |
195 | ||
97458071 | 196 | static void gen_ove_cyov(DisasContext *dc) |
9ecaa27e | 197 | { |
0c53d734 | 198 | if (dc->tb_flags & SR_OVE) { |
ad75a51e | 199 | gen_helper_ove_cyov(tcg_env); |
0c53d734 | 200 | } |
9ecaa27e RH |
201 | } |
202 | ||
203 | static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
204 | { | |
e0efc48f | 205 | TCGv t0 = tcg_temp_new(); |
9ecaa27e | 206 | TCGv res = tcg_temp_new(); |
9ecaa27e | 207 | |
e0efc48f | 208 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, srcb, dc->zero); |
97458071 | 209 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); |
9ecaa27e | 210 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 211 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
212 | |
213 | tcg_gen_mov_tl(dest, res); | |
9ecaa27e | 214 | |
97458071 | 215 | gen_ove_cyov(dc); |
9ecaa27e RH |
216 | } |
217 | ||
218 | static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
219 | { | |
e0efc48f | 220 | TCGv t0 = tcg_temp_new(); |
9ecaa27e | 221 | TCGv res = tcg_temp_new(); |
9ecaa27e | 222 | |
e0efc48f RH |
223 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, cpu_sr_cy, dc->zero); |
224 | tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, dc->zero); | |
97458071 | 225 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); |
9ecaa27e | 226 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 227 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
228 | |
229 | tcg_gen_mov_tl(dest, res); | |
9ecaa27e | 230 | |
97458071 | 231 | gen_ove_cyov(dc); |
9ecaa27e RH |
232 | } |
233 | ||
234 | static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
235 | { | |
236 | TCGv res = tcg_temp_new(); | |
9ecaa27e RH |
237 | |
238 | tcg_gen_sub_tl(res, srca, srcb); | |
97458071 RH |
239 | tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); |
240 | tcg_gen_xor_tl(cpu_sr_ov, res, srcb); | |
241 | tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); | |
242 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); | |
9ecaa27e RH |
243 | |
244 | tcg_gen_mov_tl(dest, res); | |
9ecaa27e | 245 | |
97458071 | 246 | gen_ove_cyov(dc); |
9ecaa27e RH |
247 | } |
248 | ||
249 | static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
250 | { | |
9ecaa27e RH |
251 | TCGv t0 = tcg_temp_new(); |
252 | ||
97458071 | 253 | tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); |
9ecaa27e | 254 | tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); |
cfe15887 | 255 | tcg_gen_negsetcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); |
9ecaa27e | 256 | |
97458071 | 257 | gen_ove_ov(dc); |
9ecaa27e RH |
258 | } |
259 | ||
260 | static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
261 | { | |
97458071 RH |
262 | tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); |
263 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); | |
9ecaa27e | 264 | |
97458071 | 265 | gen_ove_cy(dc); |
9ecaa27e RH |
266 | } |
267 | ||
268 | static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
269 | { | |
9ecaa27e RH |
270 | TCGv t0 = tcg_temp_new(); |
271 | ||
97458071 | 272 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); |
9ecaa27e | 273 | /* The result of divide-by-zero is undefined. |
8b81968c | 274 | Suppress the host-side exception by dividing by 1. */ |
97458071 | 275 | tcg_gen_or_tl(t0, srcb, cpu_sr_ov); |
9ecaa27e | 276 | tcg_gen_div_tl(dest, srca, t0); |
9ecaa27e | 277 | |
97458071 RH |
278 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
279 | gen_ove_ov(dc); | |
9ecaa27e RH |
280 | } |
281 | ||
282 | static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
283 | { | |
9ecaa27e RH |
284 | TCGv t0 = tcg_temp_new(); |
285 | ||
97458071 | 286 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); |
9ecaa27e | 287 | /* The result of divide-by-zero is undefined. |
8b81968c | 288 | Suppress the host-side exception by dividing by 1. */ |
97458071 | 289 | tcg_gen_or_tl(t0, srcb, cpu_sr_cy); |
9ecaa27e | 290 | tcg_gen_divu_tl(dest, srca, t0); |
9ecaa27e | 291 | |
97458071 | 292 | gen_ove_cy(dc); |
9ecaa27e | 293 | } |
da1d7759 | 294 | |
cc5de49e RH |
295 | static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) |
296 | { | |
297 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
298 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
299 | ||
300 | tcg_gen_ext_tl_i64(t1, srca); | |
301 | tcg_gen_ext_tl_i64(t2, srcb); | |
302 | if (TARGET_LONG_BITS == 32) { | |
303 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
304 | tcg_gen_movi_tl(cpu_sr_ov, 0); | |
305 | } else { | |
306 | TCGv_i64 high = tcg_temp_new_i64(); | |
307 | ||
308 | tcg_gen_muls2_i64(cpu_mac, high, t1, t2); | |
309 | tcg_gen_sari_i64(t1, cpu_mac, 63); | |
cfe15887 | 310 | tcg_gen_negsetcond_i64(TCG_COND_NE, t1, t1, high); |
cc5de49e | 311 | tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); |
cc5de49e RH |
312 | |
313 | gen_ove_ov(dc); | |
314 | } | |
cc5de49e RH |
315 | } |
316 | ||
317 | static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) | |
318 | { | |
319 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
320 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
321 | ||
322 | tcg_gen_extu_tl_i64(t1, srca); | |
323 | tcg_gen_extu_tl_i64(t2, srcb); | |
324 | if (TARGET_LONG_BITS == 32) { | |
325 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
326 | tcg_gen_movi_tl(cpu_sr_cy, 0); | |
327 | } else { | |
328 | TCGv_i64 high = tcg_temp_new_i64(); | |
329 | ||
330 | tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); | |
331 | tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); | |
332 | tcg_gen_trunc_i64_tl(cpu_sr_cy, high); | |
cc5de49e RH |
333 | |
334 | gen_ove_cy(dc); | |
335 | } | |
cc5de49e RH |
336 | } |
337 | ||
6f7332ba RH |
338 | static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) |
339 | { | |
340 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
341 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
342 | ||
343 | tcg_gen_ext_tl_i64(t1, srca); | |
344 | tcg_gen_ext_tl_i64(t2, srcb); | |
345 | tcg_gen_mul_i64(t1, t1, t2); | |
346 | ||
347 | /* Note that overflow is only computed during addition stage. */ | |
348 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
349 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
350 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
351 | tcg_gen_andc_i64(t1, t1, t2); | |
6f7332ba RH |
352 | |
353 | #if TARGET_LONG_BITS == 32 | |
354 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
355 | #else | |
356 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
357 | #endif | |
6f7332ba RH |
358 | |
359 | gen_ove_ov(dc); | |
360 | } | |
361 | ||
cc5de49e RH |
362 | static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb) |
363 | { | |
364 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
365 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
366 | ||
367 | tcg_gen_extu_tl_i64(t1, srca); | |
368 | tcg_gen_extu_tl_i64(t2, srcb); | |
369 | tcg_gen_mul_i64(t1, t1, t2); | |
cc5de49e RH |
370 | |
371 | /* Note that overflow is only computed during addition stage. */ | |
372 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
373 | tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); | |
374 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); | |
cc5de49e RH |
375 | |
376 | gen_ove_cy(dc); | |
377 | } | |
378 | ||
6f7332ba RH |
379 | static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb) |
380 | { | |
381 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
382 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
383 | ||
384 | tcg_gen_ext_tl_i64(t1, srca); | |
385 | tcg_gen_ext_tl_i64(t2, srcb); | |
386 | tcg_gen_mul_i64(t1, t1, t2); | |
387 | ||
388 | /* Note that overflow is only computed during subtraction stage. */ | |
389 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
390 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
391 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
392 | tcg_gen_and_i64(t1, t1, t2); | |
6f7332ba RH |
393 | |
394 | #if TARGET_LONG_BITS == 32 | |
395 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
396 | #else | |
397 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
398 | #endif | |
6f7332ba RH |
399 | |
400 | gen_ove_ov(dc); | |
401 | } | |
402 | ||
cc5de49e RH |
403 | static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) |
404 | { | |
405 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
406 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
407 | ||
408 | tcg_gen_extu_tl_i64(t1, srca); | |
409 | tcg_gen_extu_tl_i64(t2, srcb); | |
410 | tcg_gen_mul_i64(t1, t1, t2); | |
411 | ||
412 | /* Note that overflow is only computed during subtraction stage. */ | |
413 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); | |
414 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
415 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); | |
cc5de49e RH |
416 | |
417 | gen_ove_cy(dc); | |
418 | } | |
419 | ||
3a7be554 | 420 | static bool trans_l_add(DisasContext *dc, arg_dab *a) |
bbe418f2 | 421 | { |
cdd0f459 | 422 | check_r0_write(dc, a->d); |
8bba7619 | 423 | gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
424 | return true; |
425 | } | |
bbe418f2 | 426 | |
3a7be554 | 427 | static bool trans_l_addc(DisasContext *dc, arg_dab *a) |
6ad216ab | 428 | { |
cdd0f459 | 429 | check_r0_write(dc, a->d); |
8bba7619 | 430 | gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
431 | return true; |
432 | } | |
cf2ae442 | 433 | |
3a7be554 | 434 | static bool trans_l_sub(DisasContext *dc, arg_dab *a) |
6ad216ab | 435 | { |
cdd0f459 | 436 | check_r0_write(dc, a->d); |
8bba7619 | 437 | gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
438 | return true; |
439 | } | |
bbe418f2 | 440 | |
3a7be554 | 441 | static bool trans_l_and(DisasContext *dc, arg_dab *a) |
6ad216ab | 442 | { |
cdd0f459 | 443 | check_r0_write(dc, a->d); |
8bba7619 | 444 | tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
445 | return true; |
446 | } | |
447 | ||
3a7be554 | 448 | static bool trans_l_or(DisasContext *dc, arg_dab *a) |
6ad216ab | 449 | { |
cdd0f459 | 450 | check_r0_write(dc, a->d); |
8bba7619 | 451 | tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
452 | return true; |
453 | } | |
454 | ||
3a7be554 | 455 | static bool trans_l_xor(DisasContext *dc, arg_dab *a) |
6ad216ab | 456 | { |
cdd0f459 | 457 | check_r0_write(dc, a->d); |
8bba7619 | 458 | tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
459 | return true; |
460 | } | |
bbe418f2 | 461 | |
3a7be554 | 462 | static bool trans_l_sll(DisasContext *dc, arg_dab *a) |
6ad216ab | 463 | { |
cdd0f459 | 464 | check_r0_write(dc, a->d); |
8bba7619 | 465 | tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
466 | return true; |
467 | } | |
bbe418f2 | 468 | |
3a7be554 | 469 | static bool trans_l_srl(DisasContext *dc, arg_dab *a) |
6ad216ab | 470 | { |
cdd0f459 | 471 | check_r0_write(dc, a->d); |
8bba7619 | 472 | tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
473 | return true; |
474 | } | |
cc5de49e | 475 | |
3a7be554 | 476 | static bool trans_l_sra(DisasContext *dc, arg_dab *a) |
6ad216ab | 477 | { |
cdd0f459 | 478 | check_r0_write(dc, a->d); |
8bba7619 | 479 | tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
480 | return true; |
481 | } | |
bbe418f2 | 482 | |
3a7be554 | 483 | static bool trans_l_ror(DisasContext *dc, arg_dab *a) |
6ad216ab | 484 | { |
cdd0f459 | 485 | check_r0_write(dc, a->d); |
8bba7619 | 486 | tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
487 | return true; |
488 | } | |
bbe418f2 | 489 | |
3a7be554 | 490 | static bool trans_l_exths(DisasContext *dc, arg_da *a) |
6ad216ab | 491 | { |
cdd0f459 | 492 | check_r0_write(dc, a->d); |
8bba7619 | 493 | tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
494 | return true; |
495 | } | |
cc5de49e | 496 | |
3a7be554 | 497 | static bool trans_l_extbs(DisasContext *dc, arg_da *a) |
6ad216ab | 498 | { |
cdd0f459 | 499 | check_r0_write(dc, a->d); |
8bba7619 | 500 | tcg_gen_ext8s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
501 | return true; |
502 | } | |
503 | ||
3a7be554 | 504 | static bool trans_l_exthz(DisasContext *dc, arg_da *a) |
6ad216ab | 505 | { |
cdd0f459 | 506 | check_r0_write(dc, a->d); |
8bba7619 | 507 | tcg_gen_ext16u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
508 | return true; |
509 | } | |
510 | ||
3a7be554 | 511 | static bool trans_l_extbz(DisasContext *dc, arg_da *a) |
6ad216ab | 512 | { |
cdd0f459 | 513 | check_r0_write(dc, a->d); |
8bba7619 | 514 | tcg_gen_ext8u_tl(cpu_R(dc, a->d), cpu_R(dc, a->a)); |
6ad216ab RH |
515 | return true; |
516 | } | |
517 | ||
3a7be554 | 518 | static bool trans_l_cmov(DisasContext *dc, arg_dab *a) |
6ad216ab | 519 | { |
cdd0f459 | 520 | check_r0_write(dc, a->d); |
118671f0 | 521 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_R(dc, a->d), cpu_sr_f, dc->zero, |
8bba7619 | 522 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
523 | return true; |
524 | } | |
525 | ||
3a7be554 | 526 | static bool trans_l_ff1(DisasContext *dc, arg_da *a) |
6ad216ab | 527 | { |
cdd0f459 | 528 | check_r0_write(dc, a->d); |
8bba7619 RH |
529 | tcg_gen_ctzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), -1); |
530 | tcg_gen_addi_tl(cpu_R(dc, a->d), cpu_R(dc, a->d), 1); | |
6ad216ab RH |
531 | return true; |
532 | } | |
533 | ||
3a7be554 | 534 | static bool trans_l_fl1(DisasContext *dc, arg_da *a) |
6ad216ab | 535 | { |
cdd0f459 | 536 | check_r0_write(dc, a->d); |
8bba7619 RH |
537 | tcg_gen_clzi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), TARGET_LONG_BITS); |
538 | tcg_gen_subfi_tl(cpu_R(dc, a->d), TARGET_LONG_BITS, cpu_R(dc, a->d)); | |
6ad216ab RH |
539 | return true; |
540 | } | |
541 | ||
3a7be554 | 542 | static bool trans_l_mul(DisasContext *dc, arg_dab *a) |
6ad216ab | 543 | { |
cdd0f459 | 544 | check_r0_write(dc, a->d); |
8bba7619 | 545 | gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
546 | return true; |
547 | } | |
548 | ||
3a7be554 | 549 | static bool trans_l_mulu(DisasContext *dc, arg_dab *a) |
6ad216ab | 550 | { |
cdd0f459 | 551 | check_r0_write(dc, a->d); |
8bba7619 | 552 | gen_mulu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
553 | return true; |
554 | } | |
555 | ||
3a7be554 | 556 | static bool trans_l_div(DisasContext *dc, arg_dab *a) |
6ad216ab | 557 | { |
cdd0f459 | 558 | check_r0_write(dc, a->d); |
8bba7619 | 559 | gen_div(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
560 | return true; |
561 | } | |
562 | ||
3a7be554 | 563 | static bool trans_l_divu(DisasContext *dc, arg_dab *a) |
6ad216ab | 564 | { |
cdd0f459 | 565 | check_r0_write(dc, a->d); |
8bba7619 | 566 | gen_divu(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
567 | return true; |
568 | } | |
569 | ||
3a7be554 | 570 | static bool trans_l_muld(DisasContext *dc, arg_ab *a) |
6ad216ab | 571 | { |
8bba7619 | 572 | gen_muld(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab RH |
573 | return true; |
574 | } | |
575 | ||
3a7be554 | 576 | static bool trans_l_muldu(DisasContext *dc, arg_ab *a) |
6ad216ab | 577 | { |
8bba7619 | 578 | gen_muldu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6ad216ab | 579 | return true; |
bbe418f2 JL |
580 | } |
581 | ||
3a7be554 | 582 | static bool trans_l_j(DisasContext *dc, arg_l_j *a) |
136e13ae RH |
583 | { |
584 | target_ulong tmp_pc = dc->base.pc_next + a->n * 4; | |
585 | ||
136e13ae | 586 | tcg_gen_movi_tl(jmp_pc, tmp_pc); |
8000ba56 | 587 | dc->jmp_pc_imm = tmp_pc; |
136e13ae RH |
588 | dc->delayed_branch = 2; |
589 | return true; | |
590 | } | |
591 | ||
3a7be554 | 592 | static bool trans_l_jal(DisasContext *dc, arg_l_jal *a) |
136e13ae RH |
593 | { |
594 | target_ulong tmp_pc = dc->base.pc_next + a->n * 4; | |
595 | target_ulong ret_pc = dc->base.pc_next + 8; | |
596 | ||
8bba7619 | 597 | tcg_gen_movi_tl(cpu_regs[9], ret_pc); |
136e13ae RH |
598 | /* Optimize jal being used to load the PC for PIC. */ |
599 | if (tmp_pc != ret_pc) { | |
600 | tcg_gen_movi_tl(jmp_pc, tmp_pc); | |
8000ba56 | 601 | dc->jmp_pc_imm = tmp_pc; |
136e13ae RH |
602 | dc->delayed_branch = 2; |
603 | } | |
604 | return true; | |
605 | } | |
606 | ||
607 | static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond) | |
608 | { | |
609 | target_ulong tmp_pc = dc->base.pc_next + a->n * 4; | |
af42d354 RH |
610 | TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8); |
611 | TCGv t_true = tcg_constant_tl(tmp_pc); | |
136e13ae | 612 | |
118671f0 | 613 | tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, dc->zero, t_true, t_next); |
136e13ae RH |
614 | dc->delayed_branch = 2; |
615 | } | |
616 | ||
3a7be554 | 617 | static bool trans_l_bf(DisasContext *dc, arg_l_bf *a) |
136e13ae | 618 | { |
136e13ae RH |
619 | do_bf(dc, a, TCG_COND_NE); |
620 | return true; | |
621 | } | |
622 | ||
3a7be554 | 623 | static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a) |
136e13ae | 624 | { |
136e13ae RH |
625 | do_bf(dc, a, TCG_COND_EQ); |
626 | return true; | |
627 | } | |
628 | ||
3a7be554 | 629 | static bool trans_l_jr(DisasContext *dc, arg_l_jr *a) |
136e13ae | 630 | { |
8bba7619 | 631 | tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); |
136e13ae RH |
632 | dc->delayed_branch = 2; |
633 | return true; | |
634 | } | |
635 | ||
3a7be554 | 636 | static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a) |
136e13ae | 637 | { |
8bba7619 RH |
638 | tcg_gen_mov_tl(jmp_pc, cpu_R(dc, a->b)); |
639 | tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8); | |
136e13ae RH |
640 | dc->delayed_branch = 2; |
641 | return true; | |
642 | } | |
643 | ||
3a7be554 | 644 | static bool trans_l_lwa(DisasContext *dc, arg_load *a) |
d80bff19 RH |
645 | { |
646 | TCGv ea; | |
647 | ||
cdd0f459 | 648 | check_r0_write(dc, a->d); |
d80bff19 | 649 | ea = tcg_temp_new(); |
8bba7619 RH |
650 | tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); |
651 | tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL); | |
d80bff19 | 652 | tcg_gen_mov_tl(cpu_lock_addr, ea); |
8bba7619 | 653 | tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d)); |
d80bff19 RH |
654 | return true; |
655 | } | |
656 | ||
14776ab5 | 657 | static void do_load(DisasContext *dc, arg_load *a, MemOp mop) |
d80bff19 RH |
658 | { |
659 | TCGv ea; | |
660 | ||
cdd0f459 | 661 | check_r0_write(dc, a->d); |
d80bff19 | 662 | ea = tcg_temp_new(); |
8bba7619 RH |
663 | tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); |
664 | tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, mop); | |
d80bff19 RH |
665 | } |
666 | ||
3a7be554 | 667 | static bool trans_l_lwz(DisasContext *dc, arg_load *a) |
d80bff19 | 668 | { |
d80bff19 RH |
669 | do_load(dc, a, MO_TEUL); |
670 | return true; | |
671 | } | |
672 | ||
3a7be554 | 673 | static bool trans_l_lws(DisasContext *dc, arg_load *a) |
d80bff19 | 674 | { |
d80bff19 RH |
675 | do_load(dc, a, MO_TESL); |
676 | return true; | |
677 | } | |
678 | ||
3a7be554 | 679 | static bool trans_l_lbz(DisasContext *dc, arg_load *a) |
d80bff19 | 680 | { |
d80bff19 RH |
681 | do_load(dc, a, MO_UB); |
682 | return true; | |
683 | } | |
684 | ||
3a7be554 | 685 | static bool trans_l_lbs(DisasContext *dc, arg_load *a) |
d80bff19 | 686 | { |
d80bff19 RH |
687 | do_load(dc, a, MO_SB); |
688 | return true; | |
689 | } | |
690 | ||
3a7be554 | 691 | static bool trans_l_lhz(DisasContext *dc, arg_load *a) |
d80bff19 | 692 | { |
d80bff19 RH |
693 | do_load(dc, a, MO_TEUW); |
694 | return true; | |
695 | } | |
696 | ||
3a7be554 | 697 | static bool trans_l_lhs(DisasContext *dc, arg_load *a) |
d80bff19 | 698 | { |
d80bff19 RH |
699 | do_load(dc, a, MO_TESW); |
700 | return true; | |
701 | } | |
702 | ||
3a7be554 | 703 | static bool trans_l_swa(DisasContext *dc, arg_store *a) |
d80bff19 RH |
704 | { |
705 | TCGv ea, val; | |
706 | TCGLabel *lab_fail, *lab_done; | |
707 | ||
d80bff19 | 708 | ea = tcg_temp_new(); |
8bba7619 | 709 | tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); |
d80bff19 | 710 | |
d80bff19 RH |
711 | lab_fail = gen_new_label(); |
712 | lab_done = gen_new_label(); | |
713 | tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); | |
d80bff19 RH |
714 | |
715 | val = tcg_temp_new(); | |
716 | tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, | |
4d10fa0f | 717 | cpu_R(dc, a->b), dc->mem_idx, MO_TEUL); |
d80bff19 | 718 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); |
d80bff19 RH |
719 | |
720 | tcg_gen_br(lab_done); | |
721 | ||
722 | gen_set_label(lab_fail); | |
723 | tcg_gen_movi_tl(cpu_sr_f, 0); | |
724 | ||
725 | gen_set_label(lab_done); | |
726 | tcg_gen_movi_tl(cpu_lock_addr, -1); | |
727 | return true; | |
728 | } | |
729 | ||
14776ab5 | 730 | static void do_store(DisasContext *dc, arg_store *a, MemOp mop) |
d80bff19 RH |
731 | { |
732 | TCGv t0 = tcg_temp_new(); | |
8bba7619 RH |
733 | tcg_gen_addi_tl(t0, cpu_R(dc, a->a), a->i); |
734 | tcg_gen_qemu_st_tl(cpu_R(dc, a->b), t0, dc->mem_idx, mop); | |
d80bff19 RH |
735 | } |
736 | ||
3a7be554 | 737 | static bool trans_l_sw(DisasContext *dc, arg_store *a) |
d80bff19 | 738 | { |
d80bff19 RH |
739 | do_store(dc, a, MO_TEUL); |
740 | return true; | |
741 | } | |
742 | ||
3a7be554 | 743 | static bool trans_l_sb(DisasContext *dc, arg_store *a) |
d80bff19 | 744 | { |
d80bff19 RH |
745 | do_store(dc, a, MO_UB); |
746 | return true; | |
747 | } | |
748 | ||
3a7be554 | 749 | static bool trans_l_sh(DisasContext *dc, arg_store *a) |
d80bff19 | 750 | { |
d80bff19 RH |
751 | do_store(dc, a, MO_TEUW); |
752 | return true; | |
753 | } | |
754 | ||
3a7be554 | 755 | static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) |
bbe418f2 | 756 | { |
8816f70b RH |
757 | return true; |
758 | } | |
bbe418f2 | 759 | |
3e0e41ef RH |
760 | static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a) |
761 | { | |
762 | if (!check_v1_3(dc)) { | |
763 | return false; | |
764 | } | |
765 | check_r0_write(dc, a->d); | |
766 | ||
767 | tcg_gen_movi_i32(cpu_R(dc, a->d), | |
768 | (dc->base.pc_next & TARGET_PAGE_MASK) + | |
769 | ((target_long)a->i << TARGET_PAGE_BITS)); | |
770 | return true; | |
771 | } | |
772 | ||
3a7be554 | 773 | static bool trans_l_addi(DisasContext *dc, arg_rri *a) |
8816f70b | 774 | { |
cdd0f459 | 775 | check_r0_write(dc, a->d); |
af42d354 | 776 | gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); |
8816f70b RH |
777 | return true; |
778 | } | |
bbe418f2 | 779 | |
3a7be554 | 780 | static bool trans_l_addic(DisasContext *dc, arg_rri *a) |
8816f70b | 781 | { |
cdd0f459 | 782 | check_r0_write(dc, a->d); |
af42d354 | 783 | gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); |
8816f70b RH |
784 | return true; |
785 | } | |
bbe418f2 | 786 | |
3a7be554 | 787 | static bool trans_l_muli(DisasContext *dc, arg_rri *a) |
8816f70b | 788 | { |
cdd0f459 | 789 | check_r0_write(dc, a->d); |
af42d354 | 790 | gen_mul(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), tcg_constant_tl(a->i)); |
8816f70b RH |
791 | return true; |
792 | } | |
bbe418f2 | 793 | |
3a7be554 | 794 | static bool trans_l_maci(DisasContext *dc, arg_l_maci *a) |
8816f70b | 795 | { |
af42d354 | 796 | gen_mac(dc, cpu_R(dc, a->a), tcg_constant_tl(a->i)); |
8816f70b RH |
797 | return true; |
798 | } | |
bbe418f2 | 799 | |
3a7be554 | 800 | static bool trans_l_andi(DisasContext *dc, arg_rrk *a) |
8816f70b | 801 | { |
cdd0f459 | 802 | check_r0_write(dc, a->d); |
8bba7619 | 803 | tcg_gen_andi_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); |
8816f70b RH |
804 | return true; |
805 | } | |
bbe418f2 | 806 | |
3a7be554 | 807 | static bool trans_l_ori(DisasContext *dc, arg_rrk *a) |
8816f70b | 808 | { |
cdd0f459 | 809 | check_r0_write(dc, a->d); |
8bba7619 | 810 | tcg_gen_ori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->k); |
8816f70b RH |
811 | return true; |
812 | } | |
bbe418f2 | 813 | |
3a7be554 | 814 | static bool trans_l_xori(DisasContext *dc, arg_rri *a) |
8816f70b | 815 | { |
cdd0f459 | 816 | check_r0_write(dc, a->d); |
8bba7619 | 817 | tcg_gen_xori_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), a->i); |
8816f70b RH |
818 | return true; |
819 | } | |
bbe418f2 | 820 | |
3a7be554 | 821 | static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) |
8816f70b | 822 | { |
08f021de | 823 | TCGv spr = tcg_temp_new(); |
bbe418f2 | 824 | |
08f021de | 825 | check_r0_write(dc, a->d); |
01ec3ec9 | 826 | |
dfd1b812 | 827 | if (translator_io_start(&dc->base)) { |
01ec3ec9 RH |
828 | if (dc->delayed_branch) { |
829 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
830 | tcg_gen_discard_tl(jmp_pc); | |
831 | } else { | |
832 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); | |
833 | } | |
834 | dc->base.is_jmp = DISAS_EXIT; | |
08f021de SH |
835 | } |
836 | ||
837 | tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); | |
ad75a51e | 838 | gen_helper_mfspr(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), spr); |
08f021de SH |
839 | return true; |
840 | } | |
01ec3ec9 | 841 | |
08f021de SH |
842 | static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) |
843 | { | |
844 | TCGv spr = tcg_temp_new(); | |
845 | ||
dfd1b812 RH |
846 | translator_io_start(&dc->base); |
847 | ||
08f021de SH |
848 | /* |
849 | * For SR, we will need to exit the TB to recognize the new | |
850 | * exception state. For NPC, in theory this counts as a branch | |
851 | * (although the SPR only exists for use by an ICE). Save all | |
852 | * of the cpu state first, allowing it to be overwritten. | |
853 | */ | |
854 | if (dc->delayed_branch) { | |
855 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
856 | tcg_gen_discard_tl(jmp_pc); | |
857 | } else { | |
858 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); | |
859 | } | |
860 | dc->base.is_jmp = DISAS_EXIT; | |
861 | ||
862 | tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); | |
ad75a51e | 863 | gen_helper_mtspr(tcg_env, spr, cpu_R(dc, a->b)); |
8816f70b | 864 | return true; |
bbe418f2 JL |
865 | } |
866 | ||
3a7be554 | 867 | static bool trans_l_mac(DisasContext *dc, arg_ab *a) |
bbe418f2 | 868 | { |
8bba7619 | 869 | gen_mac(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 RH |
870 | return true; |
871 | } | |
bbe418f2 | 872 | |
3a7be554 | 873 | static bool trans_l_msb(DisasContext *dc, arg_ab *a) |
99d863d6 | 874 | { |
8bba7619 | 875 | gen_msb(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 RH |
876 | return true; |
877 | } | |
cc5de49e | 878 | |
3a7be554 | 879 | static bool trans_l_macu(DisasContext *dc, arg_ab *a) |
99d863d6 | 880 | { |
8bba7619 | 881 | gen_macu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 RH |
882 | return true; |
883 | } | |
cc5de49e | 884 | |
3a7be554 | 885 | static bool trans_l_msbu(DisasContext *dc, arg_ab *a) |
99d863d6 | 886 | { |
8bba7619 | 887 | gen_msbu(dc, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
99d863d6 | 888 | return true; |
bbe418f2 JL |
889 | } |
890 | ||
3a7be554 | 891 | static bool trans_l_slli(DisasContext *dc, arg_dal *a) |
bbe418f2 | 892 | { |
cdd0f459 | 893 | check_r0_write(dc, a->d); |
8bba7619 RH |
894 | tcg_gen_shli_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
895 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 RH |
896 | return true; |
897 | } | |
bbe418f2 | 898 | |
3a7be554 | 899 | static bool trans_l_srli(DisasContext *dc, arg_dal *a) |
e20c2592 | 900 | { |
cdd0f459 | 901 | check_r0_write(dc, a->d); |
8bba7619 RH |
902 | tcg_gen_shri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
903 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 RH |
904 | return true; |
905 | } | |
bbe418f2 | 906 | |
3a7be554 | 907 | static bool trans_l_srai(DisasContext *dc, arg_dal *a) |
e20c2592 | 908 | { |
cdd0f459 | 909 | check_r0_write(dc, a->d); |
8bba7619 RH |
910 | tcg_gen_sari_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
911 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 RH |
912 | return true; |
913 | } | |
bbe418f2 | 914 | |
3a7be554 | 915 | static bool trans_l_rori(DisasContext *dc, arg_dal *a) |
e20c2592 | 916 | { |
cdd0f459 | 917 | check_r0_write(dc, a->d); |
8bba7619 RH |
918 | tcg_gen_rotri_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), |
919 | a->l & (TARGET_LONG_BITS - 1)); | |
e20c2592 | 920 | return true; |
bbe418f2 JL |
921 | } |
922 | ||
3a7be554 | 923 | static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a) |
bbe418f2 | 924 | { |
cdd0f459 | 925 | check_r0_write(dc, a->d); |
8bba7619 | 926 | tcg_gen_movi_tl(cpu_R(dc, a->d), a->k << 16); |
e720a571 RH |
927 | return true; |
928 | } | |
bbe418f2 | 929 | |
3a7be554 | 930 | static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a) |
e720a571 | 931 | { |
cdd0f459 | 932 | check_r0_write(dc, a->d); |
8bba7619 | 933 | tcg_gen_trunc_i64_tl(cpu_R(dc, a->d), cpu_mac); |
e720a571 RH |
934 | tcg_gen_movi_i64(cpu_mac, 0); |
935 | return true; | |
bbe418f2 JL |
936 | } |
937 | ||
3a7be554 | 938 | static bool trans_l_sfeq(DisasContext *dc, arg_ab *a) |
bbe418f2 | 939 | { |
8bba7619 RH |
940 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, |
941 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
942 | return true; |
943 | } | |
bbe418f2 | 944 | |
3a7be554 | 945 | static bool trans_l_sfne(DisasContext *dc, arg_ab *a) |
fbb3e29a | 946 | { |
8bba7619 RH |
947 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, |
948 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
949 | return true; |
950 | } | |
bbe418f2 | 951 | |
3a7be554 | 952 | static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 953 | { |
8bba7619 RH |
954 | tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, |
955 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
956 | return true; |
957 | } | |
bbe418f2 | 958 | |
3a7be554 | 959 | static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 960 | { |
8bba7619 RH |
961 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, |
962 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
963 | return true; |
964 | } | |
bbe418f2 | 965 | |
3a7be554 | 966 | static bool trans_l_sfltu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 967 | { |
8bba7619 RH |
968 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, |
969 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
970 | return true; |
971 | } | |
bbe418f2 | 972 | |
3a7be554 | 973 | static bool trans_l_sfleu(DisasContext *dc, arg_ab *a) |
fbb3e29a | 974 | { |
8bba7619 RH |
975 | tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, |
976 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
977 | return true; |
978 | } | |
bbe418f2 | 979 | |
3a7be554 | 980 | static bool trans_l_sfgts(DisasContext *dc, arg_ab *a) |
fbb3e29a | 981 | { |
8bba7619 RH |
982 | tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, |
983 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
984 | return true; |
985 | } | |
bbe418f2 | 986 | |
3a7be554 | 987 | static bool trans_l_sfges(DisasContext *dc, arg_ab *a) |
fbb3e29a | 988 | { |
8bba7619 RH |
989 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, |
990 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
991 | return true; |
992 | } | |
bbe418f2 | 993 | |
3a7be554 | 994 | static bool trans_l_sflts(DisasContext *dc, arg_ab *a) |
fbb3e29a | 995 | { |
8bba7619 RH |
996 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, |
997 | cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a RH |
998 | return true; |
999 | } | |
bbe418f2 | 1000 | |
3a7be554 | 1001 | static bool trans_l_sfles(DisasContext *dc, arg_ab *a) |
fbb3e29a | 1002 | { |
8bba7619 RH |
1003 | tcg_gen_setcond_tl(TCG_COND_LE, |
1004 | cpu_sr_f, cpu_R(dc, a->a), cpu_R(dc, a->b)); | |
fbb3e29a | 1005 | return true; |
bbe418f2 JL |
1006 | } |
1007 | ||
3a7be554 | 1008 | static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a) |
bbe418f2 | 1009 | { |
8bba7619 | 1010 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1011 | return true; |
1012 | } | |
bbe418f2 | 1013 | |
3a7be554 | 1014 | static bool trans_l_sfnei(DisasContext *dc, arg_ai *a) |
032de4fc | 1015 | { |
8bba7619 | 1016 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1017 | return true; |
1018 | } | |
bbe418f2 | 1019 | |
3a7be554 | 1020 | static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a) |
032de4fc | 1021 | { |
8bba7619 | 1022 | tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1023 | return true; |
1024 | } | |
bbe418f2 | 1025 | |
3a7be554 | 1026 | static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a) |
032de4fc | 1027 | { |
8bba7619 | 1028 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1029 | return true; |
1030 | } | |
bbe418f2 | 1031 | |
3a7be554 | 1032 | static bool trans_l_sfltui(DisasContext *dc, arg_ai *a) |
032de4fc | 1033 | { |
8bba7619 | 1034 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1035 | return true; |
1036 | } | |
bbe418f2 | 1037 | |
3a7be554 | 1038 | static bool trans_l_sfleui(DisasContext *dc, arg_ai *a) |
032de4fc | 1039 | { |
8bba7619 | 1040 | tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1041 | return true; |
1042 | } | |
bbe418f2 | 1043 | |
3a7be554 | 1044 | static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a) |
032de4fc | 1045 | { |
8bba7619 | 1046 | tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1047 | return true; |
1048 | } | |
bbe418f2 | 1049 | |
3a7be554 | 1050 | static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a) |
032de4fc | 1051 | { |
8bba7619 | 1052 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1053 | return true; |
1054 | } | |
bbe418f2 | 1055 | |
3a7be554 | 1056 | static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a) |
032de4fc | 1057 | { |
8bba7619 | 1058 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc RH |
1059 | return true; |
1060 | } | |
bbe418f2 | 1061 | |
3a7be554 | 1062 | static bool trans_l_sflesi(DisasContext *dc, arg_ai *a) |
032de4fc | 1063 | { |
8bba7619 | 1064 | tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R(dc, a->a), a->i); |
032de4fc | 1065 | return true; |
bbe418f2 JL |
1066 | } |
1067 | ||
3a7be554 | 1068 | static bool trans_l_sys(DisasContext *dc, arg_l_sys *a) |
bbe418f2 | 1069 | { |
7de9729f RH |
1070 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); |
1071 | gen_exception(dc, EXCP_SYSCALL); | |
1072 | dc->base.is_jmp = DISAS_NORETURN; | |
1073 | return true; | |
1074 | } | |
bbe418f2 | 1075 | |
3a7be554 | 1076 | static bool trans_l_trap(DisasContext *dc, arg_l_trap *a) |
7de9729f | 1077 | { |
7de9729f RH |
1078 | tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); |
1079 | gen_exception(dc, EXCP_TRAP); | |
1080 | dc->base.is_jmp = DISAS_NORETURN; | |
1081 | return true; | |
1082 | } | |
bbe418f2 | 1083 | |
3a7be554 | 1084 | static bool trans_l_msync(DisasContext *dc, arg_l_msync *a) |
7de9729f | 1085 | { |
7de9729f RH |
1086 | tcg_gen_mb(TCG_MO_ALL); |
1087 | return true; | |
1088 | } | |
bbe418f2 | 1089 | |
3a7be554 | 1090 | static bool trans_l_psync(DisasContext *dc, arg_l_psync *a) |
7de9729f | 1091 | { |
7de9729f RH |
1092 | return true; |
1093 | } | |
bbe418f2 | 1094 | |
3a7be554 | 1095 | static bool trans_l_csync(DisasContext *dc, arg_l_csync *a) |
7de9729f | 1096 | { |
7de9729f | 1097 | return true; |
bbe418f2 JL |
1098 | } |
1099 | ||
3a7be554 | 1100 | static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a) |
8816f70b | 1101 | { |
2ba65417 | 1102 | if (is_user(dc)) { |
8816f70b RH |
1103 | gen_illegal_exception(dc); |
1104 | } else { | |
ad75a51e | 1105 | gen_helper_rfe(tcg_env); |
64e46c95 | 1106 | dc->base.is_jmp = DISAS_EXIT; |
8816f70b | 1107 | } |
8816f70b RH |
1108 | return true; |
1109 | } | |
1110 | ||
fe636d37 | 1111 | static bool do_fp2(DisasContext *dc, arg_da *a, |
6fd204a2 RH |
1112 | void (*fn)(TCGv, TCGv_env, TCGv)) |
1113 | { | |
fe636d37 RH |
1114 | if (!check_of32s(dc)) { |
1115 | return false; | |
1116 | } | |
cdd0f459 | 1117 | check_r0_write(dc, a->d); |
ad75a51e RH |
1118 | fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a)); |
1119 | gen_helper_update_fpcsr(tcg_env); | |
fe636d37 | 1120 | return true; |
6fd204a2 | 1121 | } |
bbe418f2 | 1122 | |
fe636d37 | 1123 | static bool do_fp3(DisasContext *dc, arg_dab *a, |
6fd204a2 RH |
1124 | void (*fn)(TCGv, TCGv_env, TCGv, TCGv)) |
1125 | { | |
fe636d37 RH |
1126 | if (!check_of32s(dc)) { |
1127 | return false; | |
1128 | } | |
cdd0f459 | 1129 | check_r0_write(dc, a->d); |
ad75a51e RH |
1130 | fn(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
1131 | gen_helper_update_fpcsr(tcg_env); | |
fe636d37 | 1132 | return true; |
6fd204a2 RH |
1133 | } |
1134 | ||
fe636d37 | 1135 | static bool do_fpcmp(DisasContext *dc, arg_ab *a, |
6fd204a2 RH |
1136 | void (*fn)(TCGv, TCGv_env, TCGv, TCGv), |
1137 | bool inv, bool swap) | |
1138 | { | |
fe636d37 RH |
1139 | if (!check_of32s(dc)) { |
1140 | return false; | |
1141 | } | |
6fd204a2 | 1142 | if (swap) { |
ad75a51e | 1143 | fn(cpu_sr_f, tcg_env, cpu_R(dc, a->b), cpu_R(dc, a->a)); |
6fd204a2 | 1144 | } else { |
ad75a51e | 1145 | fn(cpu_sr_f, tcg_env, cpu_R(dc, a->a), cpu_R(dc, a->b)); |
6fd204a2 RH |
1146 | } |
1147 | if (inv) { | |
1148 | tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); | |
bbe418f2 | 1149 | } |
ad75a51e | 1150 | gen_helper_update_fpcsr(tcg_env); |
fe636d37 | 1151 | return true; |
bbe418f2 JL |
1152 | } |
1153 | ||
3a7be554 | 1154 | static bool trans_lf_add_s(DisasContext *dc, arg_dab *a) |
bbe418f2 | 1155 | { |
fe636d37 | 1156 | return do_fp3(dc, a, gen_helper_float_add_s); |
6fd204a2 | 1157 | } |
bbe418f2 | 1158 | |
3a7be554 | 1159 | static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1160 | { |
fe636d37 | 1161 | return do_fp3(dc, a, gen_helper_float_sub_s); |
6fd204a2 RH |
1162 | } |
1163 | ||
3a7be554 | 1164 | static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1165 | { |
fe636d37 | 1166 | return do_fp3(dc, a, gen_helper_float_mul_s); |
6fd204a2 RH |
1167 | } |
1168 | ||
3a7be554 | 1169 | static bool trans_lf_div_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1170 | { |
fe636d37 | 1171 | return do_fp3(dc, a, gen_helper_float_div_s); |
6fd204a2 RH |
1172 | } |
1173 | ||
3a7be554 | 1174 | static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1175 | { |
fe636d37 | 1176 | return do_fp3(dc, a, gen_helper_float_rem_s); |
6fd204a2 RH |
1177 | return true; |
1178 | } | |
1179 | ||
3a7be554 | 1180 | static bool trans_lf_itof_s(DisasContext *dc, arg_da *a) |
6fd204a2 | 1181 | { |
fe636d37 | 1182 | return do_fp2(dc, a, gen_helper_itofs); |
6fd204a2 RH |
1183 | } |
1184 | ||
3a7be554 | 1185 | static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a) |
6fd204a2 | 1186 | { |
fe636d37 | 1187 | return do_fp2(dc, a, gen_helper_ftois); |
6fd204a2 | 1188 | } |
7de9729f | 1189 | |
3a7be554 | 1190 | static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a) |
6fd204a2 | 1191 | { |
fe636d37 RH |
1192 | if (!check_of32s(dc)) { |
1193 | return false; | |
1194 | } | |
cdd0f459 | 1195 | check_r0_write(dc, a->d); |
ad75a51e | 1196 | gen_helper_float_madd_s(cpu_R(dc, a->d), tcg_env, cpu_R(dc, a->d), |
8bba7619 | 1197 | cpu_R(dc, a->a), cpu_R(dc, a->b)); |
ad75a51e | 1198 | gen_helper_update_fpcsr(tcg_env); |
6fd204a2 RH |
1199 | return true; |
1200 | } | |
bbe418f2 | 1201 | |
3a7be554 | 1202 | static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1203 | { |
fe636d37 | 1204 | return do_fpcmp(dc, a, gen_helper_float_eq_s, false, false); |
6fd204a2 RH |
1205 | } |
1206 | ||
3a7be554 | 1207 | static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1208 | { |
fe636d37 | 1209 | return do_fpcmp(dc, a, gen_helper_float_eq_s, true, false); |
6fd204a2 RH |
1210 | } |
1211 | ||
3a7be554 | 1212 | static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1213 | { |
fe636d37 | 1214 | return do_fpcmp(dc, a, gen_helper_float_lt_s, false, true); |
6fd204a2 RH |
1215 | } |
1216 | ||
3a7be554 | 1217 | static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1218 | { |
fe636d37 | 1219 | return do_fpcmp(dc, a, gen_helper_float_le_s, false, true); |
6fd204a2 RH |
1220 | } |
1221 | ||
3a7be554 | 1222 | static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1223 | { |
fe636d37 | 1224 | return do_fpcmp(dc, a, gen_helper_float_lt_s, false, false); |
6fd204a2 RH |
1225 | } |
1226 | ||
3a7be554 | 1227 | static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a) |
6fd204a2 | 1228 | { |
fe636d37 | 1229 | return do_fpcmp(dc, a, gen_helper_float_le_s, false, false); |
6fd204a2 RH |
1230 | } |
1231 | ||
2b13b4b9 RH |
1232 | static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a) |
1233 | { | |
1234 | if (!check_v1_3(dc)) { | |
1235 | return false; | |
1236 | } | |
1237 | return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false); | |
1238 | } | |
1239 | ||
1240 | static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a) | |
1241 | { | |
1242 | if (!check_v1_3(dc)) { | |
1243 | return false; | |
1244 | } | |
1245 | return do_fpcmp(dc, a, gen_helper_float_ult_s, false, false); | |
1246 | } | |
1247 | ||
1248 | static bool trans_lf_sfugt_s(DisasContext *dc, arg_ab *a) | |
1249 | { | |
1250 | if (!check_v1_3(dc)) { | |
1251 | return false; | |
1252 | } | |
1253 | return do_fpcmp(dc, a, gen_helper_float_ult_s, false, true); | |
1254 | } | |
1255 | ||
1256 | static bool trans_lf_sfule_s(DisasContext *dc, arg_ab *a) | |
1257 | { | |
1258 | if (!check_v1_3(dc)) { | |
1259 | return false; | |
1260 | } | |
1261 | return do_fpcmp(dc, a, gen_helper_float_ule_s, false, false); | |
1262 | } | |
1263 | ||
1264 | static bool trans_lf_sfuge_s(DisasContext *dc, arg_ab *a) | |
1265 | { | |
1266 | if (!check_v1_3(dc)) { | |
1267 | return false; | |
1268 | } | |
1269 | return do_fpcmp(dc, a, gen_helper_float_ule_s, false, true); | |
1270 | } | |
1271 | ||
1272 | static bool trans_lf_sfun_s(DisasContext *dc, arg_ab *a) | |
1273 | { | |
1274 | if (!check_v1_3(dc)) { | |
1275 | return false; | |
1276 | } | |
1277 | return do_fpcmp(dc, a, gen_helper_float_un_s, false, false); | |
1278 | } | |
1279 | ||
62f2b038 RH |
1280 | static bool check_pair(DisasContext *dc, int r, int p) |
1281 | { | |
1282 | return r + 1 + p < 32; | |
1283 | } | |
1284 | ||
1285 | static void load_pair(DisasContext *dc, TCGv_i64 t, int r, int p) | |
1286 | { | |
1287 | tcg_gen_concat_i32_i64(t, cpu_R(dc, r + 1 + p), cpu_R(dc, r)); | |
1288 | } | |
1289 | ||
1290 | static void save_pair(DisasContext *dc, TCGv_i64 t, int r, int p) | |
1291 | { | |
1292 | tcg_gen_extr_i64_i32(cpu_R(dc, r + 1 + p), cpu_R(dc, r), t); | |
1293 | } | |
1294 | ||
1295 | static bool do_dp3(DisasContext *dc, arg_dab_pair *a, | |
1296 | void (*fn)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) | |
1297 | { | |
1298 | TCGv_i64 t0, t1; | |
1299 | ||
1300 | if (!check_of64a32s(dc) || | |
1301 | !check_pair(dc, a->a, a->ap) || | |
1302 | !check_pair(dc, a->b, a->bp) || | |
1303 | !check_pair(dc, a->d, a->dp)) { | |
1304 | return false; | |
1305 | } | |
1306 | check_r0_write(dc, a->d); | |
1307 | ||
1308 | t0 = tcg_temp_new_i64(); | |
1309 | t1 = tcg_temp_new_i64(); | |
1310 | load_pair(dc, t0, a->a, a->ap); | |
1311 | load_pair(dc, t1, a->b, a->bp); | |
ad75a51e | 1312 | fn(t0, tcg_env, t0, t1); |
62f2b038 | 1313 | save_pair(dc, t0, a->d, a->dp); |
62f2b038 | 1314 | |
ad75a51e | 1315 | gen_helper_update_fpcsr(tcg_env); |
62f2b038 RH |
1316 | return true; |
1317 | } | |
1318 | ||
1319 | static bool do_dp2(DisasContext *dc, arg_da_pair *a, | |
1320 | void (*fn)(TCGv_i64, TCGv_env, TCGv_i64)) | |
1321 | { | |
1322 | TCGv_i64 t0; | |
1323 | ||
1324 | if (!check_of64a32s(dc) || | |
1325 | !check_pair(dc, a->a, a->ap) || | |
1326 | !check_pair(dc, a->d, a->dp)) { | |
1327 | return false; | |
1328 | } | |
1329 | check_r0_write(dc, a->d); | |
1330 | ||
1331 | t0 = tcg_temp_new_i64(); | |
1332 | load_pair(dc, t0, a->a, a->ap); | |
ad75a51e | 1333 | fn(t0, tcg_env, t0); |
62f2b038 | 1334 | save_pair(dc, t0, a->d, a->dp); |
62f2b038 | 1335 | |
ad75a51e | 1336 | gen_helper_update_fpcsr(tcg_env); |
62f2b038 RH |
1337 | return true; |
1338 | } | |
1339 | ||
1340 | static bool do_dpcmp(DisasContext *dc, arg_ab_pair *a, | |
1341 | void (*fn)(TCGv, TCGv_env, TCGv_i64, TCGv_i64), | |
1342 | bool inv, bool swap) | |
1343 | { | |
1344 | TCGv_i64 t0, t1; | |
1345 | ||
1346 | if (!check_of64a32s(dc) || | |
1347 | !check_pair(dc, a->a, a->ap) || | |
1348 | !check_pair(dc, a->b, a->bp)) { | |
1349 | return false; | |
1350 | } | |
1351 | ||
1352 | t0 = tcg_temp_new_i64(); | |
1353 | t1 = tcg_temp_new_i64(); | |
1354 | load_pair(dc, t0, a->a, a->ap); | |
1355 | load_pair(dc, t1, a->b, a->bp); | |
1356 | if (swap) { | |
ad75a51e | 1357 | fn(cpu_sr_f, tcg_env, t1, t0); |
62f2b038 | 1358 | } else { |
ad75a51e | 1359 | fn(cpu_sr_f, tcg_env, t0, t1); |
62f2b038 | 1360 | } |
62f2b038 RH |
1361 | |
1362 | if (inv) { | |
1363 | tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1); | |
1364 | } | |
ad75a51e | 1365 | gen_helper_update_fpcsr(tcg_env); |
62f2b038 RH |
1366 | return true; |
1367 | } | |
1368 | ||
1369 | static bool trans_lf_add_d(DisasContext *dc, arg_dab_pair *a) | |
1370 | { | |
1371 | return do_dp3(dc, a, gen_helper_float_add_d); | |
1372 | } | |
1373 | ||
1374 | static bool trans_lf_sub_d(DisasContext *dc, arg_dab_pair *a) | |
1375 | { | |
1376 | return do_dp3(dc, a, gen_helper_float_sub_d); | |
1377 | } | |
1378 | ||
1379 | static bool trans_lf_mul_d(DisasContext *dc, arg_dab_pair *a) | |
1380 | { | |
1381 | return do_dp3(dc, a, gen_helper_float_mul_d); | |
1382 | } | |
1383 | ||
1384 | static bool trans_lf_div_d(DisasContext *dc, arg_dab_pair *a) | |
1385 | { | |
1386 | return do_dp3(dc, a, gen_helper_float_div_d); | |
1387 | } | |
1388 | ||
1389 | static bool trans_lf_rem_d(DisasContext *dc, arg_dab_pair *a) | |
1390 | { | |
1391 | return do_dp3(dc, a, gen_helper_float_rem_d); | |
1392 | } | |
1393 | ||
1394 | static bool trans_lf_itof_d(DisasContext *dc, arg_da_pair *a) | |
1395 | { | |
1396 | return do_dp2(dc, a, gen_helper_itofd); | |
1397 | } | |
1398 | ||
1399 | static bool trans_lf_ftoi_d(DisasContext *dc, arg_da_pair *a) | |
1400 | { | |
1401 | return do_dp2(dc, a, gen_helper_ftoid); | |
1402 | } | |
1403 | ||
1404 | static bool trans_lf_stod_d(DisasContext *dc, arg_lf_stod_d *a) | |
1405 | { | |
1406 | TCGv_i64 t0; | |
1407 | ||
1408 | if (!check_of64a32s(dc) || | |
1409 | !check_pair(dc, a->d, a->dp)) { | |
1410 | return false; | |
1411 | } | |
1412 | check_r0_write(dc, a->d); | |
1413 | ||
1414 | t0 = tcg_temp_new_i64(); | |
ad75a51e | 1415 | gen_helper_stod(t0, tcg_env, cpu_R(dc, a->a)); |
62f2b038 | 1416 | save_pair(dc, t0, a->d, a->dp); |
62f2b038 | 1417 | |
ad75a51e | 1418 | gen_helper_update_fpcsr(tcg_env); |
62f2b038 RH |
1419 | return true; |
1420 | } | |
1421 | ||
1422 | static bool trans_lf_dtos_d(DisasContext *dc, arg_lf_dtos_d *a) | |
1423 | { | |
1424 | TCGv_i64 t0; | |
1425 | ||
1426 | if (!check_of64a32s(dc) || | |
1427 | !check_pair(dc, a->a, a->ap)) { | |
1428 | return false; | |
1429 | } | |
1430 | check_r0_write(dc, a->d); | |
1431 | ||
1432 | t0 = tcg_temp_new_i64(); | |
1433 | load_pair(dc, t0, a->a, a->ap); | |
ad75a51e | 1434 | gen_helper_dtos(cpu_R(dc, a->d), tcg_env, t0); |
62f2b038 | 1435 | |
ad75a51e | 1436 | gen_helper_update_fpcsr(tcg_env); |
62f2b038 RH |
1437 | return true; |
1438 | } | |
1439 | ||
1440 | static bool trans_lf_madd_d(DisasContext *dc, arg_dab_pair *a) | |
1441 | { | |
1442 | TCGv_i64 t0, t1, t2; | |
1443 | ||
1444 | if (!check_of64a32s(dc) || | |
1445 | !check_pair(dc, a->a, a->ap) || | |
1446 | !check_pair(dc, a->b, a->bp) || | |
1447 | !check_pair(dc, a->d, a->dp)) { | |
1448 | return false; | |
1449 | } | |
1450 | check_r0_write(dc, a->d); | |
1451 | ||
1452 | t0 = tcg_temp_new_i64(); | |
1453 | t1 = tcg_temp_new_i64(); | |
1454 | t2 = tcg_temp_new_i64(); | |
1455 | load_pair(dc, t0, a->d, a->dp); | |
1456 | load_pair(dc, t1, a->a, a->ap); | |
1457 | load_pair(dc, t2, a->b, a->bp); | |
ad75a51e | 1458 | gen_helper_float_madd_d(t0, tcg_env, t0, t1, t2); |
62f2b038 | 1459 | save_pair(dc, t0, a->d, a->dp); |
62f2b038 | 1460 | |
ad75a51e | 1461 | gen_helper_update_fpcsr(tcg_env); |
62f2b038 RH |
1462 | return true; |
1463 | } | |
1464 | ||
1465 | static bool trans_lf_sfeq_d(DisasContext *dc, arg_ab_pair *a) | |
1466 | { | |
1467 | return do_dpcmp(dc, a, gen_helper_float_eq_d, false, false); | |
1468 | } | |
1469 | ||
1470 | static bool trans_lf_sfne_d(DisasContext *dc, arg_ab_pair *a) | |
1471 | { | |
1472 | return do_dpcmp(dc, a, gen_helper_float_eq_d, true, false); | |
1473 | } | |
1474 | ||
1475 | static bool trans_lf_sfgt_d(DisasContext *dc, arg_ab_pair *a) | |
1476 | { | |
1477 | return do_dpcmp(dc, a, gen_helper_float_lt_d, false, true); | |
1478 | } | |
1479 | ||
1480 | static bool trans_lf_sfge_d(DisasContext *dc, arg_ab_pair *a) | |
1481 | { | |
1482 | return do_dpcmp(dc, a, gen_helper_float_le_d, false, true); | |
1483 | } | |
1484 | ||
1485 | static bool trans_lf_sflt_d(DisasContext *dc, arg_ab_pair *a) | |
1486 | { | |
1487 | return do_dpcmp(dc, a, gen_helper_float_lt_d, false, false); | |
1488 | } | |
1489 | ||
1490 | static bool trans_lf_sfle_d(DisasContext *dc, arg_ab_pair *a) | |
1491 | { | |
1492 | return do_dpcmp(dc, a, gen_helper_float_le_d, false, false); | |
1493 | } | |
1494 | ||
2b13b4b9 RH |
1495 | static bool trans_lf_sfueq_d(DisasContext *dc, arg_ab_pair *a) |
1496 | { | |
1497 | return do_dpcmp(dc, a, gen_helper_float_ueq_d, false, false); | |
1498 | } | |
1499 | ||
1500 | static bool trans_lf_sfule_d(DisasContext *dc, arg_ab_pair *a) | |
1501 | { | |
1502 | return do_dpcmp(dc, a, gen_helper_float_ule_d, false, false); | |
1503 | } | |
1504 | ||
1505 | static bool trans_lf_sfuge_d(DisasContext *dc, arg_ab_pair *a) | |
1506 | { | |
1507 | return do_dpcmp(dc, a, gen_helper_float_ule_d, false, true); | |
1508 | } | |
1509 | ||
1510 | static bool trans_lf_sfult_d(DisasContext *dc, arg_ab_pair *a) | |
1511 | { | |
1512 | return do_dpcmp(dc, a, gen_helper_float_ult_d, false, false); | |
1513 | } | |
1514 | ||
1515 | static bool trans_lf_sfugt_d(DisasContext *dc, arg_ab_pair *a) | |
1516 | { | |
1517 | return do_dpcmp(dc, a, gen_helper_float_ult_d, false, true); | |
1518 | } | |
1519 | ||
1520 | static bool trans_lf_sfun_d(DisasContext *dc, arg_ab_pair *a) | |
1521 | { | |
1522 | return do_dpcmp(dc, a, gen_helper_float_un_d, false, false); | |
1523 | } | |
1524 | ||
a4fd3ec3 | 1525 | static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) |
e67db06e | 1526 | { |
a4fd3ec3 | 1527 | DisasContext *dc = container_of(dcb, DisasContext, base); |
b77af26e | 1528 | CPUOpenRISCState *env = cpu_env(cs); |
a4fd3ec3 | 1529 | int bound; |
1ffa4bce | 1530 | |
a4fd3ec3 | 1531 | dc->mem_idx = cpu_mmu_index(env, false); |
1ffa4bce | 1532 | dc->tb_flags = dc->base.tb->flags; |
a01deb36 | 1533 | dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0; |
fe636d37 | 1534 | dc->cpucfgr = env->cpucfgr; |
2b13b4b9 | 1535 | dc->avr = env->avr; |
8000ba56 RH |
1536 | dc->jmp_pc_imm = -1; |
1537 | ||
a4fd3ec3 EC |
1538 | bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; |
1539 | dc->base.max_insns = MIN(dc->base.max_insns, bound); | |
1540 | } | |
bbe418f2 | 1541 | |
a4fd3ec3 EC |
1542 | static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs) |
1543 | { | |
1544 | DisasContext *dc = container_of(db, DisasContext, base); | |
bbe418f2 | 1545 | |
6597c28d RH |
1546 | /* Allow the TCG optimizer to see that R0 == 0, |
1547 | when it's true, which is the common case. */ | |
118671f0 | 1548 | dc->zero = tcg_constant_tl(0); |
6597c28d | 1549 | if (dc->tb_flags & TB_FLAGS_R0_0) { |
118671f0 | 1550 | dc->R0 = dc->zero; |
6597c28d | 1551 | } else { |
d29f4368 | 1552 | dc->R0 = cpu_regs[0]; |
6597c28d | 1553 | } |
a4fd3ec3 | 1554 | } |
6597c28d | 1555 | |
a4fd3ec3 EC |
1556 | static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
1557 | { | |
1558 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
bbe418f2 | 1559 | |
a4fd3ec3 EC |
1560 | tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0) |
1561 | | (dc->base.num_insns > 1 ? 2 : 0)); | |
1562 | } | |
b933066a | 1563 | |
a4fd3ec3 EC |
1564 | static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
1565 | { | |
1566 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
1567 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); | |
4e116893 | 1568 | uint32_t insn = translator_ldl(&cpu->env, &dc->base, dc->base.pc_next); |
a4fd3ec3 | 1569 | |
c7b6f54b RH |
1570 | if (!decode(dc, insn)) { |
1571 | gen_illegal_exception(dc); | |
1572 | } | |
a4fd3ec3 EC |
1573 | dc->base.pc_next += 4; |
1574 | ||
8000ba56 RH |
1575 | /* When exiting the delay slot normally, exit via jmp_pc. |
1576 | * For DISAS_NORETURN, we have raised an exception and already exited. | |
1577 | * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing | |
1578 | * in the manual saying this is illegal, but it surely it should. | |
1579 | * At least or1ksim overrides pcnext and ignores the branch. | |
1580 | */ | |
1581 | if (dc->delayed_branch | |
1582 | && --dc->delayed_branch == 0 | |
1583 | && dc->base.is_jmp == DISAS_NEXT) { | |
1584 | dc->base.is_jmp = DISAS_JUMP; | |
bbe418f2 | 1585 | } |
a4fd3ec3 EC |
1586 | } |
1587 | ||
1588 | static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) | |
1589 | { | |
1590 | DisasContext *dc = container_of(dcbase, DisasContext, base); | |
8000ba56 | 1591 | target_ulong jmp_dest; |
24c32852 | 1592 | |
e0a369cf RH |
1593 | /* If we have already exited the TB, nothing following has effect. */ |
1594 | if (dc->base.is_jmp == DISAS_NORETURN) { | |
1595 | return; | |
1596 | } | |
1597 | ||
8000ba56 | 1598 | /* Adjust the delayed branch state for the next TB. */ |
a01deb36 RH |
1599 | if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) { |
1600 | tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0); | |
1601 | } | |
1602 | ||
8000ba56 RH |
1603 | /* For DISAS_TOO_MANY, jump to the next insn. */ |
1604 | jmp_dest = dc->base.pc_next; | |
1605 | tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4); | |
1606 | ||
e0a369cf | 1607 | switch (dc->base.is_jmp) { |
8000ba56 RH |
1608 | case DISAS_JUMP: |
1609 | jmp_dest = dc->jmp_pc_imm; | |
1610 | if (jmp_dest == -1) { | |
1611 | /* The jump destination is indirect/computed; use jmp_pc. */ | |
1612 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
1613 | tcg_gen_discard_tl(jmp_pc); | |
b21fce53 | 1614 | tcg_gen_lookup_and_goto_ptr(); |
8000ba56 RH |
1615 | break; |
1616 | } | |
1617 | /* The jump destination is direct; use jmp_pc_imm. | |
1618 | However, we will have stored into jmp_pc as well; | |
1619 | we know now that it wasn't needed. */ | |
1620 | tcg_gen_discard_tl(jmp_pc); | |
1621 | /* fallthru */ | |
1622 | ||
e0a369cf | 1623 | case DISAS_TOO_MANY: |
adf1f3de | 1624 | if (translator_use_goto_tb(&dc->base, jmp_dest)) { |
8000ba56 RH |
1625 | tcg_gen_goto_tb(0); |
1626 | tcg_gen_movi_tl(cpu_pc, jmp_dest); | |
1627 | tcg_gen_exit_tb(dc->base.tb, 0); | |
adf1f3de RH |
1628 | break; |
1629 | } | |
1630 | tcg_gen_movi_tl(cpu_pc, jmp_dest); | |
b21fce53 | 1631 | tcg_gen_lookup_and_goto_ptr(); |
e0a369cf | 1632 | break; |
8000ba56 | 1633 | |
e0a369cf | 1634 | case DISAS_EXIT: |
b21fce53 | 1635 | tcg_gen_exit_tb(NULL, 0); |
e0a369cf RH |
1636 | break; |
1637 | default: | |
1638 | g_assert_not_reached(); | |
bbe418f2 | 1639 | } |
a4fd3ec3 | 1640 | } |
bbe418f2 | 1641 | |
8eb806a7 RH |
1642 | static void openrisc_tr_disas_log(const DisasContextBase *dcbase, |
1643 | CPUState *cs, FILE *logfile) | |
a4fd3ec3 EC |
1644 | { |
1645 | DisasContext *s = container_of(dcbase, DisasContext, base); | |
0a7df5da | 1646 | |
8eb806a7 RH |
1647 | fprintf(logfile, "IN: %s\n", lookup_symbol(s->base.pc_first)); |
1648 | target_disas(logfile, cs, s->base.pc_first, s->base.tb->size); | |
a4fd3ec3 | 1649 | } |
bbe418f2 | 1650 | |
a4fd3ec3 EC |
1651 | static const TranslatorOps openrisc_tr_ops = { |
1652 | .init_disas_context = openrisc_tr_init_disas_context, | |
1653 | .tb_start = openrisc_tr_tb_start, | |
1654 | .insn_start = openrisc_tr_insn_start, | |
a4fd3ec3 EC |
1655 | .translate_insn = openrisc_tr_translate_insn, |
1656 | .tb_stop = openrisc_tr_tb_stop, | |
1657 | .disas_log = openrisc_tr_disas_log, | |
1658 | }; | |
1659 | ||
597f9b2d | 1660 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, |
32f0c394 | 1661 | vaddr pc, void *host_pc) |
a4fd3ec3 EC |
1662 | { |
1663 | DisasContext ctx; | |
1664 | ||
306c8721 RH |
1665 | translator_loop(cs, tb, max_insns, pc, host_pc, |
1666 | &openrisc_tr_ops, &ctx.base); | |
e67db06e JL |
1667 | } |
1668 | ||
90c84c56 | 1669 | void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
e67db06e | 1670 | { |
878096ee AF |
1671 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
1672 | CPUOpenRISCState *env = &cpu->env; | |
e67db06e | 1673 | int i; |
878096ee | 1674 | |
90c84c56 | 1675 | qemu_fprintf(f, "PC=%08x\n", env->pc); |
e67db06e | 1676 | for (i = 0; i < 32; ++i) { |
90c84c56 MA |
1677 | qemu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i), |
1678 | (i % 4) == 3 ? '\n' : ' '); | |
e67db06e JL |
1679 | } |
1680 | } |