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e67db06e JL |
1 | /* |
2 | * OpenRISC translation | |
3 | * | |
4 | * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> | |
5 | * Feng Gao <gf91597@gmail.com> | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
20 | ||
ed2decc6 | 21 | #include "qemu/osdep.h" |
e67db06e | 22 | #include "cpu.h" |
022c62cb | 23 | #include "exec/exec-all.h" |
76cad711 | 24 | #include "disas/disas.h" |
e67db06e JL |
25 | #include "tcg-op.h" |
26 | #include "qemu-common.h" | |
1de7afc9 | 27 | #include "qemu/log.h" |
1de7afc9 | 28 | #include "qemu/bitops.h" |
f08b6170 | 29 | #include "exec/cpu_ldst.h" |
bbe418f2 | 30 | |
2ef6175a RH |
31 | #include "exec/helper-proto.h" |
32 | #include "exec/helper-gen.h" | |
e67db06e | 33 | |
a7e30d84 | 34 | #include "trace-tcg.h" |
508127e2 | 35 | #include "exec/log.h" |
a7e30d84 | 36 | |
111ece51 RH |
37 | #define LOG_DIS(str, ...) \ |
38 | qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->pc, ## __VA_ARGS__) | |
e67db06e | 39 | |
bbe418f2 JL |
40 | typedef struct DisasContext { |
41 | TranslationBlock *tb; | |
42 | target_ulong pc, ppc, npc; | |
43 | uint32_t tb_flags, synced_flags, flags; | |
44 | uint32_t is_jmp; | |
45 | uint32_t mem_idx; | |
46 | int singlestep_enabled; | |
47 | uint32_t delayed_branch; | |
48 | } DisasContext; | |
49 | ||
1bcea73e | 50 | static TCGv_env cpu_env; |
bbe418f2 JL |
51 | static TCGv cpu_sr; |
52 | static TCGv cpu_R[32]; | |
53 | static TCGv cpu_pc; | |
54 | static TCGv jmp_pc; /* l.jr/l.jalr temp pc */ | |
55 | static TCGv cpu_npc; | |
56 | static TCGv cpu_ppc; | |
84775c43 | 57 | static TCGv cpu_sr_f; /* bf/bnf, F flag taken */ |
97458071 RH |
58 | static TCGv cpu_sr_cy; /* carry (unsigned overflow) */ |
59 | static TCGv cpu_sr_ov; /* signed overflow */ | |
930c3d00 RH |
60 | static TCGv cpu_lock_addr; |
61 | static TCGv cpu_lock_value; | |
bbe418f2 | 62 | static TCGv_i32 fpcsr; |
6f7332ba | 63 | static TCGv_i64 cpu_mac; /* MACHI:MACLO */ |
bbe418f2 JL |
64 | static TCGv fpmaddhi, fpmaddlo; |
65 | static TCGv_i32 env_flags; | |
022c62cb | 66 | #include "exec/gen-icount.h" |
bbe418f2 | 67 | |
e67db06e JL |
68 | void openrisc_translate_init(void) |
69 | { | |
bbe418f2 JL |
70 | static const char * const regnames[] = { |
71 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
72 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
73 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
74 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
75 | }; | |
76 | int i; | |
77 | ||
78 | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); | |
7c255043 | 79 | tcg_ctx.tcg_env = cpu_env; |
e1ccc054 | 80 | cpu_sr = tcg_global_mem_new(cpu_env, |
bbe418f2 | 81 | offsetof(CPUOpenRISCState, sr), "sr"); |
e1ccc054 | 82 | env_flags = tcg_global_mem_new_i32(cpu_env, |
bbe418f2 JL |
83 | offsetof(CPUOpenRISCState, flags), |
84 | "flags"); | |
e1ccc054 | 85 | cpu_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 86 | offsetof(CPUOpenRISCState, pc), "pc"); |
e1ccc054 | 87 | cpu_npc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 88 | offsetof(CPUOpenRISCState, npc), "npc"); |
e1ccc054 | 89 | cpu_ppc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 90 | offsetof(CPUOpenRISCState, ppc), "ppc"); |
e1ccc054 | 91 | jmp_pc = tcg_global_mem_new(cpu_env, |
bbe418f2 | 92 | offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc"); |
84775c43 RH |
93 | cpu_sr_f = tcg_global_mem_new(cpu_env, |
94 | offsetof(CPUOpenRISCState, sr_f), "sr_f"); | |
97458071 RH |
95 | cpu_sr_cy = tcg_global_mem_new(cpu_env, |
96 | offsetof(CPUOpenRISCState, sr_cy), "sr_cy"); | |
97 | cpu_sr_ov = tcg_global_mem_new(cpu_env, | |
98 | offsetof(CPUOpenRISCState, sr_ov), "sr_ov"); | |
930c3d00 RH |
99 | cpu_lock_addr = tcg_global_mem_new(cpu_env, |
100 | offsetof(CPUOpenRISCState, lock_addr), | |
101 | "lock_addr"); | |
102 | cpu_lock_value = tcg_global_mem_new(cpu_env, | |
103 | offsetof(CPUOpenRISCState, lock_value), | |
104 | "lock_value"); | |
e1ccc054 | 105 | fpcsr = tcg_global_mem_new_i32(cpu_env, |
bbe418f2 JL |
106 | offsetof(CPUOpenRISCState, fpcsr), |
107 | "fpcsr"); | |
6f7332ba RH |
108 | cpu_mac = tcg_global_mem_new_i64(cpu_env, |
109 | offsetof(CPUOpenRISCState, mac), | |
110 | "mac"); | |
e1ccc054 | 111 | fpmaddhi = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
112 | offsetof(CPUOpenRISCState, fpmaddhi), |
113 | "fpmaddhi"); | |
e1ccc054 | 114 | fpmaddlo = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
115 | offsetof(CPUOpenRISCState, fpmaddlo), |
116 | "fpmaddlo"); | |
117 | for (i = 0; i < 32; i++) { | |
e1ccc054 | 118 | cpu_R[i] = tcg_global_mem_new(cpu_env, |
bbe418f2 JL |
119 | offsetof(CPUOpenRISCState, gpr[i]), |
120 | regnames[i]); | |
121 | } | |
bbe418f2 JL |
122 | } |
123 | ||
bbe418f2 JL |
124 | static inline void gen_sync_flags(DisasContext *dc) |
125 | { | |
126 | /* Sync the tb dependent flag between translate and runtime. */ | |
0c53d734 RH |
127 | if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) { |
128 | tcg_gen_movi_tl(env_flags, dc->tb_flags & D_FLAG); | |
bbe418f2 JL |
129 | dc->synced_flags = dc->tb_flags; |
130 | } | |
131 | } | |
132 | ||
133 | static void gen_exception(DisasContext *dc, unsigned int excp) | |
134 | { | |
135 | TCGv_i32 tmp = tcg_const_i32(excp); | |
136 | gen_helper_exception(cpu_env, tmp); | |
137 | tcg_temp_free_i32(tmp); | |
138 | } | |
139 | ||
140 | static void gen_illegal_exception(DisasContext *dc) | |
141 | { | |
142 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
143 | gen_exception(dc, EXCP_ILLEGAL); | |
144 | dc->is_jmp = DISAS_UPDATE; | |
145 | } | |
146 | ||
147 | /* not used yet, open it when we need or64. */ | |
148 | /*#ifdef TARGET_OPENRISC64 | |
149 | static void check_ob64s(DisasContext *dc) | |
150 | { | |
151 | if (!(dc->flags & CPUCFGR_OB64S)) { | |
152 | gen_illegal_exception(dc); | |
153 | } | |
154 | } | |
155 | ||
156 | static void check_of64s(DisasContext *dc) | |
157 | { | |
158 | if (!(dc->flags & CPUCFGR_OF64S)) { | |
159 | gen_illegal_exception(dc); | |
160 | } | |
161 | } | |
162 | ||
163 | static void check_ov64s(DisasContext *dc) | |
164 | { | |
165 | if (!(dc->flags & CPUCFGR_OV64S)) { | |
166 | gen_illegal_exception(dc); | |
167 | } | |
168 | } | |
169 | #endif*/ | |
170 | ||
90aa39a1 SF |
171 | static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) |
172 | { | |
173 | if (unlikely(dc->singlestep_enabled)) { | |
174 | return false; | |
175 | } | |
176 | ||
177 | #ifndef CONFIG_USER_ONLY | |
178 | return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); | |
179 | #else | |
180 | return true; | |
181 | #endif | |
182 | } | |
183 | ||
bbe418f2 JL |
184 | static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) |
185 | { | |
90aa39a1 | 186 | if (use_goto_tb(dc, dest)) { |
bbe418f2 JL |
187 | tcg_gen_movi_tl(cpu_pc, dest); |
188 | tcg_gen_goto_tb(n); | |
90aa39a1 | 189 | tcg_gen_exit_tb((uintptr_t)dc->tb + n); |
bbe418f2 JL |
190 | } else { |
191 | tcg_gen_movi_tl(cpu_pc, dest); | |
192 | if (dc->singlestep_enabled) { | |
193 | gen_exception(dc, EXCP_DEBUG); | |
194 | } | |
195 | tcg_gen_exit_tb(0); | |
196 | } | |
197 | } | |
198 | ||
6da544a6 | 199 | static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0) |
bbe418f2 | 200 | { |
6da544a6 | 201 | target_ulong tmp_pc = dc->pc + n26 * 4; |
bbe418f2 | 202 | |
da1d7759 SM |
203 | switch (op0) { |
204 | case 0x00: /* l.j */ | |
bbe418f2 | 205 | tcg_gen_movi_tl(jmp_pc, tmp_pc); |
da1d7759 SM |
206 | break; |
207 | case 0x01: /* l.jal */ | |
bbe418f2 JL |
208 | tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8)); |
209 | tcg_gen_movi_tl(jmp_pc, tmp_pc); | |
da1d7759 SM |
210 | break; |
211 | case 0x03: /* l.bnf */ | |
212 | case 0x04: /* l.bf */ | |
213 | { | |
784696d1 RH |
214 | TCGv t_next = tcg_const_tl(dc->pc + 8); |
215 | TCGv t_true = tcg_const_tl(tmp_pc); | |
216 | TCGv t_zero = tcg_const_tl(0); | |
217 | ||
218 | tcg_gen_movcond_tl(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE, | |
219 | jmp_pc, cpu_sr_f, t_zero, t_true, t_next); | |
220 | ||
221 | tcg_temp_free(t_next); | |
222 | tcg_temp_free(t_true); | |
223 | tcg_temp_free(t_zero); | |
da1d7759 SM |
224 | } |
225 | break; | |
226 | case 0x11: /* l.jr */ | |
bbe418f2 | 227 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); |
da1d7759 SM |
228 | break; |
229 | case 0x12: /* l.jalr */ | |
bbe418f2 JL |
230 | tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8)); |
231 | tcg_gen_mov_tl(jmp_pc, cpu_R[reg]); | |
da1d7759 SM |
232 | break; |
233 | default: | |
bbe418f2 | 234 | gen_illegal_exception(dc); |
da1d7759 | 235 | break; |
bbe418f2 JL |
236 | } |
237 | ||
bbe418f2 JL |
238 | dc->delayed_branch = 2; |
239 | dc->tb_flags |= D_FLAG; | |
240 | gen_sync_flags(dc); | |
241 | } | |
242 | ||
97458071 | 243 | static void gen_ove_cy(DisasContext *dc) |
9ecaa27e | 244 | { |
0c53d734 | 245 | if (dc->tb_flags & SR_OVE) { |
97458071 | 246 | gen_helper_ove_cy(cpu_env); |
0c53d734 | 247 | } |
9ecaa27e RH |
248 | } |
249 | ||
97458071 | 250 | static void gen_ove_ov(DisasContext *dc) |
9ecaa27e | 251 | { |
0c53d734 | 252 | if (dc->tb_flags & SR_OVE) { |
97458071 | 253 | gen_helper_ove_ov(cpu_env); |
0c53d734 | 254 | } |
9ecaa27e RH |
255 | } |
256 | ||
97458071 | 257 | static void gen_ove_cyov(DisasContext *dc) |
9ecaa27e | 258 | { |
0c53d734 | 259 | if (dc->tb_flags & SR_OVE) { |
97458071 | 260 | gen_helper_ove_cyov(cpu_env); |
0c53d734 | 261 | } |
9ecaa27e RH |
262 | } |
263 | ||
264 | static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
265 | { | |
266 | TCGv t0 = tcg_const_tl(0); | |
267 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 268 | |
97458071 RH |
269 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0); |
270 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 271 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 272 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
273 | tcg_temp_free(t0); |
274 | ||
275 | tcg_gen_mov_tl(dest, res); | |
276 | tcg_temp_free(res); | |
277 | ||
97458071 | 278 | gen_ove_cyov(dc); |
9ecaa27e RH |
279 | } |
280 | ||
281 | static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
282 | { | |
283 | TCGv t0 = tcg_const_tl(0); | |
284 | TCGv res = tcg_temp_new(); | |
9ecaa27e | 285 | |
97458071 RH |
286 | tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0); |
287 | tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0); | |
288 | tcg_gen_xor_tl(cpu_sr_ov, srca, srcb); | |
9ecaa27e | 289 | tcg_gen_xor_tl(t0, res, srcb); |
97458071 | 290 | tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov); |
9ecaa27e RH |
291 | tcg_temp_free(t0); |
292 | ||
293 | tcg_gen_mov_tl(dest, res); | |
294 | tcg_temp_free(res); | |
295 | ||
97458071 | 296 | gen_ove_cyov(dc); |
9ecaa27e RH |
297 | } |
298 | ||
299 | static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
300 | { | |
301 | TCGv res = tcg_temp_new(); | |
9ecaa27e RH |
302 | |
303 | tcg_gen_sub_tl(res, srca, srcb); | |
97458071 RH |
304 | tcg_gen_xor_tl(cpu_sr_cy, srca, srcb); |
305 | tcg_gen_xor_tl(cpu_sr_ov, res, srcb); | |
306 | tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy); | |
307 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb); | |
9ecaa27e RH |
308 | |
309 | tcg_gen_mov_tl(dest, res); | |
310 | tcg_temp_free(res); | |
311 | ||
97458071 | 312 | gen_ove_cyov(dc); |
9ecaa27e RH |
313 | } |
314 | ||
315 | static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
316 | { | |
9ecaa27e RH |
317 | TCGv t0 = tcg_temp_new(); |
318 | ||
97458071 | 319 | tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); |
9ecaa27e | 320 | tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); |
97458071 | 321 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); |
9ecaa27e RH |
322 | tcg_temp_free(t0); |
323 | ||
97458071 RH |
324 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
325 | gen_ove_ov(dc); | |
9ecaa27e RH |
326 | } |
327 | ||
328 | static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
329 | { | |
97458071 RH |
330 | tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb); |
331 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0); | |
9ecaa27e | 332 | |
97458071 | 333 | gen_ove_cy(dc); |
9ecaa27e RH |
334 | } |
335 | ||
336 | static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
337 | { | |
9ecaa27e RH |
338 | TCGv t0 = tcg_temp_new(); |
339 | ||
97458071 | 340 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0); |
9ecaa27e RH |
341 | /* The result of divide-by-zero is undefined. |
342 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 343 | tcg_gen_or_tl(t0, srcb, cpu_sr_ov); |
9ecaa27e RH |
344 | tcg_gen_div_tl(dest, srca, t0); |
345 | tcg_temp_free(t0); | |
346 | ||
97458071 RH |
347 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); |
348 | gen_ove_ov(dc); | |
9ecaa27e RH |
349 | } |
350 | ||
351 | static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) | |
352 | { | |
9ecaa27e RH |
353 | TCGv t0 = tcg_temp_new(); |
354 | ||
97458071 | 355 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0); |
9ecaa27e RH |
356 | /* The result of divide-by-zero is undefined. |
357 | Supress the host-side exception by dividing by 1. */ | |
97458071 | 358 | tcg_gen_or_tl(t0, srcb, cpu_sr_cy); |
9ecaa27e RH |
359 | tcg_gen_divu_tl(dest, srca, t0); |
360 | tcg_temp_free(t0); | |
361 | ||
97458071 | 362 | gen_ove_cy(dc); |
9ecaa27e | 363 | } |
da1d7759 | 364 | |
cc5de49e RH |
365 | static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) |
366 | { | |
367 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
368 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
369 | ||
370 | tcg_gen_ext_tl_i64(t1, srca); | |
371 | tcg_gen_ext_tl_i64(t2, srcb); | |
372 | if (TARGET_LONG_BITS == 32) { | |
373 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
374 | tcg_gen_movi_tl(cpu_sr_ov, 0); | |
375 | } else { | |
376 | TCGv_i64 high = tcg_temp_new_i64(); | |
377 | ||
378 | tcg_gen_muls2_i64(cpu_mac, high, t1, t2); | |
379 | tcg_gen_sari_i64(t1, cpu_mac, 63); | |
380 | tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high); | |
381 | tcg_temp_free_i64(high); | |
382 | tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); | |
383 | tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); | |
384 | ||
385 | gen_ove_ov(dc); | |
386 | } | |
387 | tcg_temp_free_i64(t1); | |
388 | tcg_temp_free_i64(t2); | |
389 | } | |
390 | ||
391 | static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb) | |
392 | { | |
393 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
394 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
395 | ||
396 | tcg_gen_extu_tl_i64(t1, srca); | |
397 | tcg_gen_extu_tl_i64(t2, srcb); | |
398 | if (TARGET_LONG_BITS == 32) { | |
399 | tcg_gen_mul_i64(cpu_mac, t1, t2); | |
400 | tcg_gen_movi_tl(cpu_sr_cy, 0); | |
401 | } else { | |
402 | TCGv_i64 high = tcg_temp_new_i64(); | |
403 | ||
404 | tcg_gen_mulu2_i64(cpu_mac, high, t1, t2); | |
405 | tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0); | |
406 | tcg_gen_trunc_i64_tl(cpu_sr_cy, high); | |
407 | tcg_temp_free_i64(high); | |
408 | ||
409 | gen_ove_cy(dc); | |
410 | } | |
411 | tcg_temp_free_i64(t1); | |
412 | tcg_temp_free_i64(t2); | |
413 | } | |
414 | ||
6f7332ba RH |
415 | static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb) |
416 | { | |
417 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
418 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
419 | ||
420 | tcg_gen_ext_tl_i64(t1, srca); | |
421 | tcg_gen_ext_tl_i64(t2, srcb); | |
422 | tcg_gen_mul_i64(t1, t1, t2); | |
423 | ||
424 | /* Note that overflow is only computed during addition stage. */ | |
425 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
426 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
427 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
428 | tcg_gen_andc_i64(t1, t1, t2); | |
429 | tcg_temp_free_i64(t2); | |
430 | ||
431 | #if TARGET_LONG_BITS == 32 | |
432 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
433 | #else | |
434 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
435 | #endif | |
436 | tcg_temp_free_i64(t1); | |
437 | ||
438 | gen_ove_ov(dc); | |
439 | } | |
440 | ||
cc5de49e RH |
441 | static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb) |
442 | { | |
443 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
444 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
445 | ||
446 | tcg_gen_extu_tl_i64(t1, srca); | |
447 | tcg_gen_extu_tl_i64(t2, srcb); | |
448 | tcg_gen_mul_i64(t1, t1, t2); | |
449 | tcg_temp_free_i64(t2); | |
450 | ||
451 | /* Note that overflow is only computed during addition stage. */ | |
452 | tcg_gen_add_i64(cpu_mac, cpu_mac, t1); | |
453 | tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1); | |
454 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t1); | |
455 | tcg_temp_free_i64(t1); | |
456 | ||
457 | gen_ove_cy(dc); | |
458 | } | |
459 | ||
6f7332ba RH |
460 | static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb) |
461 | { | |
462 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
463 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
464 | ||
465 | tcg_gen_ext_tl_i64(t1, srca); | |
466 | tcg_gen_ext_tl_i64(t2, srcb); | |
467 | tcg_gen_mul_i64(t1, t1, t2); | |
468 | ||
469 | /* Note that overflow is only computed during subtraction stage. */ | |
470 | tcg_gen_xor_i64(t2, cpu_mac, t1); | |
471 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
472 | tcg_gen_xor_i64(t1, t1, cpu_mac); | |
473 | tcg_gen_and_i64(t1, t1, t2); | |
474 | tcg_temp_free_i64(t2); | |
475 | ||
476 | #if TARGET_LONG_BITS == 32 | |
477 | tcg_gen_extrh_i64_i32(cpu_sr_ov, t1); | |
478 | #else | |
479 | tcg_gen_mov_i64(cpu_sr_ov, t1); | |
480 | #endif | |
481 | tcg_temp_free_i64(t1); | |
482 | ||
483 | gen_ove_ov(dc); | |
484 | } | |
485 | ||
cc5de49e RH |
486 | static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb) |
487 | { | |
488 | TCGv_i64 t1 = tcg_temp_new_i64(); | |
489 | TCGv_i64 t2 = tcg_temp_new_i64(); | |
490 | ||
491 | tcg_gen_extu_tl_i64(t1, srca); | |
492 | tcg_gen_extu_tl_i64(t2, srcb); | |
493 | tcg_gen_mul_i64(t1, t1, t2); | |
494 | ||
495 | /* Note that overflow is only computed during subtraction stage. */ | |
496 | tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1); | |
497 | tcg_gen_sub_i64(cpu_mac, cpu_mac, t1); | |
498 | tcg_gen_trunc_i64_tl(cpu_sr_cy, t2); | |
499 | tcg_temp_free_i64(t2); | |
500 | tcg_temp_free_i64(t1); | |
501 | ||
502 | gen_ove_cy(dc); | |
503 | } | |
504 | ||
930c3d00 RH |
505 | static void gen_lwa(DisasContext *dc, TCGv rd, TCGv ra, int32_t ofs) |
506 | { | |
507 | TCGv ea = tcg_temp_new(); | |
508 | ||
509 | tcg_gen_addi_tl(ea, ra, ofs); | |
510 | tcg_gen_qemu_ld_tl(rd, ea, dc->mem_idx, MO_TEUL); | |
511 | tcg_gen_mov_tl(cpu_lock_addr, ea); | |
512 | tcg_gen_mov_tl(cpu_lock_value, rd); | |
513 | tcg_temp_free(ea); | |
514 | } | |
515 | ||
516 | static void gen_swa(DisasContext *dc, TCGv rb, TCGv ra, int32_t ofs) | |
517 | { | |
518 | TCGv ea, val; | |
519 | TCGLabel *lab_fail, *lab_done; | |
520 | ||
521 | ea = tcg_temp_new(); | |
522 | tcg_gen_addi_tl(ea, ra, ofs); | |
523 | ||
524 | lab_fail = gen_new_label(); | |
525 | lab_done = gen_new_label(); | |
526 | tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); | |
527 | tcg_temp_free(ea); | |
528 | ||
529 | val = tcg_temp_new(); | |
530 | tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, | |
531 | rb, dc->mem_idx, MO_TEUL); | |
84775c43 | 532 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); |
930c3d00 RH |
533 | tcg_temp_free(val); |
534 | ||
535 | tcg_gen_br(lab_done); | |
536 | ||
537 | gen_set_label(lab_fail); | |
84775c43 | 538 | tcg_gen_movi_tl(cpu_sr_f, 0); |
930c3d00 RH |
539 | |
540 | gen_set_label(lab_done); | |
541 | tcg_gen_movi_tl(cpu_lock_addr, -1); | |
930c3d00 RH |
542 | } |
543 | ||
bbe418f2 JL |
544 | static void dec_calc(DisasContext *dc, uint32_t insn) |
545 | { | |
546 | uint32_t op0, op1, op2; | |
547 | uint32_t ra, rb, rd; | |
548 | op0 = extract32(insn, 0, 4); | |
549 | op1 = extract32(insn, 8, 2); | |
550 | op2 = extract32(insn, 6, 2); | |
551 | ra = extract32(insn, 16, 5); | |
552 | rb = extract32(insn, 11, 5); | |
553 | rd = extract32(insn, 21, 5); | |
554 | ||
cf2ae442 RH |
555 | switch (op1) { |
556 | case 0: | |
557 | switch (op0) { | |
558 | case 0x0: /* l.add */ | |
bbe418f2 | 559 | LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 560 | gen_add(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 561 | return; |
bbe418f2 | 562 | |
cf2ae442 | 563 | case 0x1: /* l.addc */ |
bbe418f2 | 564 | LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 565 | gen_addc(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 566 | return; |
bbe418f2 | 567 | |
cf2ae442 | 568 | case 0x2: /* l.sub */ |
bbe418f2 | 569 | LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb); |
9ecaa27e | 570 | gen_sub(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); |
cf2ae442 | 571 | return; |
bbe418f2 | 572 | |
cf2ae442 | 573 | case 0x3: /* l.and */ |
bbe418f2 JL |
574 | LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb); |
575 | tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 576 | return; |
bbe418f2 | 577 | |
cf2ae442 | 578 | case 0x4: /* l.or */ |
bbe418f2 JL |
579 | LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb); |
580 | tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 581 | return; |
bbe418f2 | 582 | |
cf2ae442 | 583 | case 0x5: /* l.xor */ |
bbe418f2 JL |
584 | LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb); |
585 | tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
cf2ae442 | 586 | return; |
bbe418f2 | 587 | |
cf2ae442 RH |
588 | case 0x8: |
589 | switch (op2) { | |
590 | case 0: /* l.sll */ | |
591 | LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb); | |
592 | tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
593 | return; | |
594 | case 1: /* l.srl */ | |
595 | LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb); | |
596 | tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
597 | return; | |
598 | case 2: /* l.sra */ | |
599 | LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb); | |
600 | tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
601 | return; | |
602 | case 3: /* l.ror */ | |
603 | LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb); | |
604 | tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
605 | return; | |
606 | } | |
bbe418f2 | 607 | break; |
bbe418f2 | 608 | |
cf2ae442 RH |
609 | case 0xc: |
610 | switch (op2) { | |
611 | case 0: /* l.exths */ | |
612 | LOG_DIS("l.exths r%d, r%d\n", rd, ra); | |
613 | tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]); | |
614 | return; | |
615 | case 1: /* l.extbs */ | |
616 | LOG_DIS("l.extbs r%d, r%d\n", rd, ra); | |
617 | tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]); | |
618 | return; | |
619 | case 2: /* l.exthz */ | |
620 | LOG_DIS("l.exthz r%d, r%d\n", rd, ra); | |
621 | tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]); | |
622 | return; | |
623 | case 3: /* l.extbz */ | |
624 | LOG_DIS("l.extbz r%d, r%d\n", rd, ra); | |
625 | tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]); | |
626 | return; | |
627 | } | |
bbe418f2 JL |
628 | break; |
629 | ||
cf2ae442 RH |
630 | case 0xd: |
631 | switch (op2) { | |
632 | case 0: /* l.extws */ | |
633 | LOG_DIS("l.extws r%d, r%d\n", rd, ra); | |
634 | tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]); | |
635 | return; | |
636 | case 1: /* l.extwz */ | |
637 | LOG_DIS("l.extwz r%d, r%d\n", rd, ra); | |
638 | tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]); | |
639 | return; | |
640 | } | |
bbe418f2 | 641 | break; |
bbe418f2 | 642 | |
cf2ae442 | 643 | case 0xe: /* l.cmov */ |
bbe418f2 JL |
644 | LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb); |
645 | { | |
784696d1 RH |
646 | TCGv zero = tcg_const_tl(0); |
647 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[rd], cpu_sr_f, zero, | |
648 | cpu_R[ra], cpu_R[rb]); | |
649 | tcg_temp_free(zero); | |
bbe418f2 | 650 | } |
cf2ae442 | 651 | return; |
bbe418f2 | 652 | |
cf2ae442 | 653 | case 0xf: /* l.ff1 */ |
bbe418f2 | 654 | LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb); |
555baef8 RH |
655 | tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1); |
656 | tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1); | |
cf2ae442 RH |
657 | return; |
658 | } | |
659 | break; | |
660 | ||
661 | case 1: | |
662 | switch (op0) { | |
663 | case 0xf: /* l.fl1 */ | |
bbe418f2 | 664 | LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb); |
555baef8 RH |
665 | tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS); |
666 | tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]); | |
cf2ae442 | 667 | return; |
bbe418f2 JL |
668 | } |
669 | break; | |
670 | ||
cf2ae442 | 671 | case 2: |
bbe418f2 JL |
672 | break; |
673 | ||
cf2ae442 RH |
674 | case 3: |
675 | switch (op0) { | |
676 | case 0x6: /* l.mul */ | |
677 | LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb); | |
678 | gen_mul(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
679 | return; | |
bbe418f2 | 680 | |
cc5de49e RH |
681 | case 0x7: /* l.muld */ |
682 | LOG_DIS("l.muld r%d, r%d\n", ra, rb); | |
683 | gen_muld(dc, cpu_R[ra], cpu_R[rb]); | |
684 | break; | |
685 | ||
cf2ae442 RH |
686 | case 0x9: /* l.div */ |
687 | LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb); | |
688 | gen_div(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
689 | return; | |
bbe418f2 | 690 | |
cf2ae442 RH |
691 | case 0xa: /* l.divu */ |
692 | LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb); | |
693 | gen_divu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
694 | return; | |
bbe418f2 | 695 | |
cf2ae442 RH |
696 | case 0xb: /* l.mulu */ |
697 | LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb); | |
698 | gen_mulu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]); | |
699 | return; | |
cc5de49e RH |
700 | |
701 | case 0xc: /* l.muldu */ | |
702 | LOG_DIS("l.muldu r%d, r%d\n", ra, rb); | |
703 | gen_muldu(dc, cpu_R[ra], cpu_R[rb]); | |
704 | return; | |
bbe418f2 JL |
705 | } |
706 | break; | |
bbe418f2 | 707 | } |
cf2ae442 | 708 | gen_illegal_exception(dc); |
bbe418f2 JL |
709 | } |
710 | ||
711 | static void dec_misc(DisasContext *dc, uint32_t insn) | |
712 | { | |
713 | uint32_t op0, op1; | |
714 | uint32_t ra, rb, rd; | |
6da544a6 RH |
715 | uint32_t L6, K5, K16, K5_11; |
716 | int32_t I16, I5_11, N26; | |
5631e69c | 717 | TCGMemOp mop; |
9ecaa27e | 718 | TCGv t0; |
5631e69c | 719 | |
bbe418f2 JL |
720 | op0 = extract32(insn, 26, 6); |
721 | op1 = extract32(insn, 24, 2); | |
722 | ra = extract32(insn, 16, 5); | |
723 | rb = extract32(insn, 11, 5); | |
724 | rd = extract32(insn, 21, 5); | |
bbe418f2 JL |
725 | L6 = extract32(insn, 5, 6); |
726 | K5 = extract32(insn, 0, 5); | |
6da544a6 RH |
727 | K16 = extract32(insn, 0, 16); |
728 | I16 = (int16_t)K16; | |
729 | N26 = sextract32(insn, 0, 26); | |
730 | K5_11 = (extract32(insn, 21, 5) << 11) | extract32(insn, 0, 11); | |
731 | I5_11 = (int16_t)K5_11; | |
bbe418f2 JL |
732 | |
733 | switch (op0) { | |
734 | case 0x00: /* l.j */ | |
735 | LOG_DIS("l.j %d\n", N26); | |
736 | gen_jump(dc, N26, 0, op0); | |
737 | break; | |
738 | ||
739 | case 0x01: /* l.jal */ | |
740 | LOG_DIS("l.jal %d\n", N26); | |
741 | gen_jump(dc, N26, 0, op0); | |
742 | break; | |
743 | ||
744 | case 0x03: /* l.bnf */ | |
745 | LOG_DIS("l.bnf %d\n", N26); | |
746 | gen_jump(dc, N26, 0, op0); | |
747 | break; | |
748 | ||
749 | case 0x04: /* l.bf */ | |
750 | LOG_DIS("l.bf %d\n", N26); | |
751 | gen_jump(dc, N26, 0, op0); | |
752 | break; | |
753 | ||
754 | case 0x05: | |
755 | switch (op1) { | |
756 | case 0x01: /* l.nop */ | |
757 | LOG_DIS("l.nop %d\n", I16); | |
758 | break; | |
759 | ||
760 | default: | |
761 | gen_illegal_exception(dc); | |
762 | break; | |
763 | } | |
764 | break; | |
765 | ||
766 | case 0x11: /* l.jr */ | |
767 | LOG_DIS("l.jr r%d\n", rb); | |
768 | gen_jump(dc, 0, rb, op0); | |
769 | break; | |
770 | ||
771 | case 0x12: /* l.jalr */ | |
772 | LOG_DIS("l.jalr r%d\n", rb); | |
773 | gen_jump(dc, 0, rb, op0); | |
774 | break; | |
775 | ||
776 | case 0x13: /* l.maci */ | |
6da544a6 | 777 | LOG_DIS("l.maci r%d, %d\n", ra, I16); |
6f7332ba RH |
778 | t0 = tcg_const_tl(I16); |
779 | gen_mac(dc, cpu_R[ra], t0); | |
780 | tcg_temp_free(t0); | |
bbe418f2 JL |
781 | break; |
782 | ||
783 | case 0x09: /* l.rfe */ | |
784 | LOG_DIS("l.rfe\n"); | |
785 | { | |
786 | #if defined(CONFIG_USER_ONLY) | |
787 | return; | |
788 | #else | |
789 | if (dc->mem_idx == MMU_USER_IDX) { | |
790 | gen_illegal_exception(dc); | |
791 | return; | |
792 | } | |
793 | gen_helper_rfe(cpu_env); | |
794 | dc->is_jmp = DISAS_UPDATE; | |
795 | #endif | |
796 | } | |
797 | break; | |
798 | ||
930c3d00 RH |
799 | case 0x1b: /* l.lwa */ |
800 | LOG_DIS("l.lwa r%d, r%d, %d\n", rd, ra, I16); | |
801 | gen_lwa(dc, cpu_R[rd], cpu_R[ra], I16); | |
802 | break; | |
803 | ||
bbe418f2 JL |
804 | case 0x1c: /* l.cust1 */ |
805 | LOG_DIS("l.cust1\n"); | |
806 | break; | |
807 | ||
808 | case 0x1d: /* l.cust2 */ | |
809 | LOG_DIS("l.cust2\n"); | |
810 | break; | |
811 | ||
812 | case 0x1e: /* l.cust3 */ | |
813 | LOG_DIS("l.cust3\n"); | |
814 | break; | |
815 | ||
816 | case 0x1f: /* l.cust4 */ | |
817 | LOG_DIS("l.cust4\n"); | |
818 | break; | |
819 | ||
820 | case 0x3c: /* l.cust5 */ | |
821 | LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5); | |
822 | break; | |
823 | ||
824 | case 0x3d: /* l.cust6 */ | |
825 | LOG_DIS("l.cust6\n"); | |
826 | break; | |
827 | ||
828 | case 0x3e: /* l.cust7 */ | |
829 | LOG_DIS("l.cust7\n"); | |
830 | break; | |
831 | ||
832 | case 0x3f: /* l.cust8 */ | |
833 | LOG_DIS("l.cust8\n"); | |
834 | break; | |
835 | ||
836 | /* not used yet, open it when we need or64. */ | |
837 | /*#ifdef TARGET_OPENRISC64 | |
838 | case 0x20: l.ld | |
839 | LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
840 | check_ob64s(dc); |
841 | mop = MO_TEQ; | |
842 | goto do_load; | |
bbe418f2 JL |
843 | #endif*/ |
844 | ||
845 | case 0x21: /* l.lwz */ | |
846 | LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
847 | mop = MO_TEUL; |
848 | goto do_load; | |
bbe418f2 JL |
849 | |
850 | case 0x22: /* l.lws */ | |
851 | LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
852 | mop = MO_TESL; |
853 | goto do_load; | |
bbe418f2 JL |
854 | |
855 | case 0x23: /* l.lbz */ | |
856 | LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
857 | mop = MO_UB; |
858 | goto do_load; | |
bbe418f2 JL |
859 | |
860 | case 0x24: /* l.lbs */ | |
861 | LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
862 | mop = MO_SB; |
863 | goto do_load; | |
bbe418f2 JL |
864 | |
865 | case 0x25: /* l.lhz */ | |
866 | LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
867 | mop = MO_TEUW; |
868 | goto do_load; | |
bbe418f2 JL |
869 | |
870 | case 0x26: /* l.lhs */ | |
871 | LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16); | |
5631e69c RH |
872 | mop = MO_TESW; |
873 | goto do_load; | |
874 | ||
875 | do_load: | |
bbe418f2 JL |
876 | { |
877 | TCGv t0 = tcg_temp_new(); | |
6da544a6 | 878 | tcg_gen_addi_tl(t0, cpu_R[ra], I16); |
5631e69c | 879 | tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop); |
bbe418f2 JL |
880 | tcg_temp_free(t0); |
881 | } | |
882 | break; | |
883 | ||
884 | case 0x27: /* l.addi */ | |
885 | LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16); | |
9ecaa27e RH |
886 | t0 = tcg_const_tl(I16); |
887 | gen_add(dc, cpu_R[rd], cpu_R[ra], t0); | |
888 | tcg_temp_free(t0); | |
bbe418f2 JL |
889 | break; |
890 | ||
891 | case 0x28: /* l.addic */ | |
892 | LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16); | |
9ecaa27e RH |
893 | t0 = tcg_const_tl(I16); |
894 | gen_addc(dc, cpu_R[rd], cpu_R[ra], t0); | |
895 | tcg_temp_free(t0); | |
bbe418f2 JL |
896 | break; |
897 | ||
898 | case 0x29: /* l.andi */ | |
6da544a6 RH |
899 | LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, K16); |
900 | tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], K16); | |
bbe418f2 JL |
901 | break; |
902 | ||
903 | case 0x2a: /* l.ori */ | |
6da544a6 RH |
904 | LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, K16); |
905 | tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], K16); | |
bbe418f2 JL |
906 | break; |
907 | ||
908 | case 0x2b: /* l.xori */ | |
909 | LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16); | |
6da544a6 | 910 | tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], I16); |
bbe418f2 JL |
911 | break; |
912 | ||
913 | case 0x2c: /* l.muli */ | |
914 | LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16); | |
9ecaa27e RH |
915 | t0 = tcg_const_tl(I16); |
916 | gen_mul(dc, cpu_R[rd], cpu_R[ra], t0); | |
917 | tcg_temp_free(t0); | |
bbe418f2 JL |
918 | break; |
919 | ||
920 | case 0x2d: /* l.mfspr */ | |
6da544a6 | 921 | LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, K16); |
4dd044c6 JL |
922 | { |
923 | #if defined(CONFIG_USER_ONLY) | |
924 | return; | |
925 | #else | |
6da544a6 | 926 | TCGv_i32 ti = tcg_const_i32(K16); |
4dd044c6 JL |
927 | if (dc->mem_idx == MMU_USER_IDX) { |
928 | gen_illegal_exception(dc); | |
929 | return; | |
930 | } | |
931 | gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti); | |
932 | tcg_temp_free_i32(ti); | |
933 | #endif | |
934 | } | |
bbe418f2 JL |
935 | break; |
936 | ||
937 | case 0x30: /* l.mtspr */ | |
6da544a6 | 938 | LOG_DIS("l.mtspr r%d, r%d, %d\n", ra, rb, K5_11); |
4dd044c6 JL |
939 | { |
940 | #if defined(CONFIG_USER_ONLY) | |
941 | return; | |
942 | #else | |
6da544a6 | 943 | TCGv_i32 im = tcg_const_i32(K5_11); |
4dd044c6 JL |
944 | if (dc->mem_idx == MMU_USER_IDX) { |
945 | gen_illegal_exception(dc); | |
946 | return; | |
947 | } | |
948 | gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im); | |
949 | tcg_temp_free_i32(im); | |
950 | #endif | |
951 | } | |
bbe418f2 JL |
952 | break; |
953 | ||
930c3d00 | 954 | case 0x33: /* l.swa */ |
6da544a6 RH |
955 | LOG_DIS("l.swa r%d, r%d, %d\n", ra, rb, I5_11); |
956 | gen_swa(dc, cpu_R[rb], cpu_R[ra], I5_11); | |
930c3d00 RH |
957 | break; |
958 | ||
bbe418f2 JL |
959 | /* not used yet, open it when we need or64. */ |
960 | /*#ifdef TARGET_OPENRISC64 | |
961 | case 0x34: l.sd | |
6da544a6 | 962 | LOG_DIS("l.sd r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
963 | check_ob64s(dc); |
964 | mop = MO_TEQ; | |
965 | goto do_store; | |
bbe418f2 JL |
966 | #endif*/ |
967 | ||
968 | case 0x35: /* l.sw */ | |
6da544a6 | 969 | LOG_DIS("l.sw r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
970 | mop = MO_TEUL; |
971 | goto do_store; | |
bbe418f2 JL |
972 | |
973 | case 0x36: /* l.sb */ | |
6da544a6 | 974 | LOG_DIS("l.sb r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
975 | mop = MO_UB; |
976 | goto do_store; | |
bbe418f2 JL |
977 | |
978 | case 0x37: /* l.sh */ | |
6da544a6 | 979 | LOG_DIS("l.sh r%d, r%d, %d\n", ra, rb, I5_11); |
5631e69c RH |
980 | mop = MO_TEUW; |
981 | goto do_store; | |
982 | ||
983 | do_store: | |
bbe418f2 JL |
984 | { |
985 | TCGv t0 = tcg_temp_new(); | |
6da544a6 | 986 | tcg_gen_addi_tl(t0, cpu_R[ra], I5_11); |
5631e69c | 987 | tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop); |
bbe418f2 JL |
988 | tcg_temp_free(t0); |
989 | } | |
990 | break; | |
991 | ||
992 | default: | |
993 | gen_illegal_exception(dc); | |
994 | break; | |
995 | } | |
996 | } | |
997 | ||
998 | static void dec_mac(DisasContext *dc, uint32_t insn) | |
999 | { | |
1000 | uint32_t op0; | |
1001 | uint32_t ra, rb; | |
1002 | op0 = extract32(insn, 0, 4); | |
1003 | ra = extract32(insn, 16, 5); | |
1004 | rb = extract32(insn, 11, 5); | |
1005 | ||
1006 | switch (op0) { | |
1007 | case 0x0001: /* l.mac */ | |
1008 | LOG_DIS("l.mac r%d, r%d\n", ra, rb); | |
6f7332ba | 1009 | gen_mac(dc, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1010 | break; |
1011 | ||
1012 | case 0x0002: /* l.msb */ | |
1013 | LOG_DIS("l.msb r%d, r%d\n", ra, rb); | |
6f7332ba | 1014 | gen_msb(dc, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1015 | break; |
1016 | ||
cc5de49e RH |
1017 | case 0x0003: /* l.macu */ |
1018 | LOG_DIS("l.macu r%d, r%d\n", ra, rb); | |
1019 | gen_macu(dc, cpu_R[ra], cpu_R[rb]); | |
1020 | break; | |
1021 | ||
1022 | case 0x0004: /* l.msbu */ | |
1023 | LOG_DIS("l.msbu r%d, r%d\n", ra, rb); | |
1024 | gen_msbu(dc, cpu_R[ra], cpu_R[rb]); | |
1025 | break; | |
1026 | ||
bbe418f2 JL |
1027 | default: |
1028 | gen_illegal_exception(dc); | |
1029 | break; | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | static void dec_logic(DisasContext *dc, uint32_t insn) | |
1034 | { | |
1035 | uint32_t op0; | |
6da544a6 | 1036 | uint32_t rd, ra, L6, S6; |
bbe418f2 JL |
1037 | op0 = extract32(insn, 6, 2); |
1038 | rd = extract32(insn, 21, 5); | |
1039 | ra = extract32(insn, 16, 5); | |
1040 | L6 = extract32(insn, 0, 6); | |
6da544a6 | 1041 | S6 = L6 & (TARGET_LONG_BITS - 1); |
bbe418f2 JL |
1042 | |
1043 | switch (op0) { | |
1044 | case 0x00: /* l.slli */ | |
1045 | LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 1046 | tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
1047 | break; |
1048 | ||
1049 | case 0x01: /* l.srli */ | |
1050 | LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 1051 | tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
1052 | break; |
1053 | ||
1054 | case 0x02: /* l.srai */ | |
1055 | LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 RH |
1056 | tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], S6); |
1057 | break; | |
bbe418f2 JL |
1058 | |
1059 | case 0x03: /* l.rori */ | |
1060 | LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6); | |
6da544a6 | 1061 | tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], S6); |
bbe418f2 JL |
1062 | break; |
1063 | ||
1064 | default: | |
1065 | gen_illegal_exception(dc); | |
1066 | break; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | static void dec_M(DisasContext *dc, uint32_t insn) | |
1071 | { | |
1072 | uint32_t op0; | |
1073 | uint32_t rd; | |
1074 | uint32_t K16; | |
1075 | op0 = extract32(insn, 16, 1); | |
1076 | rd = extract32(insn, 21, 5); | |
1077 | K16 = extract32(insn, 0, 16); | |
1078 | ||
1079 | switch (op0) { | |
1080 | case 0x0: /* l.movhi */ | |
1081 | LOG_DIS("l.movhi r%d, %d\n", rd, K16); | |
1082 | tcg_gen_movi_tl(cpu_R[rd], (K16 << 16)); | |
1083 | break; | |
1084 | ||
1085 | case 0x1: /* l.macrc */ | |
1086 | LOG_DIS("l.macrc r%d\n", rd); | |
6f7332ba RH |
1087 | tcg_gen_trunc_i64_tl(cpu_R[rd], cpu_mac); |
1088 | tcg_gen_movi_i64(cpu_mac, 0); | |
bbe418f2 JL |
1089 | break; |
1090 | ||
1091 | default: | |
1092 | gen_illegal_exception(dc); | |
1093 | break; | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | static void dec_comp(DisasContext *dc, uint32_t insn) | |
1098 | { | |
1099 | uint32_t op0; | |
1100 | uint32_t ra, rb; | |
1101 | ||
1102 | op0 = extract32(insn, 21, 5); | |
1103 | ra = extract32(insn, 16, 5); | |
1104 | rb = extract32(insn, 11, 5); | |
1105 | ||
bbe418f2 JL |
1106 | /* unsigned integers */ |
1107 | tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]); | |
1108 | tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]); | |
1109 | ||
1110 | switch (op0) { | |
1111 | case 0x0: /* l.sfeq */ | |
1112 | LOG_DIS("l.sfeq r%d, r%d\n", ra, rb); | |
84775c43 | 1113 | tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1114 | break; |
1115 | ||
1116 | case 0x1: /* l.sfne */ | |
1117 | LOG_DIS("l.sfne r%d, r%d\n", ra, rb); | |
84775c43 | 1118 | tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1119 | break; |
1120 | ||
1121 | case 0x2: /* l.sfgtu */ | |
1122 | LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb); | |
84775c43 | 1123 | tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1124 | break; |
1125 | ||
1126 | case 0x3: /* l.sfgeu */ | |
1127 | LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb); | |
84775c43 | 1128 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1129 | break; |
1130 | ||
1131 | case 0x4: /* l.sfltu */ | |
1132 | LOG_DIS("l.sfltu r%d, r%d\n", ra, rb); | |
84775c43 | 1133 | tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1134 | break; |
1135 | ||
1136 | case 0x5: /* l.sfleu */ | |
1137 | LOG_DIS("l.sfleu r%d, r%d\n", ra, rb); | |
84775c43 | 1138 | tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1139 | break; |
1140 | ||
1141 | case 0xa: /* l.sfgts */ | |
1142 | LOG_DIS("l.sfgts r%d, r%d\n", ra, rb); | |
84775c43 | 1143 | tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1144 | break; |
1145 | ||
1146 | case 0xb: /* l.sfges */ | |
1147 | LOG_DIS("l.sfges r%d, r%d\n", ra, rb); | |
84775c43 | 1148 | tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1149 | break; |
1150 | ||
1151 | case 0xc: /* l.sflts */ | |
1152 | LOG_DIS("l.sflts r%d, r%d\n", ra, rb); | |
84775c43 | 1153 | tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1154 | break; |
1155 | ||
1156 | case 0xd: /* l.sfles */ | |
1157 | LOG_DIS("l.sfles r%d, r%d\n", ra, rb); | |
84775c43 | 1158 | tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1159 | break; |
1160 | ||
1161 | default: | |
1162 | gen_illegal_exception(dc); | |
1163 | break; | |
1164 | } | |
bbe418f2 JL |
1165 | } |
1166 | ||
1167 | static void dec_compi(DisasContext *dc, uint32_t insn) | |
1168 | { | |
6da544a6 RH |
1169 | uint32_t op0, ra; |
1170 | int32_t I16; | |
bbe418f2 JL |
1171 | |
1172 | op0 = extract32(insn, 21, 5); | |
1173 | ra = extract32(insn, 16, 5); | |
6da544a6 | 1174 | I16 = sextract32(insn, 0, 16); |
bbe418f2 | 1175 | |
bbe418f2 JL |
1176 | switch (op0) { |
1177 | case 0x0: /* l.sfeqi */ | |
1178 | LOG_DIS("l.sfeqi r%d, %d\n", ra, I16); | |
84775c43 | 1179 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1180 | break; |
1181 | ||
1182 | case 0x1: /* l.sfnei */ | |
1183 | LOG_DIS("l.sfnei r%d, %d\n", ra, I16); | |
84775c43 | 1184 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1185 | break; |
1186 | ||
1187 | case 0x2: /* l.sfgtui */ | |
1188 | LOG_DIS("l.sfgtui r%d, %d\n", ra, I16); | |
84775c43 | 1189 | tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1190 | break; |
1191 | ||
1192 | case 0x3: /* l.sfgeui */ | |
1193 | LOG_DIS("l.sfgeui r%d, %d\n", ra, I16); | |
84775c43 | 1194 | tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1195 | break; |
1196 | ||
1197 | case 0x4: /* l.sfltui */ | |
1198 | LOG_DIS("l.sfltui r%d, %d\n", ra, I16); | |
84775c43 | 1199 | tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1200 | break; |
1201 | ||
1202 | case 0x5: /* l.sfleui */ | |
1203 | LOG_DIS("l.sfleui r%d, %d\n", ra, I16); | |
84775c43 | 1204 | tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1205 | break; |
1206 | ||
1207 | case 0xa: /* l.sfgtsi */ | |
1208 | LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16); | |
84775c43 | 1209 | tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1210 | break; |
1211 | ||
1212 | case 0xb: /* l.sfgesi */ | |
1213 | LOG_DIS("l.sfgesi r%d, %d\n", ra, I16); | |
84775c43 | 1214 | tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1215 | break; |
1216 | ||
1217 | case 0xc: /* l.sfltsi */ | |
1218 | LOG_DIS("l.sfltsi r%d, %d\n", ra, I16); | |
84775c43 | 1219 | tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1220 | break; |
1221 | ||
1222 | case 0xd: /* l.sflesi */ | |
1223 | LOG_DIS("l.sflesi r%d, %d\n", ra, I16); | |
84775c43 | 1224 | tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[ra], I16); |
bbe418f2 JL |
1225 | break; |
1226 | ||
1227 | default: | |
1228 | gen_illegal_exception(dc); | |
1229 | break; | |
1230 | } | |
bbe418f2 JL |
1231 | } |
1232 | ||
1233 | static void dec_sys(DisasContext *dc, uint32_t insn) | |
1234 | { | |
1235 | uint32_t op0; | |
bbe418f2 | 1236 | uint32_t K16; |
111ece51 | 1237 | |
3d59b680 | 1238 | op0 = extract32(insn, 16, 10); |
bbe418f2 | 1239 | K16 = extract32(insn, 0, 16); |
bbe418f2 JL |
1240 | |
1241 | switch (op0) { | |
1242 | case 0x000: /* l.sys */ | |
1243 | LOG_DIS("l.sys %d\n", K16); | |
1244 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1245 | gen_exception(dc, EXCP_SYSCALL); | |
1246 | dc->is_jmp = DISAS_UPDATE; | |
1247 | break; | |
1248 | ||
1249 | case 0x100: /* l.trap */ | |
1250 | LOG_DIS("l.trap %d\n", K16); | |
bbe418f2 JL |
1251 | tcg_gen_movi_tl(cpu_pc, dc->pc); |
1252 | gen_exception(dc, EXCP_TRAP); | |
bbe418f2 JL |
1253 | break; |
1254 | ||
1255 | case 0x300: /* l.csync */ | |
1256 | LOG_DIS("l.csync\n"); | |
bbe418f2 JL |
1257 | break; |
1258 | ||
1259 | case 0x200: /* l.msync */ | |
1260 | LOG_DIS("l.msync\n"); | |
24fc5c0f | 1261 | tcg_gen_mb(TCG_MO_ALL); |
bbe418f2 JL |
1262 | break; |
1263 | ||
1264 | case 0x270: /* l.psync */ | |
1265 | LOG_DIS("l.psync\n"); | |
bbe418f2 JL |
1266 | break; |
1267 | ||
1268 | default: | |
1269 | gen_illegal_exception(dc); | |
1270 | break; | |
1271 | } | |
1272 | } | |
1273 | ||
1274 | static void dec_float(DisasContext *dc, uint32_t insn) | |
1275 | { | |
1276 | uint32_t op0; | |
1277 | uint32_t ra, rb, rd; | |
1278 | op0 = extract32(insn, 0, 8); | |
1279 | ra = extract32(insn, 16, 5); | |
1280 | rb = extract32(insn, 11, 5); | |
1281 | rd = extract32(insn, 21, 5); | |
1282 | ||
1283 | switch (op0) { | |
1284 | case 0x00: /* lf.add.s */ | |
1285 | LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb); | |
1286 | gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1287 | break; | |
1288 | ||
1289 | case 0x01: /* lf.sub.s */ | |
1290 | LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb); | |
1291 | gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1292 | break; | |
1293 | ||
1294 | ||
1295 | case 0x02: /* lf.mul.s */ | |
1296 | LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb); | |
1297 | if (ra != 0 && rb != 0) { | |
1298 | gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1299 | } else { | |
1300 | tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF); | |
1301 | tcg_gen_movi_i32(cpu_R[rd], 0x0); | |
1302 | } | |
1303 | break; | |
1304 | ||
1305 | case 0x03: /* lf.div.s */ | |
1306 | LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb); | |
1307 | gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1308 | break; | |
1309 | ||
1310 | case 0x04: /* lf.itof.s */ | |
1311 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); | |
1312 | gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1313 | break; | |
1314 | ||
1315 | case 0x05: /* lf.ftoi.s */ | |
1316 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); | |
1317 | gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1318 | break; | |
1319 | ||
1320 | case 0x06: /* lf.rem.s */ | |
1321 | LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb); | |
1322 | gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1323 | break; | |
1324 | ||
1325 | case 0x07: /* lf.madd.s */ | |
1326 | LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb); | |
1327 | gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1328 | break; | |
1329 | ||
1330 | case 0x08: /* lf.sfeq.s */ | |
1331 | LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb); | |
84775c43 | 1332 | gen_helper_float_eq_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1333 | break; |
1334 | ||
1335 | case 0x09: /* lf.sfne.s */ | |
1336 | LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb); | |
84775c43 | 1337 | gen_helper_float_ne_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1338 | break; |
1339 | ||
1340 | case 0x0a: /* lf.sfgt.s */ | |
1341 | LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb); | |
84775c43 | 1342 | gen_helper_float_gt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1343 | break; |
1344 | ||
1345 | case 0x0b: /* lf.sfge.s */ | |
1346 | LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb); | |
84775c43 | 1347 | gen_helper_float_ge_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1348 | break; |
1349 | ||
1350 | case 0x0c: /* lf.sflt.s */ | |
1351 | LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb); | |
84775c43 | 1352 | gen_helper_float_lt_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1353 | break; |
1354 | ||
1355 | case 0x0d: /* lf.sfle.s */ | |
1356 | LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb); | |
84775c43 | 1357 | gen_helper_float_le_s(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1358 | break; |
1359 | ||
1360 | /* not used yet, open it when we need or64. */ | |
1361 | /*#ifdef TARGET_OPENRISC64 | |
1362 | case 0x10: lf.add.d | |
1363 | LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb); | |
1364 | check_of64s(dc); | |
1365 | gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1366 | break; | |
1367 | ||
1368 | case 0x11: lf.sub.d | |
1369 | LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb); | |
1370 | check_of64s(dc); | |
1371 | gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1372 | break; | |
1373 | ||
1374 | case 0x12: lf.mul.d | |
1375 | LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb); | |
1376 | check_of64s(dc); | |
1377 | if (ra != 0 && rb != 0) { | |
1378 | gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1379 | } else { | |
1380 | tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF); | |
1381 | tcg_gen_movi_i64(cpu_R[rd], 0x0); | |
1382 | } | |
1383 | break; | |
1384 | ||
1385 | case 0x13: lf.div.d | |
1386 | LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb); | |
1387 | check_of64s(dc); | |
1388 | gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1389 | break; | |
1390 | ||
1391 | case 0x14: lf.itof.d | |
1392 | LOG_DIS("lf.itof r%d, r%d\n", rd, ra); | |
1393 | check_of64s(dc); | |
1394 | gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1395 | break; | |
1396 | ||
1397 | case 0x15: lf.ftoi.d | |
1398 | LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra); | |
1399 | check_of64s(dc); | |
1400 | gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]); | |
1401 | break; | |
1402 | ||
1403 | case 0x16: lf.rem.d | |
1404 | LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb); | |
1405 | check_of64s(dc); | |
1406 | gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1407 | break; | |
1408 | ||
1409 | case 0x17: lf.madd.d | |
1410 | LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb); | |
1411 | check_of64s(dc); | |
1412 | gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]); | |
1413 | break; | |
1414 | ||
1415 | case 0x18: lf.sfeq.d | |
1416 | LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb); | |
1417 | check_of64s(dc); | |
84775c43 | 1418 | gen_helper_float_eq_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1419 | break; |
1420 | ||
1421 | case 0x1a: lf.sfgt.d | |
1422 | LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb); | |
1423 | check_of64s(dc); | |
84775c43 | 1424 | gen_helper_float_gt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1425 | break; |
1426 | ||
1427 | case 0x1b: lf.sfge.d | |
1428 | LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb); | |
1429 | check_of64s(dc); | |
84775c43 | 1430 | gen_helper_float_ge_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1431 | break; |
1432 | ||
1433 | case 0x19: lf.sfne.d | |
1434 | LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb); | |
1435 | check_of64s(dc); | |
84775c43 | 1436 | gen_helper_float_ne_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1437 | break; |
1438 | ||
1439 | case 0x1c: lf.sflt.d | |
1440 | LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb); | |
1441 | check_of64s(dc); | |
84775c43 | 1442 | gen_helper_float_lt_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1443 | break; |
1444 | ||
1445 | case 0x1d: lf.sfle.d | |
1446 | LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb); | |
1447 | check_of64s(dc); | |
84775c43 | 1448 | gen_helper_float_le_d(cpu_sr_f, cpu_env, cpu_R[ra], cpu_R[rb]); |
bbe418f2 JL |
1449 | break; |
1450 | #endif*/ | |
1451 | ||
1452 | default: | |
1453 | gen_illegal_exception(dc); | |
1454 | break; | |
1455 | } | |
bbe418f2 JL |
1456 | } |
1457 | ||
1458 | static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu) | |
1459 | { | |
1460 | uint32_t op0; | |
1461 | uint32_t insn; | |
1462 | insn = cpu_ldl_code(&cpu->env, dc->pc); | |
1463 | op0 = extract32(insn, 26, 6); | |
1464 | ||
1465 | switch (op0) { | |
1466 | case 0x06: | |
1467 | dec_M(dc, insn); | |
1468 | break; | |
1469 | ||
1470 | case 0x08: | |
1471 | dec_sys(dc, insn); | |
1472 | break; | |
1473 | ||
1474 | case 0x2e: | |
1475 | dec_logic(dc, insn); | |
1476 | break; | |
1477 | ||
1478 | case 0x2f: | |
1479 | dec_compi(dc, insn); | |
1480 | break; | |
1481 | ||
1482 | case 0x31: | |
1483 | dec_mac(dc, insn); | |
1484 | break; | |
1485 | ||
1486 | case 0x32: | |
1487 | dec_float(dc, insn); | |
1488 | break; | |
1489 | ||
1490 | case 0x38: | |
1491 | dec_calc(dc, insn); | |
1492 | break; | |
1493 | ||
1494 | case 0x39: | |
1495 | dec_comp(dc, insn); | |
1496 | break; | |
1497 | ||
1498 | default: | |
1499 | dec_misc(dc, insn); | |
1500 | break; | |
1501 | } | |
1502 | } | |
1503 | ||
4e5e1215 | 1504 | void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) |
e67db06e | 1505 | { |
4e5e1215 | 1506 | OpenRISCCPU *cpu = openrisc_env_get_cpu(env); |
ed2803da | 1507 | CPUState *cs = CPU(cpu); |
bbe418f2 | 1508 | struct DisasContext ctx, *dc = &ctx; |
bbe418f2 | 1509 | uint32_t pc_start; |
bbe418f2 JL |
1510 | uint32_t next_page_start; |
1511 | int num_insns; | |
1512 | int max_insns; | |
1513 | ||
bbe418f2 JL |
1514 | pc_start = tb->pc; |
1515 | dc->tb = tb; | |
1516 | ||
bbe418f2 JL |
1517 | dc->is_jmp = DISAS_NEXT; |
1518 | dc->ppc = pc_start; | |
1519 | dc->pc = pc_start; | |
1520 | dc->flags = cpu->env.cpucfgr; | |
97ed5ccd | 1521 | dc->mem_idx = cpu_mmu_index(&cpu->env, false); |
bbe418f2 | 1522 | dc->synced_flags = dc->tb_flags = tb->flags; |
0c53d734 | 1523 | dc->delayed_branch = (dc->tb_flags & D_FLAG) != 0; |
ed2803da | 1524 | dc->singlestep_enabled = cs->singlestep_enabled; |
bbe418f2 JL |
1525 | |
1526 | next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; | |
bbe418f2 JL |
1527 | num_insns = 0; |
1528 | max_insns = tb->cflags & CF_COUNT_MASK; | |
1529 | ||
1530 | if (max_insns == 0) { | |
1531 | max_insns = CF_COUNT_MASK; | |
1532 | } | |
190ce7fb RH |
1533 | if (max_insns > TCG_MAX_INSNS) { |
1534 | max_insns = TCG_MAX_INSNS; | |
1535 | } | |
bbe418f2 | 1536 | |
111ece51 RH |
1537 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
1538 | && qemu_log_in_addr_range(pc_start)) { | |
1539 | qemu_log_lock(); | |
1540 | qemu_log("----------------\n"); | |
1541 | qemu_log("IN: %s\n", lookup_symbol(pc_start)); | |
1542 | } | |
1543 | ||
cd42d5b2 | 1544 | gen_tb_start(tb); |
bbe418f2 JL |
1545 | |
1546 | do { | |
667b8e29 | 1547 | tcg_gen_insn_start(dc->pc); |
959082fc | 1548 | num_insns++; |
bbe418f2 | 1549 | |
b933066a RH |
1550 | if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { |
1551 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1552 | gen_exception(dc, EXCP_DEBUG); | |
1553 | dc->is_jmp = DISAS_UPDATE; | |
522a0d4e RH |
1554 | /* The address covered by the breakpoint must be included in |
1555 | [tb->pc, tb->pc + tb->size) in order to for it to be | |
1556 | properly cleared -- thus we increment the PC here so that | |
1557 | the logic setting tb->size below does the right thing. */ | |
1558 | dc->pc += 4; | |
b933066a RH |
1559 | break; |
1560 | } | |
1561 | ||
959082fc | 1562 | if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { |
bbe418f2 JL |
1563 | gen_io_start(); |
1564 | } | |
1565 | dc->ppc = dc->pc - 4; | |
1566 | dc->npc = dc->pc + 4; | |
1567 | tcg_gen_movi_tl(cpu_ppc, dc->ppc); | |
1568 | tcg_gen_movi_tl(cpu_npc, dc->npc); | |
1569 | disas_openrisc_insn(dc, cpu); | |
1570 | dc->pc = dc->npc; | |
bbe418f2 JL |
1571 | /* delay slot */ |
1572 | if (dc->delayed_branch) { | |
1573 | dc->delayed_branch--; | |
1574 | if (!dc->delayed_branch) { | |
1575 | dc->tb_flags &= ~D_FLAG; | |
1576 | gen_sync_flags(dc); | |
1577 | tcg_gen_mov_tl(cpu_pc, jmp_pc); | |
1578 | tcg_gen_mov_tl(cpu_npc, jmp_pc); | |
1579 | tcg_gen_movi_tl(jmp_pc, 0); | |
1580 | tcg_gen_exit_tb(0); | |
1581 | dc->is_jmp = DISAS_JUMP; | |
1582 | break; | |
1583 | } | |
1584 | } | |
1585 | } while (!dc->is_jmp | |
fe700adb | 1586 | && !tcg_op_buf_full() |
ed2803da | 1587 | && !cs->singlestep_enabled |
bbe418f2 JL |
1588 | && !singlestep |
1589 | && (dc->pc < next_page_start) | |
1590 | && num_insns < max_insns); | |
1591 | ||
1592 | if (tb->cflags & CF_LAST_IO) { | |
1593 | gen_io_end(); | |
1594 | } | |
1595 | if (dc->is_jmp == DISAS_NEXT) { | |
1596 | dc->is_jmp = DISAS_UPDATE; | |
1597 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1598 | } | |
ed2803da | 1599 | if (unlikely(cs->singlestep_enabled)) { |
bbe418f2 JL |
1600 | if (dc->is_jmp == DISAS_NEXT) { |
1601 | tcg_gen_movi_tl(cpu_pc, dc->pc); | |
1602 | } | |
1603 | gen_exception(dc, EXCP_DEBUG); | |
1604 | } else { | |
1605 | switch (dc->is_jmp) { | |
1606 | case DISAS_NEXT: | |
1607 | gen_goto_tb(dc, 0, dc->pc); | |
1608 | break; | |
1609 | default: | |
1610 | case DISAS_JUMP: | |
1611 | break; | |
1612 | case DISAS_UPDATE: | |
1613 | /* indicate that the hash table must be used | |
1614 | to find the next TB */ | |
1615 | tcg_gen_exit_tb(0); | |
1616 | break; | |
1617 | case DISAS_TB_JUMP: | |
1618 | /* nothing more to generate */ | |
1619 | break; | |
1620 | } | |
1621 | } | |
1622 | ||
806f352d | 1623 | gen_tb_end(tb, num_insns); |
0a7df5da | 1624 | |
4e5e1215 RH |
1625 | tb->size = dc->pc - pc_start; |
1626 | tb->icount = num_insns; | |
bbe418f2 | 1627 | |
4910e6e4 RH |
1628 | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) |
1629 | && qemu_log_in_addr_range(pc_start)) { | |
111ece51 RH |
1630 | log_target_disas(cs, pc_start, tb->size, 0); |
1631 | qemu_log("\n"); | |
1ee73216 | 1632 | qemu_log_unlock(); |
bbe418f2 | 1633 | } |
e67db06e JL |
1634 | } |
1635 | ||
878096ee AF |
1636 | void openrisc_cpu_dump_state(CPUState *cs, FILE *f, |
1637 | fprintf_function cpu_fprintf, | |
1638 | int flags) | |
e67db06e | 1639 | { |
878096ee AF |
1640 | OpenRISCCPU *cpu = OPENRISC_CPU(cs); |
1641 | CPUOpenRISCState *env = &cpu->env; | |
e67db06e | 1642 | int i; |
878096ee | 1643 | |
e67db06e JL |
1644 | cpu_fprintf(f, "PC=%08x\n", env->pc); |
1645 | for (i = 0; i < 32; ++i) { | |
878096ee | 1646 | cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i], |
e67db06e JL |
1647 | (i % 4) == 3 ? '\n' : ' '); |
1648 | } | |
1649 | } | |
1650 | ||
1651 | void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, | |
bad729e2 | 1652 | target_ulong *data) |
e67db06e | 1653 | { |
bad729e2 | 1654 | env->pc = data[0]; |
e67db06e | 1655 | } |