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00b70788 ND |
1 | /* |
2 | * PowerPC CPU routines for qemu. | |
3 | * | |
4 | * Copyright (c) 2017 Nikunj A Dadhania, IBM Corporation. | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
6bd039cd | 9 | * version 2.1 of the License, or (at your option) any later version. |
00b70788 ND |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #include "qemu/osdep.h" | |
21 | #include "cpu.h" | |
22 | #include "cpu-models.h" | |
172d74ef BL |
23 | #include "cpu-qom.h" |
24 | #include "exec/log.h" | |
c19940db | 25 | #include "fpu/softfloat-helpers.h" |
172d74ef | 26 | #include "mmu-hash64.h" |
a3f5c315 | 27 | #include "helper_regs.h" |
fe43ba97 | 28 | #include "sysemu/tcg.h" |
00b70788 | 29 | |
10de0521 | 30 | target_ulong cpu_read_xer(const CPUPPCState *env) |
00b70788 | 31 | { |
dd09c361 ND |
32 | if (is_isa300(env)) { |
33 | return env->xer | (env->so << XER_SO) | | |
34 | (env->ov << XER_OV) | (env->ca << XER_CA) | | |
35 | (env->ov32 << XER_OV32) | (env->ca32 << XER_CA32); | |
36 | } | |
37 | ||
00b70788 ND |
38 | return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | |
39 | (env->ca << XER_CA); | |
40 | } | |
41 | ||
42 | void cpu_write_xer(CPUPPCState *env, target_ulong xer) | |
43 | { | |
44 | env->so = (xer >> XER_SO) & 1; | |
45 | env->ov = (xer >> XER_OV) & 1; | |
46 | env->ca = (xer >> XER_CA) & 1; | |
dd09c361 ND |
47 | /* write all the flags, while reading back check of isa300 */ |
48 | env->ov32 = (xer >> XER_OV32) & 1; | |
49 | env->ca32 = (xer >> XER_CA32) & 1; | |
50 | env->xer = xer & ~((1ul << XER_SO) | | |
51 | (1ul << XER_OV) | (1ul << XER_CA) | | |
52 | (1ul << XER_OV32) | (1ul << XER_CA32)); | |
00b70788 | 53 | } |
c19940db BL |
54 | |
55 | void ppc_store_vscr(CPUPPCState *env, uint32_t vscr) | |
56 | { | |
57 | env->vscr = vscr & ~(1u << VSCR_SAT); | |
58 | /* Which bit we set is completely arbitrary, but clear the rest. */ | |
59 | env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT); | |
60 | env->vscr_sat.u64[1] = 0; | |
61 | set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); | |
62 | } | |
63 | ||
64 | uint32_t ppc_get_vscr(CPUPPCState *env) | |
65 | { | |
66 | uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0; | |
67 | return env->vscr | (sat << VSCR_SAT); | |
68 | } | |
172d74ef | 69 | |
a3f5c315 BL |
70 | /* GDBstub can read and write MSR... */ |
71 | void ppc_store_msr(CPUPPCState *env, target_ulong value) | |
72 | { | |
73 | hreg_store_msr(env, value, 0); | |
74 | } | |
75 | ||
6a8e8188 | 76 | #if !defined(CONFIG_USER_ONLY) |
a3f5c315 BL |
77 | void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) |
78 | { | |
79 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
80 | CPUPPCState *env = &cpu->env; | |
81 | ||
82 | env->spr[SPR_LPCR] = val & pcc->lpcr_mask; | |
83 | /* The gtse bit affects hflags */ | |
84 | hreg_compute_hflags(env); | |
2fdedcbc MF |
85 | |
86 | ppc_maybe_interrupt(env); | |
a3f5c315 | 87 | } |
6a8e8188 | 88 | #endif |
fe43ba97 BL |
89 | |
90 | static inline void fpscr_set_rounding_mode(CPUPPCState *env) | |
91 | { | |
92 | int rnd_type; | |
93 | ||
94 | /* Set rounding mode */ | |
208d8033 | 95 | switch (env->fpscr & FP_RN) { |
fe43ba97 BL |
96 | case 0: |
97 | /* Best approximation (round to nearest) */ | |
98 | rnd_type = float_round_nearest_even; | |
99 | break; | |
100 | case 1: | |
101 | /* Smaller magnitude (round toward zero) */ | |
102 | rnd_type = float_round_to_zero; | |
103 | break; | |
104 | case 2: | |
105 | /* Round toward +infinite */ | |
106 | rnd_type = float_round_up; | |
107 | break; | |
108 | default: | |
109 | case 3: | |
110 | /* Round toward -infinite */ | |
111 | rnd_type = float_round_down; | |
112 | break; | |
113 | } | |
114 | set_float_rounding_mode(rnd_type, &env->fp_status); | |
115 | } | |
116 | ||
117 | void ppc_store_fpscr(CPUPPCState *env, target_ulong val) | |
118 | { | |
25ee608d | 119 | val &= FPSCR_MTFS_MASK; |
fe43ba97 BL |
120 | if (val & FPSCR_IX) { |
121 | val |= FP_VX; | |
122 | } | |
123 | if ((val >> FPSCR_XX) & (val >> FPSCR_XE) & 0x1f) { | |
124 | val |= FP_FEX; | |
125 | } | |
126 | env->fpscr = val; | |
08e185ca LMC |
127 | env->fp_status.rebias_overflow = (FP_OE & env->fpscr) ? true : false; |
128 | env->fp_status.rebias_underflow = (FP_UE & env->fpscr) ? true : false; | |
fe43ba97 BL |
129 | if (tcg_enabled()) { |
130 | fpscr_set_rounding_mode(env); | |
131 | } | |
132 | } |