]> git.proxmox.com Git - mirror_qemu.git/blame - target/ppc/cpu.h
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-12-20' into staging
[mirror_qemu.git] / target / ppc / cpu.h
CommitLineData
79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 18 */
07f5a258
MA		 19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
79aceca5 22
9a78eead 23#include "qemu-common.h"
60caf221 24#include "qemu/int128.h"
3fc6c082 25
a4f30719
JM		 26//#define PPC_EMULATE_32BITS_HYPV
27
76a66253 28#if defined (TARGET_PPC64)
3cd7d1dd 29/* PowerPC 64 definitions */
d9d7210c 30#define TARGET_LONG_BITS 64
35cdaad6 31#define TARGET_PAGE_BITS 12
3cd7d1dd 32
f0b0685d
ND		 33#define TCG_GUEST_DEFAULT_MO 0
34
52705890
RH		 35/* Note that the official physical address space bits is 62-M where M
36 is implementation dependent. I've not looked up M for the set of
37 cpus we emulate at the system level. */
38#define TARGET_PHYS_ADDR_SPACE_BITS 62
39
40/* Note that the PPC environment architecture talks about 80 bit virtual
41 addresses, with segmentation. Obviously that's not all visible to a
42 single process, which is all we're concerned with here. */
43#ifdef TARGET_ABI32
44# define TARGET_VIRT_ADDR_SPACE_BITS 32
45#else
46# define TARGET_VIRT_ADDR_SPACE_BITS 64
47#endif
48
ad3e67d0 49#define TARGET_PAGE_BITS_64K 16
81762d6d
DG		 50#define TARGET_PAGE_BITS_16M 24
51
3cd7d1dd
JM		 52#else /* defined (TARGET_PPC64) */
53/* PowerPC 32 definitions */
d9d7210c 54#define TARGET_LONG_BITS 32
3cd7d1dd 55#define TARGET_PAGE_BITS 12
3cd7d1dd 56
8b242eba 57#define TARGET_PHYS_ADDR_SPACE_BITS 36
52705890
RH		 58#define TARGET_VIRT_ADDR_SPACE_BITS 32
59
3cd7d1dd 60#endif /* defined (TARGET_PPC64) */
3cf1e035 61
9349b4f9 62#define CPUArchState struct CPUPPCState
c2764719 63
022c62cb 64#include "exec/cpu-defs.h"
2d34fe39 65#include "cpu-qom.h"
4ecc3190 66
7f70c937 67#if defined (TARGET_PPC64)
4ecd4d16 68#define PPC_ELF_MACHINE EM_PPC64
76a66253 69#else
4ecd4d16 70#define PPC_ELF_MACHINE EM_PPC
76a66253 71#endif
9042c0e2 72
2a83f997
CLG		 73#define PPC_BIT(bit) (0x8000000000000000UL >> (bit))
74#define PPC_BIT32(bit) (0x80000000UL >> (bit))
75#define PPC_BIT8(bit) (0x80UL >> (bit))
76#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
77#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
78 PPC_BIT32(bs))
a6a444a8
CLG		 79#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
80
81#if HOST_LONG_BITS == 32
82# define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
83#elif HOST_LONG_BITS == 64
84# define MASK_TO_LSH(m) (__builtin_ffsl(m) - 1)
85#else
86# error Unknown sizeof long
87#endif
88
89#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
90#define SETFIELD(m, v, val) \
91 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
2a83f997 92
e1833e1f
JM		 93/*****************************************************************************/
94/* Exception vectors definitions */
95enum {
96 POWERPC_EXCP_NONE = -1,
97 /* The 64 first entries are used by the PowerPC embedded specification */
98 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
99 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
100 POWERPC_EXCP_DSI = 2, /* Data storage exception */
101 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
102 POWERPC_EXCP_EXTERNAL = 4, /* External input */
103 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
104 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
105 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
106 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
107 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
108 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
109 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
110 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 111 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
112 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 113 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
114 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 115 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
116 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
117 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
118 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
119 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
120 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 121 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
122 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
123 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
124 /* Vectors 42 to 63 are reserved */
e1833e1f
JM		 125 /* Exceptions defined in the PowerPC server specification */
126 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 127 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
128 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 129 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 130 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 131 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
132 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
133 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
134 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 135 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
136 /* 40x specific exceptions */
137 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
138 /* 601 specific exceptions */
139 POWERPC_EXCP_IO = 75, /* IO error exception */
140 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
141 /* 602 specific exceptions */
142 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
143 /* 602/603 specific exceptions */
b4095fed 144 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 145 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
146 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
147 /* Exceptions available on most PowerPC */
148 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 149 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
150 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
151 POWERPC_EXCP_SMI = 84, /* System management interrupt */
152 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 153 /* 7xx/74xx specific exceptions */
b4095fed 154 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 155 /* 74xx specific exceptions */
b4095fed 156 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 157 /* 970FX specific exceptions */
b4095fed
JM		 158 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
159 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 160 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 161 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
162 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
163 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
164 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
1f29871c
TM		 165 /* VSX Unavailable (Power ISA 2.06 and later) */
166 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
7019cb3d 167 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
f03a1af5
BH		 168 /* Additional ISA 2.06 and later server exceptions */
169 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
170 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
171 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
1414c75d
CLG		 172 /* Server doorbell variants */
173 POWERPC_EXCP_SDOOR = 99,
174 POWERPC_EXCP_SDOOR_HV = 100,
e1833e1f 175 /* EOL */
1414c75d 176 POWERPC_EXCP_NB = 101,
5cbdb3a3 177 /* QEMU exceptions: used internally during code translation */
e1833e1f
JM		 178 POWERPC_EXCP_STOP = 0x200, /* stop translation */
179 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
5cbdb3a3 180 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 181 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
182 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
183};
184
e1833e1f
JM		 185/* Exceptions error codes */
186enum {
187 /* Exception subtypes for POWERPC_EXCP_ALIGN */
188 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
189 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
190 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
191 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
192 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
193 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
194 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
195 /* FP exceptions */
196 POWERPC_EXCP_FP = 0x10,
197 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
198 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
199 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
200 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 201 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 202 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
203 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
204 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
205 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
206 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
207 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
208 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
209 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
210 /* Invalid instruction */
211 POWERPC_EXCP_INVAL = 0x20,
212 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
213 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
214 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
215 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
216 /* Privileged instruction */
217 POWERPC_EXCP_PRIV = 0x30,
218 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
219 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
220 /* Trap */
221 POWERPC_EXCP_TRAP = 0x40,
222};
223
a750fc0b 224#define PPC_INPUT(env) (env->bus_model)
3fc6c082 225
be147d08 226/*****************************************************************************/
c227f099 227typedef struct opc_handler_t opc_handler_t;
79aceca5 228
3fc6c082 229/*****************************************************************************/
7222b94a 230/* Types used to describe some PowerPC registers etc. */
69b058c8 231typedef struct DisasContext DisasContext;
c227f099 232typedef struct ppc_spr_t ppc_spr_t;
c227f099
AL		 233typedef union ppc_avr_t ppc_avr_t;
234typedef union ppc_tlb_t ppc_tlb_t;
1ad9f0a4 235typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
76a66253 236
3fc6c082 237/* SPR access micro-ops generations callbacks */
c227f099 238struct ppc_spr_t {
69b058c8
PB		 239 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
240 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 241#if !defined(CONFIG_USER_ONLY)
69b058c8
PB		 242 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
243 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
244 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
245 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 246#endif
b55266b5 247 const char *name;
d197fdbc 248 target_ulong default_value;
d67d40ea
DG		 249#ifdef CONFIG_KVM
250 /* We (ab)use the fact that all the SPRs will have ids for the
251 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
252 * don't sync this */
253 uint64_t one_reg_id;
254#endif
3fc6c082
FB		 255};
256
257/* Altivec registers (128 bits) */
c227f099 258union ppc_avr_t {
0f6fbcbc 259 float32 f[4];
a9d9eb8f
JM		 260 uint8_t u8[16];
261 uint16_t u16[8];
262 uint32_t u32[4];
ab5f265d
AJ		 263 int8_t s8[16];
264 int16_t s16[8];
265 int32_t s32[4];
a9d9eb8f 266 uint64_t u64[2];
bb527533
TM		 267 int64_t s64[2];
268#ifdef CONFIG_INT128
269 __uint128_t u128;
270#endif
60caf221 271 Int128 s128;
3fc6c082 272};
9fddaa0c 273
3c7b48b7 274#if !defined(CONFIG_USER_ONLY)
3fc6c082 275/* Software TLB cache */
c227f099
AL		 276typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
277struct ppc6xx_tlb_t {
76a66253
JM		 278 target_ulong pte0;
279 target_ulong pte1;
280 target_ulong EPN;
1d0a48fb
JM		 281};
282
c227f099
AL		 283typedef struct ppcemb_tlb_t ppcemb_tlb_t;
284struct ppcemb_tlb_t {
b162d02e 285 uint64_t RPN;
1d0a48fb 286 target_ulong EPN;
76a66253 287 target_ulong PID;
c55e9aef
JM		 288 target_ulong size;
289 uint32_t prot;
290 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 291};
292
d1e256fe
AG		 293typedef struct ppcmas_tlb_t {
294 uint32_t mas8;
295 uint32_t mas1;
296 uint64_t mas2;
297 uint64_t mas7_3;
298} ppcmas_tlb_t;
299
c227f099 300union ppc_tlb_t {
1c53accc
AG		 301 ppc6xx_tlb_t *tlb6;
302 ppcemb_tlb_t *tlbe;
303 ppcmas_tlb_t *tlbm;
3fc6c082 304};
1c53accc
AG		 305
306/* possible TLB variants */
307#define TLB_NONE 0
308#define TLB_6XX 1
309#define TLB_EMB 2
310#define TLB_MAS 3
3c7b48b7 311#endif
3fc6c082 312
b07c59f7
DG		 313typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
314
c227f099
AL		 315typedef struct ppc_slb_t ppc_slb_t;
316struct ppc_slb_t {
81762d6d
DG		 317 uint64_t esid;
318 uint64_t vsid;
b07c59f7 319 const PPCHash64SegmentPageSizes *sps;
8eee0af9
BS		 320};
321
d83af167 322#define MAX_SLB_ENTRIES 64
81762d6d
DG		 323#define SEGMENT_SHIFT_256M 28
324#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
325
cdaee006
DG		 326#define SEGMENT_SHIFT_1T 40
327#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
328
329
3fc6c082
FB		 330/*****************************************************************************/
331/* Machine state register bits definition */
76a66253 332#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 333#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 334#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
a4f30719 335#define MSR_SHV 60 /* hypervisor state hflags */
cdcdda27
AK		 336#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
337#define MSR_TS1 33
338#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
363be49c
JM		 339#define MSR_CM 31 /* Computation mode for BookE hflags */
340#define MSR_ICM 30 /* Interrupt computation mode for BookE */
a4f30719 341#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
71afeb61 342#define MSR_GS 28 /* guest state for BookE */
363be49c 343#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 344#define MSR_VR 25 /* altivec available x hflags */
345#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253 346#define MSR_AP 23 /* Access privilege state on 602 hflags */
1f29871c 347#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
76a66253 348#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 349#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 350#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 351#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
352#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 353#define MSR_ILE 16 /* Interrupt little-endian mode */
354#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 355#define MSR_PR 14 /* Problem state hflags */
356#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 357#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 358#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 359#define MSR_SE 10 /* Single-step trace enable x hflags */
360#define MSR_DWE 10 /* Debug wait enable on 405 x */
361#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
362#define MSR_BE 9 /* Branch trace enable x hflags */
363#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 364#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 365#define MSR_AL 7 /* AL bit on POWER */
0411a972 366#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 367#define MSR_IR 5 /* Instruction relocate */
3fc6c082 368#define MSR_DR 4 /* Data relocate */
9fb04491
BH		 369#define MSR_IS 5 /* Instruction address space (BookE) */
370#define MSR_DS 4 /* Data address space (BookE) */
25ba3a68 371#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 372#define MSR_PX 2 /* Protection exclusive on 403 x */
373#define MSR_PMM 2 /* Performance monitor mark on POWER x */
374#define MSR_RI 1 /* Recoverable interrupt 1 */
375#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972 376
1488270e 377/* LPCR bits */
2a83f997
CLG		 378#define LPCR_VPM0 PPC_BIT(0)
379#define LPCR_VPM1 PPC_BIT(1)
380#define LPCR_ISL PPC_BIT(2)
381#define LPCR_KBV PPC_BIT(3)
88536935 382#define LPCR_DPFD_SHIFT (63 - 11)
7659ca1a 383#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
88536935
BH		 384#define LPCR_VRMASD_SHIFT (63 - 16)
385#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
18aa49ec
SJS		 386/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
387#define LPCR_PECE_U_SHIFT (63 - 19)
388#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
2a83f997 389#define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
88536935
BH		 390#define LPCR_RMLS_SHIFT (63 - 37)
391#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
2a83f997 392#define LPCR_ILE PPC_BIT(38)
1488270e
BH		 393#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
394#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
2a83f997
CLG		 395#define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
396#define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
397#define LPCR_ONL PPC_BIT(45)
398#define LPCR_LD PPC_BIT(46) /* Large Decrementer */
399#define LPCR_P7_PECE0 PPC_BIT(49)
400#define LPCR_P7_PECE1 PPC_BIT(50)
401#define LPCR_P7_PECE2 PPC_BIT(51)
402#define LPCR_P8_PECE0 PPC_BIT(47)
403#define LPCR_P8_PECE1 PPC_BIT(48)
404#define LPCR_P8_PECE2 PPC_BIT(49)
405#define LPCR_P8_PECE3 PPC_BIT(50)
406#define LPCR_P8_PECE4 PPC_BIT(51)
18aa49ec
SJS		 407/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
408#define LPCR_PECE_L_SHIFT (63 - 51)
409#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
2a83f997
CLG		 410#define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
411#define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
412#define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
413#define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
414#define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
415#define LPCR_MER PPC_BIT(52)
416#define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
417#define LPCR_TC PPC_BIT(54)
418#define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
419#define LPCR_LPES0 PPC_BIT(60)
420#define LPCR_LPES1 PPC_BIT(61)
421#define LPCR_RMI PPC_BIT(62)
422#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
423#define LPCR_HDICE PPC_BIT(63)
1e0c7e55 424
0411a972
JM		 425#define msr_sf ((env->msr >> MSR_SF) & 1)
426#define msr_isf ((env->msr >> MSR_ISF) & 1)
a4f30719 427#define msr_shv ((env->msr >> MSR_SHV) & 1)
0411a972
JM		 428#define msr_cm ((env->msr >> MSR_CM) & 1)
429#define msr_icm ((env->msr >> MSR_ICM) & 1)
a4f30719 430#define msr_thv ((env->msr >> MSR_THV) & 1)
71afeb61 431#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 432#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
433#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 434#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972 435#define msr_ap ((env->msr >> MSR_AP) & 1)
1f29871c 436#define msr_vsx ((env->msr >> MSR_VSX) & 1)
0411a972
JM		 437#define msr_sa ((env->msr >> MSR_SA) & 1)
438#define msr_key ((env->msr >> MSR_KEY) & 1)
439#define msr_pow ((env->msr >> MSR_POW) & 1)
440#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
441#define msr_ce ((env->msr >> MSR_CE) & 1)
442#define msr_ile ((env->msr >> MSR_ILE) & 1)
443#define msr_ee ((env->msr >> MSR_EE) & 1)
444#define msr_pr ((env->msr >> MSR_PR) & 1)
445#define msr_fp ((env->msr >> MSR_FP) & 1)
446#define msr_me ((env->msr >> MSR_ME) & 1)
447#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
448#define msr_se ((env->msr >> MSR_SE) & 1)
449#define msr_dwe ((env->msr >> MSR_DWE) & 1)
450#define msr_uble ((env->msr >> MSR_UBLE) & 1)
451#define msr_be ((env->msr >> MSR_BE) & 1)
452#define msr_de ((env->msr >> MSR_DE) & 1)
453#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
454#define msr_al ((env->msr >> MSR_AL) & 1)
455#define msr_ep ((env->msr >> MSR_EP) & 1)
456#define msr_ir ((env->msr >> MSR_IR) & 1)
457#define msr_dr ((env->msr >> MSR_DR) & 1)
9fb04491
BH		 458#define msr_is ((env->msr >> MSR_IS) & 1)
459#define msr_ds ((env->msr >> MSR_DS) & 1)
0411a972
JM		 460#define msr_pe ((env->msr >> MSR_PE) & 1)
461#define msr_px ((env->msr >> MSR_PX) & 1)
462#define msr_pmm ((env->msr >> MSR_PMM) & 1)
463#define msr_ri ((env->msr >> MSR_RI) & 1)
464#define msr_le ((env->msr >> MSR_LE) & 1)
cdcdda27
AK		 465#define msr_ts ((env->msr >> MSR_TS1) & 3)
466#define msr_tm ((env->msr >> MSR_TM) & 1)
467
0e3bf489
RK		 468#define DBCR0_ICMP (1 << 27)
469#define DBCR0_BRT (1 << 26)
470#define DBSR_ICMP (1 << 27)
471#define DBSR_BRT (1 << 26)
472
a4f30719
JM		 473/* Hypervisor bit is more specific */
474#if defined(TARGET_PPC64)
475#define MSR_HVB (1ULL << MSR_SHV)
476#define msr_hv msr_shv
477#else
478#if defined(PPC_EMULATE_32BITS_HYPV)
479#define MSR_HVB (1ULL << MSR_THV)
480#define msr_hv msr_thv
a4f30719
JM		 481#else
482#define MSR_HVB (0ULL)
483#define msr_hv (0)
484#endif
485#endif
79aceca5 486
da82c73a
SJS		 487/* DSISR */
488#define DSISR_NOPTE 0x40000000
489/* Not permitted by access authority of encoded access authority */
490#define DSISR_PROTFAULT 0x08000000
491#define DSISR_ISSTORE 0x02000000
492/* Not permitted by virtual page class key protection */
493#define DSISR_AMR 0x00200000
d5fee0bb
SJS		 494/* Unsupported Radix Tree Configuration */
495#define DSISR_R_BADCONFIG 0x00080000
da82c73a 496
a6152b52
SJS		 497/* SRR1 error code fields */
498
da82c73a
SJS		 499#define SRR1_NOPTE DSISR_NOPTE
500/* Not permitted due to no-execute or guard bit set */
07a68f99 501#define SRR1_NOEXEC_GUARD 0x10000000
da82c73a
SJS		 502#define SRR1_PROTFAULT DSISR_PROTFAULT
503#define SRR1_IAMR DSISR_AMR
a6152b52 504
7019cb3d
AK		 505/* Facility Status and Control (FSCR) bits */
506#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
507#define FSCR_TAR (63 - 55) /* Target Address Register */
508/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
509#define FSCR_IC_MASK (0xFFULL)
510#define FSCR_IC_POS (63 - 7)
511#define FSCR_IC_DSCR_SPR3 2
512#define FSCR_IC_PMU 3
513#define FSCR_IC_BHRB 4
514#define FSCR_IC_TM 5
515#define FSCR_IC_EBB 7
516#define FSCR_IC_TAR 8
517
a586e548 518/* Exception state register bits definition */
2a83f997
CLG		 519#define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
520#define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
521#define ESR_PTR PPC_BIT(38) /* Trap */
522#define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
523#define ESR_ST PPC_BIT(40) /* Store Operation */
524#define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
525#define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
526#define ESR_BO PPC_BIT(46) /* Byte Ordering */
527#define ESR_PIE PPC_BIT(47) /* Imprecise exception */
528#define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
529#define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
530#define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
531#define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
532#define ESR_EPID PPC_BIT(57) /* External Process ID operation */
533#define ESR_VLEMI PPC_BIT(58) /* VLE operation */
534#define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
a586e548 535
aac86237
TM		 536/* Transaction EXception And Summary Register bits */
537#define TEXASR_FAILURE_PERSISTENT (63 - 7)
538#define TEXASR_DISALLOWED (63 - 8)
539#define TEXASR_NESTING_OVERFLOW (63 - 9)
540#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
541#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
542#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
543#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
544#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
545#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
546#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
547#define TEXASR_ABORT (63 - 31)
548#define TEXASR_SUSPENDED (63 - 32)
549#define TEXASR_PRIVILEGE_HV (63 - 34)
550#define TEXASR_PRIVILEGE_PR (63 - 35)
551#define TEXASR_FAILURE_SUMMARY (63 - 36)
552#define TEXASR_TFIAR_EXACT (63 - 37)
553#define TEXASR_ROT (63 - 38)
554#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
555
d26bfc9a 556enum {
4018bae9 557 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 558 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 559 POWERPC_FLAG_SPE = 0x00000001,
560 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 561 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 562 POWERPC_FLAG_TGPR = 0x00000004,
563 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 564 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 565 POWERPC_FLAG_SE = 0x00000010,
566 POWERPC_FLAG_DWE = 0x00000020,
567 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 568 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 569 POWERPC_FLAG_BE = 0x00000080,
570 POWERPC_FLAG_DE = 0x00000100,
a4f30719 571 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 572 POWERPC_FLAG_PX = 0x00000200,
573 POWERPC_FLAG_PMM = 0x00000400,
574 /* Flag for special features */
575 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
576 POWERPC_FLAG_RTC_CLK = 0x00010000,
577 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 578 /* Has CFAR */
579 POWERPC_FLAG_CFAR = 0x00040000,
74f23997
TM		 580 /* Has VSX */
581 POWERPC_FLAG_VSX = 0x00080000,
e43668a7
TM		 582 /* Has Transaction Memory (ISA 2.07) */
583 POWERPC_FLAG_TM = 0x00100000,
d26bfc9a
JM		 584};
585
7c58044c
JM		 586/*****************************************************************************/
587/* Floating point status and control register */
588#define FPSCR_FX 31 /* Floating-point exception summary */
589#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
590#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
591#define FPSCR_OX 28 /* Floating-point overflow exception */
592#define FPSCR_UX 27 /* Floating-point underflow exception */
593#define FPSCR_ZX 26 /* Floating-point zero divide exception */
594#define FPSCR_XX 25 /* Floating-point inexact exception */
595#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
596#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
597#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
598#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
599#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
600#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
601#define FPSCR_FR 18 /* Floating-point fraction rounded */
602#define FPSCR_FI 17 /* Floating-point fraction inexact */
603#define FPSCR_C 16 /* Floating-point result class descriptor */
604#define FPSCR_FL 15 /* Floating-point less than or negative */
605#define FPSCR_FG 14 /* Floating-point greater than or negative */
606#define FPSCR_FE 13 /* Floating-point equal or zero */
607#define FPSCR_FU 12 /* Floating-point unordered or NaN */
608#define FPSCR_FPCC 12 /* Floating-point condition code */
609#define FPSCR_FPRF 12 /* Floating-point result flags */
610#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
611#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
612#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
613#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
614#define FPSCR_OE 6 /* Floating-point overflow exception enable */
615#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
616#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
617#define FPSCR_XE 3 /* Floating-point inexact exception enable */
618#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
619#define FPSCR_RN1 1
620#define FPSCR_RN 0 /* Floating-point rounding control */
621#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
622#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
623#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
624#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
625#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
626#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
627#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
628#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
629#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
630#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
631#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
632#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
633#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
634#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
635#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
636#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
637#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
638#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
639#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
640#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
641#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
642#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
643#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
644/* Invalid operation exception summary */
645#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
646 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
647 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
648 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
649 (1 << FPSCR_VXCVI)))
650/* exception summary */
651#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
652/* enabled exception summary */
653#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
654 0x1F)
655
dbdc13a1
MS		 656#define FP_FX (1ull << FPSCR_FX)
657#define FP_FEX (1ull << FPSCR_FEX)
fc03cfef 658#define FP_VX (1ull << FPSCR_VX)
dbdc13a1 659#define FP_OX (1ull << FPSCR_OX)
dbdc13a1 660#define FP_UX (1ull << FPSCR_UX)
dbdc13a1 661#define FP_ZX (1ull << FPSCR_ZX)
fc03cfef 662#define FP_XX (1ull << FPSCR_XX)
dbdc13a1
MS		 663#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
664#define FP_VXISI (1ull << FPSCR_VXISI)
dbdc13a1 665#define FP_VXIDI (1ull << FPSCR_VXIDI)
fc03cfef
JC		 666#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
667#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
dbdc13a1 668#define FP_VXVC (1ull << FPSCR_VXVC)
fc03cfef
JC		 669#define FP_FR (1ull << FSPCR_FR)
670#define FP_FI (1ull << FPSCR_FI)
671#define FP_C (1ull << FPSCR_C)
672#define FP_FL (1ull << FPSCR_FL)
673#define FP_FG (1ull << FPSCR_FG)
674#define FP_FE (1ull << FPSCR_FE)
675#define FP_FU (1ull << FPSCR_FU)
676#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
677#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
678#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
679#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
dbdc13a1
MS		 680#define FP_VXCVI (1ull << FPSCR_VXCVI)
681#define FP_VE (1ull << FPSCR_VE)
fc03cfef
JC		 682#define FP_OE (1ull << FPSCR_OE)
683#define FP_UE (1ull << FPSCR_UE)
684#define FP_ZE (1ull << FPSCR_ZE)
685#define FP_XE (1ull << FPSCR_XE)
686#define FP_NI (1ull << FPSCR_NI)
687#define FP_RN1 (1ull << FPSCR_RN1)
688#define FP_RN (1ull << FPSCR_RN)
dbdc13a1 689
d1277156
JC		 690/* the exception bits which can be cleared by mcrfs - includes FX */
691#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
692 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
693 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
694 FP_VXSQRT | FP_VXCVI)
695
7c58044c 696/*****************************************************************************/
6fa724a3
AJ		 697/* Vector status and control register */
698#define VSCR_NJ 16 /* Vector non-java */
699#define VSCR_SAT 0 /* Vector saturation */
700#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
701#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
702
01662f3e
AG		 703/*****************************************************************************/
704/* BookE e500 MMU registers */
705
706#define MAS0_NV_SHIFT 0
707#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
708
709#define MAS0_WQ_SHIFT 12
710#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
711/* Write TLB entry regardless of reservation */
712#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
713/* Write TLB entry only already in use */
714#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
715/* Clear TLB entry */
716#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
717
718#define MAS0_HES_SHIFT 14
719#define MAS0_HES (1 << MAS0_HES_SHIFT)
720
721#define MAS0_ESEL_SHIFT 16
722#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
723
724#define MAS0_TLBSEL_SHIFT 28
725#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
726#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
727#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
728#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
729#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
730
731#define MAS0_ATSEL_SHIFT 31
732#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
733#define MAS0_ATSEL_TLB 0
734#define MAS0_ATSEL_LRAT MAS0_ATSEL
735
2bd9543c
SW		 736#define MAS1_TSIZE_SHIFT 7
737#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 738
739#define MAS1_TS_SHIFT 12
740#define MAS1_TS (1 << MAS1_TS_SHIFT)
741
742#define MAS1_IND_SHIFT 13
743#define MAS1_IND (1 << MAS1_IND_SHIFT)
744
745#define MAS1_TID_SHIFT 16
746#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
747
748#define MAS1_IPROT_SHIFT 30
749#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
750
751#define MAS1_VALID_SHIFT 31
752#define MAS1_VALID 0x80000000
753
754#define MAS2_EPN_SHIFT 12
96091698 755#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 756
757#define MAS2_ACM_SHIFT 6
758#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
759
760#define MAS2_VLE_SHIFT 5
761#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
762
763#define MAS2_W_SHIFT 4
764#define MAS2_W (1 << MAS2_W_SHIFT)
765
766#define MAS2_I_SHIFT 3
767#define MAS2_I (1 << MAS2_I_SHIFT)
768
769#define MAS2_M_SHIFT 2
770#define MAS2_M (1 << MAS2_M_SHIFT)
771
772#define MAS2_G_SHIFT 1
773#define MAS2_G (1 << MAS2_G_SHIFT)
774
775#define MAS2_E_SHIFT 0
776#define MAS2_E (1 << MAS2_E_SHIFT)
777
778#define MAS3_RPN_SHIFT 12
779#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
780
781#define MAS3_U0 0x00000200
782#define MAS3_U1 0x00000100
783#define MAS3_U2 0x00000080
784#define MAS3_U3 0x00000040
785#define MAS3_UX 0x00000020
786#define MAS3_SX 0x00000010
787#define MAS3_UW 0x00000008
788#define MAS3_SW 0x00000004
789#define MAS3_UR 0x00000002
790#define MAS3_SR 0x00000001
791#define MAS3_SPSIZE_SHIFT 1
792#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
793
794#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
795#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
796#define MAS4_TIDSELD_MASK 0x00030000
797#define MAS4_TIDSELD_PID0 0x00000000
798#define MAS4_TIDSELD_PID1 0x00010000
799#define MAS4_TIDSELD_PID2 0x00020000
800#define MAS4_TIDSELD_PIDZ 0x00030000
801#define MAS4_INDD 0x00008000 /* Default IND */
802#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
803#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
804#define MAS4_ACMD 0x00000040
805#define MAS4_VLED 0x00000020
806#define MAS4_WD 0x00000010
807#define MAS4_ID 0x00000008
808#define MAS4_MD 0x00000004
809#define MAS4_GD 0x00000002
810#define MAS4_ED 0x00000001
811#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
812#define MAS4_WIMGED_SHIFT 0
813
814#define MAS5_SGS 0x80000000
815#define MAS5_SLPID_MASK 0x00000fff
816
817#define MAS6_SPID0 0x3fff0000
818#define MAS6_SPID1 0x00007ffe
819#define MAS6_ISIZE(x) MAS1_TSIZE(x)
820#define MAS6_SAS 0x00000001
821#define MAS6_SPID MAS6_SPID0
822#define MAS6_SIND 0x00000002 /* Indirect page */
823#define MAS6_SIND_SHIFT 1
824#define MAS6_SPID_MASK 0x3fff0000
825#define MAS6_SPID_SHIFT 16
826#define MAS6_ISIZE_MASK 0x00000f80
827#define MAS6_ISIZE_SHIFT 7
828
829#define MAS7_RPN 0xffffffff
830
831#define MAS8_TGS 0x80000000
832#define MAS8_VF 0x40000000
833#define MAS8_TLBPID 0x00000fff
834
835/* Bit definitions for MMUCFG */
836#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
837#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
838#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
839#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
840#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
841#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
842#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
843#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
844#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
845
846/* Bit definitions for MMUCSR0 */
847#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
848#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
849#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
850#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
851#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
852 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
853#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
854#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
855#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
856#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
857
858/* TLBnCFG encoding */
859#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
860#define TLBnCFG_HES 0x00002000 /* HW select supported */
861#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
862#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
863#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
864#define TLBnCFG_IND 0x00020000 /* IND entries supported */
865#define TLBnCFG_PT 0x00040000 /* Can load from page table */
866#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
867#define TLBnCFG_MINSIZE_SHIFT 20
868#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
869#define TLBnCFG_MAXSIZE_SHIFT 16
870#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
871#define TLBnCFG_ASSOC_SHIFT 24
872
873/* TLBnPS encoding */
874#define TLBnPS_4K 0x00000004
875#define TLBnPS_8K 0x00000008
876#define TLBnPS_16K 0x00000010
877#define TLBnPS_32K 0x00000020
878#define TLBnPS_64K 0x00000040
879#define TLBnPS_128K 0x00000080
880#define TLBnPS_256K 0x00000100
881#define TLBnPS_512K 0x00000200
882#define TLBnPS_1M 0x00000400
883#define TLBnPS_2M 0x00000800
884#define TLBnPS_4M 0x00001000
885#define TLBnPS_8M 0x00002000
886#define TLBnPS_16M 0x00004000
887#define TLBnPS_32M 0x00008000
888#define TLBnPS_64M 0x00010000
889#define TLBnPS_128M 0x00020000
890#define TLBnPS_256M 0x00040000
891#define TLBnPS_512M 0x00080000
892#define TLBnPS_1G 0x00100000
893#define TLBnPS_2G 0x00200000
894#define TLBnPS_4G 0x00400000
895#define TLBnPS_8G 0x00800000
896#define TLBnPS_16G 0x01000000
897#define TLBnPS_32G 0x02000000
898#define TLBnPS_64G 0x04000000
899#define TLBnPS_128G 0x08000000
900#define TLBnPS_256G 0x10000000
901
902/* tlbilx action encoding */
903#define TLBILX_T_ALL 0
904#define TLBILX_T_TID 1
905#define TLBILX_T_FULLMATCH 3
906#define TLBILX_T_CLASS0 4
907#define TLBILX_T_CLASS1 5
908#define TLBILX_T_CLASS2 6
909#define TLBILX_T_CLASS3 7
910
911/* BookE 2.06 helper defines */
912
913#define BOOKE206_FLUSH_TLB0 (1 << 0)
914#define BOOKE206_FLUSH_TLB1 (1 << 1)
915#define BOOKE206_FLUSH_TLB2 (1 << 2)
916#define BOOKE206_FLUSH_TLB3 (1 << 3)
917
918/* number of possible TLBs */
919#define BOOKE206_MAX_TLBN 4
920
50728199
RK		 921#define EPID_EPID_SHIFT 0x0
922#define EPID_EPID 0xFF
923#define EPID_ELPID_SHIFT 0x10
924#define EPID_ELPID 0x3F0000
925#define EPID_EGS 0x20000000
926#define EPID_EGS_SHIFT 29
927#define EPID_EAS 0x40000000
928#define EPID_EAS_SHIFT 30
929#define EPID_EPR 0x80000000
930#define EPID_EPR_SHIFT 31
931/* We don't support EGS and ELPID */
932#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
933
58e00a24 934/*****************************************************************************/
7af1e7b0 935/* Server and Embedded Processor Control */
58e00a24
AG		 936
937#define DBELL_TYPE_SHIFT 27
938#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
939#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
940#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
941#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
942#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
943#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
944
7af1e7b0
CLG		 945#define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
946
947#define DBELL_BRDCAST PPC_BIT(37)
58e00a24
AG		 948#define DBELL_LPIDTAG_SHIFT 14
949#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
950#define DBELL_PIRTAG_MASK 0x3fff
951
7af1e7b0
CLG		 952#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
953
4656e1f0
BH		 954#define PPC_PAGE_SIZES_MAX_SZ 8
955
c64abd1f
SB		 956struct ppc_radix_page_info {
957 uint32_t count;
958 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
959};
4656e1f0 960
6fa724a3 961/*****************************************************************************/
7c58044c 962/* The whole PowerPC CPU context */
50728199
RK		 963
964/* PowerPC needs eight modes for different hypervisor/supervisor/guest +
965 * real/paged mode combinations. The other two modes are for external PID
966 * load/store.
967 */
968#define NB_MMU_MODES 10
969#define MMU_MODE8_SUFFIX _epl
970#define MMU_MODE9_SUFFIX _eps
971#define PPC_TLB_EPID_LOAD 8
972#define PPC_TLB_EPID_STORE 9
6ebbf390 973
54ff58bb
BR		 974#define PPC_CPU_OPCODES_LEN 0x40
975#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
b048960f 976
3fc6c082
FB		 977struct CPUPPCState {
978 /* First are the most commonly used resources
979 * during translated code execution
980 */
79aceca5 981 /* general purpose registers */
bd7d9a6d 982 target_ulong gpr[32];
3cd7d1dd 983 /* Storage for GPR MSB, used by the SPE extension */
bd7d9a6d 984 target_ulong gprh[32];
3fc6c082
FB		 985 /* LR */
986 target_ulong lr;
987 /* CTR */
988 target_ulong ctr;
989 /* condition register */
47e4661c 990 uint32_t crf[8];
697ab892
DG		 991#if defined(TARGET_PPC64)
992 /* CFAR */
993 target_ulong cfar;
994#endif
da91a00f 995 /* XER (with SO, OV, CA split out) */
3d7b417e 996 target_ulong xer;
da91a00f
RH		 997 target_ulong so;
998 target_ulong ov;
999 target_ulong ca;
dd09c361
ND		 1000 target_ulong ov32;
1001 target_ulong ca32;
79aceca5 1002 /* Reservation address */
18b21a2f
NF		 1003 target_ulong reserve_addr;
1004 /* Reservation value */
1005 target_ulong reserve_val;
9c294d5a 1006 target_ulong reserve_val2;
3fc6c082
FB		 1007
1008 /* Those ones are used in supervisor mode only */
79aceca5 1009 /* machine state register */
0411a972 1010 target_ulong msr;
3fc6c082 1011 /* temporary general purpose registers */
bd7d9a6d 1012 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
3fc6c082
FB		 1013
1014 /* Floating point execution context */
4ecc3190 1015 float_status fp_status;
3fc6c082
FB		 1016 /* floating point registers */
1017 float64 fpr[32];
1018 /* floating point status and control register */
30304420 1019 target_ulong fpscr;
4ecc3190 1020
cb2dbfc3
AJ		 1021 /* Next instruction pointer */
1022 target_ulong nip;
a316d335 1023
94bf2658
RH		 1024 /* High part of 128-bit helper return. */
1025 uint64_t retxh;
1026
ac9eb073
FB		 1027 int access_type; /* when a memory exception occurs, the access
1028 type is stored here */
a541f297 1029
cb2dbfc3
AJ		 1030 CPU_COMMON
1031
f2e63a42
JM		 1032 /* MMU context - only relevant for full system emulation */
1033#if !defined(CONFIG_USER_ONLY)
1034#if defined(TARGET_PPC64)
f2e63a42 1035 /* PowerPC 64 SLB area */
d83af167 1036 ppc_slb_t slb[MAX_SLB_ENTRIES];
cd0c6f47 1037 /* tcg TLB needs flush (deferred slb inval instruction typically) */
f2e63a42 1038#endif
3fc6c082 1039 /* segment registers */
74d37793 1040 target_ulong sr[32];
3fc6c082 1041 /* BATs */
a90db158 1042 uint32_t nb_BATs;
3fc6c082
FB		 1043 target_ulong DBAT[2][8];
1044 target_ulong IBAT[2][8];
01662f3e 1045 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
a90db158 1046 int32_t nb_tlb; /* Total number of TLB */
f2e63a42
JM		 1047 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1048 int nb_ways; /* Number of ways in the TLB set */
1049 int last_way; /* Last used way used to allocate TLB in a LRU way */
1050 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1051 int nb_pids; /* Number of available PID registers */
1c53accc
AG		 1052 int tlb_type; /* Type of TLB we're dealing with */
1053 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
f2e63a42
JM		 1054 /* 403 dedicated access protection registers */
1055 target_ulong pb[4];
93dd5e85
SW		 1056 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1057 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
c5a8d8f3 1058 uint32_t tlb_need_flush; /* Delayed flush needed */
a8a6d53e 1059#define TLB_NEED_LOCAL_FLUSH 0x1
d76ab5e1 1060#define TLB_NEED_GLOBAL_FLUSH 0x2
f2e63a42 1061#endif
9fddaa0c 1062
3fc6c082
FB		 1063 /* Other registers */
1064 /* Special purpose registers */
1065 target_ulong spr[1024];
c227f099 1066 ppc_spr_t spr_cb[1024];
3fc6c082 1067 /* Altivec registers */
c227f099 1068 ppc_avr_t avr[32];
3fc6c082 1069 uint32_t vscr;
30304420
DG		 1070 /* VSX registers */
1071 uint64_t vsr[32];
d9bce9d9 1072 /* SPE registers */
2231ef10 1073 uint64_t spe_acc;
d9bce9d9 1074 uint32_t spe_fscr;
fbd265b6
AJ		 1075 /* SPE and Altivec can share a status since they will never be used
1076 * simultaneously */
1077 float_status vec_status;
3fc6c082
FB		 1078
1079 /* Internal devices resources */
9fddaa0c 1080 /* Time base and decrementer */
c227f099 1081 ppc_tb_t *tb_env;
3fc6c082 1082 /* Device control registers */
c227f099 1083 ppc_dcr_t *dcr_env;
3fc6c082 1084
d63001d1
JM		 1085 int dcache_line_size;
1086 int icache_line_size;
1087
3fc6c082
FB		 1088 /* Those resources are used during exception processing */
1089 /* CPU model definition */
a750fc0b 1090 target_ulong msr_mask;
c227f099
AL		 1091 powerpc_mmu_t mmu_model;
1092 powerpc_excp_t excp_model;
1093 powerpc_input_t bus_model;
237c0af0 1094 int bfd_mach;
3fc6c082 1095 uint32_t flags;
c29b735c 1096 uint64_t insns_flags;
a5858d7a 1097 uint64_t insns_flags2;
4656e1f0 1098#if defined(TARGET_PPC64)
912acdf4
BH		 1099 ppc_slb_t vrma_slb;
1100 target_ulong rmls;
4656e1f0 1101#endif
3fc6c082 1102
3fc6c082 1103 int error_code;
47103572 1104 uint32_t pending_interrupts;
e9df014c 1105#if !defined(CONFIG_USER_ONLY)
4abf79a4 1106 /* This is the IRQ controller, which is implementation dependent
e9df014c
JM		 1107 * and only relevant when emulating a complete machine.
1108 */
1109 uint32_t irq_input_state;
1110 void **irq_inputs;
e1833e1f
JM		 1111 /* Exception vectors */
1112 target_ulong excp_vectors[POWERPC_EXCP_NB];
1113 target_ulong excp_prefix;
1114 target_ulong ivor_mask;
1115 target_ulong ivpr_mask;
d63001d1 1116 target_ulong hreset_vector;
68c2dd70
AG		 1117 hwaddr mpic_iack;
1118 /* true when the external proxy facility mode is enabled */
1119 bool mpic_proxy;
932ccbdd
BH		 1120 /* set when the processor has an HV mode, thus HV priv
1121 * instructions and SPRs are diallowed if MSR:HV is 0
1122 */
1123 bool has_hv_mode;
7778a575
BH		 1124 /* On P7/P8, set when in PM state, we need to handle resume
1125 * in a special way (such as routing some resume causes to
1126 * 0x100), so flag this here.
1127 */
1128 bool in_pm_state;
e9df014c 1129#endif
3fc6c082
FB		 1130
1131 /* Those resources are used only during code translation */
3fc6c082 1132 /* opcode handlers */
b048960f 1133 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
3fc6c082 1134
5cbdb3a3 1135 /* Those resources are used only in QEMU core */
056401ea 1136 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
4abf79a4 1137 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
9fb04491
BH		 1138 int immu_idx; /* precomputed MMU index to speed up insn access */
1139 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
3fc6c082 1140
9fddaa0c 1141 /* Power management */
cd346349 1142 int (*check_pow)(CPUPPCState *env);
a541f297 1143
2c50e26e
EI		 1144#if !defined(CONFIG_USER_ONLY)
1145 void *load_info; /* Holds boot loading state. */
1146#endif
ddd1055b
FC		 1147
1148 /* booke timers */
1149
1150 /* Specifies bit locations of the Time Base used to signal a fixed timer
1151 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1152 *
1153 * 0 selects the least significant bit.
1154 * 63 selects the most significant bit.
1155 */
1156 uint8_t fit_period[4];
1157 uint8_t wdt_period[4];
80b3f79b
AK		 1158
1159 /* Transactional memory state */
1160 target_ulong tm_gpr[32];
1161 ppc_avr_t tm_vsr[64];
1162 uint64_t tm_cr;
1163 uint64_t tm_lr;
1164 uint64_t tm_ctr;
1165 uint64_t tm_fpscr;
1166 uint64_t tm_amr;
1167 uint64_t tm_ppr;
1168 uint64_t tm_vrsave;
1169 uint32_t tm_vscr;
1170 uint64_t tm_dscr;
1171 uint64_t tm_tar;
3fc6c082 1172};
79aceca5 1173
ddd1055b
FC		 1174#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1175do { \
1176 env->fit_period[0] = (a_); \
1177 env->fit_period[1] = (b_); \
1178 env->fit_period[2] = (c_); \
1179 env->fit_period[3] = (d_); \
1180 } while (0)
1181
1182#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1183do { \
1184 env->wdt_period[0] = (a_); \
1185 env->wdt_period[1] = (b_); \
1186 env->wdt_period[2] = (c_); \
1187 env->wdt_period[3] = (d_); \
1188 } while (0)
1189
1d1be34d
DG		 1190typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1191typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
1192
2d34fe39
PB		 1193/**
1194 * PowerPCCPU:
1195 * @env: #CPUPPCState
81210c20 1196 * @vcpu_id: vCPU identifier given to KVM
d6e166c0 1197 * @compat_pvr: Current logical PVR, zero if in "raw" mode
2d34fe39
PB		 1198 *
1199 * A PowerPC CPU.
1200 */
1201struct PowerPCCPU {
1202 /*< private >*/
1203 CPUState parent_obj;
1204 /*< public >*/
1205
1206 CPUPPCState env;
81210c20 1207 int vcpu_id;
d6e166c0 1208 uint32_t compat_pvr;
1d1be34d 1209 PPCVirtualHypervisor *vhyp;
ad5d1add 1210 Object *intc;
7388efaf 1211 void *machine_data;
15f8b142 1212 int32_t node_id; /* NUMA node this CPU belongs to */
b07c59f7 1213 PPCHash64Options *hash64_opts;
16a2497b 1214
146c11f1
DG		 1215 /* Fields related to migration compatibility hacks */
1216 bool pre_2_8_migration;
16a2497b
DG		 1217 target_ulong mig_msr_mask;
1218 uint64_t mig_insns_flags;
1219 uint64_t mig_insns_flags2;
1220 uint32_t mig_nb_BATs;
d5fc133e 1221 bool pre_2_10_migration;
d8c0c7af 1222 bool pre_3_0_migration;
67d7d66f 1223 int32_t mig_slb_nr;
2d34fe39
PB		 1224};
1225
1226static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
1227{
1228 return container_of(env, PowerPCCPU, env);
1229}
1230
1231#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
1232
1233#define ENV_OFFSET offsetof(PowerPCCPU, env)
1234
1235PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1236PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
e9edd931 1237PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
2d34fe39 1238
1d1be34d
DG		 1239struct PPCVirtualHypervisor {
1240 Object parent;
1241};
1242
1243struct PPCVirtualHypervisorClass {
1244 InterfaceClass parent;
1245 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
e57ca75c
DG		 1246 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1247 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1248 hwaddr ptex, int n);
1249 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1250 const ppc_hash_pte64_t *hptes,
1251 hwaddr ptex, int n);
1252 void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1253 uint64_t pte0, uint64_t pte1);
9861bb3e 1254 uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
1ec26c75 1255 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
1d1be34d
DG		 1256};
1257
1258#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1259#define PPC_VIRTUAL_HYPERVISOR(obj) \
1260 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1261#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1262 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1263 TYPE_PPC_VIRTUAL_HYPERVISOR)
1264#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1265 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1266 TYPE_PPC_VIRTUAL_HYPERVISOR)
1267
2d34fe39
PB		 1268void ppc_cpu_do_interrupt(CPUState *cpu);
1269bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
1270void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
1271 int flags);
1272void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
1273 fprintf_function cpu_fprintf, int flags);
2d34fe39
PB		 1274hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1275int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1276int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1277int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1278int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
1279int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1280 int cpuid, void *opaque);
356bb70e
MN		 1281int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1282 int cpuid, void *opaque);
2d34fe39
PB		 1283#ifndef CONFIG_USER_ONLY
1284void ppc_cpu_do_system_reset(CPUState *cs);
1285extern const struct VMStateDescription vmstate_ppc_cpu;
1286#endif
1d0cb67d 1287
3fc6c082 1288/*****************************************************************************/
2e70f6ef 1289void ppc_translate_init(void);
79aceca5
FB		 1290/* you can call this signal handler from your SIGBUS and SIGSEGV
1291 signal handlers to inform the virtual CPU of exceptions. non zero
1292 is returned if the signal was handled by the virtual CPU. */
36081602
JM		 1293int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1294 void *puc);
cc8eae8a 1295#if defined(CONFIG_USER_ONLY)
98670d47 1296int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
7510454e 1297 int mmu_idx);
cc8eae8a 1298#endif
a541f297 1299
76a66253 1300#if !defined(CONFIG_USER_ONLY)
45d827d2 1301void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
4a7518e0 1302void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
12de9a39 1303#endif /* !defined(CONFIG_USER_ONLY) */
0411a972 1304void ppc_store_msr (CPUPPCState *env, target_ulong value);
3fc6c082 1305
9a78eead 1306void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
aaed909a 1307
9fddaa0c
FB		 1308/* Time-base and decrementer management */
1309#ifndef NO_CPU_IO_DEFS
e3ea6529 1310uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
9fddaa0c
FB		 1311uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1312void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1313void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
b711de95 1314uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
a062e36c
JM		 1315uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1316void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1317void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
e81a982a 1318bool ppc_decr_clear_on_delivery(CPUPPCState *env);
9fddaa0c
FB		 1319uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1320void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
58a7d328
JM		 1321uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1322void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1323uint64_t cpu_ppc_load_purr (CPUPPCState *env);
d9bce9d9
JM		 1324uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1325uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1326#if !defined(CONFIG_USER_ONLY)
1327void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1328void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1329target_ulong load_40x_pit (CPUPPCState *env);
1330void store_40x_pit (CPUPPCState *env, target_ulong val);
8ecc7913 1331void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
c294fc58 1332void store_40x_sler (CPUPPCState *env, uint32_t val);
d9bce9d9
JM		 1333void store_booke_tcr (CPUPPCState *env, target_ulong val);
1334void store_booke_tsr (CPUPPCState *env, target_ulong val);
0a032cbe 1335void ppc_tlb_invalidate_all (CPUPPCState *env);
daf4f96e 1336void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
da20aed1 1337void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
d9bce9d9 1338#endif
9fddaa0c 1339#endif
79aceca5 1340
d6478bc7
FC		 1341void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1342
636aa200 1343static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1344{
1345 uint64_t gprv;
1346
1347 gprv = env->gpr[gprn];
6b542af7
JM		 1348 if (env->flags & POWERPC_FLAG_SPE) {
1349 /* If the CPU implements the SPE extension, we have to get the
1350 * high bits of the GPR from the gprh storage area
1351 */
1352 gprv &= 0xFFFFFFFFULL;
1353 gprv |= (uint64_t)env->gprh[gprn] << 32;
1354 }
6b542af7
JM		 1355
1356 return gprv;
1357}
1358
2e719ba3 1359/* Device control registers */
73b01960
AG		 1360int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1361int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1362
c9137065
IM		 1363#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1364#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
0dacec87 1365#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
c9137065 1366
9467d44c 1367#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1368#define cpu_list ppc_cpu_list
9467d44c 1369
6ebbf390 1370/* MMU modes definitions */
6ebbf390 1371#define MMU_USER_IDX 0
97ed5ccd 1372static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
6ebbf390 1373{
9fb04491 1374 return ifetch ? env->immu_idx : env->dmmu_idx;
6ebbf390
JM		 1375}
1376
9d6f1065
DG		 1377/* Compatibility modes */
1378#if defined(TARGET_PPC64)
9d2179d6
DG		 1379bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1380 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
ad99d04c
DG		 1381bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1382 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1383
9d6f1065 1384void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
ad99d04c 1385
f6f242c7
DG		 1386#if !defined(CONFIG_USER_ONLY)
1387void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1388#endif
abbc1247 1389int ppc_compat_max_vthreads(PowerPCCPU *cpu);
7843c0d6
DG		 1390void ppc_compat_add_property(Object *obj, const char *name,
1391 uint32_t *compat_pvr, const char *basedesc,
1392 Error **errp);
9d6f1065
DG		 1393#endif /* defined(TARGET_PPC64) */
1394
022c62cb 1395#include "exec/cpu-all.h"
79aceca5 1396
3fc6c082 1397/*****************************************************************************/
e1571908 1398/* CRF definitions */
efa73196
ND		 1399#define CRF_LT_BIT 3
1400#define CRF_GT_BIT 2
1401#define CRF_EQ_BIT 1
1402#define CRF_SO_BIT 0
1403#define CRF_LT (1 << CRF_LT_BIT)
1404#define CRF_GT (1 << CRF_GT_BIT)
1405#define CRF_EQ (1 << CRF_EQ_BIT)
1406#define CRF_SO (1 << CRF_SO_BIT)
1407/* For SPE extensions */
1408#define CRF_CH (1 << CRF_LT_BIT)
1409#define CRF_CL (1 << CRF_GT_BIT)
1410#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1411#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
e1571908
AJ		 1412
1413/* XER definitions */
3d7b417e
AJ		 1414#define XER_SO 31
1415#define XER_OV 30
1416#define XER_CA 29
dd09c361
ND		 1417#define XER_OV32 19
1418#define XER_CA32 18
3d7b417e
AJ		 1419#define XER_CMP 8
1420#define XER_BC 0
da91a00f
RH		 1421#define xer_so (env->so)
1422#define xer_ov (env->ov)
1423#define xer_ca (env->ca)
dd09c361
ND		 1424#define xer_ov32 (env->ov)
1425#define xer_ca32 (env->ca)
3d7b417e
AJ		 1426#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1427#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1428
3fc6c082 1429/* SPR definitions */
80d11f44
JM		 1430#define SPR_MQ (0x000)
1431#define SPR_XER (0x001)
1432#define SPR_601_VRTCU (0x004)
1433#define SPR_601_VRTCL (0x005)
1434#define SPR_601_UDECR (0x006)
1435#define SPR_LR (0x008)
1436#define SPR_CTR (0x009)
f244115c 1437#define SPR_UAMR (0x00D)
697ab892 1438#define SPR_DSCR (0x011)
80d11f44
JM		 1439#define SPR_DSISR (0x012)
1440#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1441#define SPR_601_RTCU (0x014)
1442#define SPR_601_RTCL (0x015)
1443#define SPR_DECR (0x016)
1444#define SPR_SDR1 (0x019)
1445#define SPR_SRR0 (0x01A)
1446#define SPR_SRR1 (0x01B)
697ab892 1447#define SPR_CFAR (0x01C)
80d11f44 1448#define SPR_AMR (0x01D)
9c1cf38d 1449#define SPR_ACOP (0x01F)
80d11f44 1450#define SPR_BOOKE_PID (0x030)
9c1cf38d 1451#define SPR_BOOKS_PID (0x030)
80d11f44
JM		 1452#define SPR_BOOKE_DECAR (0x036)
1453#define SPR_BOOKE_CSRR0 (0x03A)
1454#define SPR_BOOKE_CSRR1 (0x03B)
1455#define SPR_BOOKE_DEAR (0x03D)
a6eabb9e 1456#define SPR_IAMR (0x03D)
80d11f44
JM		 1457#define SPR_BOOKE_ESR (0x03E)
1458#define SPR_BOOKE_IVPR (0x03F)
1459#define SPR_MPC_EIE (0x050)
1460#define SPR_MPC_EID (0x051)
1461#define SPR_MPC_NRI (0x052)
cdcdda27
AK		 1462#define SPR_TFHAR (0x080)
1463#define SPR_TFIAR (0x081)
1464#define SPR_TEXASR (0x082)
1465#define SPR_TEXASRU (0x083)
0bfe9299 1466#define SPR_UCTRL (0x088)
650f3287 1467#define SPR_TIDR (0x090)
80d11f44
JM		 1468#define SPR_MPC_CMPA (0x090)
1469#define SPR_MPC_CMPB (0x091)
1470#define SPR_MPC_CMPC (0x092)
1471#define SPR_MPC_CMPD (0x093)
1472#define SPR_MPC_ECR (0x094)
1473#define SPR_MPC_DER (0x095)
1474#define SPR_MPC_COUNTA (0x096)
1475#define SPR_MPC_COUNTB (0x097)
0bfe9299 1476#define SPR_CTRL (0x098)
80d11f44
JM		 1477#define SPR_MPC_CMPE (0x098)
1478#define SPR_MPC_CMPF (0x099)
7019cb3d 1479#define SPR_FSCR (0x099)
80d11f44
JM		 1480#define SPR_MPC_CMPG (0x09A)
1481#define SPR_MPC_CMPH (0x09B)
1482#define SPR_MPC_LCTRL1 (0x09C)
1483#define SPR_MPC_LCTRL2 (0x09D)
f80872e2 1484#define SPR_UAMOR (0x09D)
80d11f44
JM		 1485#define SPR_MPC_ICTRL (0x09E)
1486#define SPR_MPC_BAR (0x09F)
d6f1445f 1487#define SPR_PSPB (0x09F)
1488270e
BH		 1488#define SPR_DAWR (0x0B4)
1489#define SPR_RPR (0x0BA)
eb5ceb4d 1490#define SPR_CIABR (0x0BB)
1488270e
BH		 1491#define SPR_DAWRX (0x0BC)
1492#define SPR_HFSCR (0x0BE)
80d11f44
JM		 1493#define SPR_VRSAVE (0x100)
1494#define SPR_USPRG0 (0x100)
1495#define SPR_USPRG1 (0x101)
1496#define SPR_USPRG2 (0x102)
1497#define SPR_USPRG3 (0x103)
1498#define SPR_USPRG4 (0x104)
1499#define SPR_USPRG5 (0x105)
1500#define SPR_USPRG6 (0x106)
1501#define SPR_USPRG7 (0x107)
1502#define SPR_VTBL (0x10C)
1503#define SPR_VTBU (0x10D)
1504#define SPR_SPRG0 (0x110)
1505#define SPR_SPRG1 (0x111)
1506#define SPR_SPRG2 (0x112)
1507#define SPR_SPRG3 (0x113)
1508#define SPR_SPRG4 (0x114)
1509#define SPR_SCOMC (0x114)
1510#define SPR_SPRG5 (0x115)
1511#define SPR_SCOMD (0x115)
1512#define SPR_SPRG6 (0x116)
1513#define SPR_SPRG7 (0x117)
1514#define SPR_ASR (0x118)
1515#define SPR_EAR (0x11A)
1516#define SPR_TBL (0x11C)
1517#define SPR_TBU (0x11D)
1518#define SPR_TBU40 (0x11E)
1519#define SPR_SVR (0x11E)
1520#define SPR_BOOKE_PIR (0x11E)
1521#define SPR_PVR (0x11F)
1522#define SPR_HSPRG0 (0x130)
1523#define SPR_BOOKE_DBSR (0x130)
1524#define SPR_HSPRG1 (0x131)
1525#define SPR_HDSISR (0x132)
1526#define SPR_HDAR (0x133)
90dc8812 1527#define SPR_BOOKE_EPCR (0x133)
9d52e907 1528#define SPR_SPURR (0x134)
80d11f44
JM		 1529#define SPR_BOOKE_DBCR0 (0x134)
1530#define SPR_IBCR (0x135)
1531#define SPR_PURR (0x135)
1532#define SPR_BOOKE_DBCR1 (0x135)
1533#define SPR_DBCR (0x136)
1534#define SPR_HDEC (0x136)
1535#define SPR_BOOKE_DBCR2 (0x136)
1536#define SPR_HIOR (0x137)
1537#define SPR_MBAR (0x137)
1538#define SPR_RMOR (0x138)
1539#define SPR_BOOKE_IAC1 (0x138)
1540#define SPR_HRMOR (0x139)
1541#define SPR_BOOKE_IAC2 (0x139)
1542#define SPR_HSRR0 (0x13A)
1543#define SPR_BOOKE_IAC3 (0x13A)
1544#define SPR_HSRR1 (0x13B)
1545#define SPR_BOOKE_IAC4 (0x13B)
80d11f44 1546#define SPR_BOOKE_DAC1 (0x13C)
1488270e 1547#define SPR_MMCRH (0x13C)
80d11f44
JM		 1548#define SPR_DABR2 (0x13D)
1549#define SPR_BOOKE_DAC2 (0x13D)
1488270e 1550#define SPR_TFMR (0x13D)
80d11f44 1551#define SPR_BOOKE_DVC1 (0x13E)
6475c9f0 1552#define SPR_LPCR (0x13E)
80d11f44 1553#define SPR_BOOKE_DVC2 (0x13F)
1488270e 1554#define SPR_LPIDR (0x13F)
80d11f44 1555#define SPR_BOOKE_TSR (0x150)
1488270e
BH		 1556#define SPR_HMER (0x150)
1557#define SPR_HMEER (0x151)
6d9412ea 1558#define SPR_PCR (0x152)
1488270e 1559#define SPR_BOOKE_LPIDR (0x152)
80d11f44 1560#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1561#define SPR_BOOKE_TLB0PS (0x158)
1562#define SPR_BOOKE_TLB1PS (0x159)
1563#define SPR_BOOKE_TLB2PS (0x15A)
1564#define SPR_BOOKE_TLB3PS (0x15B)
1488270e 1565#define SPR_AMOR (0x15D)
84755ed5 1566#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1567#define SPR_BOOKE_IVOR0 (0x190)
1568#define SPR_BOOKE_IVOR1 (0x191)
1569#define SPR_BOOKE_IVOR2 (0x192)
1570#define SPR_BOOKE_IVOR3 (0x193)
1571#define SPR_BOOKE_IVOR4 (0x194)
1572#define SPR_BOOKE_IVOR5 (0x195)
1573#define SPR_BOOKE_IVOR6 (0x196)
1574#define SPR_BOOKE_IVOR7 (0x197)
1575#define SPR_BOOKE_IVOR8 (0x198)
1576#define SPR_BOOKE_IVOR9 (0x199)
1577#define SPR_BOOKE_IVOR10 (0x19A)
1578#define SPR_BOOKE_IVOR11 (0x19B)
1579#define SPR_BOOKE_IVOR12 (0x19C)
1580#define SPR_BOOKE_IVOR13 (0x19D)
1581#define SPR_BOOKE_IVOR14 (0x19E)
1582#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1583#define SPR_BOOKE_IVOR38 (0x1B0)
1584#define SPR_BOOKE_IVOR39 (0x1B1)
1585#define SPR_BOOKE_IVOR40 (0x1B2)
1586#define SPR_BOOKE_IVOR41 (0x1B3)
1587#define SPR_BOOKE_IVOR42 (0x1B4)
45eb5611
AG		 1588#define SPR_BOOKE_GIVOR2 (0x1B8)
1589#define SPR_BOOKE_GIVOR3 (0x1B9)
1590#define SPR_BOOKE_GIVOR4 (0x1BA)
1591#define SPR_BOOKE_GIVOR8 (0x1BB)
1592#define SPR_BOOKE_GIVOR13 (0x1BC)
1593#define SPR_BOOKE_GIVOR14 (0x1BD)
d1a721ab 1594#define SPR_TIR (0x1BE)
4a7518e0 1595#define SPR_PTCR (0x1D0)
80d11f44
JM		 1596#define SPR_BOOKE_SPEFSCR (0x200)
1597#define SPR_Exxx_BBEAR (0x201)
1598#define SPR_Exxx_BBTAR (0x202)
1599#define SPR_Exxx_L1CFG0 (0x203)
d2ea2bf7 1600#define SPR_Exxx_L1CFG1 (0x204)
80d11f44
JM		 1601#define SPR_Exxx_NPIDR (0x205)
1602#define SPR_ATBL (0x20E)
1603#define SPR_ATBU (0x20F)
1604#define SPR_IBAT0U (0x210)
1605#define SPR_BOOKE_IVOR32 (0x210)
1606#define SPR_RCPU_MI_GRA (0x210)
1607#define SPR_IBAT0L (0x211)
1608#define SPR_BOOKE_IVOR33 (0x211)
1609#define SPR_IBAT1U (0x212)
1610#define SPR_BOOKE_IVOR34 (0x212)
1611#define SPR_IBAT1L (0x213)
1612#define SPR_BOOKE_IVOR35 (0x213)
1613#define SPR_IBAT2U (0x214)
1614#define SPR_BOOKE_IVOR36 (0x214)
1615#define SPR_IBAT2L (0x215)
1616#define SPR_BOOKE_IVOR37 (0x215)
1617#define SPR_IBAT3U (0x216)
1618#define SPR_IBAT3L (0x217)
1619#define SPR_DBAT0U (0x218)
1620#define SPR_RCPU_L2U_GRA (0x218)
1621#define SPR_DBAT0L (0x219)
1622#define SPR_DBAT1U (0x21A)
1623#define SPR_DBAT1L (0x21B)
1624#define SPR_DBAT2U (0x21C)
1625#define SPR_DBAT2L (0x21D)
1626#define SPR_DBAT3U (0x21E)
1627#define SPR_DBAT3L (0x21F)
1628#define SPR_IBAT4U (0x230)
1629#define SPR_RPCU_BBCMCR (0x230)
1630#define SPR_MPC_IC_CST (0x230)
1631#define SPR_Exxx_CTXCR (0x230)
1632#define SPR_IBAT4L (0x231)
1633#define SPR_MPC_IC_ADR (0x231)
1634#define SPR_Exxx_DBCR3 (0x231)
1635#define SPR_IBAT5U (0x232)
1636#define SPR_MPC_IC_DAT (0x232)
1637#define SPR_Exxx_DBCNT (0x232)
1638#define SPR_IBAT5L (0x233)
1639#define SPR_IBAT6U (0x234)
1640#define SPR_IBAT6L (0x235)
1641#define SPR_IBAT7U (0x236)
1642#define SPR_IBAT7L (0x237)
1643#define SPR_DBAT4U (0x238)
1644#define SPR_RCPU_L2U_MCR (0x238)
1645#define SPR_MPC_DC_CST (0x238)
1646#define SPR_Exxx_ALTCTXCR (0x238)
1647#define SPR_DBAT4L (0x239)
1648#define SPR_MPC_DC_ADR (0x239)
1649#define SPR_DBAT5U (0x23A)
1650#define SPR_BOOKE_MCSRR0 (0x23A)
1651#define SPR_MPC_DC_DAT (0x23A)
1652#define SPR_DBAT5L (0x23B)
1653#define SPR_BOOKE_MCSRR1 (0x23B)
1654#define SPR_DBAT6U (0x23C)
1655#define SPR_BOOKE_MCSR (0x23C)
1656#define SPR_DBAT6L (0x23D)
1657#define SPR_Exxx_MCAR (0x23D)
1658#define SPR_DBAT7U (0x23E)
1659#define SPR_BOOKE_DSRR0 (0x23E)
1660#define SPR_DBAT7L (0x23F)
1661#define SPR_BOOKE_DSRR1 (0x23F)
1662#define SPR_BOOKE_SPRG8 (0x25C)
1663#define SPR_BOOKE_SPRG9 (0x25D)
1664#define SPR_BOOKE_MAS0 (0x270)
1665#define SPR_BOOKE_MAS1 (0x271)
1666#define SPR_BOOKE_MAS2 (0x272)
1667#define SPR_BOOKE_MAS3 (0x273)
1668#define SPR_BOOKE_MAS4 (0x274)
1669#define SPR_BOOKE_MAS5 (0x275)
1670#define SPR_BOOKE_MAS6 (0x276)
1671#define SPR_BOOKE_PID1 (0x279)
1672#define SPR_BOOKE_PID2 (0x27A)
1673#define SPR_MPC_DPDR (0x280)
1674#define SPR_MPC_IMMR (0x288)
1675#define SPR_BOOKE_TLB0CFG (0x2B0)
1676#define SPR_BOOKE_TLB1CFG (0x2B1)
1677#define SPR_BOOKE_TLB2CFG (0x2B2)
1678#define SPR_BOOKE_TLB3CFG (0x2B3)
1679#define SPR_BOOKE_EPR (0x2BE)
1680#define SPR_PERF0 (0x300)
1681#define SPR_RCPU_MI_RBA0 (0x300)
1682#define SPR_MPC_MI_CTR (0x300)
14646457 1683#define SPR_POWER_USIER (0x300)
80d11f44
JM		 1684#define SPR_PERF1 (0x301)
1685#define SPR_RCPU_MI_RBA1 (0x301)
70c53407 1686#define SPR_POWER_UMMCR2 (0x301)
80d11f44
JM		 1687#define SPR_PERF2 (0x302)
1688#define SPR_RCPU_MI_RBA2 (0x302)
1689#define SPR_MPC_MI_AP (0x302)
75b9c321 1690#define SPR_POWER_UMMCRA (0x302)
80d11f44
JM		 1691#define SPR_PERF3 (0x303)
1692#define SPR_RCPU_MI_RBA3 (0x303)
1693#define SPR_MPC_MI_EPN (0x303)
fd51ff63 1694#define SPR_POWER_UPMC1 (0x303)
80d11f44 1695#define SPR_PERF4 (0x304)
fd51ff63 1696#define SPR_POWER_UPMC2 (0x304)
80d11f44
JM		 1697#define SPR_PERF5 (0x305)
1698#define SPR_MPC_MI_TWC (0x305)
fd51ff63 1699#define SPR_POWER_UPMC3 (0x305)
80d11f44
JM		 1700#define SPR_PERF6 (0x306)
1701#define SPR_MPC_MI_RPN (0x306)
fd51ff63 1702#define SPR_POWER_UPMC4 (0x306)
80d11f44 1703#define SPR_PERF7 (0x307)
fd51ff63 1704#define SPR_POWER_UPMC5 (0x307)
80d11f44
JM		 1705#define SPR_PERF8 (0x308)
1706#define SPR_RCPU_L2U_RBA0 (0x308)
1707#define SPR_MPC_MD_CTR (0x308)
fd51ff63 1708#define SPR_POWER_UPMC6 (0x308)
80d11f44
JM		 1709#define SPR_PERF9 (0x309)
1710#define SPR_RCPU_L2U_RBA1 (0x309)
1711#define SPR_MPC_MD_CASID (0x309)
c36c97f8 1712#define SPR_970_UPMC7 (0X309)
80d11f44
JM		 1713#define SPR_PERFA (0x30A)
1714#define SPR_RCPU_L2U_RBA2 (0x30A)
1715#define SPR_MPC_MD_AP (0x30A)
c36c97f8 1716#define SPR_970_UPMC8 (0X30A)
80d11f44
JM		 1717#define SPR_PERFB (0x30B)
1718#define SPR_RCPU_L2U_RBA3 (0x30B)
1719#define SPR_MPC_MD_EPN (0x30B)
fd51ff63 1720#define SPR_POWER_UMMCR0 (0X30B)
80d11f44
JM		 1721#define SPR_PERFC (0x30C)
1722#define SPR_MPC_MD_TWB (0x30C)
fd51ff63 1723#define SPR_POWER_USIAR (0X30C)
80d11f44
JM		 1724#define SPR_PERFD (0x30D)
1725#define SPR_MPC_MD_TWC (0x30D)
fd51ff63 1726#define SPR_POWER_USDAR (0X30D)
80d11f44
JM		 1727#define SPR_PERFE (0x30E)
1728#define SPR_MPC_MD_RPN (0x30E)
fd51ff63 1729#define SPR_POWER_UMMCR1 (0X30E)
80d11f44
JM		 1730#define SPR_PERFF (0x30F)
1731#define SPR_MPC_MD_TW (0x30F)
1732#define SPR_UPERF0 (0x310)
14646457 1733#define SPR_POWER_SIER (0x310)
80d11f44 1734#define SPR_UPERF1 (0x311)
70c53407 1735#define SPR_POWER_MMCR2 (0x311)
80d11f44 1736#define SPR_UPERF2 (0x312)
75b9c321 1737#define SPR_POWER_MMCRA (0X312)
80d11f44 1738#define SPR_UPERF3 (0x313)
fd51ff63 1739#define SPR_POWER_PMC1 (0X313)
80d11f44 1740#define SPR_UPERF4 (0x314)
fd51ff63 1741#define SPR_POWER_PMC2 (0X314)
80d11f44 1742#define SPR_UPERF5 (0x315)
fd51ff63 1743#define SPR_POWER_PMC3 (0X315)
80d11f44 1744#define SPR_UPERF6 (0x316)
fd51ff63 1745#define SPR_POWER_PMC4 (0X316)
80d11f44 1746#define SPR_UPERF7 (0x317)
fd51ff63 1747#define SPR_POWER_PMC5 (0X317)
80d11f44 1748#define SPR_UPERF8 (0x318)
fd51ff63 1749#define SPR_POWER_PMC6 (0X318)
80d11f44 1750#define SPR_UPERF9 (0x319)
c36c97f8 1751#define SPR_970_PMC7 (0X319)
80d11f44 1752#define SPR_UPERFA (0x31A)
c36c97f8 1753#define SPR_970_PMC8 (0X31A)
80d11f44 1754#define SPR_UPERFB (0x31B)
fd51ff63 1755#define SPR_POWER_MMCR0 (0X31B)
80d11f44 1756#define SPR_UPERFC (0x31C)
fd51ff63 1757#define SPR_POWER_SIAR (0X31C)
80d11f44 1758#define SPR_UPERFD (0x31D)
fd51ff63 1759#define SPR_POWER_SDAR (0X31D)
80d11f44 1760#define SPR_UPERFE (0x31E)
fd51ff63 1761#define SPR_POWER_MMCR1 (0X31E)
80d11f44
JM		 1762#define SPR_UPERFF (0x31F)
1763#define SPR_RCPU_MI_RA0 (0x320)
1764#define SPR_MPC_MI_DBCAM (0x320)
4ee4a03b 1765#define SPR_BESCRS (0x320)
80d11f44
JM		 1766#define SPR_RCPU_MI_RA1 (0x321)
1767#define SPR_MPC_MI_DBRAM0 (0x321)
4ee4a03b 1768#define SPR_BESCRSU (0x321)
80d11f44
JM		 1769#define SPR_RCPU_MI_RA2 (0x322)
1770#define SPR_MPC_MI_DBRAM1 (0x322)
4ee4a03b 1771#define SPR_BESCRR (0x322)
80d11f44 1772#define SPR_RCPU_MI_RA3 (0x323)
4ee4a03b
AK		 1773#define SPR_BESCRRU (0x323)
1774#define SPR_EBBHR (0x324)
1775#define SPR_EBBRR (0x325)
1776#define SPR_BESCR (0x326)
80d11f44
JM		 1777#define SPR_RCPU_L2U_RA0 (0x328)
1778#define SPR_MPC_MD_DBCAM (0x328)
1779#define SPR_RCPU_L2U_RA1 (0x329)
1780#define SPR_MPC_MD_DBRAM0 (0x329)
1781#define SPR_RCPU_L2U_RA2 (0x32A)
1782#define SPR_MPC_MD_DBRAM1 (0x32A)
1783#define SPR_RCPU_L2U_RA3 (0x32B)
60511041 1784#define SPR_TAR (0x32F)
21a558be 1785#define SPR_IC (0x350)
3ba55e39 1786#define SPR_VTB (0x351)
1488270e 1787#define SPR_MMCRC (0x353)
b8af5b2d 1788#define SPR_PSSCR (0x357)
80d11f44
JM		 1789#define SPR_440_INV0 (0x370)
1790#define SPR_440_INV1 (0x371)
1791#define SPR_440_INV2 (0x372)
1792#define SPR_440_INV3 (0x373)
1793#define SPR_440_ITV0 (0x374)
1794#define SPR_440_ITV1 (0x375)
1795#define SPR_440_ITV2 (0x376)
1796#define SPR_440_ITV3 (0x377)
1797#define SPR_440_CCR1 (0x378)
14646457
BH		 1798#define SPR_TACR (0x378)
1799#define SPR_TCSCR (0x379)
1800#define SPR_CSIGR (0x37a)
80d11f44 1801#define SPR_DCRIPR (0x37B)
14646457
BH		 1802#define SPR_POWER_SPMC1 (0x37C)
1803#define SPR_POWER_SPMC2 (0x37D)
70c53407 1804#define SPR_POWER_MMCRS (0x37E)
9c1cf38d 1805#define SPR_WORT (0x37F)
80d11f44 1806#define SPR_PPR (0x380)
bd928eba 1807#define SPR_750_GQR0 (0x390)
80d11f44 1808#define SPR_440_DNV0 (0x390)
bd928eba 1809#define SPR_750_GQR1 (0x391)
80d11f44 1810#define SPR_440_DNV1 (0x391)
bd928eba 1811#define SPR_750_GQR2 (0x392)
80d11f44 1812#define SPR_440_DNV2 (0x392)
bd928eba 1813#define SPR_750_GQR3 (0x393)
80d11f44 1814#define SPR_440_DNV3 (0x393)
bd928eba 1815#define SPR_750_GQR4 (0x394)
80d11f44 1816#define SPR_440_DTV0 (0x394)
bd928eba 1817#define SPR_750_GQR5 (0x395)
80d11f44 1818#define SPR_440_DTV1 (0x395)
bd928eba 1819#define SPR_750_GQR6 (0x396)
80d11f44 1820#define SPR_440_DTV2 (0x396)
bd928eba 1821#define SPR_750_GQR7 (0x397)
80d11f44 1822#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1823#define SPR_750_THRM4 (0x398)
1824#define SPR_750CL_HID2 (0x398)
80d11f44 1825#define SPR_440_DVLIM (0x398)
bd928eba 1826#define SPR_750_WPAR (0x399)
80d11f44 1827#define SPR_440_IVLIM (0x399)
1488270e 1828#define SPR_TSCR (0x399)
bd928eba
JM		 1829#define SPR_750_DMAU (0x39A)
1830#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1831#define SPR_440_RSTCFG (0x39B)
1832#define SPR_BOOKE_DCDBTRL (0x39C)
1833#define SPR_BOOKE_DCDBTRH (0x39D)
1834#define SPR_BOOKE_ICDBTRL (0x39E)
1835#define SPR_BOOKE_ICDBTRH (0x39F)
cb8b8bf8
AK		 1836#define SPR_74XX_UMMCR2 (0x3A0)
1837#define SPR_7XX_UPMC5 (0x3A1)
1838#define SPR_7XX_UPMC6 (0x3A2)
80d11f44 1839#define SPR_UBAMR (0x3A7)
cb8b8bf8
AK		 1840#define SPR_7XX_UMMCR0 (0x3A8)
1841#define SPR_7XX_UPMC1 (0x3A9)
1842#define SPR_7XX_UPMC2 (0x3AA)
1843#define SPR_7XX_USIAR (0x3AB)
1844#define SPR_7XX_UMMCR1 (0x3AC)
1845#define SPR_7XX_UPMC3 (0x3AD)
1846#define SPR_7XX_UPMC4 (0x3AE)
80d11f44
JM		 1847#define SPR_USDA (0x3AF)
1848#define SPR_40x_ZPR (0x3B0)
1849#define SPR_BOOKE_MAS7 (0x3B0)
cb8b8bf8
AK		 1850#define SPR_74XX_MMCR2 (0x3B0)
1851#define SPR_7XX_PMC5 (0x3B1)
80d11f44 1852#define SPR_40x_PID (0x3B1)
cb8b8bf8 1853#define SPR_7XX_PMC6 (0x3B2)
80d11f44 1854#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1855#define SPR_4xx_CCR0 (0x3B3)
1856#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1857#define SPR_405_IAC3 (0x3B4)
1858#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1859#define SPR_405_IAC4 (0x3B5)
80d11f44 1860#define SPR_405_DVC1 (0x3B6)
80d11f44 1861#define SPR_405_DVC2 (0x3B7)
80d11f44 1862#define SPR_BAMR (0x3B7)
cb8b8bf8
AK		 1863#define SPR_7XX_MMCR0 (0x3B8)
1864#define SPR_7XX_PMC1 (0x3B9)
80d11f44 1865#define SPR_40x_SGR (0x3B9)
cb8b8bf8 1866#define SPR_7XX_PMC2 (0x3BA)
80d11f44 1867#define SPR_40x_DCWR (0x3BA)
cb8b8bf8 1868#define SPR_7XX_SIAR (0x3BB)
80d11f44 1869#define SPR_405_SLER (0x3BB)
cb8b8bf8 1870#define SPR_7XX_MMCR1 (0x3BC)
80d11f44 1871#define SPR_405_SU0R (0x3BC)
80d11f44 1872#define SPR_401_SKR (0x3BC)
cb8b8bf8 1873#define SPR_7XX_PMC3 (0x3BD)
80d11f44 1874#define SPR_405_DBCR1 (0x3BD)
cb8b8bf8 1875#define SPR_7XX_PMC4 (0x3BE)
80d11f44 1876#define SPR_SDA (0x3BF)
80d11f44
JM		 1877#define SPR_403_VTBL (0x3CC)
1878#define SPR_403_VTBU (0x3CD)
1879#define SPR_DMISS (0x3D0)
1880#define SPR_DCMP (0x3D1)
1881#define SPR_HASH1 (0x3D2)
1882#define SPR_HASH2 (0x3D3)
1883#define SPR_BOOKE_ICDBDR (0x3D3)
1884#define SPR_TLBMISS (0x3D4)
1885#define SPR_IMISS (0x3D4)
1886#define SPR_40x_ESR (0x3D4)
1887#define SPR_PTEHI (0x3D5)
1888#define SPR_ICMP (0x3D5)
1889#define SPR_40x_DEAR (0x3D5)
1890#define SPR_PTELO (0x3D6)
1891#define SPR_RPA (0x3D6)
1892#define SPR_40x_EVPR (0x3D6)
1893#define SPR_L3PM (0x3D7)
1894#define SPR_403_CDBCR (0x3D7)
4e777442 1895#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1896#define SPR_TCR (0x3D8)
1897#define SPR_40x_TSR (0x3D8)
1898#define SPR_IBR (0x3DA)
1899#define SPR_40x_TCR (0x3DA)
1900#define SPR_ESASRR (0x3DB)
1901#define SPR_40x_PIT (0x3DB)
1902#define SPR_403_TBL (0x3DC)
1903#define SPR_403_TBU (0x3DD)
1904#define SPR_SEBR (0x3DE)
1905#define SPR_40x_SRR2 (0x3DE)
1906#define SPR_SER (0x3DF)
1907#define SPR_40x_SRR3 (0x3DF)
4e777442 1908#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1909#define SPR_L3ITCR1 (0x3E9)
1910#define SPR_L3ITCR2 (0x3EA)
1911#define SPR_L3ITCR3 (0x3EB)
1912#define SPR_HID0 (0x3F0)
1913#define SPR_40x_DBSR (0x3F0)
1914#define SPR_HID1 (0x3F1)
1915#define SPR_IABR (0x3F2)
1916#define SPR_40x_DBCR0 (0x3F2)
1917#define SPR_601_HID2 (0x3F2)
1918#define SPR_Exxx_L1CSR0 (0x3F2)
1919#define SPR_ICTRL (0x3F3)
1920#define SPR_HID2 (0x3F3)
bd928eba 1921#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1922#define SPR_Exxx_L1CSR1 (0x3F3)
1923#define SPR_440_DBDR (0x3F3)
1924#define SPR_LDSTDB (0x3F4)
bd928eba 1925#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1926#define SPR_40x_IAC1 (0x3F4)
1927#define SPR_MMUCSR0 (0x3F4)
ba881002 1928#define SPR_970_HID4 (0x3F4)
80d11f44 1929#define SPR_DABR (0x3F5)
3fc6c082 1930#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1931#define SPR_Exxx_BUCSR (0x3F5)
1932#define SPR_40x_IAC2 (0x3F5)
1933#define SPR_601_HID5 (0x3F5)
1934#define SPR_40x_DAC1 (0x3F6)
1935#define SPR_MSSCR0 (0x3F6)
1936#define SPR_970_HID5 (0x3F6)
1937#define SPR_MSSSR0 (0x3F7)
4e777442 1938#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1939#define SPR_DABRX (0x3F7)
1940#define SPR_40x_DAC2 (0x3F7)
1941#define SPR_MMUCFG (0x3F7)
1942#define SPR_LDSTCR (0x3F8)
1943#define SPR_L2PMCR (0x3F8)
bd928eba 1944#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1945#define SPR_Exxx_L1FINV0 (0x3F8)
1946#define SPR_L2CR (0x3F9)
80d11f44 1947#define SPR_L3CR (0x3FA)
bd928eba 1948#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1949#define SPR_IABR2 (0x3FA)
1950#define SPR_40x_DCCR (0x3FA)
1951#define SPR_ICTC (0x3FB)
1952#define SPR_40x_ICCR (0x3FB)
1953#define SPR_THRM1 (0x3FC)
1954#define SPR_403_PBL1 (0x3FC)
1955#define SPR_SP (0x3FD)
1956#define SPR_THRM2 (0x3FD)
1957#define SPR_403_PBU1 (0x3FD)
1958#define SPR_604_HID13 (0x3FD)
1959#define SPR_LT (0x3FE)
1960#define SPR_THRM3 (0x3FE)
1961#define SPR_RCPU_FPECR (0x3FE)
1962#define SPR_403_PBL2 (0x3FE)
1963#define SPR_PIR (0x3FF)
1964#define SPR_403_PBU2 (0x3FF)
1965#define SPR_601_HID15 (0x3FF)
1966#define SPR_604_HID15 (0x3FF)
1967#define SPR_E500_SVR (0x3FF)
79aceca5 1968
84755ed5
AG		 1969/* Disable MAS Interrupt Updates for Hypervisor */
1970#define EPCR_DMIUH (1 << 22)
1971/* Disable Guest TLB Management Instructions */
1972#define EPCR_DGTMI (1 << 23)
1973/* Guest Interrupt Computation Mode */
1974#define EPCR_GICM (1 << 24)
1975/* Interrupt Computation Mode */
1976#define EPCR_ICM (1 << 25)
1977/* Disable Embedded Hypervisor Debug */
1978#define EPCR_DUVD (1 << 26)
1979/* Instruction Storage Interrupt Directed to Guest State */
1980#define EPCR_ISIGS (1 << 27)
1981/* Data Storage Interrupt Directed to Guest State */
1982#define EPCR_DSIGS (1 << 28)
1983/* Instruction TLB Error Interrupt Directed to Guest State */
1984#define EPCR_ITLBGS (1 << 29)
1985/* Data TLB Error Interrupt Directed to Guest State */
1986#define EPCR_DTLBGS (1 << 30)
1987/* External Input Interrupt Directed to Guest State */
1988#define EPCR_EXTGS (1 << 31)
1989
ea71258d
AG		 1990#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1991#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1992#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1993#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1994#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1995
1996#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1997#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1998#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1999#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
2000#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
2001
bbc01ca7 2002/* HID0 bits */
1488270e
BH		 2003#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
2004#define HID0_DOZE (1 << 23) /* pre-2.06 */
2005#define HID0_NAP (1 << 22) /* pre-2.06 */
2a83f997 2006#define HID0_HILE PPC_BIT(19) /* POWER8 */
0bfc0cf0 2007#define HID0_POWER9_HILE PPC_BIT(4)
bbc01ca7 2008
c29b735c
NF		 2009/*****************************************************************************/
2010/* PowerPC Instructions types definitions */
2011enum {
2012 PPC_NONE = 0x0000000000000000ULL,
2013 /* PowerPC base instructions set */
2014 PPC_INSNS_BASE = 0x0000000000000001ULL,
2015 /* integer operations instructions */
2016#define PPC_INTEGER PPC_INSNS_BASE
2017 /* flow control instructions */
2018#define PPC_FLOW PPC_INSNS_BASE
2019 /* virtual memory instructions */
2020#define PPC_MEM PPC_INSNS_BASE
2021 /* ld/st with reservation instructions */
2022#define PPC_RES PPC_INSNS_BASE
2023 /* spr/msr access instructions */
2024#define PPC_MISC PPC_INSNS_BASE
2025 /* Deprecated instruction sets */
2026 /* Original POWER instruction set */
2027 PPC_POWER = 0x0000000000000002ULL,
2028 /* POWER2 instruction set extension */
2029 PPC_POWER2 = 0x0000000000000004ULL,
2030 /* Power RTC support */
2031 PPC_POWER_RTC = 0x0000000000000008ULL,
2032 /* Power-to-PowerPC bridge (601) */
2033 PPC_POWER_BR = 0x0000000000000010ULL,
2034 /* 64 bits PowerPC instruction set */
2035 PPC_64B = 0x0000000000000020ULL,
2036 /* New 64 bits extensions (PowerPC 2.0x) */
2037 PPC_64BX = 0x0000000000000040ULL,
2038 /* 64 bits hypervisor extensions */
2039 PPC_64H = 0x0000000000000080ULL,
2040 /* New wait instruction (PowerPC 2.0x) */
2041 PPC_WAIT = 0x0000000000000100ULL,
2042 /* Time base mftb instruction */
2043 PPC_MFTB = 0x0000000000000200ULL,
2044
2045 /* Fixed-point unit extensions */
2046 /* PowerPC 602 specific */
2047 PPC_602_SPEC = 0x0000000000000400ULL,
2048 /* isel instruction */
2049 PPC_ISEL = 0x0000000000000800ULL,
2050 /* popcntb instruction */
2051 PPC_POPCNTB = 0x0000000000001000ULL,
2052 /* string load / store */
2053 PPC_STRING = 0x0000000000002000ULL,
b7815375
BH		 2054 /* real mode cache inhibited load / store */
2055 PPC_CILDST = 0x0000000000004000ULL,
c29b735c
NF		 2056
2057 /* Floating-point unit extensions */
2058 /* Optional floating point instructions */
2059 PPC_FLOAT = 0x0000000000010000ULL,
2060 /* New floating-point extensions (PowerPC 2.0x) */
2061 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2062 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2063 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2064 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2065 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2066 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2067 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2068
2069 /* Vector/SIMD extensions */
2070 /* Altivec support */
2071 PPC_ALTIVEC = 0x0000000001000000ULL,
2072 /* PowerPC 2.03 SPE extension */
2073 PPC_SPE = 0x0000000002000000ULL,
2074 /* PowerPC 2.03 SPE single-precision floating-point extension */
2075 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2076 /* PowerPC 2.03 SPE double-precision floating-point extension */
2077 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2078
2079 /* Optional memory control instructions */
2080 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2081 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2082 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2083 /* sync instruction */
2084 PPC_MEM_SYNC = 0x0000000080000000ULL,
2085 /* eieio instruction */
2086 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2087
2088 /* Cache control instructions */
2089 PPC_CACHE = 0x0000000200000000ULL,
2090 /* icbi instruction */
2091 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 2092 /* dcbz instruction */
c29b735c 2093 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 2094 /* dcba instruction */
2095 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2096 /* Freescale cache locking instructions */
2097 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2098
2099 /* MMU related extensions */
2100 /* external control instructions */
2101 PPC_EXTERN = 0x0000010000000000ULL,
2102 /* segment register access instructions */
2103 PPC_SEGMENT = 0x0000020000000000ULL,
2104 /* PowerPC 6xx TLB management instructions */
2105 PPC_6xx_TLB = 0x0000040000000000ULL,
2106 /* PowerPC 74xx TLB management instructions */
2107 PPC_74xx_TLB = 0x0000080000000000ULL,
2108 /* PowerPC 40x TLB management instructions */
2109 PPC_40x_TLB = 0x0000100000000000ULL,
2110 /* segment register access instructions for PowerPC 64 "bridge" */
2111 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2112 /* SLB management */
2113 PPC_SLBI = 0x0000400000000000ULL,
2114
2115 /* Embedded PowerPC dedicated instructions */
2116 PPC_WRTEE = 0x0001000000000000ULL,
2117 /* PowerPC 40x exception model */
2118 PPC_40x_EXCP = 0x0002000000000000ULL,
2119 /* PowerPC 405 Mac instructions */
2120 PPC_405_MAC = 0x0004000000000000ULL,
2121 /* PowerPC 440 specific instructions */
2122 PPC_440_SPEC = 0x0008000000000000ULL,
2123 /* BookE (embedded) PowerPC specification */
2124 PPC_BOOKE = 0x0010000000000000ULL,
2125 /* mfapidi instruction */
2126 PPC_MFAPIDI = 0x0020000000000000ULL,
2127 /* tlbiva instruction */
2128 PPC_TLBIVA = 0x0040000000000000ULL,
2129 /* tlbivax instruction */
2130 PPC_TLBIVAX = 0x0080000000000000ULL,
2131 /* PowerPC 4xx dedicated instructions */
2132 PPC_4xx_COMMON = 0x0100000000000000ULL,
2133 /* PowerPC 40x ibct instructions */
2134 PPC_40x_ICBT = 0x0200000000000000ULL,
2135 /* rfmci is not implemented in all BookE PowerPC */
2136 PPC_RFMCI = 0x0400000000000000ULL,
2137 /* rfdi instruction */
2138 PPC_RFDI = 0x0800000000000000ULL,
2139 /* DCR accesses */
2140 PPC_DCR = 0x1000000000000000ULL,
2141 /* DCR extended accesse */
2142 PPC_DCRX = 0x2000000000000000ULL,
2143 /* user-mode DCR access, implemented in PowerPC 460 */
2144 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 2145 /* popcntw and popcntd instructions */
2146 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 2147
02d4eae4
DG		 2148#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2149 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2150 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2151 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2152 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2153 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2154 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2155 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2156 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2157 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2158 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2159 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2160 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 2161 | PPC_CACHE_DCBZ \
02d4eae4
DG		 2162 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2163 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2164 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2165 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2166 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2167 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2168 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2169 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
b7815375 2170 | PPC_POPCNTWD | PPC_CILDST)
02d4eae4 2171
01662f3e
AG		 2172 /* extended type values */
2173
2174 /* BookE 2.06 PowerPC specification */
2175 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 2176 /* VSX (extensions to Altivec / VMX) */
2177 PPC2_VSX = 0x0000000000000002ULL,
2178 /* Decimal Floating Point (DFP) */
2179 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 2180 /* Embedded.Processor Control */
2181 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 2182 /* Byte-reversed, indexed, double-word load and store */
2183 PPC2_DBRX = 0x0000000000000010ULL,
9c2627b0
AJ		 2184 /* Book I 2.05 PowerPC specification */
2185 PPC2_ISA205 = 0x0000000000000020ULL,
dbcc48fa
TM		 2186 /* VSX additions in ISA 2.07 */
2187 PPC2_VSX207 = 0x0000000000000040ULL,
86ba37ed
TM		 2188 /* ISA 2.06B bpermd */
2189 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
a824bc19
TM		 2190 /* ISA 2.06B divide extended variants */
2191 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1fa6c533
TM		 2192 /* ISA 2.06B larx/stcx. instructions */
2193 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1b0bd002
TM		 2194 /* ISA 2.06B floating point integer conversion */
2195 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
29a0e4e9
TM		 2196 /* ISA 2.06B floating point test instructions */
2197 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
94840e07
TM		 2198 /* ISA 2.07 bctar instruction */
2199 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
38a85337
TM		 2200 /* ISA 2.07 load/store quadword */
2201 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
32ea54ab
TM		 2202 /* ISA 2.07 Altivec */
2203 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
df99d30d
AK		 2204 /* PowerISA 2.07 Book3s specification */
2205 PPC2_ISA207S = 0x0000000000008000ULL,
4171853c
PM		 2206 /* Double precision floating point conversion for signed integer 64 */
2207 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
f90468b6
TM		 2208 /* Transactional Memory (ISA 2.07, Book II) */
2209 PPC2_TM = 0x0000000000020000ULL,
7778a575
BH		 2210 /* Server PM instructgions (ISA 2.06, Book III) */
2211 PPC2_PM_ISA206 = 0x0000000000040000ULL,
eb640b13
ND		 2212 /* POWER ISA 3.0 */
2213 PPC2_ISA300 = 0x0000000000080000ULL,
02d4eae4 2214
74f23997 2215#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
a824bc19 2216 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1b0bd002 2217 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
94840e07 2218 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
32ea54ab 2219 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
4171853c 2220 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
eb640b13
ND		 2221 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
2222 PPC2_ISA300)
c29b735c
NF		 2223};
2224
76a66253 2225/*****************************************************************************/
9a64fbe4
FB		 2226/* Memory access type :
2227 * may be needed for precise access rights control and precise exceptions.
2228 */
79aceca5 2229enum {
9a64fbe4
FB		 2230 /* 1 bit to define user level / supervisor access */
2231 ACCESS_USER = 0x00,
2232 ACCESS_SUPER = 0x01,
2233 /* Type of instruction that generated the access */
2234 ACCESS_CODE = 0x10, /* Code fetch access */
2235 ACCESS_INT = 0x20, /* Integer load/store access */
2236 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2237 ACCESS_RES = 0x40, /* load/store with reservation */
2238 ACCESS_EXT = 0x50, /* external access */
2239 ACCESS_CACHE = 0x60, /* Cache manipulation */
2240};
2241
47103572
JM		 2242/* Hardware interruption sources:
2243 * all those exception can be raised simulteaneously
2244 */
e9df014c
JM		 2245/* Input pins definitions */
2246enum {
2247 /* 6xx bus input pins */
24be5ae3
JM		 2248 PPC6xx_INPUT_HRESET = 0,
2249 PPC6xx_INPUT_SRESET = 1,
2250 PPC6xx_INPUT_CKSTP_IN = 2,
2251 PPC6xx_INPUT_MCP = 3,
2252 PPC6xx_INPUT_SMI = 4,
2253 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 2254 PPC6xx_INPUT_TBEN = 6,
2255 PPC6xx_INPUT_WAKEUP = 7,
2256 PPC6xx_INPUT_NB,
24be5ae3
JM		 2257};
2258
2259enum {
e9df014c 2260 /* Embedded PowerPC input pins */
24be5ae3
JM		 2261 PPCBookE_INPUT_HRESET = 0,
2262 PPCBookE_INPUT_SRESET = 1,
2263 PPCBookE_INPUT_CKSTP_IN = 2,
2264 PPCBookE_INPUT_MCP = 3,
2265 PPCBookE_INPUT_SMI = 4,
2266 PPCBookE_INPUT_INT = 5,
2267 PPCBookE_INPUT_CINT = 6,
d68f1306 2268 PPCBookE_INPUT_NB,
24be5ae3
JM		 2269};
2270
9fdc60bf
AJ		 2271enum {
2272 /* PowerPC E500 input pins */
2273 PPCE500_INPUT_RESET_CORE = 0,
2274 PPCE500_INPUT_MCK = 1,
2275 PPCE500_INPUT_CINT = 3,
2276 PPCE500_INPUT_INT = 4,
2277 PPCE500_INPUT_DEBUG = 6,
2278 PPCE500_INPUT_NB,
2279};
2280
a750fc0b 2281enum {
4e290a0b
JM		 2282 /* PowerPC 40x input pins */
2283 PPC40x_INPUT_RESET_CORE = 0,
2284 PPC40x_INPUT_RESET_CHIP = 1,
2285 PPC40x_INPUT_RESET_SYS = 2,
2286 PPC40x_INPUT_CINT = 3,
2287 PPC40x_INPUT_INT = 4,
2288 PPC40x_INPUT_HALT = 5,
2289 PPC40x_INPUT_DEBUG = 6,
2290 PPC40x_INPUT_NB,
e9df014c
JM		 2291};
2292
b4095fed
JM		 2293enum {
2294 /* RCPU input pins */
2295 PPCRCPU_INPUT_PORESET = 0,
2296 PPCRCPU_INPUT_HRESET = 1,
2297 PPCRCPU_INPUT_SRESET = 2,
2298 PPCRCPU_INPUT_IRQ0 = 3,
2299 PPCRCPU_INPUT_IRQ1 = 4,
2300 PPCRCPU_INPUT_IRQ2 = 5,
2301 PPCRCPU_INPUT_IRQ3 = 6,
2302 PPCRCPU_INPUT_IRQ4 = 7,
2303 PPCRCPU_INPUT_IRQ5 = 8,
2304 PPCRCPU_INPUT_IRQ6 = 9,
2305 PPCRCPU_INPUT_IRQ7 = 10,
2306 PPCRCPU_INPUT_NB,
2307};
2308
00af685f 2309#if defined(TARGET_PPC64)
d0dfae6e
JM		 2310enum {
2311 /* PowerPC 970 input pins */
2312 PPC970_INPUT_HRESET = 0,
2313 PPC970_INPUT_SRESET = 1,
2314 PPC970_INPUT_CKSTP = 2,
2315 PPC970_INPUT_TBEN = 3,
2316 PPC970_INPUT_MCP = 4,
2317 PPC970_INPUT_INT = 5,
2318 PPC970_INPUT_THINT = 6,
7b62a955 2319 PPC970_INPUT_NB,
9d52e907
DG		 2320};
2321
2322enum {
2323 /* POWER7 input pins */
2324 POWER7_INPUT_INT = 0,
2325 /* POWER7 probably has other inputs, but we don't care about them
2326 * for any existing machine. We can wire these up when we need
2327 * them */
2328 POWER7_INPUT_NB,
d0dfae6e 2329};
00af685f 2330#endif
d0dfae6e 2331
e9df014c 2332/* Hardware exceptions definitions */
47103572 2333enum {
e9df014c 2334 /* External hardware exception sources */
e1833e1f 2335 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 2336 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2337 PPC_INTERRUPT_MCK, /* Machine check exception */
2338 PPC_INTERRUPT_EXT, /* External interrupt */
2339 PPC_INTERRUPT_SMI, /* System management interrupt */
2340 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2341 PPC_INTERRUPT_DEBUG, /* External debug exception */
2342 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 2343 /* Internal hardware exception sources */
d68f1306
JM		 2344 PPC_INTERRUPT_DECR, /* Decrementer exception */
2345 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2346 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2347 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2348 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2349 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2350 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2351 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
f03a1af5
BH		 2352 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2353 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
47103572
JM		 2354};
2355
6d9412ea
AK		 2356/* Processor Compatibility mask (PCR) */
2357enum {
a6a444a8
CLG		 2358 PCR_COMPAT_2_05 = PPC_BIT(62),
2359 PCR_COMPAT_2_06 = PPC_BIT(61),
2360 PCR_COMPAT_2_07 = PPC_BIT(60),
2361 PCR_COMPAT_3_00 = PPC_BIT(59),
2362 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2363 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2364 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
6d9412ea
AK		 2365};
2366
1488270e
BH		 2367/* HMER/HMEER */
2368enum {
a6a444a8
CLG		 2369 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2370 HMER_PROC_RECV_DONE = PPC_BIT(2),
2371 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2372 HMER_TFAC_ERROR = PPC_BIT(4),
2373 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2374 HMER_XSCOM_FAIL = PPC_BIT(8),
2375 HMER_XSCOM_DONE = PPC_BIT(9),
2376 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2377 HMER_WARN_RISE = PPC_BIT(14),
2378 HMER_WARN_FALL = PPC_BIT(15),
2379 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2380 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2381 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2382 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
1488270e
BH		 2383};
2384
5c94b2a5
CLG		 2385/* Alternate Interrupt Location (AIL) */
2386enum {
2387 AIL_NONE = 0,
2388 AIL_RESERVED = 1,
2389 AIL_0001_8000 = 2,
2390 AIL_C000_0000_0000_4000 = 3,
2391};
2392
9a64fbe4
FB		 2393/*****************************************************************************/
2394
dd09c361 2395#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
00b70788
ND		 2396target_ulong cpu_read_xer(CPUPPCState *env);
2397void cpu_write_xer(CPUPPCState *env, target_ulong xer);
da91a00f 2398
1328c2bf 2399static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
89fee74a 2400 target_ulong *cs_base, uint32_t *flags)
6b917547
AL		 2401{
2402 *pc = env->nip;
2403 *cs_base = 0;
2404 *flags = env->hflags;
2405}
2406
db789c6c
BH		 2407void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2408void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2409 uintptr_t raddr);
2410void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2411 uint32_t error_code);
2412void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2413 uint32_t error_code, uintptr_t raddr);
2414
01662f3e 2415#if !defined(CONFIG_USER_ONLY)
1328c2bf 2416static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2417{
d1e256fe 2418 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2419 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2420
1c53accc 2421 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2422}
2423
1328c2bf 2424static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2425{
2426 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2427 int r = tlbncfg & TLBnCFG_N_ENTRY;
2428 return r;
2429}
2430
1328c2bf 2431static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2432{
2433 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2434 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2435 return r;
2436}
2437
1328c2bf 2438static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2439{
d1e256fe 2440 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2441 int end = 0;
2442 int i;
2443
2444 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2445 end += booke206_tlb_size(env, i);
2446 if (id < end) {
2447 return i;
2448 }
2449 }
2450
a47dddd7 2451 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
01662f3e
AG		 2452 return 0;
2453}
2454
1328c2bf 2455static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2456{
d1e256fe
AG		 2457 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2458 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2459 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2460}
2461
1328c2bf 2462static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2463 target_ulong ea, int way)
2464{
2465 int r;
2466 uint32_t ways = booke206_tlb_ways(env, tlbn);
786a4ea8
SH		 2467 int ways_bits = ctz32(ways);
2468 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
01662f3e
AG		 2469 int i;
2470
2471 way &= ways - 1;
2472 ea >>= MAS2_EPN_SHIFT;
2473 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2474 r = (ea << ways_bits) | way;
2475
3f162d11
AG		 2476 if (r >= booke206_tlb_size(env, tlbn)) {
2477 return NULL;
2478 }
2479
01662f3e
AG		 2480 /* bump up to tlbn index */
2481 for (i = 0; i < tlbn; i++) {
2482 r += booke206_tlb_size(env, i);
2483 }
2484
1c53accc 2485 return &env->tlb.tlbm[r];
01662f3e
AG		 2486}
2487
a1ef618a 2488/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2489static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a 2490{
a1ef618a
AG		 2491 uint32_t ret = 0;
2492
3f330293
KF		 2493 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2494 /* MAV2 */
a1ef618a
AG		 2495 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2496 } else {
2497 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2498 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2499 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2500 int i;
2501 for (i = min; i <= max; i++) {
2502 ret |= (1 << (i << 1));
2503 }
2504 }
2505
2506 return ret;
2507}
2508
c449d8ba
KF		 2509static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2510 ppcmas_tlb_t *tlb)
2511{
2512 uint8_t i;
2513 int32_t tsize = -1;
2514
2515 for (i = 0; i < 32; i++) {
2516 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2517 if (tsize == -1) {
2518 tsize = i;
2519 } else {
2520 return;
2521 }
2522 }
2523 }
2524
2525 /* TLBnPS unimplemented? Odd.. */
2526 assert(tsize != -1);
2527 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2528 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2529}
2530
01662f3e
AG		 2531#endif
2532
e42a61f1
AG		 2533static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2534{
2535 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2536 return msr & (1ULL << MSR_CM);
2537 }
2538
2539 return msr & (1ULL << MSR_SF);
2540}
2541
afbee712
TH		 2542/**
2543 * Check whether register rx is in the range between start and
2544 * start + nregs (as needed by the LSWX and LSWI instructions)
2545 */
2546static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2547{
2548 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2549 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2550}
2551
1328c2bf 2552void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
bebabbc7 2553
376dbce0 2554void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
07f5a258 2555#endif /* PPC_CPU_H */
QEMU mirror