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Move QOM typedefs and add missing includes
[mirror_qemu.git] / target / ppc / cpu.h
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79aceca5 1/*
3fc6c082 2 * PowerPC emulation cpu definitions for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
79aceca5
FB		 5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
79aceca5 18 */
07f5a258
MA		 19
20#ifndef PPC_CPU_H
21#define PPC_CPU_H
79aceca5 22
60caf221 23#include "qemu/int128.h"
74433bf0
RH		 24#include "exec/cpu-defs.h"
25#include "cpu-qom.h"
db1015e9 26#include "qom/object.h"
3fc6c082 27
f0b0685d
ND		 28#define TCG_GUEST_DEFAULT_MO 0
29
ad3e67d0 30#define TARGET_PAGE_BITS_64K 16
81762d6d
DG		 31#define TARGET_PAGE_BITS_16M 24
32
c647e3fe 33#if defined(TARGET_PPC64)
4ecd4d16 34#define PPC_ELF_MACHINE EM_PPC64
76a66253 35#else
4ecd4d16 36#define PPC_ELF_MACHINE EM_PPC
76a66253 37#endif
9042c0e2 38
a7d4b1bf
CLG		 39#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
40#define PPC_BIT32(bit) (0x80000000 >> (bit))
41#define PPC_BIT8(bit) (0x80 >> (bit))
2a83f997
CLG		 42#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
43#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
44 PPC_BIT32(bs))
a6a444a8
CLG		 45#define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs))
46
e1833e1f
JM		 47/*****************************************************************************/
48/* Exception vectors definitions */
49enum {
50 POWERPC_EXCP_NONE = -1,
51 /* The 64 first entries are used by the PowerPC embedded specification */
52 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
53 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
54 POWERPC_EXCP_DSI = 2, /* Data storage exception */
55 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
56 POWERPC_EXCP_EXTERNAL = 4, /* External input */
57 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
58 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
59 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
60 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
61 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
62 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
63 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
64 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
b4095fed
JM		 65 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
66 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
e1833e1f
JM		 67 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
68 /* Vectors 16 to 31 are reserved */
e1833e1f
JM		 69 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
70 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
71 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
72 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
73 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
74 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
0ef654e3
AG		 75 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
76 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
77 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
78 /* Vectors 42 to 63 are reserved */
e1833e1f
JM		 79 /* Exceptions defined in the PowerPC server specification */
80 POWERPC_EXCP_RESET = 64, /* System reset exception */
e1833e1f
JM		 81 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
82 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
e1833e1f 83 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
e1833e1f 84 POWERPC_EXCP_TRACE = 68, /* Trace exception */
e1833e1f
JM		 85 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
86 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
87 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
88 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
e1833e1f
JM		 89 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
90 /* 40x specific exceptions */
91 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
92 /* 601 specific exceptions */
93 POWERPC_EXCP_IO = 75, /* IO error exception */
94 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
95 /* 602 specific exceptions */
96 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
97 /* 602/603 specific exceptions */
b4095fed 98 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
e1833e1f
JM		 99 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
100 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
101 /* Exceptions available on most PowerPC */
102 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
b4095fed
JM		 103 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
104 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
105 POWERPC_EXCP_SMI = 84, /* System management interrupt */
106 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
e1833e1f 107 /* 7xx/74xx specific exceptions */
b4095fed 108 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
e1833e1f 109 /* 74xx specific exceptions */
b4095fed 110 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
e1833e1f 111 /* 970FX specific exceptions */
b4095fed
JM		 112 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
113 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
5b46d07d 114 /* Freescale embedded cores specific exceptions */
b4095fed
JM		 115 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
116 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
117 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
118 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
1f29871c
TM		 119 /* VSX Unavailable (Power ISA 2.06 and later) */
120 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
7019cb3d 121 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
f03a1af5
BH		 122 /* Additional ISA 2.06 and later server exceptions */
123 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */
124 POWERPC_EXCP_HV_MAINT = 97, /* HMI */
125 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */
1414c75d
CLG		 126 /* Server doorbell variants */
127 POWERPC_EXCP_SDOOR = 99,
128 POWERPC_EXCP_SDOOR_HV = 100,
d8ce5fd6
BH		 129 /* ISA 3.00 additions */
130 POWERPC_EXCP_HVIRT = 101,
3c89b8d6 131 POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
e1833e1f 132 /* EOL */
3c89b8d6 133 POWERPC_EXCP_NB = 103,
5cbdb3a3 134 /* QEMU exceptions: used internally during code translation */
e1833e1f
JM		 135 POWERPC_EXCP_STOP = 0x200, /* stop translation */
136 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
5cbdb3a3 137 /* QEMU exceptions: special cases we want to stop translation */
e1833e1f
JM		 138 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
139 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
140};
141
e1833e1f
JM		 142/* Exceptions error codes */
143enum {
144 /* Exception subtypes for POWERPC_EXCP_ALIGN */
145 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
146 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
147 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
148 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
149 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
150 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
151 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
152 /* FP exceptions */
153 POWERPC_EXCP_FP = 0x10,
154 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
155 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
156 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
157 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
7c58044c 158 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
e1833e1f
JM		 159 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
160 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
161 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
162 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
163 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
164 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
165 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
166 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
167 /* Invalid instruction */
168 POWERPC_EXCP_INVAL = 0x20,
169 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
170 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
171 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
172 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
173 /* Privileged instruction */
174 POWERPC_EXCP_PRIV = 0x30,
175 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
176 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
177 /* Trap */
178 POWERPC_EXCP_TRAP = 0x40,
179};
180
25458103 181#define PPC_INPUT(env) ((env)->bus_model)
3fc6c082 182
be147d08 183/*****************************************************************************/
c227f099 184typedef struct opc_handler_t opc_handler_t;
79aceca5 185
3fc6c082 186/*****************************************************************************/
7222b94a 187/* Types used to describe some PowerPC registers etc. */
69b058c8 188typedef struct DisasContext DisasContext;
c227f099 189typedef struct ppc_spr_t ppc_spr_t;
c227f099 190typedef union ppc_tlb_t ppc_tlb_t;
1ad9f0a4 191typedef struct ppc_hash_pte64 ppc_hash_pte64_t;
76a66253 192
3fc6c082 193/* SPR access micro-ops generations callbacks */
c227f099 194struct ppc_spr_t {
69b058c8
PB		 195 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
196 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
76a66253 197#if !defined(CONFIG_USER_ONLY)
69b058c8
PB		 198 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
199 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
200 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
201 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
707c7c2e 202 unsigned int gdb_id;
76a66253 203#endif
b55266b5 204 const char *name;
d197fdbc 205 target_ulong default_value;
d67d40ea 206#ifdef CONFIG_KVM
c647e3fe
DG		 207 /*
208 * We (ab)use the fact that all the SPRs will have ids for the
d67d40ea 209 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
c647e3fe
DG		 210 * don't sync this
211 */
d67d40ea
DG		 212 uint64_t one_reg_id;
213#endif
3fc6c082
FB		 214};
215
05ee3e8a
MCA		 216/* VSX/Altivec registers (128 bits) */
217typedef union _ppc_vsr_t {
a9d9eb8f
JM		 218 uint8_t u8[16];
219 uint16_t u16[8];
220 uint32_t u32[4];
05ee3e8a 221 uint64_t u64[2];
ab5f265d
AJ		 222 int8_t s8[16];
223 int16_t s16[8];
224 int32_t s32[4];
bb527533 225 int64_t s64[2];
05ee3e8a
MCA		 226 float32 f32[4];
227 float64 f64[2];
228 float128 f128;
bb527533
TM		 229#ifdef CONFIG_INT128
230 __uint128_t u128;
231#endif
05ee3e8a
MCA		 232 Int128 s128;
233} ppc_vsr_t;
234
235typedef ppc_vsr_t ppc_avr_t;
d9acba31 236typedef ppc_vsr_t ppc_fprp_t;
9fddaa0c 237
3c7b48b7 238#if !defined(CONFIG_USER_ONLY)
3fc6c082 239/* Software TLB cache */
c227f099
AL		 240typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
241struct ppc6xx_tlb_t {
76a66253
JM		 242 target_ulong pte0;
243 target_ulong pte1;
244 target_ulong EPN;
1d0a48fb
JM		 245};
246
c227f099
AL		 247typedef struct ppcemb_tlb_t ppcemb_tlb_t;
248struct ppcemb_tlb_t {
b162d02e 249 uint64_t RPN;
1d0a48fb 250 target_ulong EPN;
76a66253 251 target_ulong PID;
c55e9aef
JM		 252 target_ulong size;
253 uint32_t prot;
254 uint32_t attr; /* Storage attributes */
1d0a48fb
JM		 255};
256
d1e256fe
AG		 257typedef struct ppcmas_tlb_t {
258 uint32_t mas8;
259 uint32_t mas1;
260 uint64_t mas2;
261 uint64_t mas7_3;
262} ppcmas_tlb_t;
263
c227f099 264union ppc_tlb_t {
1c53accc
AG		 265 ppc6xx_tlb_t *tlb6;
266 ppcemb_tlb_t *tlbe;
267 ppcmas_tlb_t *tlbm;
3fc6c082 268};
1c53accc
AG		 269
270/* possible TLB variants */
271#define TLB_NONE 0
272#define TLB_6XX 1
273#define TLB_EMB 2
274#define TLB_MAS 3
3c7b48b7 275#endif
3fc6c082 276
b07c59f7
DG		 277typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes;
278
c227f099
AL		 279typedef struct ppc_slb_t ppc_slb_t;
280struct ppc_slb_t {
81762d6d
DG		 281 uint64_t esid;
282 uint64_t vsid;
b07c59f7 283 const PPCHash64SegmentPageSizes *sps;
8eee0af9
BS		 284};
285
d83af167 286#define MAX_SLB_ENTRIES 64
81762d6d
DG		 287#define SEGMENT_SHIFT_256M 28
288#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
289
cdaee006
DG		 290#define SEGMENT_SHIFT_1T 40
291#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
292
79825f4d
BH		 293typedef struct ppc_v3_pate_t {
294 uint64_t dw0;
295 uint64_t dw1;
296} ppc_v3_pate_t;
cdaee006 297
3fc6c082
FB		 298/*****************************************************************************/
299/* Machine state register bits definition */
76a66253 300#define MSR_SF 63 /* Sixty-four-bit mode hflags */
bd928eba 301#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
3fc6c082 302#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
23513f81 303#define MSR_HV 60 /* hypervisor state hflags */
cdcdda27
AK		 304#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
305#define MSR_TS1 33
306#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
363be49c
JM		 307#define MSR_CM 31 /* Computation mode for BookE hflags */
308#define MSR_ICM 30 /* Interrupt computation mode for BookE */
71afeb61 309#define MSR_GS 28 /* guest state for BookE */
363be49c 310#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
d26bfc9a
JM		 311#define MSR_VR 25 /* altivec available x hflags */
312#define MSR_SPE 25 /* SPE enable for BookE x hflags */
76a66253 313#define MSR_AP 23 /* Access privilege state on 602 hflags */
1f29871c 314#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
76a66253 315#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
3fc6c082 316#define MSR_KEY 19 /* key bit on 603e */
25ba3a68 317#define MSR_POW 18 /* Power management */
d26bfc9a
JM		 318#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
319#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
3fc6c082
FB		 320#define MSR_ILE 16 /* Interrupt little-endian mode */
321#define MSR_EE 15 /* External interrupt enable */
76a66253
JM		 322#define MSR_PR 14 /* Problem state hflags */
323#define MSR_FP 13 /* Floating point available hflags */
3fc6c082 324#define MSR_ME 12 /* Machine check interrupt enable */
76a66253 325#define MSR_FE0 11 /* Floating point exception mode 0 hflags */
d26bfc9a
JM		 326#define MSR_SE 10 /* Single-step trace enable x hflags */
327#define MSR_DWE 10 /* Debug wait enable on 405 x */
328#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
329#define MSR_BE 9 /* Branch trace enable x hflags */
330#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
76a66253 331#define MSR_FE1 8 /* Floating point exception mode 1 hflags */
3fc6c082 332#define MSR_AL 7 /* AL bit on POWER */
0411a972 333#define MSR_EP 6 /* Exception prefix on 601 */
3fc6c082 334#define MSR_IR 5 /* Instruction relocate */
3fc6c082 335#define MSR_DR 4 /* Data relocate */
9fb04491
BH		 336#define MSR_IS 5 /* Instruction address space (BookE) */
337#define MSR_DS 4 /* Data address space (BookE) */
25ba3a68 338#define MSR_PE 3 /* Protection enable on 403 */
d26bfc9a
JM		 339#define MSR_PX 2 /* Protection exclusive on 403 x */
340#define MSR_PMM 2 /* Performance monitor mark on POWER x */
341#define MSR_RI 1 /* Recoverable interrupt 1 */
342#define MSR_LE 0 /* Little-endian mode 1 hflags */
0411a972 343
1488270e 344/* LPCR bits */
2a83f997
CLG		 345#define LPCR_VPM0 PPC_BIT(0)
346#define LPCR_VPM1 PPC_BIT(1)
347#define LPCR_ISL PPC_BIT(2)
348#define LPCR_KBV PPC_BIT(3)
88536935 349#define LPCR_DPFD_SHIFT (63 - 11)
7659ca1a 350#define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT)
88536935
BH		 351#define LPCR_VRMASD_SHIFT (63 - 16)
352#define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT)
18aa49ec
SJS		 353/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
354#define LPCR_PECE_U_SHIFT (63 - 19)
355#define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT)
2a83f997 356#define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */
88536935
BH		 357#define LPCR_RMLS_SHIFT (63 - 37)
358#define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT)
2a83f997 359#define LPCR_ILE PPC_BIT(38)
1488270e
BH		 360#define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
361#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
2a83f997
CLG		 362#define LPCR_UPRT PPC_BIT(41) /* Use Process Table */
363#define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */
00fd075e 364#define LPCR_HR PPC_BIT(43) /* Host Radix */
2a83f997
CLG		 365#define LPCR_ONL PPC_BIT(45)
366#define LPCR_LD PPC_BIT(46) /* Large Decrementer */
367#define LPCR_P7_PECE0 PPC_BIT(49)
368#define LPCR_P7_PECE1 PPC_BIT(50)
369#define LPCR_P7_PECE2 PPC_BIT(51)
370#define LPCR_P8_PECE0 PPC_BIT(47)
371#define LPCR_P8_PECE1 PPC_BIT(48)
372#define LPCR_P8_PECE2 PPC_BIT(49)
373#define LPCR_P8_PECE3 PPC_BIT(50)
374#define LPCR_P8_PECE4 PPC_BIT(51)
18aa49ec
SJS		 375/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
376#define LPCR_PECE_L_SHIFT (63 - 51)
377#define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT)
2a83f997
CLG		 378#define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */
379#define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */
380#define LPCR_EEE PPC_BIT(49) /* External Exit Enable */
381#define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */
382#define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */
383#define LPCR_MER PPC_BIT(52)
384#define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */
385#define LPCR_TC PPC_BIT(54)
386#define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */
387#define LPCR_LPES0 PPC_BIT(60)
388#define LPCR_LPES1 PPC_BIT(61)
389#define LPCR_RMI PPC_BIT(62)
390#define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */
391#define LPCR_HDICE PPC_BIT(63)
1e0c7e55 392
21c0d66a
BH		 393/* PSSCR bits */
394#define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
395#define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
396
493028d8
CLG		 397/* HFSCR bits */
398#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
399#define HFSCR_IC_MSGP 0xA
400
0411a972
JM		 401#define msr_sf ((env->msr >> MSR_SF) & 1)
402#define msr_isf ((env->msr >> MSR_ISF) & 1)
23513f81
DG		 403#if defined(TARGET_PPC64)
404#define msr_hv ((env->msr >> MSR_HV) & 1)
405#else
406#define msr_hv (0)
407#endif
0411a972
JM		 408#define msr_cm ((env->msr >> MSR_CM) & 1)
409#define msr_icm ((env->msr >> MSR_ICM) & 1)
71afeb61 410#define msr_gs ((env->msr >> MSR_GS) & 1)
0411a972
JM		 411#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
412#define msr_vr ((env->msr >> MSR_VR) & 1)
f9320410 413#define msr_spe ((env->msr >> MSR_SPE) & 1)
0411a972 414#define msr_ap ((env->msr >> MSR_AP) & 1)
1f29871c 415#define msr_vsx ((env->msr >> MSR_VSX) & 1)
0411a972
JM		 416#define msr_sa ((env->msr >> MSR_SA) & 1)
417#define msr_key ((env->msr >> MSR_KEY) & 1)
418#define msr_pow ((env->msr >> MSR_POW) & 1)
419#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
420#define msr_ce ((env->msr >> MSR_CE) & 1)
421#define msr_ile ((env->msr >> MSR_ILE) & 1)
422#define msr_ee ((env->msr >> MSR_EE) & 1)
423#define msr_pr ((env->msr >> MSR_PR) & 1)
424#define msr_fp ((env->msr >> MSR_FP) & 1)
425#define msr_me ((env->msr >> MSR_ME) & 1)
426#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
427#define msr_se ((env->msr >> MSR_SE) & 1)
428#define msr_dwe ((env->msr >> MSR_DWE) & 1)
429#define msr_uble ((env->msr >> MSR_UBLE) & 1)
430#define msr_be ((env->msr >> MSR_BE) & 1)
431#define msr_de ((env->msr >> MSR_DE) & 1)
432#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
433#define msr_al ((env->msr >> MSR_AL) & 1)
434#define msr_ep ((env->msr >> MSR_EP) & 1)
435#define msr_ir ((env->msr >> MSR_IR) & 1)
436#define msr_dr ((env->msr >> MSR_DR) & 1)
9fb04491
BH		 437#define msr_is ((env->msr >> MSR_IS) & 1)
438#define msr_ds ((env->msr >> MSR_DS) & 1)
0411a972
JM		 439#define msr_pe ((env->msr >> MSR_PE) & 1)
440#define msr_px ((env->msr >> MSR_PX) & 1)
441#define msr_pmm ((env->msr >> MSR_PMM) & 1)
442#define msr_ri ((env->msr >> MSR_RI) & 1)
443#define msr_le ((env->msr >> MSR_LE) & 1)
cdcdda27
AK		 444#define msr_ts ((env->msr >> MSR_TS1) & 3)
445#define msr_tm ((env->msr >> MSR_TM) & 1)
446
0e3bf489
RK		 447#define DBCR0_ICMP (1 << 27)
448#define DBCR0_BRT (1 << 26)
449#define DBSR_ICMP (1 << 27)
450#define DBSR_BRT (1 << 26)
451
a4f30719
JM		 452/* Hypervisor bit is more specific */
453#if defined(TARGET_PPC64)
23513f81 454#define MSR_HVB (1ULL << MSR_HV)
a4f30719
JM		 455#else
456#define MSR_HVB (0ULL)
a4f30719 457#endif
79aceca5 458
da82c73a
SJS		 459/* DSISR */
460#define DSISR_NOPTE 0x40000000
461/* Not permitted by access authority of encoded access authority */
462#define DSISR_PROTFAULT 0x08000000
463#define DSISR_ISSTORE 0x02000000
464/* Not permitted by virtual page class key protection */
465#define DSISR_AMR 0x00200000
d5fee0bb
SJS		 466/* Unsupported Radix Tree Configuration */
467#define DSISR_R_BADCONFIG 0x00080000
d04ea940
CLG		 468#define DSISR_ATOMIC_RC 0x00040000
469/* Unable to translate address of (guest) pde or process/page table entry */
470#define DSISR_PRTABLE_FAULT 0x00020000
da82c73a 471
a6152b52
SJS		 472/* SRR1 error code fields */
473
da82c73a
SJS		 474#define SRR1_NOPTE DSISR_NOPTE
475/* Not permitted due to no-execute or guard bit set */
07a68f99 476#define SRR1_NOEXEC_GUARD 0x10000000
da82c73a
SJS		 477#define SRR1_PROTFAULT DSISR_PROTFAULT
478#define SRR1_IAMR DSISR_AMR
a6152b52 479
0911a60c
LB		 480/* SRR1[42:45] wakeup fields for System Reset Interrupt */
481
482#define SRR1_WAKEMASK 0x003c0000 /* reason for wakeup */
483
484#define SRR1_WAKEHMI 0x00280000 /* Hypervisor maintenance */
485#define SRR1_WAKEHVI 0x00240000 /* Hypervisor Virt. Interrupt (P9) */
486#define SRR1_WAKEEE 0x00200000 /* External interrupt */
487#define SRR1_WAKEDEC 0x00180000 /* Decrementer interrupt */
488#define SRR1_WAKEDBELL 0x00140000 /* Privileged doorbell */
489#define SRR1_WAKERESET 0x00100000 /* System reset */
490#define SRR1_WAKEHDBELL 0x000c0000 /* Hypervisor doorbell */
491#define SRR1_WAKESCOM 0x00080000 /* SCOM not in power-saving mode */
492
493/* SRR1[46:47] power-saving exit mode */
494
495#define SRR1_WAKESTATE 0x00030000 /* Powersave exit mask */
496
497#define SRR1_WS_HVLOSS 0x00030000 /* HV resources not maintained */
498#define SRR1_WS_GPRLOSS 0x00020000 /* GPRs not maintained */
499#define SRR1_WS_NOLOSS 0x00010000 /* All resources maintained */
500
7019cb3d
AK		 501/* Facility Status and Control (FSCR) bits */
502#define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
503#define FSCR_TAR (63 - 55) /* Target Address Register */
3c89b8d6 504#define FSCR_SCV (63 - 51) /* System call vectored */
7019cb3d
AK		 505/* Interrupt cause mask and position in FSCR. HFSCR has the same format */
506#define FSCR_IC_MASK (0xFFULL)
507#define FSCR_IC_POS (63 - 7)
508#define FSCR_IC_DSCR_SPR3 2
509#define FSCR_IC_PMU 3
510#define FSCR_IC_BHRB 4
511#define FSCR_IC_TM 5
512#define FSCR_IC_EBB 7
513#define FSCR_IC_TAR 8
3c89b8d6 514#define FSCR_IC_SCV 12
7019cb3d 515
a586e548 516/* Exception state register bits definition */
2a83f997
CLG		 517#define ESR_PIL PPC_BIT(36) /* Illegal Instruction */
518#define ESR_PPR PPC_BIT(37) /* Privileged Instruction */
519#define ESR_PTR PPC_BIT(38) /* Trap */
520#define ESR_FP PPC_BIT(39) /* Floating-Point Operation */
521#define ESR_ST PPC_BIT(40) /* Store Operation */
522#define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */
523#define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */
524#define ESR_BO PPC_BIT(46) /* Byte Ordering */
525#define ESR_PIE PPC_BIT(47) /* Imprecise exception */
526#define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */
527#define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */
528#define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */
529#define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */
530#define ESR_EPID PPC_BIT(57) /* External Process ID operation */
531#define ESR_VLEMI PPC_BIT(58) /* VLE operation */
532#define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */
a586e548 533
aac86237
TM		 534/* Transaction EXception And Summary Register bits */
535#define TEXASR_FAILURE_PERSISTENT (63 - 7)
536#define TEXASR_DISALLOWED (63 - 8)
537#define TEXASR_NESTING_OVERFLOW (63 - 9)
538#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
539#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
540#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
541#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
542#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
543#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
544#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
545#define TEXASR_ABORT (63 - 31)
546#define TEXASR_SUSPENDED (63 - 32)
547#define TEXASR_PRIVILEGE_HV (63 - 34)
548#define TEXASR_PRIVILEGE_PR (63 - 35)
549#define TEXASR_FAILURE_SUMMARY (63 - 36)
550#define TEXASR_TFIAR_EXACT (63 - 37)
551#define TEXASR_ROT (63 - 38)
552#define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
553
d26bfc9a 554enum {
4018bae9 555 POWERPC_FLAG_NONE = 0x00000000,
d26bfc9a 556 /* Flag for MSR bit 25 signification (VRE/SPE) */
4018bae9
JM		 557 POWERPC_FLAG_SPE = 0x00000001,
558 POWERPC_FLAG_VRE = 0x00000002,
d26bfc9a 559 /* Flag for MSR bit 17 signification (TGPR/CE) */
4018bae9
JM		 560 POWERPC_FLAG_TGPR = 0x00000004,
561 POWERPC_FLAG_CE = 0x00000008,
d26bfc9a 562 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
4018bae9
JM		 563 POWERPC_FLAG_SE = 0x00000010,
564 POWERPC_FLAG_DWE = 0x00000020,
565 POWERPC_FLAG_UBLE = 0x00000040,
d26bfc9a 566 /* Flag for MSR bit 9 signification (BE/DE) */
4018bae9
JM		 567 POWERPC_FLAG_BE = 0x00000080,
568 POWERPC_FLAG_DE = 0x00000100,
a4f30719 569 /* Flag for MSR bit 2 signification (PX/PMM) */
4018bae9
JM		 570 POWERPC_FLAG_PX = 0x00000200,
571 POWERPC_FLAG_PMM = 0x00000400,
572 /* Flag for special features */
573 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
574 POWERPC_FLAG_RTC_CLK = 0x00010000,
575 POWERPC_FLAG_BUS_CLK = 0x00020000,
697ab892
DG		 576 /* Has CFAR */
577 POWERPC_FLAG_CFAR = 0x00040000,
74f23997
TM		 578 /* Has VSX */
579 POWERPC_FLAG_VSX = 0x00080000,
e43668a7
TM		 580 /* Has Transaction Memory (ISA 2.07) */
581 POWERPC_FLAG_TM = 0x00100000,
3c89b8d6
NP		 582 /* Has SCV (ISA 3.00) */
583 POWERPC_FLAG_SCV = 0x00200000,
d26bfc9a
JM		 584};
585
7c58044c
JM		 586/*****************************************************************************/
587/* Floating point status and control register */
a2735cf4
PC		 588#define FPSCR_DRN2 34 /* Decimal Floating-Point rounding control */
589#define FPSCR_DRN1 33 /* Decimal Floating-Point rounding control */
590#define FPSCR_DRN0 32 /* Decimal Floating-Point rounding control */
7c58044c
JM		 591#define FPSCR_FX 31 /* Floating-point exception summary */
592#define FPSCR_FEX 30 /* Floating-point enabled exception summary */
593#define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
594#define FPSCR_OX 28 /* Floating-point overflow exception */
595#define FPSCR_UX 27 /* Floating-point underflow exception */
596#define FPSCR_ZX 26 /* Floating-point zero divide exception */
597#define FPSCR_XX 25 /* Floating-point inexact exception */
598#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
599#define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
600#define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
601#define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
602#define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
603#define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
604#define FPSCR_FR 18 /* Floating-point fraction rounded */
605#define FPSCR_FI 17 /* Floating-point fraction inexact */
606#define FPSCR_C 16 /* Floating-point result class descriptor */
607#define FPSCR_FL 15 /* Floating-point less than or negative */
608#define FPSCR_FG 14 /* Floating-point greater than or negative */
609#define FPSCR_FE 13 /* Floating-point equal or zero */
610#define FPSCR_FU 12 /* Floating-point unordered or NaN */
611#define FPSCR_FPCC 12 /* Floating-point condition code */
612#define FPSCR_FPRF 12 /* Floating-point result flags */
613#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
614#define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
615#define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
616#define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
617#define FPSCR_OE 6 /* Floating-point overflow exception enable */
618#define FPSCR_UE 5 /* Floating-point undeflow exception enable */
619#define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
620#define FPSCR_XE 3 /* Floating-point inexact exception enable */
621#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
622#define FPSCR_RN1 1
31eb7ddd 623#define FPSCR_RN0 0 /* Floating-point rounding control */
a2735cf4 624#define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
7c58044c
JM		 625#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
626#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
627#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
628#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
629#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
630#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
631#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
632#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
633#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
634#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
635#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
636#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
637#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
638#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
639#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
640#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
641#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
642#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
643#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
644#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
645#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
646#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
31eb7ddd 647#define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)
7c58044c
JM		 648/* Invalid operation exception summary */
649#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
650 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
651 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
652 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
653 (1 << FPSCR_VXCVI)))
654/* exception summary */
655#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
656/* enabled exception summary */
657#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
658 0x1F)
659
a2735cf4
PC		 660#define FP_DRN2 (1ull << FPSCR_DRN2)
661#define FP_DRN1 (1ull << FPSCR_DRN1)
662#define FP_DRN0 (1ull << FPSCR_DRN0)
663#define FP_DRN (FP_DRN2 | FP_DRN1 | FP_DRN0)
c647e3fe
DG		 664#define FP_FX (1ull << FPSCR_FX)
665#define FP_FEX (1ull << FPSCR_FEX)
666#define FP_VX (1ull << FPSCR_VX)
667#define FP_OX (1ull << FPSCR_OX)
668#define FP_UX (1ull << FPSCR_UX)
669#define FP_ZX (1ull << FPSCR_ZX)
670#define FP_XX (1ull << FPSCR_XX)
671#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
672#define FP_VXISI (1ull << FPSCR_VXISI)
673#define FP_VXIDI (1ull << FPSCR_VXIDI)
674#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
675#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
676#define FP_VXVC (1ull << FPSCR_VXVC)
31eb7ddd 677#define FP_FR (1ull << FPSCR_FR)
c647e3fe
DG		 678#define FP_FI (1ull << FPSCR_FI)
679#define FP_C (1ull << FPSCR_C)
680#define FP_FL (1ull << FPSCR_FL)
681#define FP_FG (1ull << FPSCR_FG)
682#define FP_FE (1ull << FPSCR_FE)
683#define FP_FU (1ull << FPSCR_FU)
684#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
31eb7ddd 685#define FP_FPRF (FP_C | FP_FPCC)
c647e3fe
DG		 686#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
687#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
688#define FP_VXCVI (1ull << FPSCR_VXCVI)
689#define FP_VE (1ull << FPSCR_VE)
690#define FP_OE (1ull << FPSCR_OE)
691#define FP_UE (1ull << FPSCR_UE)
692#define FP_ZE (1ull << FPSCR_ZE)
693#define FP_XE (1ull << FPSCR_XE)
694#define FP_NI (1ull << FPSCR_NI)
695#define FP_RN1 (1ull << FPSCR_RN1)
31eb7ddd
PC		 696#define FP_RN0 (1ull << FPSCR_RN0)
697#define FP_RN (FP_RN1 | FP_RN0)
698
31eb7ddd
PC		 699#define FP_ENABLES (FP_VE | FP_OE | FP_UE | FP_ZE | FP_XE)
700#define FP_STATUS (FP_FR | FP_FI | FP_FPRF)
dbdc13a1 701
d1277156
JC		 702/* the exception bits which can be cleared by mcrfs - includes FX */
703#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
704 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
705 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
706 FP_VXSQRT | FP_VXCVI)
707
7c58044c 708/*****************************************************************************/
6fa724a3 709/* Vector status and control register */
c647e3fe
DG		 710#define VSCR_NJ 16 /* Vector non-java */
711#define VSCR_SAT 0 /* Vector saturation */
6fa724a3 712
01662f3e
AG		 713/*****************************************************************************/
714/* BookE e500 MMU registers */
715
716#define MAS0_NV_SHIFT 0
717#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
718
719#define MAS0_WQ_SHIFT 12
720#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
721/* Write TLB entry regardless of reservation */
722#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
723/* Write TLB entry only already in use */
724#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
725/* Clear TLB entry */
726#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
727
728#define MAS0_HES_SHIFT 14
729#define MAS0_HES (1 << MAS0_HES_SHIFT)
730
731#define MAS0_ESEL_SHIFT 16
732#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
733
734#define MAS0_TLBSEL_SHIFT 28
735#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
736#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
737#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
738#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
739#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
740
741#define MAS0_ATSEL_SHIFT 31
742#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
743#define MAS0_ATSEL_TLB 0
744#define MAS0_ATSEL_LRAT MAS0_ATSEL
745
2bd9543c
SW		 746#define MAS1_TSIZE_SHIFT 7
747#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
01662f3e
AG		 748
749#define MAS1_TS_SHIFT 12
750#define MAS1_TS (1 << MAS1_TS_SHIFT)
751
752#define MAS1_IND_SHIFT 13
753#define MAS1_IND (1 << MAS1_IND_SHIFT)
754
755#define MAS1_TID_SHIFT 16
756#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
757
758#define MAS1_IPROT_SHIFT 30
759#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
760
761#define MAS1_VALID_SHIFT 31
762#define MAS1_VALID 0x80000000
763
764#define MAS2_EPN_SHIFT 12
96091698 765#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
01662f3e
AG		 766
767#define MAS2_ACM_SHIFT 6
768#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
769
770#define MAS2_VLE_SHIFT 5
771#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
772
773#define MAS2_W_SHIFT 4
774#define MAS2_W (1 << MAS2_W_SHIFT)
775
776#define MAS2_I_SHIFT 3
777#define MAS2_I (1 << MAS2_I_SHIFT)
778
779#define MAS2_M_SHIFT 2
780#define MAS2_M (1 << MAS2_M_SHIFT)
781
782#define MAS2_G_SHIFT 1
783#define MAS2_G (1 << MAS2_G_SHIFT)
784
785#define MAS2_E_SHIFT 0
786#define MAS2_E (1 << MAS2_E_SHIFT)
787
788#define MAS3_RPN_SHIFT 12
789#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
790
791#define MAS3_U0 0x00000200
792#define MAS3_U1 0x00000100
793#define MAS3_U2 0x00000080
794#define MAS3_U3 0x00000040
795#define MAS3_UX 0x00000020
796#define MAS3_SX 0x00000010
797#define MAS3_UW 0x00000008
798#define MAS3_SW 0x00000004
799#define MAS3_UR 0x00000002
800#define MAS3_SR 0x00000001
801#define MAS3_SPSIZE_SHIFT 1
802#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
803
804#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
805#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
806#define MAS4_TIDSELD_MASK 0x00030000
807#define MAS4_TIDSELD_PID0 0x00000000
808#define MAS4_TIDSELD_PID1 0x00010000
809#define MAS4_TIDSELD_PID2 0x00020000
810#define MAS4_TIDSELD_PIDZ 0x00030000
811#define MAS4_INDD 0x00008000 /* Default IND */
812#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
813#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
814#define MAS4_ACMD 0x00000040
815#define MAS4_VLED 0x00000020
816#define MAS4_WD 0x00000010
817#define MAS4_ID 0x00000008
818#define MAS4_MD 0x00000004
819#define MAS4_GD 0x00000002
820#define MAS4_ED 0x00000001
821#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
822#define MAS4_WIMGED_SHIFT 0
823
824#define MAS5_SGS 0x80000000
825#define MAS5_SLPID_MASK 0x00000fff
826
827#define MAS6_SPID0 0x3fff0000
828#define MAS6_SPID1 0x00007ffe
829#define MAS6_ISIZE(x) MAS1_TSIZE(x)
830#define MAS6_SAS 0x00000001
831#define MAS6_SPID MAS6_SPID0
832#define MAS6_SIND 0x00000002 /* Indirect page */
833#define MAS6_SIND_SHIFT 1
834#define MAS6_SPID_MASK 0x3fff0000
835#define MAS6_SPID_SHIFT 16
836#define MAS6_ISIZE_MASK 0x00000f80
837#define MAS6_ISIZE_SHIFT 7
838
839#define MAS7_RPN 0xffffffff
840
841#define MAS8_TGS 0x80000000
842#define MAS8_VF 0x40000000
843#define MAS8_TLBPID 0x00000fff
844
845/* Bit definitions for MMUCFG */
846#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
847#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
848#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
849#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
850#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
851#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
852#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
853#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
854#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
855
856/* Bit definitions for MMUCSR0 */
857#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
858#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
859#define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
860#define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
861#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
862 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
863#define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
864#define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
865#define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
866#define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
867
868/* TLBnCFG encoding */
869#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
870#define TLBnCFG_HES 0x00002000 /* HW select supported */
871#define TLBnCFG_AVAIL 0x00004000 /* variable page size */
872#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
873#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
874#define TLBnCFG_IND 0x00020000 /* IND entries supported */
875#define TLBnCFG_PT 0x00040000 /* Can load from page table */
876#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
877#define TLBnCFG_MINSIZE_SHIFT 20
878#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
879#define TLBnCFG_MAXSIZE_SHIFT 16
880#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
881#define TLBnCFG_ASSOC_SHIFT 24
882
883/* TLBnPS encoding */
884#define TLBnPS_4K 0x00000004
885#define TLBnPS_8K 0x00000008
886#define TLBnPS_16K 0x00000010
887#define TLBnPS_32K 0x00000020
888#define TLBnPS_64K 0x00000040
889#define TLBnPS_128K 0x00000080
890#define TLBnPS_256K 0x00000100
891#define TLBnPS_512K 0x00000200
892#define TLBnPS_1M 0x00000400
893#define TLBnPS_2M 0x00000800
894#define TLBnPS_4M 0x00001000
895#define TLBnPS_8M 0x00002000
896#define TLBnPS_16M 0x00004000
897#define TLBnPS_32M 0x00008000
898#define TLBnPS_64M 0x00010000
899#define TLBnPS_128M 0x00020000
900#define TLBnPS_256M 0x00040000
901#define TLBnPS_512M 0x00080000
902#define TLBnPS_1G 0x00100000
903#define TLBnPS_2G 0x00200000
904#define TLBnPS_4G 0x00400000
905#define TLBnPS_8G 0x00800000
906#define TLBnPS_16G 0x01000000
907#define TLBnPS_32G 0x02000000
908#define TLBnPS_64G 0x04000000
909#define TLBnPS_128G 0x08000000
910#define TLBnPS_256G 0x10000000
911
912/* tlbilx action encoding */
913#define TLBILX_T_ALL 0
914#define TLBILX_T_TID 1
915#define TLBILX_T_FULLMATCH 3
916#define TLBILX_T_CLASS0 4
917#define TLBILX_T_CLASS1 5
918#define TLBILX_T_CLASS2 6
919#define TLBILX_T_CLASS3 7
920
921/* BookE 2.06 helper defines */
922
923#define BOOKE206_FLUSH_TLB0 (1 << 0)
924#define BOOKE206_FLUSH_TLB1 (1 << 1)
925#define BOOKE206_FLUSH_TLB2 (1 << 2)
926#define BOOKE206_FLUSH_TLB3 (1 << 3)
927
928/* number of possible TLBs */
929#define BOOKE206_MAX_TLBN 4
930
50728199
RK		 931#define EPID_EPID_SHIFT 0x0
932#define EPID_EPID 0xFF
933#define EPID_ELPID_SHIFT 0x10
934#define EPID_ELPID 0x3F0000
935#define EPID_EGS 0x20000000
936#define EPID_EGS_SHIFT 29
937#define EPID_EAS 0x40000000
938#define EPID_EAS_SHIFT 30
939#define EPID_EPR 0x80000000
940#define EPID_EPR_SHIFT 31
941/* We don't support EGS and ELPID */
942#define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR)
943
58e00a24 944/*****************************************************************************/
7af1e7b0 945/* Server and Embedded Processor Control */
58e00a24
AG		 946
947#define DBELL_TYPE_SHIFT 27
948#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
949#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
950#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
951#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
952#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
953#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
954
7af1e7b0
CLG		 955#define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT)
956
957#define DBELL_BRDCAST PPC_BIT(37)
58e00a24
AG		 958#define DBELL_LPIDTAG_SHIFT 14
959#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
960#define DBELL_PIRTAG_MASK 0x3fff
961
7af1e7b0
CLG		 962#define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63)
963
4656e1f0
BH		 964#define PPC_PAGE_SIZES_MAX_SZ 8
965
c64abd1f
SB		 966struct ppc_radix_page_info {
967 uint32_t count;
968 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ];
969};
4656e1f0 970
6fa724a3 971/*****************************************************************************/
7c58044c 972/* The whole PowerPC CPU context */
50728199 973
c647e3fe
DG		 974/*
975 * PowerPC needs eight modes for different hypervisor/supervisor/guest
976 * + real/paged mode combinations. The other two modes are for
977 * external PID load/store.
50728199 978 */
50728199
RK		 979#define PPC_TLB_EPID_LOAD 8
980#define PPC_TLB_EPID_STORE 9
6ebbf390 981
54ff58bb
BR		 982#define PPC_CPU_OPCODES_LEN 0x40
983#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
b048960f 984
3fc6c082 985struct CPUPPCState {
ad5db2e7
BZ		 986 /* Most commonly used resources during translated code execution first */
987 target_ulong gpr[32]; /* general purpose registers */
988 target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extension */
3fc6c082 989 target_ulong lr;
3fc6c082 990 target_ulong ctr;
ad5db2e7 991 uint32_t crf[8]; /* condition register */
697ab892 992#if defined(TARGET_PPC64)
697ab892
DG		 993 target_ulong cfar;
994#endif
ad5db2e7 995 target_ulong xer; /* XER (with SO, OV, CA split out) */
da91a00f
RH		 996 target_ulong so;
997 target_ulong ov;
998 target_ulong ca;
dd09c361
ND		 999 target_ulong ov32;
1000 target_ulong ca32;
3fc6c082 1001
ad5db2e7
BZ		 1002 target_ulong reserve_addr; /* Reservation address */
1003 target_ulong reserve_val; /* Reservation value */
1004 target_ulong reserve_val2;
3fc6c082 1005
ad5db2e7
BZ		 1006 /* These are used in supervisor mode only */
1007 target_ulong msr; /* machine state register */
1008 target_ulong tgpr[4]; /* temporary general purpose registers, */
1009 /* used to speed-up TLB assist handlers */
a316d335 1010
ad5db2e7
BZ		 1011 target_ulong nip; /* next instruction pointer */
1012 uint64_t retxh; /* high part of 128-bit helper return */
94bf2658 1013
c647e3fe
DG		 1014 /* when a memory exception occurs, the access type is stored here */
1015 int access_type;
a541f297 1016
f2e63a42 1017#if !defined(CONFIG_USER_ONLY)
ad5db2e7 1018 /* MMU context, only relevant for full system emulation */
f2e63a42 1019#if defined(TARGET_PPC64)
ad5db2e7 1020 ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */
f2e63a42 1021#endif
ad5db2e7
BZ		 1022 target_ulong sr[32]; /* segment registers */
1023 uint32_t nb_BATs; /* number of BATs */
3fc6c082
FB		 1024 target_ulong DBAT[2][8];
1025 target_ulong IBAT[2][8];
01662f3e 1026 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
ad5db2e7 1027 int32_t nb_tlb; /* Total number of TLB */
f2e63a42 1028 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
ad5db2e7
BZ		 1029 int nb_ways; /* Number of ways in the TLB set */
1030 int last_way; /* Last used way used to allocate TLB in a LRU way */
f2e63a42 1031 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
ad5db2e7
BZ		 1032 int nb_pids; /* Number of available PID registers */
1033 int tlb_type; /* Type of TLB we're dealing with */
1034 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1035 target_ulong pb[4]; /* 403 dedicated access protection registers */
1036 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1037 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
c5a8d8f3 1038 uint32_t tlb_need_flush; /* Delayed flush needed */
a8a6d53e 1039#define TLB_NEED_LOCAL_FLUSH 0x1
d76ab5e1 1040#define TLB_NEED_GLOBAL_FLUSH 0x2
f2e63a42 1041#endif
9fddaa0c 1042
3fc6c082 1043 /* Other registers */
ad5db2e7 1044 target_ulong spr[1024]; /* special purpose registers */
c227f099 1045 ppc_spr_t spr_cb[1024];
ad5db2e7 1046 /* Vector status and control register, minus VSCR_SAT */
3fc6c082 1047 uint32_t vscr;
ef96e3ae
MCA		 1048 /* VSX registers (including FP and AVR) */
1049 ppc_vsr_t vsr[64] QEMU_ALIGNED(16);
ad5db2e7 1050 /* Non-zero if and only if VSCR_SAT should be set */
9b5b74da 1051 ppc_vsr_t vscr_sat QEMU_ALIGNED(16);
d9bce9d9 1052 /* SPE registers */
2231ef10 1053 uint64_t spe_acc;
d9bce9d9 1054 uint32_t spe_fscr;
ad5db2e7 1055 /* SPE and Altivec share status as they'll never be used simultaneously */
fbd265b6 1056 float_status vec_status;
ad5db2e7
BZ		 1057 float_status fp_status; /* Floating point execution context */
1058 target_ulong fpscr; /* Floating point status and control register */
3fc6c082
FB		 1059
1060 /* Internal devices resources */
ad5db2e7
BZ		 1061 ppc_tb_t *tb_env; /* Time base and decrementer */
1062 ppc_dcr_t *dcr_env; /* Device control registers */
3fc6c082 1063
d63001d1
JM		 1064 int dcache_line_size;
1065 int icache_line_size;
1066
ad5db2e7 1067 /* These resources are used during exception processing */
3fc6c082 1068 /* CPU model definition */
a750fc0b 1069 target_ulong msr_mask;
c227f099
AL		 1070 powerpc_mmu_t mmu_model;
1071 powerpc_excp_t excp_model;
1072 powerpc_input_t bus_model;
237c0af0 1073 int bfd_mach;
3fc6c082 1074 uint32_t flags;
c29b735c 1075 uint64_t insns_flags;
a5858d7a 1076 uint64_t insns_flags2;
3fc6c082 1077
3fc6c082 1078 int error_code;
47103572 1079 uint32_t pending_interrupts;
e9df014c 1080#if !defined(CONFIG_USER_ONLY)
c647e3fe 1081 /*
ad5db2e7
BZ		 1082 * This is the IRQ controller, which is implementation dependent and only
1083 * relevant when emulating a complete machine. Note that this isn't used
1084 * by recent Book3s compatible CPUs (POWER7 and newer).
e9df014c
JM		 1085 */
1086 uint32_t irq_input_state;
1087 void **irq_inputs;
ad5db2e7
BZ		 1088
1089 target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
e1833e1f
JM		 1090 target_ulong excp_prefix;
1091 target_ulong ivor_mask;
1092 target_ulong ivpr_mask;
d63001d1 1093 target_ulong hreset_vector;
68c2dd70 1094 hwaddr mpic_iack;
ad5db2e7
BZ		 1095 bool mpic_proxy; /* true if the external proxy facility mode is enabled */
1096 bool has_hv_mode; /* set when the processor has an HV mode, thus HV priv */
1097 /* instructions and SPRs are diallowed if MSR:HV is 0 */
21c0d66a 1098 /*
ad5db2e7
BZ		 1099 * On P7/P8/P9, set when in PM state so we need to handle resume in a
1100 * special way (such as routing some resume causes to 0x100, i.e. sreset).
7778a575 1101 */
1e7fd61d 1102 bool resume_as_sreset;
e9df014c 1103#endif
3fc6c082 1104
ad5db2e7
BZ		 1105 /* These resources are used only in QEMU core */
1106 target_ulong hflags; /* hflags is MSR & HFLAGS_MASK */
4abf79a4 1107 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
ad5db2e7
BZ		 1108 int immu_idx; /* precomputed MMU index to speed up insn accesses */
1109 int dmmu_idx; /* precomputed MMU index to speed up data accesses */
3fc6c082 1110
9fddaa0c 1111 /* Power management */
cd346349 1112 int (*check_pow)(CPUPPCState *env);
a541f297 1113
2c50e26e 1114#if !defined(CONFIG_USER_ONLY)
ad5db2e7 1115 void *load_info; /* holds boot loading state */
2c50e26e 1116#endif
ddd1055b
FC		 1117
1118 /* booke timers */
1119
c647e3fe 1120 /*
ad5db2e7
BZ		 1121 * Specifies bit locations of the Time Base used to signal a fixed timer
1122 * exception on a transition from 0 to 1 (watchdog or fixed-interval timer)
ddd1055b 1123 *
ad5db2e7 1124 * 0 selects the least significant bit, 63 selects the most significant bit
ddd1055b
FC		 1125 */
1126 uint8_t fit_period[4];
1127 uint8_t wdt_period[4];
80b3f79b
AK		 1128
1129 /* Transactional memory state */
1130 target_ulong tm_gpr[32];
1131 ppc_avr_t tm_vsr[64];
1132 uint64_t tm_cr;
1133 uint64_t tm_lr;
1134 uint64_t tm_ctr;
1135 uint64_t tm_fpscr;
1136 uint64_t tm_amr;
1137 uint64_t tm_ppr;
1138 uint64_t tm_vrsave;
1139 uint32_t tm_vscr;
1140 uint64_t tm_dscr;
1141 uint64_t tm_tar;
3fc6c082 1142};
79aceca5 1143
ddd1055b
FC		 1144#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1145do { \
1146 env->fit_period[0] = (a_); \
1147 env->fit_period[1] = (b_); \
1148 env->fit_period[2] = (c_); \
1149 env->fit_period[3] = (d_); \
1150 } while (0)
1151
1152#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1153do { \
1154 env->wdt_period[0] = (a_); \
1155 env->wdt_period[1] = (b_); \
1156 env->wdt_period[2] = (c_); \
1157 env->wdt_period[3] = (d_); \
1158 } while (0)
1159
1d1be34d
DG		 1160typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
1161typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
0d8d6a24 1162
2d34fe39
PB		 1163/**
1164 * PowerPCCPU:
1165 * @env: #CPUPPCState
81210c20 1166 * @vcpu_id: vCPU identifier given to KVM
d6e166c0 1167 * @compat_pvr: Current logical PVR, zero if in "raw" mode
2d34fe39
PB		 1168 *
1169 * A PowerPC CPU.
1170 */
1171struct PowerPCCPU {
1172 /*< private >*/
1173 CPUState parent_obj;
1174 /*< public >*/
1175
5b146dc7 1176 CPUNegativeOffsetState neg;
2d34fe39 1177 CPUPPCState env;
5b146dc7 1178
81210c20 1179 int vcpu_id;
d6e166c0 1180 uint32_t compat_pvr;
1d1be34d 1181 PPCVirtualHypervisor *vhyp;
7388efaf 1182 void *machine_data;
15f8b142 1183 int32_t node_id; /* NUMA node this CPU belongs to */
b07c59f7 1184 PPCHash64Options *hash64_opts;
16a2497b 1185
28876bf2
AB		 1186 /* Those resources are used only during code translation */
1187 /* opcode handlers */
1188 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1189
146c11f1
DG		 1190 /* Fields related to migration compatibility hacks */
1191 bool pre_2_8_migration;
16a2497b
DG		 1192 target_ulong mig_msr_mask;
1193 uint64_t mig_insns_flags;
1194 uint64_t mig_insns_flags2;
1195 uint32_t mig_nb_BATs;
d5fc133e 1196 bool pre_2_10_migration;
d8c0c7af 1197 bool pre_3_0_migration;
67d7d66f 1198 int32_t mig_slb_nr;
2d34fe39
PB		 1199};
1200
2d34fe39
PB		 1201
1202PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
1203PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
e9edd931 1204PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
2d34fe39 1205
e89aac1a 1206#ifndef CONFIG_USER_ONLY
1d1be34d
DG		 1207struct PPCVirtualHypervisorClass {
1208 InterfaceClass parent;
1209 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
e57ca75c
DG		 1210 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
1211 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
1212 hwaddr ptex, int n);
1213 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp,
1214 const ppc_hash_pte64_t *hptes,
1215 hwaddr ptex, int n);
a2dd4e83
BH		 1216 void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
1217 void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
79825f4d 1218 void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
1ec26c75 1219 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
03ef074c
NP		 1220 void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1221 void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
1d1be34d
DG		 1222};
1223
1224#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
1225#define PPC_VIRTUAL_HYPERVISOR(obj) \
1226 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
1227#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
1228 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
1229 TYPE_PPC_VIRTUAL_HYPERVISOR)
1230#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
1231 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
1232 TYPE_PPC_VIRTUAL_HYPERVISOR)
e89aac1a 1233#endif /* CONFIG_USER_ONLY */
1d1be34d 1234
2d34fe39
PB		 1235void ppc_cpu_do_interrupt(CPUState *cpu);
1236bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
90c84c56 1237void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
11cb6c15 1238void ppc_cpu_dump_statistics(CPUState *cpu, int flags);
2d34fe39 1239hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
a010bdbe
AB		 1240int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1241int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int reg);
2d34fe39
PB		 1242int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1243int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
707c7c2e
FR		 1244#ifndef CONFIG_USER_ONLY
1245void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu);
1246const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name);
1247#endif
2d34fe39
PB		 1248int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1249 int cpuid, void *opaque);
356bb70e
MN		 1250int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1251 int cpuid, void *opaque);
2d34fe39 1252#ifndef CONFIG_USER_ONLY
b5b7f391 1253void ppc_cpu_do_system_reset(CPUState *cs);
ad77c6ca 1254void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector);
8a9358cc 1255extern const VMStateDescription vmstate_ppc_cpu;
2d34fe39 1256#endif
1d0cb67d 1257
3fc6c082 1258/*****************************************************************************/
2e70f6ef 1259void ppc_translate_init(void);
c647e3fe
DG		 1260/*
1261 * you can call this signal handler from your SIGBUS and SIGSEGV
1262 * signal handlers to inform the virtual CPU of exceptions. non zero
1263 * is returned if the signal was handled by the virtual CPU.
1264 */
1265int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
351bc97e
RH		 1266bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1267 MMUAccessType access_type, int mmu_idx,
1268 bool probe, uintptr_t retaddr);
a541f297 1269
76a66253 1270#if !defined(CONFIG_USER_ONLY)
c647e3fe 1271void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
4a7518e0 1272void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
12de9a39 1273#endif /* !defined(CONFIG_USER_ONLY) */
c647e3fe 1274void ppc_store_msr(CPUPPCState *env, target_ulong value);
3fc6c082 1275
0442428a 1276void ppc_cpu_list(void);
aaed909a 1277
9fddaa0c
FB		 1278/* Time-base and decrementer management */
1279#ifndef NO_CPU_IO_DEFS
c647e3fe
DG		 1280uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
1281uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
1282void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
1283void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
1284uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
1285uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
1286void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
1287void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
5d62725b
SJS		 1288uint64_t cpu_ppc_load_vtb(CPUPPCState *env);
1289void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value);
e81a982a 1290bool ppc_decr_clear_on_delivery(CPUPPCState *env);
a8dafa52
SJS		 1291target_ulong cpu_ppc_load_decr(CPUPPCState *env);
1292void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
1293target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
1294void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
f0ec31b1 1295void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value);
c647e3fe 1296uint64_t cpu_ppc_load_purr(CPUPPCState *env);
5cc7e69f 1297void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value);
c647e3fe
DG		 1298uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
1299uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
d9bce9d9 1300#if !defined(CONFIG_USER_ONLY)
c647e3fe
DG		 1301void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
1302void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
1303target_ulong load_40x_pit(CPUPPCState *env);
1304void store_40x_pit(CPUPPCState *env, target_ulong val);
1305void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
1306void store_40x_sler(CPUPPCState *env, uint32_t val);
1307void store_booke_tcr(CPUPPCState *env, target_ulong val);
1308void store_booke_tsr(CPUPPCState *env, target_ulong val);
1309void ppc_tlb_invalidate_all(CPUPPCState *env);
1310void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
da20aed1 1311void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
d9bce9d9 1312#endif
9fddaa0c 1313#endif
79aceca5 1314
d6478bc7 1315void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
493028d8
CLG		 1316void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
1317 const char *caller, uint32_t cause);
d6478bc7 1318
636aa200 1319static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
6b542af7
JM		 1320{
1321 uint64_t gprv;
1322
1323 gprv = env->gpr[gprn];
6b542af7 1324 if (env->flags & POWERPC_FLAG_SPE) {
c647e3fe
DG		 1325 /*
1326 * If the CPU implements the SPE extension, we have to get the
6b542af7
JM		 1327 * high bits of the GPR from the gprh storage area
1328 */
1329 gprv &= 0xFFFFFFFFULL;
1330 gprv |= (uint64_t)env->gprh[gprn] << 32;
1331 }
6b542af7
JM		 1332
1333 return gprv;
1334}
1335
2e719ba3 1336/* Device control registers */
c647e3fe
DG		 1337int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1338int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
2e719ba3 1339
c9137065
IM		 1340#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
1341#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
0dacec87 1342#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU
c9137065 1343
9467d44c 1344#define cpu_signal_handler cpu_ppc_signal_handler
c732abe2 1345#define cpu_list ppc_cpu_list
9467d44c 1346
6ebbf390 1347/* MMU modes definitions */
6ebbf390 1348#define MMU_USER_IDX 0
c647e3fe 1349static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
6ebbf390 1350{
9fb04491 1351 return ifetch ? env->immu_idx : env->dmmu_idx;
6ebbf390
JM		 1352}
1353
9d6f1065
DG		 1354/* Compatibility modes */
1355#if defined(TARGET_PPC64)
9d2179d6
DG		 1356bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
1357 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
ad99d04c
DG		 1358bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr,
1359 uint32_t min_compat_pvr, uint32_t max_compat_pvr);
1360
9d6f1065 1361void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
ad99d04c 1362
f6f242c7
DG		 1363#if !defined(CONFIG_USER_ONLY)
1364void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
1365#endif
abbc1247 1366int ppc_compat_max_vthreads(PowerPCCPU *cpu);
7843c0d6 1367void ppc_compat_add_property(Object *obj, const char *name,
40c2281c 1368 uint32_t *compat_pvr, const char *basedesc);
9d6f1065
DG		 1369#endif /* defined(TARGET_PPC64) */
1370
4f7c64b3 1371typedef CPUPPCState CPUArchState;
2161a612 1372typedef PowerPCCPU ArchCPU;
4f7c64b3 1373
022c62cb 1374#include "exec/cpu-all.h"
79aceca5 1375
3fc6c082 1376/*****************************************************************************/
e1571908 1377/* CRF definitions */
efa73196
ND		 1378#define CRF_LT_BIT 3
1379#define CRF_GT_BIT 2
1380#define CRF_EQ_BIT 1
1381#define CRF_SO_BIT 0
1382#define CRF_LT (1 << CRF_LT_BIT)
1383#define CRF_GT (1 << CRF_GT_BIT)
1384#define CRF_EQ (1 << CRF_EQ_BIT)
1385#define CRF_SO (1 << CRF_SO_BIT)
1386/* For SPE extensions */
1387#define CRF_CH (1 << CRF_LT_BIT)
1388#define CRF_CL (1 << CRF_GT_BIT)
1389#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
1390#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
e1571908
AJ		 1391
1392/* XER definitions */
3d7b417e
AJ		 1393#define XER_SO 31
1394#define XER_OV 30
1395#define XER_CA 29
dd09c361
ND		 1396#define XER_OV32 19
1397#define XER_CA32 18
3d7b417e
AJ		 1398#define XER_CMP 8
1399#define XER_BC 0
da91a00f
RH		 1400#define xer_so (env->so)
1401#define xer_ov (env->ov)
1402#define xer_ca (env->ca)
dd09c361
ND		 1403#define xer_ov32 (env->ov)
1404#define xer_ca32 (env->ca)
3d7b417e
AJ		 1405#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1406#define xer_bc ((env->xer >> XER_BC) & 0x7F)
79aceca5 1407
3fc6c082 1408/* SPR definitions */
80d11f44
JM		 1409#define SPR_MQ (0x000)
1410#define SPR_XER (0x001)
1411#define SPR_601_VRTCU (0x004)
1412#define SPR_601_VRTCL (0x005)
1413#define SPR_601_UDECR (0x006)
1414#define SPR_LR (0x008)
1415#define SPR_CTR (0x009)
f244115c 1416#define SPR_UAMR (0x00D)
697ab892 1417#define SPR_DSCR (0x011)
80d11f44
JM		 1418#define SPR_DSISR (0x012)
1419#define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1420#define SPR_601_RTCU (0x014)
1421#define SPR_601_RTCL (0x015)
1422#define SPR_DECR (0x016)
1423#define SPR_SDR1 (0x019)
1424#define SPR_SRR0 (0x01A)
1425#define SPR_SRR1 (0x01B)
697ab892 1426#define SPR_CFAR (0x01C)
80d11f44 1427#define SPR_AMR (0x01D)
9c1cf38d 1428#define SPR_ACOP (0x01F)
80d11f44 1429#define SPR_BOOKE_PID (0x030)
9c1cf38d 1430#define SPR_BOOKS_PID (0x030)
80d11f44
JM		 1431#define SPR_BOOKE_DECAR (0x036)
1432#define SPR_BOOKE_CSRR0 (0x03A)
1433#define SPR_BOOKE_CSRR1 (0x03B)
1434#define SPR_BOOKE_DEAR (0x03D)
a6eabb9e 1435#define SPR_IAMR (0x03D)
80d11f44
JM		 1436#define SPR_BOOKE_ESR (0x03E)
1437#define SPR_BOOKE_IVPR (0x03F)
1438#define SPR_MPC_EIE (0x050)
1439#define SPR_MPC_EID (0x051)
1440#define SPR_MPC_NRI (0x052)
cdcdda27
AK		 1441#define SPR_TFHAR (0x080)
1442#define SPR_TFIAR (0x081)
1443#define SPR_TEXASR (0x082)
1444#define SPR_TEXASRU (0x083)
0bfe9299 1445#define SPR_UCTRL (0x088)
650f3287 1446#define SPR_TIDR (0x090)
80d11f44
JM		 1447#define SPR_MPC_CMPA (0x090)
1448#define SPR_MPC_CMPB (0x091)
1449#define SPR_MPC_CMPC (0x092)
1450#define SPR_MPC_CMPD (0x093)
1451#define SPR_MPC_ECR (0x094)
1452#define SPR_MPC_DER (0x095)
1453#define SPR_MPC_COUNTA (0x096)
1454#define SPR_MPC_COUNTB (0x097)
0bfe9299 1455#define SPR_CTRL (0x098)
80d11f44
JM		 1456#define SPR_MPC_CMPE (0x098)
1457#define SPR_MPC_CMPF (0x099)
7019cb3d 1458#define SPR_FSCR (0x099)
80d11f44
JM		 1459#define SPR_MPC_CMPG (0x09A)
1460#define SPR_MPC_CMPH (0x09B)
1461#define SPR_MPC_LCTRL1 (0x09C)
1462#define SPR_MPC_LCTRL2 (0x09D)
f80872e2 1463#define SPR_UAMOR (0x09D)
80d11f44
JM		 1464#define SPR_MPC_ICTRL (0x09E)
1465#define SPR_MPC_BAR (0x09F)
d6f1445f 1466#define SPR_PSPB (0x09F)
cfc61ba6 1467#define SPR_DPDES (0x0B0)
1488270e
BH		 1468#define SPR_DAWR (0x0B4)
1469#define SPR_RPR (0x0BA)
eb5ceb4d 1470#define SPR_CIABR (0x0BB)
1488270e
BH		 1471#define SPR_DAWRX (0x0BC)
1472#define SPR_HFSCR (0x0BE)
80d11f44
JM		 1473#define SPR_VRSAVE (0x100)
1474#define SPR_USPRG0 (0x100)
1475#define SPR_USPRG1 (0x101)
1476#define SPR_USPRG2 (0x102)
1477#define SPR_USPRG3 (0x103)
1478#define SPR_USPRG4 (0x104)
1479#define SPR_USPRG5 (0x105)
1480#define SPR_USPRG6 (0x106)
1481#define SPR_USPRG7 (0x107)
1482#define SPR_VTBL (0x10C)
1483#define SPR_VTBU (0x10D)
1484#define SPR_SPRG0 (0x110)
1485#define SPR_SPRG1 (0x111)
1486#define SPR_SPRG2 (0x112)
1487#define SPR_SPRG3 (0x113)
1488#define SPR_SPRG4 (0x114)
1489#define SPR_SCOMC (0x114)
1490#define SPR_SPRG5 (0x115)
1491#define SPR_SCOMD (0x115)
1492#define SPR_SPRG6 (0x116)
1493#define SPR_SPRG7 (0x117)
1494#define SPR_ASR (0x118)
1495#define SPR_EAR (0x11A)
1496#define SPR_TBL (0x11C)
1497#define SPR_TBU (0x11D)
1498#define SPR_TBU40 (0x11E)
1499#define SPR_SVR (0x11E)
1500#define SPR_BOOKE_PIR (0x11E)
1501#define SPR_PVR (0x11F)
1502#define SPR_HSPRG0 (0x130)
1503#define SPR_BOOKE_DBSR (0x130)
1504#define SPR_HSPRG1 (0x131)
1505#define SPR_HDSISR (0x132)
1506#define SPR_HDAR (0x133)
90dc8812 1507#define SPR_BOOKE_EPCR (0x133)
9d52e907 1508#define SPR_SPURR (0x134)
80d11f44
JM		 1509#define SPR_BOOKE_DBCR0 (0x134)
1510#define SPR_IBCR (0x135)
1511#define SPR_PURR (0x135)
1512#define SPR_BOOKE_DBCR1 (0x135)
1513#define SPR_DBCR (0x136)
1514#define SPR_HDEC (0x136)
1515#define SPR_BOOKE_DBCR2 (0x136)
1516#define SPR_HIOR (0x137)
1517#define SPR_MBAR (0x137)
1518#define SPR_RMOR (0x138)
1519#define SPR_BOOKE_IAC1 (0x138)
1520#define SPR_HRMOR (0x139)
1521#define SPR_BOOKE_IAC2 (0x139)
1522#define SPR_HSRR0 (0x13A)
1523#define SPR_BOOKE_IAC3 (0x13A)
1524#define SPR_HSRR1 (0x13B)
1525#define SPR_BOOKE_IAC4 (0x13B)
80d11f44 1526#define SPR_BOOKE_DAC1 (0x13C)
1488270e 1527#define SPR_MMCRH (0x13C)
80d11f44
JM		 1528#define SPR_DABR2 (0x13D)
1529#define SPR_BOOKE_DAC2 (0x13D)
1488270e 1530#define SPR_TFMR (0x13D)
80d11f44 1531#define SPR_BOOKE_DVC1 (0x13E)
6475c9f0 1532#define SPR_LPCR (0x13E)
80d11f44 1533#define SPR_BOOKE_DVC2 (0x13F)
1488270e 1534#define SPR_LPIDR (0x13F)
80d11f44 1535#define SPR_BOOKE_TSR (0x150)
1488270e
BH		 1536#define SPR_HMER (0x150)
1537#define SPR_HMEER (0x151)
6d9412ea 1538#define SPR_PCR (0x152)
1488270e 1539#define SPR_BOOKE_LPIDR (0x152)
80d11f44 1540#define SPR_BOOKE_TCR (0x154)
a1ef618a
AG		 1541#define SPR_BOOKE_TLB0PS (0x158)
1542#define SPR_BOOKE_TLB1PS (0x159)
1543#define SPR_BOOKE_TLB2PS (0x15A)
1544#define SPR_BOOKE_TLB3PS (0x15B)
1488270e 1545#define SPR_AMOR (0x15D)
84755ed5 1546#define SPR_BOOKE_MAS7_MAS3 (0x174)
80d11f44
JM		 1547#define SPR_BOOKE_IVOR0 (0x190)
1548#define SPR_BOOKE_IVOR1 (0x191)
1549#define SPR_BOOKE_IVOR2 (0x192)
1550#define SPR_BOOKE_IVOR3 (0x193)
1551#define SPR_BOOKE_IVOR4 (0x194)
1552#define SPR_BOOKE_IVOR5 (0x195)
1553#define SPR_BOOKE_IVOR6 (0x196)
1554#define SPR_BOOKE_IVOR7 (0x197)
1555#define SPR_BOOKE_IVOR8 (0x198)
1556#define SPR_BOOKE_IVOR9 (0x199)
1557#define SPR_BOOKE_IVOR10 (0x19A)
1558#define SPR_BOOKE_IVOR11 (0x19B)
1559#define SPR_BOOKE_IVOR12 (0x19C)
1560#define SPR_BOOKE_IVOR13 (0x19D)
1561#define SPR_BOOKE_IVOR14 (0x19E)
1562#define SPR_BOOKE_IVOR15 (0x19F)
e9205258
AG		 1563#define SPR_BOOKE_IVOR38 (0x1B0)
1564#define SPR_BOOKE_IVOR39 (0x1B1)
1565#define SPR_BOOKE_IVOR40 (0x1B2)
1566#define SPR_BOOKE_IVOR41 (0x1B3)
1567#define SPR_BOOKE_IVOR42 (0x1B4)
45eb5611
AG		 1568#define SPR_BOOKE_GIVOR2 (0x1B8)
1569#define SPR_BOOKE_GIVOR3 (0x1B9)
1570#define SPR_BOOKE_GIVOR4 (0x1BA)
1571#define SPR_BOOKE_GIVOR8 (0x1BB)
1572#define SPR_BOOKE_GIVOR13 (0x1BC)
1573#define SPR_BOOKE_GIVOR14 (0x1BD)
d1a721ab 1574#define SPR_TIR (0x1BE)
4a7518e0 1575#define SPR_PTCR (0x1D0)
80d11f44
JM		 1576#define SPR_BOOKE_SPEFSCR (0x200)
1577#define SPR_Exxx_BBEAR (0x201)
1578#define SPR_Exxx_BBTAR (0x202)
1579#define SPR_Exxx_L1CFG0 (0x203)
d2ea2bf7 1580#define SPR_Exxx_L1CFG1 (0x204)
80d11f44
JM		 1581#define SPR_Exxx_NPIDR (0x205)
1582#define SPR_ATBL (0x20E)
1583#define SPR_ATBU (0x20F)
1584#define SPR_IBAT0U (0x210)
1585#define SPR_BOOKE_IVOR32 (0x210)
1586#define SPR_RCPU_MI_GRA (0x210)
1587#define SPR_IBAT0L (0x211)
1588#define SPR_BOOKE_IVOR33 (0x211)
1589#define SPR_IBAT1U (0x212)
1590#define SPR_BOOKE_IVOR34 (0x212)
1591#define SPR_IBAT1L (0x213)
1592#define SPR_BOOKE_IVOR35 (0x213)
1593#define SPR_IBAT2U (0x214)
1594#define SPR_BOOKE_IVOR36 (0x214)
1595#define SPR_IBAT2L (0x215)
1596#define SPR_BOOKE_IVOR37 (0x215)
1597#define SPR_IBAT3U (0x216)
1598#define SPR_IBAT3L (0x217)
1599#define SPR_DBAT0U (0x218)
1600#define SPR_RCPU_L2U_GRA (0x218)
1601#define SPR_DBAT0L (0x219)
1602#define SPR_DBAT1U (0x21A)
1603#define SPR_DBAT1L (0x21B)
1604#define SPR_DBAT2U (0x21C)
1605#define SPR_DBAT2L (0x21D)
1606#define SPR_DBAT3U (0x21E)
1607#define SPR_DBAT3L (0x21F)
1608#define SPR_IBAT4U (0x230)
1609#define SPR_RPCU_BBCMCR (0x230)
1610#define SPR_MPC_IC_CST (0x230)
1611#define SPR_Exxx_CTXCR (0x230)
1612#define SPR_IBAT4L (0x231)
1613#define SPR_MPC_IC_ADR (0x231)
1614#define SPR_Exxx_DBCR3 (0x231)
1615#define SPR_IBAT5U (0x232)
1616#define SPR_MPC_IC_DAT (0x232)
1617#define SPR_Exxx_DBCNT (0x232)
1618#define SPR_IBAT5L (0x233)
1619#define SPR_IBAT6U (0x234)
1620#define SPR_IBAT6L (0x235)
1621#define SPR_IBAT7U (0x236)
1622#define SPR_IBAT7L (0x237)
1623#define SPR_DBAT4U (0x238)
1624#define SPR_RCPU_L2U_MCR (0x238)
1625#define SPR_MPC_DC_CST (0x238)
1626#define SPR_Exxx_ALTCTXCR (0x238)
1627#define SPR_DBAT4L (0x239)
1628#define SPR_MPC_DC_ADR (0x239)
1629#define SPR_DBAT5U (0x23A)
1630#define SPR_BOOKE_MCSRR0 (0x23A)
1631#define SPR_MPC_DC_DAT (0x23A)
1632#define SPR_DBAT5L (0x23B)
1633#define SPR_BOOKE_MCSRR1 (0x23B)
1634#define SPR_DBAT6U (0x23C)
1635#define SPR_BOOKE_MCSR (0x23C)
1636#define SPR_DBAT6L (0x23D)
1637#define SPR_Exxx_MCAR (0x23D)
1638#define SPR_DBAT7U (0x23E)
1639#define SPR_BOOKE_DSRR0 (0x23E)
1640#define SPR_DBAT7L (0x23F)
1641#define SPR_BOOKE_DSRR1 (0x23F)
1642#define SPR_BOOKE_SPRG8 (0x25C)
1643#define SPR_BOOKE_SPRG9 (0x25D)
1644#define SPR_BOOKE_MAS0 (0x270)
1645#define SPR_BOOKE_MAS1 (0x271)
1646#define SPR_BOOKE_MAS2 (0x272)
1647#define SPR_BOOKE_MAS3 (0x273)
1648#define SPR_BOOKE_MAS4 (0x274)
1649#define SPR_BOOKE_MAS5 (0x275)
1650#define SPR_BOOKE_MAS6 (0x276)
1651#define SPR_BOOKE_PID1 (0x279)
1652#define SPR_BOOKE_PID2 (0x27A)
1653#define SPR_MPC_DPDR (0x280)
1654#define SPR_MPC_IMMR (0x288)
1655#define SPR_BOOKE_TLB0CFG (0x2B0)
1656#define SPR_BOOKE_TLB1CFG (0x2B1)
1657#define SPR_BOOKE_TLB2CFG (0x2B2)
1658#define SPR_BOOKE_TLB3CFG (0x2B3)
1659#define SPR_BOOKE_EPR (0x2BE)
1660#define SPR_PERF0 (0x300)
1661#define SPR_RCPU_MI_RBA0 (0x300)
1662#define SPR_MPC_MI_CTR (0x300)
14646457 1663#define SPR_POWER_USIER (0x300)
80d11f44
JM		 1664#define SPR_PERF1 (0x301)
1665#define SPR_RCPU_MI_RBA1 (0x301)
70c53407 1666#define SPR_POWER_UMMCR2 (0x301)
80d11f44
JM		 1667#define SPR_PERF2 (0x302)
1668#define SPR_RCPU_MI_RBA2 (0x302)
1669#define SPR_MPC_MI_AP (0x302)
75b9c321 1670#define SPR_POWER_UMMCRA (0x302)
80d11f44
JM		 1671#define SPR_PERF3 (0x303)
1672#define SPR_RCPU_MI_RBA3 (0x303)
1673#define SPR_MPC_MI_EPN (0x303)
fd51ff63 1674#define SPR_POWER_UPMC1 (0x303)
80d11f44 1675#define SPR_PERF4 (0x304)
fd51ff63 1676#define SPR_POWER_UPMC2 (0x304)
80d11f44
JM		 1677#define SPR_PERF5 (0x305)
1678#define SPR_MPC_MI_TWC (0x305)
fd51ff63 1679#define SPR_POWER_UPMC3 (0x305)
80d11f44
JM		 1680#define SPR_PERF6 (0x306)
1681#define SPR_MPC_MI_RPN (0x306)
fd51ff63 1682#define SPR_POWER_UPMC4 (0x306)
80d11f44 1683#define SPR_PERF7 (0x307)
fd51ff63 1684#define SPR_POWER_UPMC5 (0x307)
80d11f44
JM		 1685#define SPR_PERF8 (0x308)
1686#define SPR_RCPU_L2U_RBA0 (0x308)
1687#define SPR_MPC_MD_CTR (0x308)
fd51ff63 1688#define SPR_POWER_UPMC6 (0x308)
80d11f44
JM		 1689#define SPR_PERF9 (0x309)
1690#define SPR_RCPU_L2U_RBA1 (0x309)
1691#define SPR_MPC_MD_CASID (0x309)
c36c97f8 1692#define SPR_970_UPMC7 (0X309)
80d11f44
JM		 1693#define SPR_PERFA (0x30A)
1694#define SPR_RCPU_L2U_RBA2 (0x30A)
1695#define SPR_MPC_MD_AP (0x30A)
c36c97f8 1696#define SPR_970_UPMC8 (0X30A)
80d11f44
JM		 1697#define SPR_PERFB (0x30B)
1698#define SPR_RCPU_L2U_RBA3 (0x30B)
1699#define SPR_MPC_MD_EPN (0x30B)
fd51ff63 1700#define SPR_POWER_UMMCR0 (0X30B)
80d11f44
JM		 1701#define SPR_PERFC (0x30C)
1702#define SPR_MPC_MD_TWB (0x30C)
fd51ff63 1703#define SPR_POWER_USIAR (0X30C)
80d11f44
JM		 1704#define SPR_PERFD (0x30D)
1705#define SPR_MPC_MD_TWC (0x30D)
fd51ff63 1706#define SPR_POWER_USDAR (0X30D)
80d11f44
JM		 1707#define SPR_PERFE (0x30E)
1708#define SPR_MPC_MD_RPN (0x30E)
fd51ff63 1709#define SPR_POWER_UMMCR1 (0X30E)
80d11f44
JM		 1710#define SPR_PERFF (0x30F)
1711#define SPR_MPC_MD_TW (0x30F)
1712#define SPR_UPERF0 (0x310)
14646457 1713#define SPR_POWER_SIER (0x310)
80d11f44 1714#define SPR_UPERF1 (0x311)
70c53407 1715#define SPR_POWER_MMCR2 (0x311)
80d11f44 1716#define SPR_UPERF2 (0x312)
75b9c321 1717#define SPR_POWER_MMCRA (0X312)
80d11f44 1718#define SPR_UPERF3 (0x313)
fd51ff63 1719#define SPR_POWER_PMC1 (0X313)
80d11f44 1720#define SPR_UPERF4 (0x314)
fd51ff63 1721#define SPR_POWER_PMC2 (0X314)
80d11f44 1722#define SPR_UPERF5 (0x315)
fd51ff63 1723#define SPR_POWER_PMC3 (0X315)
80d11f44 1724#define SPR_UPERF6 (0x316)
fd51ff63 1725#define SPR_POWER_PMC4 (0X316)
80d11f44 1726#define SPR_UPERF7 (0x317)
fd51ff63 1727#define SPR_POWER_PMC5 (0X317)
80d11f44 1728#define SPR_UPERF8 (0x318)
fd51ff63 1729#define SPR_POWER_PMC6 (0X318)
80d11f44 1730#define SPR_UPERF9 (0x319)
c36c97f8 1731#define SPR_970_PMC7 (0X319)
80d11f44 1732#define SPR_UPERFA (0x31A)
c36c97f8 1733#define SPR_970_PMC8 (0X31A)
80d11f44 1734#define SPR_UPERFB (0x31B)
fd51ff63 1735#define SPR_POWER_MMCR0 (0X31B)
80d11f44 1736#define SPR_UPERFC (0x31C)
fd51ff63 1737#define SPR_POWER_SIAR (0X31C)
80d11f44 1738#define SPR_UPERFD (0x31D)
fd51ff63 1739#define SPR_POWER_SDAR (0X31D)
80d11f44 1740#define SPR_UPERFE (0x31E)
fd51ff63 1741#define SPR_POWER_MMCR1 (0X31E)
80d11f44
JM		 1742#define SPR_UPERFF (0x31F)
1743#define SPR_RCPU_MI_RA0 (0x320)
1744#define SPR_MPC_MI_DBCAM (0x320)
4ee4a03b 1745#define SPR_BESCRS (0x320)
80d11f44
JM		 1746#define SPR_RCPU_MI_RA1 (0x321)
1747#define SPR_MPC_MI_DBRAM0 (0x321)
4ee4a03b 1748#define SPR_BESCRSU (0x321)
80d11f44
JM		 1749#define SPR_RCPU_MI_RA2 (0x322)
1750#define SPR_MPC_MI_DBRAM1 (0x322)
4ee4a03b 1751#define SPR_BESCRR (0x322)
80d11f44 1752#define SPR_RCPU_MI_RA3 (0x323)
4ee4a03b
AK		 1753#define SPR_BESCRRU (0x323)
1754#define SPR_EBBHR (0x324)
1755#define SPR_EBBRR (0x325)
1756#define SPR_BESCR (0x326)
80d11f44
JM		 1757#define SPR_RCPU_L2U_RA0 (0x328)
1758#define SPR_MPC_MD_DBCAM (0x328)
1759#define SPR_RCPU_L2U_RA1 (0x329)
1760#define SPR_MPC_MD_DBRAM0 (0x329)
1761#define SPR_RCPU_L2U_RA2 (0x32A)
1762#define SPR_MPC_MD_DBRAM1 (0x32A)
1763#define SPR_RCPU_L2U_RA3 (0x32B)
60511041 1764#define SPR_TAR (0x32F)
32d0f0d8 1765#define SPR_ASDR (0x330)
21a558be 1766#define SPR_IC (0x350)
3ba55e39 1767#define SPR_VTB (0x351)
1488270e 1768#define SPR_MMCRC (0x353)
b8af5b2d 1769#define SPR_PSSCR (0x357)
80d11f44
JM		 1770#define SPR_440_INV0 (0x370)
1771#define SPR_440_INV1 (0x371)
1772#define SPR_440_INV2 (0x372)
1773#define SPR_440_INV3 (0x373)
1774#define SPR_440_ITV0 (0x374)
1775#define SPR_440_ITV1 (0x375)
1776#define SPR_440_ITV2 (0x376)
1777#define SPR_440_ITV3 (0x377)
1778#define SPR_440_CCR1 (0x378)
14646457
BH		 1779#define SPR_TACR (0x378)
1780#define SPR_TCSCR (0x379)
1781#define SPR_CSIGR (0x37a)
80d11f44 1782#define SPR_DCRIPR (0x37B)
14646457
BH		 1783#define SPR_POWER_SPMC1 (0x37C)
1784#define SPR_POWER_SPMC2 (0x37D)
70c53407 1785#define SPR_POWER_MMCRS (0x37E)
9c1cf38d 1786#define SPR_WORT (0x37F)
80d11f44 1787#define SPR_PPR (0x380)
bd928eba 1788#define SPR_750_GQR0 (0x390)
80d11f44 1789#define SPR_440_DNV0 (0x390)
bd928eba 1790#define SPR_750_GQR1 (0x391)
80d11f44 1791#define SPR_440_DNV1 (0x391)
bd928eba 1792#define SPR_750_GQR2 (0x392)
80d11f44 1793#define SPR_440_DNV2 (0x392)
bd928eba 1794#define SPR_750_GQR3 (0x393)
80d11f44 1795#define SPR_440_DNV3 (0x393)
bd928eba 1796#define SPR_750_GQR4 (0x394)
80d11f44 1797#define SPR_440_DTV0 (0x394)
bd928eba 1798#define SPR_750_GQR5 (0x395)
80d11f44 1799#define SPR_440_DTV1 (0x395)
bd928eba 1800#define SPR_750_GQR6 (0x396)
80d11f44 1801#define SPR_440_DTV2 (0x396)
bd928eba 1802#define SPR_750_GQR7 (0x397)
80d11f44 1803#define SPR_440_DTV3 (0x397)
bd928eba
JM		 1804#define SPR_750_THRM4 (0x398)
1805#define SPR_750CL_HID2 (0x398)
80d11f44 1806#define SPR_440_DVLIM (0x398)
bd928eba 1807#define SPR_750_WPAR (0x399)
80d11f44 1808#define SPR_440_IVLIM (0x399)
1488270e 1809#define SPR_TSCR (0x399)
bd928eba
JM		 1810#define SPR_750_DMAU (0x39A)
1811#define SPR_750_DMAL (0x39B)
80d11f44
JM		 1812#define SPR_440_RSTCFG (0x39B)
1813#define SPR_BOOKE_DCDBTRL (0x39C)
1814#define SPR_BOOKE_DCDBTRH (0x39D)
1815#define SPR_BOOKE_ICDBTRL (0x39E)
1816#define SPR_BOOKE_ICDBTRH (0x39F)
cb8b8bf8
AK		 1817#define SPR_74XX_UMMCR2 (0x3A0)
1818#define SPR_7XX_UPMC5 (0x3A1)
1819#define SPR_7XX_UPMC6 (0x3A2)
80d11f44 1820#define SPR_UBAMR (0x3A7)
cb8b8bf8
AK		 1821#define SPR_7XX_UMMCR0 (0x3A8)
1822#define SPR_7XX_UPMC1 (0x3A9)
1823#define SPR_7XX_UPMC2 (0x3AA)
1824#define SPR_7XX_USIAR (0x3AB)
1825#define SPR_7XX_UMMCR1 (0x3AC)
1826#define SPR_7XX_UPMC3 (0x3AD)
1827#define SPR_7XX_UPMC4 (0x3AE)
80d11f44
JM		 1828#define SPR_USDA (0x3AF)
1829#define SPR_40x_ZPR (0x3B0)
1830#define SPR_BOOKE_MAS7 (0x3B0)
cb8b8bf8
AK		 1831#define SPR_74XX_MMCR2 (0x3B0)
1832#define SPR_7XX_PMC5 (0x3B1)
80d11f44 1833#define SPR_40x_PID (0x3B1)
cb8b8bf8 1834#define SPR_7XX_PMC6 (0x3B2)
80d11f44 1835#define SPR_440_MMUCR (0x3B2)
80d11f44
JM		 1836#define SPR_4xx_CCR0 (0x3B3)
1837#define SPR_BOOKE_EPLC (0x3B3)
80d11f44
JM		 1838#define SPR_405_IAC3 (0x3B4)
1839#define SPR_BOOKE_EPSC (0x3B4)
80d11f44 1840#define SPR_405_IAC4 (0x3B5)
80d11f44 1841#define SPR_405_DVC1 (0x3B6)
80d11f44 1842#define SPR_405_DVC2 (0x3B7)
80d11f44 1843#define SPR_BAMR (0x3B7)
cb8b8bf8
AK		 1844#define SPR_7XX_MMCR0 (0x3B8)
1845#define SPR_7XX_PMC1 (0x3B9)
80d11f44 1846#define SPR_40x_SGR (0x3B9)
cb8b8bf8 1847#define SPR_7XX_PMC2 (0x3BA)
80d11f44 1848#define SPR_40x_DCWR (0x3BA)
cb8b8bf8 1849#define SPR_7XX_SIAR (0x3BB)
80d11f44 1850#define SPR_405_SLER (0x3BB)
cb8b8bf8 1851#define SPR_7XX_MMCR1 (0x3BC)
80d11f44 1852#define SPR_405_SU0R (0x3BC)
80d11f44 1853#define SPR_401_SKR (0x3BC)
cb8b8bf8 1854#define SPR_7XX_PMC3 (0x3BD)
80d11f44 1855#define SPR_405_DBCR1 (0x3BD)
cb8b8bf8 1856#define SPR_7XX_PMC4 (0x3BE)
80d11f44 1857#define SPR_SDA (0x3BF)
80d11f44
JM		 1858#define SPR_403_VTBL (0x3CC)
1859#define SPR_403_VTBU (0x3CD)
1860#define SPR_DMISS (0x3D0)
1861#define SPR_DCMP (0x3D1)
1862#define SPR_HASH1 (0x3D2)
1863#define SPR_HASH2 (0x3D3)
1864#define SPR_BOOKE_ICDBDR (0x3D3)
1865#define SPR_TLBMISS (0x3D4)
1866#define SPR_IMISS (0x3D4)
1867#define SPR_40x_ESR (0x3D4)
1868#define SPR_PTEHI (0x3D5)
1869#define SPR_ICMP (0x3D5)
1870#define SPR_40x_DEAR (0x3D5)
1871#define SPR_PTELO (0x3D6)
1872#define SPR_RPA (0x3D6)
1873#define SPR_40x_EVPR (0x3D6)
1874#define SPR_L3PM (0x3D7)
1875#define SPR_403_CDBCR (0x3D7)
4e777442 1876#define SPR_L3ITCR0 (0x3D8)
80d11f44
JM		 1877#define SPR_TCR (0x3D8)
1878#define SPR_40x_TSR (0x3D8)
1879#define SPR_IBR (0x3DA)
1880#define SPR_40x_TCR (0x3DA)
1881#define SPR_ESASRR (0x3DB)
1882#define SPR_40x_PIT (0x3DB)
1883#define SPR_403_TBL (0x3DC)
1884#define SPR_403_TBU (0x3DD)
1885#define SPR_SEBR (0x3DE)
1886#define SPR_40x_SRR2 (0x3DE)
1887#define SPR_SER (0x3DF)
1888#define SPR_40x_SRR3 (0x3DF)
4e777442 1889#define SPR_L3OHCR (0x3E8)
80d11f44
JM		 1890#define SPR_L3ITCR1 (0x3E9)
1891#define SPR_L3ITCR2 (0x3EA)
1892#define SPR_L3ITCR3 (0x3EB)
1893#define SPR_HID0 (0x3F0)
1894#define SPR_40x_DBSR (0x3F0)
1895#define SPR_HID1 (0x3F1)
1896#define SPR_IABR (0x3F2)
1897#define SPR_40x_DBCR0 (0x3F2)
1898#define SPR_601_HID2 (0x3F2)
1899#define SPR_Exxx_L1CSR0 (0x3F2)
1900#define SPR_ICTRL (0x3F3)
1901#define SPR_HID2 (0x3F3)
bd928eba 1902#define SPR_750CL_HID4 (0x3F3)
80d11f44
JM		 1903#define SPR_Exxx_L1CSR1 (0x3F3)
1904#define SPR_440_DBDR (0x3F3)
1905#define SPR_LDSTDB (0x3F4)
bd928eba 1906#define SPR_750_TDCL (0x3F4)
80d11f44
JM		 1907#define SPR_40x_IAC1 (0x3F4)
1908#define SPR_MMUCSR0 (0x3F4)
ba881002 1909#define SPR_970_HID4 (0x3F4)
80d11f44 1910#define SPR_DABR (0x3F5)
3fc6c082 1911#define DABR_MASK (~(target_ulong)0x7)
80d11f44
JM		 1912#define SPR_Exxx_BUCSR (0x3F5)
1913#define SPR_40x_IAC2 (0x3F5)
1914#define SPR_601_HID5 (0x3F5)
1915#define SPR_40x_DAC1 (0x3F6)
1916#define SPR_MSSCR0 (0x3F6)
1917#define SPR_970_HID5 (0x3F6)
1918#define SPR_MSSSR0 (0x3F7)
4e777442 1919#define SPR_MSSCR1 (0x3F7)
80d11f44
JM		 1920#define SPR_DABRX (0x3F7)
1921#define SPR_40x_DAC2 (0x3F7)
1922#define SPR_MMUCFG (0x3F7)
1923#define SPR_LDSTCR (0x3F8)
1924#define SPR_L2PMCR (0x3F8)
bd928eba 1925#define SPR_750FX_HID2 (0x3F8)
80d11f44
JM		 1926#define SPR_Exxx_L1FINV0 (0x3F8)
1927#define SPR_L2CR (0x3F9)
80d11f44 1928#define SPR_L3CR (0x3FA)
bd928eba 1929#define SPR_750_TDCH (0x3FA)
80d11f44
JM		 1930#define SPR_IABR2 (0x3FA)
1931#define SPR_40x_DCCR (0x3FA)
1932#define SPR_ICTC (0x3FB)
1933#define SPR_40x_ICCR (0x3FB)
1934#define SPR_THRM1 (0x3FC)
1935#define SPR_403_PBL1 (0x3FC)
1936#define SPR_SP (0x3FD)
1937#define SPR_THRM2 (0x3FD)
1938#define SPR_403_PBU1 (0x3FD)
1939#define SPR_604_HID13 (0x3FD)
1940#define SPR_LT (0x3FE)
1941#define SPR_THRM3 (0x3FE)
1942#define SPR_RCPU_FPECR (0x3FE)
1943#define SPR_403_PBL2 (0x3FE)
1944#define SPR_PIR (0x3FF)
1945#define SPR_403_PBU2 (0x3FF)
1946#define SPR_601_HID15 (0x3FF)
1947#define SPR_604_HID15 (0x3FF)
1948#define SPR_E500_SVR (0x3FF)
79aceca5 1949
84755ed5
AG		 1950/* Disable MAS Interrupt Updates for Hypervisor */
1951#define EPCR_DMIUH (1 << 22)
1952/* Disable Guest TLB Management Instructions */
1953#define EPCR_DGTMI (1 << 23)
1954/* Guest Interrupt Computation Mode */
1955#define EPCR_GICM (1 << 24)
1956/* Interrupt Computation Mode */
1957#define EPCR_ICM (1 << 25)
1958/* Disable Embedded Hypervisor Debug */
1959#define EPCR_DUVD (1 << 26)
1960/* Instruction Storage Interrupt Directed to Guest State */
1961#define EPCR_ISIGS (1 << 27)
1962/* Data Storage Interrupt Directed to Guest State */
1963#define EPCR_DSIGS (1 << 28)
1964/* Instruction TLB Error Interrupt Directed to Guest State */
1965#define EPCR_ITLBGS (1 << 29)
1966/* Data TLB Error Interrupt Directed to Guest State */
1967#define EPCR_DTLBGS (1 << 30)
1968/* External Input Interrupt Directed to Guest State */
1969#define EPCR_EXTGS (1 << 31)
1970
c647e3fe
DG		 1971#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1972#define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1973#define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1974#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1975#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
ea71258d 1976
c647e3fe
DG		 1977#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1978#define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1979#define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1980#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1981#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
ea71258d 1982
bbc01ca7 1983/* HID0 bits */
1488270e
BH		 1984#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1985#define HID0_DOZE (1 << 23) /* pre-2.06 */
1986#define HID0_NAP (1 << 22) /* pre-2.06 */
2a83f997 1987#define HID0_HILE PPC_BIT(19) /* POWER8 */
0bfc0cf0 1988#define HID0_POWER9_HILE PPC_BIT(4)
bbc01ca7 1989
c29b735c
NF		 1990/*****************************************************************************/
1991/* PowerPC Instructions types definitions */
1992enum {
1993 PPC_NONE = 0x0000000000000000ULL,
1994 /* PowerPC base instructions set */
1995 PPC_INSNS_BASE = 0x0000000000000001ULL,
1996 /* integer operations instructions */
1997#define PPC_INTEGER PPC_INSNS_BASE
1998 /* flow control instructions */
1999#define PPC_FLOW PPC_INSNS_BASE
2000 /* virtual memory instructions */
2001#define PPC_MEM PPC_INSNS_BASE
2002 /* ld/st with reservation instructions */
2003#define PPC_RES PPC_INSNS_BASE
2004 /* spr/msr access instructions */
2005#define PPC_MISC PPC_INSNS_BASE
2006 /* Deprecated instruction sets */
2007 /* Original POWER instruction set */
2008 PPC_POWER = 0x0000000000000002ULL,
2009 /* POWER2 instruction set extension */
2010 PPC_POWER2 = 0x0000000000000004ULL,
2011 /* Power RTC support */
2012 PPC_POWER_RTC = 0x0000000000000008ULL,
2013 /* Power-to-PowerPC bridge (601) */
2014 PPC_POWER_BR = 0x0000000000000010ULL,
2015 /* 64 bits PowerPC instruction set */
2016 PPC_64B = 0x0000000000000020ULL,
2017 /* New 64 bits extensions (PowerPC 2.0x) */
2018 PPC_64BX = 0x0000000000000040ULL,
2019 /* 64 bits hypervisor extensions */
2020 PPC_64H = 0x0000000000000080ULL,
2021 /* New wait instruction (PowerPC 2.0x) */
2022 PPC_WAIT = 0x0000000000000100ULL,
2023 /* Time base mftb instruction */
2024 PPC_MFTB = 0x0000000000000200ULL,
2025
2026 /* Fixed-point unit extensions */
2027 /* PowerPC 602 specific */
2028 PPC_602_SPEC = 0x0000000000000400ULL,
2029 /* isel instruction */
2030 PPC_ISEL = 0x0000000000000800ULL,
2031 /* popcntb instruction */
2032 PPC_POPCNTB = 0x0000000000001000ULL,
2033 /* string load / store */
2034 PPC_STRING = 0x0000000000002000ULL,
b7815375
BH		 2035 /* real mode cache inhibited load / store */
2036 PPC_CILDST = 0x0000000000004000ULL,
c29b735c
NF		 2037
2038 /* Floating-point unit extensions */
2039 /* Optional floating point instructions */
2040 PPC_FLOAT = 0x0000000000010000ULL,
2041 /* New floating-point extensions (PowerPC 2.0x) */
2042 PPC_FLOAT_EXT = 0x0000000000020000ULL,
2043 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
2044 PPC_FLOAT_FRES = 0x0000000000080000ULL,
2045 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
2046 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
2047 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
2048 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
2049
2050 /* Vector/SIMD extensions */
2051 /* Altivec support */
2052 PPC_ALTIVEC = 0x0000000001000000ULL,
2053 /* PowerPC 2.03 SPE extension */
2054 PPC_SPE = 0x0000000002000000ULL,
2055 /* PowerPC 2.03 SPE single-precision floating-point extension */
2056 PPC_SPE_SINGLE = 0x0000000004000000ULL,
2057 /* PowerPC 2.03 SPE double-precision floating-point extension */
2058 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
2059
2060 /* Optional memory control instructions */
2061 PPC_MEM_TLBIA = 0x0000000010000000ULL,
2062 PPC_MEM_TLBIE = 0x0000000020000000ULL,
2063 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
2064 /* sync instruction */
2065 PPC_MEM_SYNC = 0x0000000080000000ULL,
2066 /* eieio instruction */
2067 PPC_MEM_EIEIO = 0x0000000100000000ULL,
2068
2069 /* Cache control instructions */
2070 PPC_CACHE = 0x0000000200000000ULL,
2071 /* icbi instruction */
2072 PPC_CACHE_ICBI = 0x0000000400000000ULL,
8e33944f 2073 /* dcbz instruction */
c29b735c 2074 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
c29b735c
NF		 2075 /* dcba instruction */
2076 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2077 /* Freescale cache locking instructions */
2078 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2079
2080 /* MMU related extensions */
2081 /* external control instructions */
2082 PPC_EXTERN = 0x0000010000000000ULL,
2083 /* segment register access instructions */
2084 PPC_SEGMENT = 0x0000020000000000ULL,
2085 /* PowerPC 6xx TLB management instructions */
2086 PPC_6xx_TLB = 0x0000040000000000ULL,
2087 /* PowerPC 74xx TLB management instructions */
2088 PPC_74xx_TLB = 0x0000080000000000ULL,
2089 /* PowerPC 40x TLB management instructions */
2090 PPC_40x_TLB = 0x0000100000000000ULL,
2091 /* segment register access instructions for PowerPC 64 "bridge" */
2092 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2093 /* SLB management */
2094 PPC_SLBI = 0x0000400000000000ULL,
2095
2096 /* Embedded PowerPC dedicated instructions */
2097 PPC_WRTEE = 0x0001000000000000ULL,
2098 /* PowerPC 40x exception model */
2099 PPC_40x_EXCP = 0x0002000000000000ULL,
2100 /* PowerPC 405 Mac instructions */
2101 PPC_405_MAC = 0x0004000000000000ULL,
2102 /* PowerPC 440 specific instructions */
2103 PPC_440_SPEC = 0x0008000000000000ULL,
2104 /* BookE (embedded) PowerPC specification */
2105 PPC_BOOKE = 0x0010000000000000ULL,
2106 /* mfapidi instruction */
2107 PPC_MFAPIDI = 0x0020000000000000ULL,
2108 /* tlbiva instruction */
2109 PPC_TLBIVA = 0x0040000000000000ULL,
2110 /* tlbivax instruction */
2111 PPC_TLBIVAX = 0x0080000000000000ULL,
2112 /* PowerPC 4xx dedicated instructions */
2113 PPC_4xx_COMMON = 0x0100000000000000ULL,
2114 /* PowerPC 40x ibct instructions */
2115 PPC_40x_ICBT = 0x0200000000000000ULL,
2116 /* rfmci is not implemented in all BookE PowerPC */
2117 PPC_RFMCI = 0x0400000000000000ULL,
2118 /* rfdi instruction */
2119 PPC_RFDI = 0x0800000000000000ULL,
2120 /* DCR accesses */
2121 PPC_DCR = 0x1000000000000000ULL,
2122 /* DCR extended accesse */
2123 PPC_DCRX = 0x2000000000000000ULL,
2124 /* user-mode DCR access, implemented in PowerPC 460 */
2125 PPC_DCRUX = 0x4000000000000000ULL,
eaabeef2
DG		 2126 /* popcntw and popcntd instructions */
2127 PPC_POPCNTWD = 0x8000000000000000ULL,
01662f3e 2128
02d4eae4
DG		 2129#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2130 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2131 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2132 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2133 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2134 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2135 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2136 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2137 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2138 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2139 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2140 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2141 | PPC_CACHE | PPC_CACHE_ICBI \
8e33944f 2142 | PPC_CACHE_DCBZ \
02d4eae4
DG		 2143 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2144 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2145 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2146 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2147 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2148 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2149 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2150 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
b7815375 2151 | PPC_POPCNTWD | PPC_CILDST)
02d4eae4 2152
01662f3e
AG		 2153 /* extended type values */
2154
2155 /* BookE 2.06 PowerPC specification */
2156 PPC2_BOOKE206 = 0x0000000000000001ULL,
a7342588
DG		 2157 /* VSX (extensions to Altivec / VMX) */
2158 PPC2_VSX = 0x0000000000000002ULL,
2159 /* Decimal Floating Point (DFP) */
2160 PPC2_DFP = 0x0000000000000004ULL,
3f9f6a50
AG		 2161 /* Embedded.Processor Control */
2162 PPC2_PRCNTL = 0x0000000000000008ULL,
cd6e9320
TH		 2163 /* Byte-reversed, indexed, double-word load and store */
2164 PPC2_DBRX = 0x0000000000000010ULL,
9c2627b0
AJ		 2165 /* Book I 2.05 PowerPC specification */
2166 PPC2_ISA205 = 0x0000000000000020ULL,
dbcc48fa
TM		 2167 /* VSX additions in ISA 2.07 */
2168 PPC2_VSX207 = 0x0000000000000040ULL,
86ba37ed
TM		 2169 /* ISA 2.06B bpermd */
2170 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
a824bc19
TM		 2171 /* ISA 2.06B divide extended variants */
2172 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1fa6c533
TM		 2173 /* ISA 2.06B larx/stcx. instructions */
2174 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1b0bd002
TM		 2175 /* ISA 2.06B floating point integer conversion */
2176 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
29a0e4e9
TM		 2177 /* ISA 2.06B floating point test instructions */
2178 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
94840e07
TM		 2179 /* ISA 2.07 bctar instruction */
2180 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
38a85337
TM		 2181 /* ISA 2.07 load/store quadword */
2182 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
32ea54ab
TM		 2183 /* ISA 2.07 Altivec */
2184 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
df99d30d
AK		 2185 /* PowerISA 2.07 Book3s specification */
2186 PPC2_ISA207S = 0x0000000000008000ULL,
4171853c
PM		 2187 /* Double precision floating point conversion for signed integer 64 */
2188 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
f90468b6
TM		 2189 /* Transactional Memory (ISA 2.07, Book II) */
2190 PPC2_TM = 0x0000000000020000ULL,
7778a575
BH		 2191 /* Server PM instructgions (ISA 2.06, Book III) */
2192 PPC2_PM_ISA206 = 0x0000000000040000ULL,
eb640b13
ND		 2193 /* POWER ISA 3.0 */
2194 PPC2_ISA300 = 0x0000000000080000ULL,
ca7a2fda
LP		 2195 /* POWER ISA 3.1 */
2196 PPC2_ISA310 = 0x0000000000100000ULL,
02d4eae4 2197
74f23997 2198#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
a824bc19 2199 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1b0bd002 2200 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
94840e07 2201 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
32ea54ab 2202 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
4171853c 2203 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
eb640b13 2204 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
9495edb0 2205 PPC2_ISA300 | PPC2_ISA310)
c29b735c
NF		 2206};
2207
76a66253 2208/*****************************************************************************/
c647e3fe
DG		 2209/*
2210 * Memory access type :
9a64fbe4
FB		 2211 * may be needed for precise access rights control and precise exceptions.
2212 */
79aceca5 2213enum {
9a64fbe4
FB		 2214 /* 1 bit to define user level / supervisor access */
2215 ACCESS_USER = 0x00,
2216 ACCESS_SUPER = 0x01,
2217 /* Type of instruction that generated the access */
2218 ACCESS_CODE = 0x10, /* Code fetch access */
2219 ACCESS_INT = 0x20, /* Integer load/store access */
2220 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2221 ACCESS_RES = 0x40, /* load/store with reservation */
2222 ACCESS_EXT = 0x50, /* external access */
2223 ACCESS_CACHE = 0x60, /* Cache manipulation */
2224};
2225
c647e3fe
DG		 2226/*
2227 * Hardware interrupt sources:
2228 * all those exception can be raised simulteaneously
47103572 2229 */
e9df014c
JM		 2230/* Input pins definitions */
2231enum {
2232 /* 6xx bus input pins */
24be5ae3
JM		 2233 PPC6xx_INPUT_HRESET = 0,
2234 PPC6xx_INPUT_SRESET = 1,
2235 PPC6xx_INPUT_CKSTP_IN = 2,
2236 PPC6xx_INPUT_MCP = 3,
2237 PPC6xx_INPUT_SMI = 4,
2238 PPC6xx_INPUT_INT = 5,
d68f1306
JM		 2239 PPC6xx_INPUT_TBEN = 6,
2240 PPC6xx_INPUT_WAKEUP = 7,
2241 PPC6xx_INPUT_NB,
24be5ae3
JM		 2242};
2243
2244enum {
e9df014c 2245 /* Embedded PowerPC input pins */
24be5ae3
JM		 2246 PPCBookE_INPUT_HRESET = 0,
2247 PPCBookE_INPUT_SRESET = 1,
2248 PPCBookE_INPUT_CKSTP_IN = 2,
2249 PPCBookE_INPUT_MCP = 3,
2250 PPCBookE_INPUT_SMI = 4,
2251 PPCBookE_INPUT_INT = 5,
2252 PPCBookE_INPUT_CINT = 6,
d68f1306 2253 PPCBookE_INPUT_NB,
24be5ae3
JM		 2254};
2255
9fdc60bf
AJ		 2256enum {
2257 /* PowerPC E500 input pins */
2258 PPCE500_INPUT_RESET_CORE = 0,
2259 PPCE500_INPUT_MCK = 1,
2260 PPCE500_INPUT_CINT = 3,
2261 PPCE500_INPUT_INT = 4,
2262 PPCE500_INPUT_DEBUG = 6,
2263 PPCE500_INPUT_NB,
2264};
2265
a750fc0b 2266enum {
4e290a0b
JM		 2267 /* PowerPC 40x input pins */
2268 PPC40x_INPUT_RESET_CORE = 0,
2269 PPC40x_INPUT_RESET_CHIP = 1,
2270 PPC40x_INPUT_RESET_SYS = 2,
2271 PPC40x_INPUT_CINT = 3,
2272 PPC40x_INPUT_INT = 4,
2273 PPC40x_INPUT_HALT = 5,
2274 PPC40x_INPUT_DEBUG = 6,
2275 PPC40x_INPUT_NB,
e9df014c
JM		 2276};
2277
b4095fed
JM		 2278enum {
2279 /* RCPU input pins */
2280 PPCRCPU_INPUT_PORESET = 0,
2281 PPCRCPU_INPUT_HRESET = 1,
2282 PPCRCPU_INPUT_SRESET = 2,
2283 PPCRCPU_INPUT_IRQ0 = 3,
2284 PPCRCPU_INPUT_IRQ1 = 4,
2285 PPCRCPU_INPUT_IRQ2 = 5,
2286 PPCRCPU_INPUT_IRQ3 = 6,
2287 PPCRCPU_INPUT_IRQ4 = 7,
2288 PPCRCPU_INPUT_IRQ5 = 8,
2289 PPCRCPU_INPUT_IRQ6 = 9,
2290 PPCRCPU_INPUT_IRQ7 = 10,
2291 PPCRCPU_INPUT_NB,
2292};
2293
00af685f 2294#if defined(TARGET_PPC64)
d0dfae6e
JM		 2295enum {
2296 /* PowerPC 970 input pins */
2297 PPC970_INPUT_HRESET = 0,
2298 PPC970_INPUT_SRESET = 1,
2299 PPC970_INPUT_CKSTP = 2,
2300 PPC970_INPUT_TBEN = 3,
2301 PPC970_INPUT_MCP = 4,
2302 PPC970_INPUT_INT = 5,
2303 PPC970_INPUT_THINT = 6,
7b62a955 2304 PPC970_INPUT_NB,
9d52e907
DG		 2305};
2306
2307enum {
2308 /* POWER7 input pins */
2309 POWER7_INPUT_INT = 0,
c647e3fe
DG		 2310 /*
2311 * POWER7 probably has other inputs, but we don't care about them
9d52e907 2312 * for any existing machine. We can wire these up when we need
c647e3fe
DG		 2313 * them
2314 */
9d52e907 2315 POWER7_INPUT_NB,
d0dfae6e 2316};
67afe775
BH		 2317
2318enum {
2319 /* POWER9 input pins */
2320 POWER9_INPUT_INT = 0,
2321 POWER9_INPUT_HINT = 1,
2322 POWER9_INPUT_NB,
2323};
00af685f 2324#endif
d0dfae6e 2325
e9df014c 2326/* Hardware exceptions definitions */
47103572 2327enum {
e9df014c 2328 /* External hardware exception sources */
e1833e1f 2329 PPC_INTERRUPT_RESET = 0, /* Reset exception */
d68f1306
JM		 2330 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2331 PPC_INTERRUPT_MCK, /* Machine check exception */
2332 PPC_INTERRUPT_EXT, /* External interrupt */
2333 PPC_INTERRUPT_SMI, /* System management interrupt */
2334 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2335 PPC_INTERRUPT_DEBUG, /* External debug exception */
2336 PPC_INTERRUPT_THERM, /* Thermal exception */
e9df014c 2337 /* Internal hardware exception sources */
d68f1306
JM		 2338 PPC_INTERRUPT_DECR, /* Decrementer exception */
2339 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2340 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2341 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2342 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2343 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2344 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2345 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
f03a1af5
BH		 2346 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */
2347 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
d8ce5fd6 2348 PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
47103572
JM		 2349};
2350
6d9412ea
AK		 2351/* Processor Compatibility mask (PCR) */
2352enum {
a6a444a8
CLG		 2353 PCR_COMPAT_2_05 = PPC_BIT(62),
2354 PCR_COMPAT_2_06 = PPC_BIT(61),
2355 PCR_COMPAT_2_07 = PPC_BIT(60),
2356 PCR_COMPAT_3_00 = PPC_BIT(59),
7d37b274 2357 PCR_COMPAT_3_10 = PPC_BIT(58),
a6a444a8
CLG		 2358 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
2359 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
2360 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
6d9412ea
AK		 2361};
2362
1488270e
BH		 2363/* HMER/HMEER */
2364enum {
a6a444a8
CLG		 2365 HMER_MALFUNCTION_ALERT = PPC_BIT(0),
2366 HMER_PROC_RECV_DONE = PPC_BIT(2),
2367 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3),
2368 HMER_TFAC_ERROR = PPC_BIT(4),
2369 HMER_TFMR_PARITY_ERROR = PPC_BIT(5),
2370 HMER_XSCOM_FAIL = PPC_BIT(8),
2371 HMER_XSCOM_DONE = PPC_BIT(9),
2372 HMER_PROC_RECV_AGAIN = PPC_BIT(11),
2373 HMER_WARN_RISE = PPC_BIT(14),
2374 HMER_WARN_FALL = PPC_BIT(15),
2375 HMER_SCOM_FIR_HMI = PPC_BIT(16),
2376 HMER_TRIG_FIR_HMI = PPC_BIT(17),
2377 HMER_HYP_RESOURCE_ERR = PPC_BIT(20),
2378 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23),
1488270e
BH		 2379};
2380
5c94b2a5
CLG		 2381/* Alternate Interrupt Location (AIL) */
2382enum {
2383 AIL_NONE = 0,
2384 AIL_RESERVED = 1,
2385 AIL_0001_8000 = 2,
2386 AIL_C000_0000_0000_4000 = 3,
2387};
2388
9a64fbe4
FB		 2389/*****************************************************************************/
2390
dd09c361 2391#define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300))
00b70788
ND		 2392target_ulong cpu_read_xer(CPUPPCState *env);
2393void cpu_write_xer(CPUPPCState *env, target_ulong xer);
da91a00f 2394
d0db7cad
GK		 2395/*
2396 * All 64-bit server processors compliant with arch 2.x, ie. 970 and newer,
2397 * have PPC_SEGMENT_64B.
2398 */
2399#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
2400
1328c2bf 2401static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
89fee74a 2402 target_ulong *cs_base, uint32_t *flags)
6b917547
AL		 2403{
2404 *pc = env->nip;
2405 *cs_base = 0;
2406 *flags = env->hflags;
2407}
2408
db789c6c
BH		 2409void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception);
2410void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception,
2411 uintptr_t raddr);
2412void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
2413 uint32_t error_code);
2414void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
2415 uint32_t error_code, uintptr_t raddr);
2416
01662f3e 2417#if !defined(CONFIG_USER_ONLY)
1328c2bf 2418static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2419{
d1e256fe 2420 uintptr_t tlbml = (uintptr_t)tlbm;
1c53accc 2421 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
01662f3e 2422
1c53accc 2423 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
01662f3e
AG		 2424}
2425
1328c2bf 2426static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
01662f3e
AG		 2427{
2428 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2429 int r = tlbncfg & TLBnCFG_N_ENTRY;
2430 return r;
2431}
2432
1328c2bf 2433static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
01662f3e
AG		 2434{
2435 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2436 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2437 return r;
2438}
2439
1328c2bf 2440static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
01662f3e 2441{
d1e256fe 2442 int id = booke206_tlbm_id(env, tlbm);
01662f3e
AG		 2443 int end = 0;
2444 int i;
2445
2446 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2447 end += booke206_tlb_size(env, i);
2448 if (id < end) {
2449 return i;
2450 }
2451 }
2452
db70b311 2453 cpu_abort(env_cpu(env), "Unknown TLBe: %d\n", id);
01662f3e
AG		 2454 return 0;
2455}
2456
1328c2bf 2457static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
01662f3e 2458{
d1e256fe
AG		 2459 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2460 int tlbid = booke206_tlbm_id(env, tlb);
01662f3e
AG		 2461 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2462}
2463
1328c2bf 2464static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
01662f3e
AG		 2465 target_ulong ea, int way)
2466{
2467 int r;
2468 uint32_t ways = booke206_tlb_ways(env, tlbn);
786a4ea8
SH		 2469 int ways_bits = ctz32(ways);
2470 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
01662f3e
AG		 2471 int i;
2472
2473 way &= ways - 1;
2474 ea >>= MAS2_EPN_SHIFT;
2475 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2476 r = (ea << ways_bits) | way;
2477
3f162d11
AG		 2478 if (r >= booke206_tlb_size(env, tlbn)) {
2479 return NULL;
2480 }
2481
01662f3e
AG		 2482 /* bump up to tlbn index */
2483 for (i = 0; i < tlbn; i++) {
2484 r += booke206_tlb_size(env, i);
2485 }
2486
1c53accc 2487 return &env->tlb.tlbm[r];
01662f3e
AG		 2488}
2489
a1ef618a 2490/* returns bitmap of supported page sizes for a given TLB */
1328c2bf 2491static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
a1ef618a 2492{
a1ef618a
AG		 2493 uint32_t ret = 0;
2494
3f330293
KF		 2495 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
2496 /* MAV2 */
a1ef618a
AG		 2497 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2498 } else {
2499 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2500 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2501 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2502 int i;
2503 for (i = min; i <= max; i++) {
2504 ret |= (1 << (i << 1));
2505 }
2506 }
2507
2508 return ret;
2509}
2510
c449d8ba
KF		 2511static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn,
2512 ppcmas_tlb_t *tlb)
2513{
2514 uint8_t i;
2515 int32_t tsize = -1;
2516
2517 for (i = 0; i < 32; i++) {
2518 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) {
2519 if (tsize == -1) {
2520 tsize = i;
2521 } else {
2522 return;
2523 }
2524 }
2525 }
2526
2527 /* TLBnPS unimplemented? Odd.. */
2528 assert(tsize != -1);
2529 tlb->mas1 &= ~MAS1_TSIZE_MASK;
2530 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT;
2531}
2532
01662f3e
AG		 2533#endif
2534
e42a61f1
AG		 2535static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2536{
2537 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2538 return msr & (1ULL << MSR_CM);
2539 }
2540
2541 return msr & (1ULL << MSR_SF);
2542}
2543
afbee712
TH		 2544/**
2545 * Check whether register rx is in the range between start and
2546 * start + nregs (as needed by the LSWX and LSWI instructions)
2547 */
2548static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2549{
2550 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2551 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2552}
2553
ef96e3ae 2554/* Accessors for FP, VMX and VSX registers */
da7815ef
MCA		 2555#if defined(HOST_WORDS_BIGENDIAN)
2556#define VsrB(i) u8[i]
2557#define VsrSB(i) s8[i]
2558#define VsrH(i) u16[i]
2559#define VsrSH(i) s16[i]
2560#define VsrW(i) u32[i]
2561#define VsrSW(i) s32[i]
2562#define VsrD(i) u64[i]
2563#define VsrSD(i) s64[i]
2564#else
2565#define VsrB(i) u8[15 - (i)]
2566#define VsrSB(i) s8[15 - (i)]
2567#define VsrH(i) u16[7 - (i)]
2568#define VsrSH(i) s16[7 - (i)]
2569#define VsrW(i) u32[3 - (i)]
2570#define VsrSW(i) s32[3 - (i)]
2571#define VsrD(i) u64[1 - (i)]
2572#define VsrSD(i) s64[1 - (i)]
2573#endif
2574
d59d1182 2575static inline int vsr64_offset(int i, bool high)
e7d3b272 2576{
d59d1182 2577 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1));
e7d3b272
MCA		 2578}
2579
d59d1182 2580static inline int vsr_full_offset(int i)
ef96e3ae 2581{
d59d1182 2582 return offsetof(CPUPPCState, vsr[i].u64[0]);
ef96e3ae
MCA		 2583}
2584
d59d1182 2585static inline int fpr_offset(int i)
45141dfd 2586{
d59d1182 2587 return vsr64_offset(i, true);
45141dfd
MCA		 2588}
2589
d59d1182 2590static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
c82a8a85 2591{
d59d1182 2592 return (uint64_t *)((uintptr_t)env + fpr_offset(i));
c82a8a85
MCA		 2593}
2594
ef96e3ae
MCA		 2595static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
2596{
d59d1182 2597 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false));
ef96e3ae
MCA		 2598}
2599
37da91f1
MCA		 2600static inline long avr64_offset(int i, bool high)
2601{
d59d1182 2602 return vsr64_offset(i + 32, high);
37da91f1
MCA		 2603}
2604
c82a8a85
MCA		 2605static inline int avr_full_offset(int i)
2606{
2607 return vsr_full_offset(i + 32);
2608}
2609
ef96e3ae
MCA		 2610static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i)
2611{
c82a8a85 2612 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i));
ef96e3ae
MCA		 2613}
2614
fad866da 2615void dump_mmu(CPUPPCState *env);
bebabbc7 2616
376dbce0 2617void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
07f5a258 2618#endif /* PPC_CPU_H */
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