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hw/core: Add CPUClass.get_pc
[mirror_qemu.git] / target / ppc / cpu_init.c
CommitLineData
3fc6c082
FB		 1/*
2 * PowerPC CPU initialization for qemu.
5fafdf24 3 *
76a66253 4 * Copyright (c) 2003-2007 Jocelyn Mayer
f7aa5583 5 * Copyright 2011 Freescale Semiconductor, Inc.
3fc6c082
FB		 6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
6bd039cd 10 * version 2.1 of the License, or (at your option) any later version.
3fc6c082
FB		 11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
8167ee88 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
3fc6c082
FB		 19 */
20
3e770bf7 21#include "qemu/osdep.h"
3979fca4 22#include "disas/dis-asm.h"
022c62cb 23#include "exec/gdbstub.h"
a1e98583 24#include "kvm_ppc.h"
fe828a4d 25#include "sysemu/cpus.h"
b3946626 26#include "sysemu/hw_accel.h"
14a48c1d 27#include "sysemu/tcg.h"
953af181 28#include "cpu-models.h"
b632a148
DG		 29#include "mmu-hash32.h"
30#include "mmu-hash64.h"
4a44d85e 31#include "qemu/error-report.h"
0b8fa32f 32#include "qemu/module.h"
0442428a 33#include "qemu/qemu-print.h"
e688df6b 34#include "qapi/error.h"
198a1032 35#include "qapi/qmp/qnull.h"
8dfa3a5e
AK		 36#include "qapi/visitor.h"
37#include "hw/qdev-properties.h"
aa5a9e24 38#include "hw/ppc/ppc.h"
b2899495 39#include "mmu-book3s-v3.h"
b376db77 40#include "qemu/cutils.h"
ac226899 41#include "disas/capstone.h"
24f91e81 42#include "fpu/softfloat.h"
7f7b4e7a 43#include "qapi/qapi-commands-machine-target.h"
237c0af0 44
3e770bf7
BL		 45#include "helper_regs.h"
46#include "internal.h"
99e964ef 47#include "spr_common.h"
8f2e9d40 48#include "power8-pmu.h"
3e770bf7 49
c7e89de1
MOA		 50#ifndef CONFIG_USER_ONLY
51#include "hw/boards.h"
52#endif
53
1d28b5f6 54/* #define PPC_DEBUG_SPR */
b3cad3ab 55/* #define USE_APPLE_GDB */
3fc6c082 56
c364946d 57static inline void vscr_init(CPUPPCState *env, uint32_t val)
cf8358c8 58{
cf8358c8
AJ		 59 /* Altivec always uses round-to-nearest */
60 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
c19940db 61 ppc_store_vscr(env, val);
cf8358c8
AJ		 62}
63
a5d1120b 64static void register_745_sprs(CPUPPCState *env)
76a66253
JM		 65{
66 /* SGPRs */
67 spr_register(env, SPR_SPRG4, "SPRG4",
68 SPR_NOACCESS, SPR_NOACCESS,
69 &spr_read_generic, &spr_write_generic,
70 0x00000000);
71 spr_register(env, SPR_SPRG5, "SPRG5",
72 SPR_NOACCESS, SPR_NOACCESS,
73 &spr_read_generic, &spr_write_generic,
74 0x00000000);
75 spr_register(env, SPR_SPRG6, "SPRG6",
76 SPR_NOACCESS, SPR_NOACCESS,
77 &spr_read_generic, &spr_write_generic,
78 0x00000000);
79 spr_register(env, SPR_SPRG7, "SPRG7",
80 SPR_NOACCESS, SPR_NOACCESS,
81 &spr_read_generic, &spr_write_generic,
82 0x00000000);
a5d1120b
FR		 83
84 /* Hardware implementation registers */
85 spr_register(env, SPR_HID0, "HID0",
86 SPR_NOACCESS, SPR_NOACCESS,
87 &spr_read_generic, &spr_write_generic,
88 0x00000000);
89
90 spr_register(env, SPR_HID1, "HID1",
91 SPR_NOACCESS, SPR_NOACCESS,
92 &spr_read_generic, &spr_write_generic,
93 0x00000000);
94
95 spr_register(env, SPR_HID2, "HID2",
96 SPR_NOACCESS, SPR_NOACCESS,
97 &spr_read_generic, &spr_write_generic,
98 0x00000000);
76a66253
JM		 99}
100
28930245
FR		 101static void register_755_sprs(CPUPPCState *env)
102{
103 /* L2 cache control */
104 spr_register(env, SPR_L2CR, "L2CR",
105 SPR_NOACCESS, SPR_NOACCESS,
106 &spr_read_generic, spr_access_nop,
107 0x00000000);
108
109 spr_register(env, SPR_L2PMCR, "L2PMCR",
110 SPR_NOACCESS, SPR_NOACCESS,
111 &spr_read_generic, &spr_write_generic,
112 0x00000000);
113}
114
3fc6c082 115/* SPR common to all 7xx PowerPC implementations */
a08eea67 116static void register_7xx_sprs(CPUPPCState *env)
3fc6c082
FB		 117{
118 /* Breakpoints */
d67d40ea
DG		 119 spr_register_kvm(env, SPR_DABR, "DABR",
120 SPR_NOACCESS, SPR_NOACCESS,
121 &spr_read_generic, &spr_write_generic,
122 KVM_REG_PPC_DABR, 0x00000000);
acf629eb 123
3fc6c082
FB		 124 spr_register(env, SPR_IABR, "IABR",
125 SPR_NOACCESS, SPR_NOACCESS,
126 &spr_read_generic, &spr_write_generic,
127 0x00000000);
128 /* Cache management */
3fc6c082
FB		 129 spr_register(env, SPR_ICTC, "ICTC",
130 SPR_NOACCESS, SPR_NOACCESS,
131 &spr_read_generic, &spr_write_generic,
132 0x00000000);
133 /* Performance monitors */
cb8b8bf8 134 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
3fc6c082
FB		 135 SPR_NOACCESS, SPR_NOACCESS,
136 &spr_read_generic, &spr_write_generic,
137 0x00000000);
acf629eb 138
cb8b8bf8 139 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
3fc6c082
FB		 140 SPR_NOACCESS, SPR_NOACCESS,
141 &spr_read_generic, &spr_write_generic,
142 0x00000000);
acf629eb 143
cb8b8bf8 144 spr_register(env, SPR_7XX_PMC1, "PMC1",
3fc6c082
FB		 145 SPR_NOACCESS, SPR_NOACCESS,
146 &spr_read_generic, &spr_write_generic,
147 0x00000000);
acf629eb 148
cb8b8bf8 149 spr_register(env, SPR_7XX_PMC2, "PMC2",
3fc6c082
FB		 150 SPR_NOACCESS, SPR_NOACCESS,
151 &spr_read_generic, &spr_write_generic,
152 0x00000000);
acf629eb 153
cb8b8bf8 154 spr_register(env, SPR_7XX_PMC3, "PMC3",
3fc6c082
FB		 155 SPR_NOACCESS, SPR_NOACCESS,
156 &spr_read_generic, &spr_write_generic,
157 0x00000000);
acf629eb 158
cb8b8bf8 159 spr_register(env, SPR_7XX_PMC4, "PMC4",
3fc6c082
FB		 160 SPR_NOACCESS, SPR_NOACCESS,
161 &spr_read_generic, &spr_write_generic,
162 0x00000000);
acf629eb 163
cb8b8bf8 164 spr_register(env, SPR_7XX_SIAR, "SIAR",
3fc6c082
FB		 165 SPR_NOACCESS, SPR_NOACCESS,
166 &spr_read_generic, SPR_NOACCESS,
167 0x00000000);
acf629eb 168
cb8b8bf8 169 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
3fc6c082
FB		 170 &spr_read_ureg, SPR_NOACCESS,
171 &spr_read_ureg, SPR_NOACCESS,
172 0x00000000);
acf629eb 173
cb8b8bf8 174 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
3fc6c082
FB		 175 &spr_read_ureg, SPR_NOACCESS,
176 &spr_read_ureg, SPR_NOACCESS,
177 0x00000000);
acf629eb 178
cb8b8bf8 179 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
3fc6c082
FB		 180 &spr_read_ureg, SPR_NOACCESS,
181 &spr_read_ureg, SPR_NOACCESS,
182 0x00000000);
acf629eb 183
cb8b8bf8 184 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
3fc6c082
FB		 185 &spr_read_ureg, SPR_NOACCESS,
186 &spr_read_ureg, SPR_NOACCESS,
187 0x00000000);
acf629eb 188
cb8b8bf8 189 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
3fc6c082
FB		 190 &spr_read_ureg, SPR_NOACCESS,
191 &spr_read_ureg, SPR_NOACCESS,
192 0x00000000);
acf629eb 193
cb8b8bf8 194 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
3fc6c082
FB		 195 &spr_read_ureg, SPR_NOACCESS,
196 &spr_read_ureg, SPR_NOACCESS,
197 0x00000000);
acf629eb 198
cb8b8bf8 199 spr_register(env, SPR_7XX_USIAR, "USIAR",
3fc6c082
FB		 200 &spr_read_ureg, SPR_NOACCESS,
201 &spr_read_ureg, SPR_NOACCESS,
202 0x00000000);
a750fc0b 203 /* External access control */
a750fc0b 204 spr_register(env, SPR_EAR, "EAR",
3fc6c082
FB		 205 SPR_NOACCESS, SPR_NOACCESS,
206 &spr_read_generic, &spr_write_generic,
207 0x00000000);
0301b39c
FR		 208
209 /* Hardware implementation registers */
210 spr_register(env, SPR_HID0, "HID0",
211 SPR_NOACCESS, SPR_NOACCESS,
212 &spr_read_generic, &spr_write_generic,
213 0x00000000);
214
215 spr_register(env, SPR_HID1, "HID1",
216 SPR_NOACCESS, SPR_NOACCESS,
217 &spr_read_generic, &spr_write_generic,
218 0x00000000);
a750fc0b
JM		 219}
220
f80872e2 221#ifdef TARGET_PPC64
a08eea67 222static void register_amr_sprs(CPUPPCState *env)
f80872e2
DG		 223{
224#ifndef CONFIG_USER_ONLY
1d28b5f6
DG		 225 /*
226 * Virtual Page Class Key protection
227 *
228 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
f80872e2 229 * userspace accessible, 29 is privileged. So we only need to set
1d28b5f6
DG		 230 * the kvm ONE_REG id on one of them, we use 29
231 */
f80872e2 232 spr_register(env, SPR_UAMR, "UAMR",
97eaf30e
BH		 233 &spr_read_generic, &spr_write_amr,
234 &spr_read_generic, &spr_write_amr,
f80872e2 235 0);
97eaf30e 236 spr_register_kvm_hv(env, SPR_AMR, "AMR",
f80872e2 237 SPR_NOACCESS, SPR_NOACCESS,
97eaf30e 238 &spr_read_generic, &spr_write_amr,
f80872e2 239 &spr_read_generic, &spr_write_generic,
0dc083fe 240 KVM_REG_PPC_AMR, 0);
97eaf30e 241 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
f80872e2 242 SPR_NOACCESS, SPR_NOACCESS,
97eaf30e 243 &spr_read_generic, &spr_write_uamor,
f80872e2
DG		 244 &spr_read_generic, &spr_write_generic,
245 KVM_REG_PPC_UAMOR, 0);
f401dd32
BH		 246 spr_register_hv(env, SPR_AMOR, "AMOR",
247 SPR_NOACCESS, SPR_NOACCESS,
248 SPR_NOACCESS, SPR_NOACCESS,
249 &spr_read_generic, &spr_write_generic,
250 0);
4f4f28ff
SJS		 251#endif /* !CONFIG_USER_ONLY */
252}
253
a08eea67 254static void register_iamr_sprs(CPUPPCState *env)
4f4f28ff
SJS		 255{
256#ifndef CONFIG_USER_ONLY
257 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
258 SPR_NOACCESS, SPR_NOACCESS,
259 &spr_read_generic, &spr_write_iamr,
260 &spr_read_generic, &spr_write_generic,
261 KVM_REG_PPC_IAMR, 0);
f80872e2
DG		 262#endif /* !CONFIG_USER_ONLY */
263}
264#endif /* TARGET_PPC64 */
265
3fc6c082 266/* SPR specific to PowerPC 604 implementation */
a08eea67 267static void register_604_sprs(CPUPPCState *env)
3fc6c082
FB		 268{
269 /* Processor identification */
270 spr_register(env, SPR_PIR, "PIR",
271 SPR_NOACCESS, SPR_NOACCESS,
272 &spr_read_generic, &spr_write_pir,
273 0x00000000);
274 /* Breakpoints */
3fc6c082
FB		 275 spr_register(env, SPR_IABR, "IABR",
276 SPR_NOACCESS, SPR_NOACCESS,
277 &spr_read_generic, &spr_write_generic,
278 0x00000000);
acf629eb 279
d67d40ea
DG		 280 spr_register_kvm(env, SPR_DABR, "DABR",
281 SPR_NOACCESS, SPR_NOACCESS,
282 &spr_read_generic, &spr_write_generic,
283 KVM_REG_PPC_DABR, 0x00000000);
3fc6c082 284 /* Performance counters */
cb8b8bf8 285 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
3fc6c082
FB		 286 SPR_NOACCESS, SPR_NOACCESS,
287 &spr_read_generic, &spr_write_generic,
288 0x00000000);
acf629eb 289
cb8b8bf8 290 spr_register(env, SPR_7XX_PMC1, "PMC1",
3fc6c082
FB		 291 SPR_NOACCESS, SPR_NOACCESS,
292 &spr_read_generic, &spr_write_generic,
293 0x00000000);
acf629eb 294
cb8b8bf8 295 spr_register(env, SPR_7XX_PMC2, "PMC2",
3fc6c082
FB		 296 SPR_NOACCESS, SPR_NOACCESS,
297 &spr_read_generic, &spr_write_generic,
298 0x00000000);
acf629eb 299
cb8b8bf8 300 spr_register(env, SPR_7XX_SIAR, "SIAR",
3fc6c082
FB		 301 SPR_NOACCESS, SPR_NOACCESS,
302 &spr_read_generic, SPR_NOACCESS,
303 0x00000000);
acf629eb 304
3fc6c082
FB		 305 spr_register(env, SPR_SDA, "SDA",
306 SPR_NOACCESS, SPR_NOACCESS,
307 &spr_read_generic, SPR_NOACCESS,
308 0x00000000);
309 /* External access control */
3fc6c082
FB		 310 spr_register(env, SPR_EAR, "EAR",
311 SPR_NOACCESS, SPR_NOACCESS,
312 &spr_read_generic, &spr_write_generic,
313 0x00000000);
20f6fb99
FR		 314
315 /* Hardware implementation registers */
316 spr_register(env, SPR_HID0, "HID0",
317 SPR_NOACCESS, SPR_NOACCESS,
318 &spr_read_generic, &spr_write_generic,
319 0x00000000);
3fc6c082
FB		 320}
321
3b18ec76
FR		 322static void register_604e_sprs(CPUPPCState *env)
323{
324 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
325 SPR_NOACCESS, SPR_NOACCESS,
326 &spr_read_generic, &spr_write_generic,
327 0x00000000);
328
329 spr_register(env, SPR_7XX_PMC3, "PMC3",
330 SPR_NOACCESS, SPR_NOACCESS,
331 &spr_read_generic, &spr_write_generic,
332 0x00000000);
333
334 spr_register(env, SPR_7XX_PMC4, "PMC4",
335 SPR_NOACCESS, SPR_NOACCESS,
336 &spr_read_generic, &spr_write_generic,
337 0x00000000);
338 /* Hardware implementation registers */
339 spr_register(env, SPR_HID1, "HID1",
340 SPR_NOACCESS, SPR_NOACCESS,
341 &spr_read_generic, &spr_write_generic,
342 0x00000000);
343}
344
76a66253 345/* SPR specific to PowerPC 603 implementation */
a08eea67 346static void register_603_sprs(CPUPPCState *env)
3fc6c082 347{
76a66253 348 /* External access control */
76a66253 349 spr_register(env, SPR_EAR, "EAR",
3fc6c082 350 SPR_NOACCESS, SPR_NOACCESS,
76a66253
JM		 351 &spr_read_generic, &spr_write_generic,
352 0x00000000);
2bc17322 353 /* Breakpoints */
2bc17322
FC		 354 spr_register(env, SPR_IABR, "IABR",
355 SPR_NOACCESS, SPR_NOACCESS,
356 &spr_read_generic, &spr_write_generic,
357 0x00000000);
358
d2b29d0a
FR		 359 spr_register(env, SPR_HID0, "HID0",
360 SPR_NOACCESS, SPR_NOACCESS,
361 &spr_read_generic, &spr_write_generic,
362 0x00000000);
363
364 spr_register(env, SPR_HID1, "HID1",
365 SPR_NOACCESS, SPR_NOACCESS,
366 &spr_read_generic, &spr_write_generic,
367 0x00000000);
3fc6c082
FB		 368}
369
a3a27674
FR		 370static void register_e300_sprs(CPUPPCState *env)
371{
372 /* hardware implementation registers */
373 spr_register(env, SPR_HID2, "HID2",
374 SPR_NOACCESS, SPR_NOACCESS,
375 &spr_read_generic, &spr_write_generic,
376 0x00000000);
377 /* Breakpoints */
378 spr_register(env, SPR_DABR, "DABR",
379 SPR_NOACCESS, SPR_NOACCESS,
380 &spr_read_generic, &spr_write_generic,
381 0x00000000);
382
383 spr_register(env, SPR_DABR2, "DABR2",
384 SPR_NOACCESS, SPR_NOACCESS,
385 &spr_read_generic, &spr_write_generic,
386 0x00000000);
387
388 spr_register(env, SPR_IABR2, "IABR2",
389 SPR_NOACCESS, SPR_NOACCESS,
390 &spr_read_generic, &spr_write_generic,
391 0x00000000);
392
393 spr_register(env, SPR_IBCR, "IBCR",
394 SPR_NOACCESS, SPR_NOACCESS,
395 &spr_read_generic, &spr_write_generic,
396 0x00000000);
397
398 spr_register(env, SPR_DBCR, "DBCR",
399 SPR_NOACCESS, SPR_NOACCESS,
400 &spr_read_generic, &spr_write_generic,
401 0x00000000);
402}
403
76a66253 404/* SPR specific to PowerPC G2 implementation */
a08eea67 405static void register_G2_sprs(CPUPPCState *env)
3fc6c082 406{
76a66253
JM		 407 /* Memory base address */
408 /* MBAR */
409 spr_register(env, SPR_MBAR, "MBAR",
410 SPR_NOACCESS, SPR_NOACCESS,
411 &spr_read_generic, &spr_write_generic,
412 0x00000000);
76a66253 413 /* Exception processing */
363be49c 414 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 415 SPR_NOACCESS, SPR_NOACCESS,
416 &spr_read_generic, &spr_write_generic,
417 0x00000000);
363be49c 418 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
76a66253
JM		 419 SPR_NOACCESS, SPR_NOACCESS,
420 &spr_read_generic, &spr_write_generic,
421 0x00000000);
422 /* Breakpoints */
76a66253
JM		 423 spr_register(env, SPR_DABR, "DABR",
424 SPR_NOACCESS, SPR_NOACCESS,
425 &spr_read_generic, &spr_write_generic,
426 0x00000000);
acf629eb 427
76a66253
JM		 428 spr_register(env, SPR_DABR2, "DABR2",
429 SPR_NOACCESS, SPR_NOACCESS,
430 &spr_read_generic, &spr_write_generic,
431 0x00000000);
acf629eb 432
76a66253
JM		 433 spr_register(env, SPR_IABR, "IABR",
434 SPR_NOACCESS, SPR_NOACCESS,
435 &spr_read_generic, &spr_write_generic,
436 0x00000000);
acf629eb 437
76a66253
JM		 438 spr_register(env, SPR_IABR2, "IABR2",
439 SPR_NOACCESS, SPR_NOACCESS,
440 &spr_read_generic, &spr_write_generic,
441 0x00000000);
acf629eb 442
76a66253
JM		 443 spr_register(env, SPR_IBCR, "IBCR",
444 SPR_NOACCESS, SPR_NOACCESS,
445 &spr_read_generic, &spr_write_generic,
446 0x00000000);
acf629eb 447
76a66253
JM		 448 spr_register(env, SPR_DBCR, "DBCR",
449 SPR_NOACCESS, SPR_NOACCESS,
450 &spr_read_generic, &spr_write_generic,
451 0x00000000);
e599bced
FR		 452
453 /* External access control */
454 spr_register(env, SPR_EAR, "EAR",
455 SPR_NOACCESS, SPR_NOACCESS,
456 &spr_read_generic, &spr_write_generic,
457 0x00000000);
458 /* Hardware implementation register */
459 spr_register(env, SPR_HID0, "HID0",
460 SPR_NOACCESS, SPR_NOACCESS,
461 &spr_read_generic, &spr_write_generic,
462 0x00000000);
463
464 spr_register(env, SPR_HID1, "HID1",
465 SPR_NOACCESS, SPR_NOACCESS,
466 &spr_read_generic, &spr_write_generic,
467 0x00000000);
468
469 spr_register(env, SPR_HID2, "HID2",
470 SPR_NOACCESS, SPR_NOACCESS,
471 &spr_read_generic, &spr_write_generic,
472 0x00000000);
473
1a71c5d1
FR		 474 /* SGPRs */
475 spr_register(env, SPR_SPRG4, "SPRG4",
476 SPR_NOACCESS, SPR_NOACCESS,
477 &spr_read_generic, &spr_write_generic,
478 0x00000000);
479 spr_register(env, SPR_SPRG5, "SPRG5",
480 SPR_NOACCESS, SPR_NOACCESS,
481 &spr_read_generic, &spr_write_generic,
482 0x00000000);
483 spr_register(env, SPR_SPRG6, "SPRG6",
484 SPR_NOACCESS, SPR_NOACCESS,
485 &spr_read_generic, &spr_write_generic,
486 0x00000000);
487 spr_register(env, SPR_SPRG7, "SPRG7",
488 SPR_NOACCESS, SPR_NOACCESS,
489 &spr_read_generic, &spr_write_generic,
490 0x00000000);
76a66253
JM		 491}
492
a08eea67 493static void register_74xx_sprs(CPUPPCState *env)
a750fc0b 494{
674f4509
FR		 495 /* Breakpoints */
496 spr_register_kvm(env, SPR_DABR, "DABR",
497 SPR_NOACCESS, SPR_NOACCESS,
498 &spr_read_generic, &spr_write_generic,
499 KVM_REG_PPC_DABR, 0x00000000);
500
501 spr_register(env, SPR_IABR, "IABR",
502 SPR_NOACCESS, SPR_NOACCESS,
503 &spr_read_generic, &spr_write_generic,
504 0x00000000);
505 /* Cache management */
506 spr_register(env, SPR_ICTC, "ICTC",
507 SPR_NOACCESS, SPR_NOACCESS,
508 &spr_read_generic, &spr_write_generic,
509 0x00000000);
510 /* Performance monitors */
511 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
512 SPR_NOACCESS, SPR_NOACCESS,
513 &spr_read_generic, &spr_write_generic,
514 0x00000000);
515
516 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
517 SPR_NOACCESS, SPR_NOACCESS,
518 &spr_read_generic, &spr_write_generic,
519 0x00000000);
520
521 spr_register(env, SPR_7XX_PMC1, "PMC1",
522 SPR_NOACCESS, SPR_NOACCESS,
523 &spr_read_generic, &spr_write_generic,
524 0x00000000);
525
526 spr_register(env, SPR_7XX_PMC2, "PMC2",
527 SPR_NOACCESS, SPR_NOACCESS,
528 &spr_read_generic, &spr_write_generic,
529 0x00000000);
530
531 spr_register(env, SPR_7XX_PMC3, "PMC3",
532 SPR_NOACCESS, SPR_NOACCESS,
533 &spr_read_generic, &spr_write_generic,
534 0x00000000);
535
536 spr_register(env, SPR_7XX_PMC4, "PMC4",
537 SPR_NOACCESS, SPR_NOACCESS,
538 &spr_read_generic, &spr_write_generic,
539 0x00000000);
540
541 spr_register(env, SPR_7XX_SIAR, "SIAR",
542 SPR_NOACCESS, SPR_NOACCESS,
543 &spr_read_generic, SPR_NOACCESS,
544 0x00000000);
545
546 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
547 &spr_read_ureg, SPR_NOACCESS,
548 &spr_read_ureg, SPR_NOACCESS,
549 0x00000000);
550
551 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
552 &spr_read_ureg, SPR_NOACCESS,
553 &spr_read_ureg, SPR_NOACCESS,
554 0x00000000);
555
556 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
557 &spr_read_ureg, SPR_NOACCESS,
558 &spr_read_ureg, SPR_NOACCESS,
559 0x00000000);
560
561 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
562 &spr_read_ureg, SPR_NOACCESS,
563 &spr_read_ureg, SPR_NOACCESS,
564 0x00000000);
565
566 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
567 &spr_read_ureg, SPR_NOACCESS,
568 &spr_read_ureg, SPR_NOACCESS,
569 0x00000000);
570
571 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
572 &spr_read_ureg, SPR_NOACCESS,
573 &spr_read_ureg, SPR_NOACCESS,
574 0x00000000);
575
576 spr_register(env, SPR_7XX_USIAR, "USIAR",
577 &spr_read_ureg, SPR_NOACCESS,
578 &spr_read_ureg, SPR_NOACCESS,
579 0x00000000);
580 /* External access control */
581 spr_register(env, SPR_EAR, "EAR",
582 SPR_NOACCESS, SPR_NOACCESS,
583 &spr_read_generic, &spr_write_generic,
584 0x00000000);
585
a750fc0b
JM		 586 /* Processor identification */
587 spr_register(env, SPR_PIR, "PIR",
588 SPR_NOACCESS, SPR_NOACCESS,
589 &spr_read_generic, &spr_write_pir,
590 0x00000000);
acf629eb 591
cb8b8bf8 592 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
a750fc0b
JM		 593 SPR_NOACCESS, SPR_NOACCESS,
594 &spr_read_generic, &spr_write_generic,
595 0x00000000);
acf629eb 596
cb8b8bf8 597 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
a750fc0b
JM		 598 &spr_read_ureg, SPR_NOACCESS,
599 &spr_read_ureg, SPR_NOACCESS,
600 0x00000000);
acf629eb 601
a750fc0b
JM		 602 spr_register(env, SPR_BAMR, "BAMR",
603 SPR_NOACCESS, SPR_NOACCESS,
604 &spr_read_generic, &spr_write_generic,
605 0x00000000);
acf629eb 606
a750fc0b
JM		 607 spr_register(env, SPR_MSSCR0, "MSSCR0",
608 SPR_NOACCESS, SPR_NOACCESS,
609 &spr_read_generic, &spr_write_generic,
610 0x00000000);
611 /* Hardware implementation registers */
a750fc0b
JM		 612 spr_register(env, SPR_HID0, "HID0",
613 SPR_NOACCESS, SPR_NOACCESS,
614 &spr_read_generic, &spr_write_generic,
615 0x00000000);
acf629eb 616
a750fc0b
JM		 617 spr_register(env, SPR_HID1, "HID1",
618 SPR_NOACCESS, SPR_NOACCESS,
619 &spr_read_generic, &spr_write_generic,
620 0x00000000);
621 /* Altivec */
622 spr_register(env, SPR_VRSAVE, "VRSAVE",
623 &spr_read_generic, &spr_write_generic,
624 &spr_read_generic, &spr_write_generic,
625 0x00000000);
acf629eb 626
bd928eba
JM		 627 spr_register(env, SPR_L2CR, "L2CR",
628 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 629 &spr_read_generic, spr_access_nop,
bd928eba 630 0x00000000);
a750fc0b
JM		 631}
632
a08eea67 633static void register_l3_ctrl(CPUPPCState *env)
a750fc0b
JM		 634{
635 /* L3CR */
a750fc0b
JM		 636 spr_register(env, SPR_L3CR, "L3CR",
637 SPR_NOACCESS, SPR_NOACCESS,
638 &spr_read_generic, &spr_write_generic,
639 0x00000000);
640 /* L3ITCR0 */
641 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
642 SPR_NOACCESS, SPR_NOACCESS,
643 &spr_read_generic, &spr_write_generic,
644 0x00000000);
a750fc0b
JM		 645 /* L3PM */
646 spr_register(env, SPR_L3PM, "L3PM",
647 SPR_NOACCESS, SPR_NOACCESS,
648 &spr_read_generic, &spr_write_generic,
649 0x00000000);
650}
a750fc0b 651
80d11f44 652/* PowerPC BookE SPR */
a08eea67 653static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
80d11f44 654{
b55266b5 655 const char *ivor_names[64] = {
80d11f44
JM		 656 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
657 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
658 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
659 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
660 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
661 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
662 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
663 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
664 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
665 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
666 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
667 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
668 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
669 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
670 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
671 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
672 };
673#define SPR_BOOKE_IVORxx (-1)
674 int ivor_sprn[64] = {
675 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
676 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
677 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
678 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
679 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
683 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
e9205258
AG		 684 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
685 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
80d11f44
JM		 686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
691 };
692 int i;
693
76a66253 694 /* Interrupt processing */
363be49c 695 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
76a66253
JM		 696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_generic, &spr_write_generic,
698 0x00000000);
363be49c
JM		 699 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
700 SPR_NOACCESS, SPR_NOACCESS,
701 &spr_read_generic, &spr_write_generic,
702 0x00000000);
76a66253 703 /* Debug */
76a66253
JM		 704 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
705 SPR_NOACCESS, SPR_NOACCESS,
706 &spr_read_generic, &spr_write_generic,
707 0x00000000);
acf629eb 708
76a66253
JM		 709 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
acf629eb 713
76a66253
JM		 714 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
acf629eb 718
76a66253
JM		 719 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
acf629eb 723
76a66253
JM		 724 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
725 SPR_NOACCESS, SPR_NOACCESS,
e598a9c5 726 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253 727 0x00000000);
acf629eb 728
76a66253
JM		 729 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 0x00000000);
acf629eb 733
76a66253
JM		 734 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_generic, &spr_write_generic,
737 0x00000000);
0e3bf489
RK		 738 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_generic, &spr_write_generic,
741 0x00000000);
742 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_generic, &spr_write_generic,
745 0x00000000);
acf629eb 746
76a66253
JM		 747 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
748 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 749 &spr_read_generic, &spr_write_clear,
76a66253
JM		 750 0x00000000);
751 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
752 SPR_NOACCESS, SPR_NOACCESS,
753 &spr_read_generic, &spr_write_generic,
754 0x00000000);
755 spr_register(env, SPR_BOOKE_ESR, "ESR",
756 SPR_NOACCESS, SPR_NOACCESS,
757 &spr_read_generic, &spr_write_generic,
758 0x00000000);
363be49c
JM		 759 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
760 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 761 &spr_read_generic, &spr_write_excp_prefix,
363be49c
JM		 762 0x00000000);
763 /* Exception vectors */
80d11f44
JM		 764 for (i = 0; i < 64; i++) {
765 if (ivor_mask & (1ULL << i)) {
766 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
767 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
768 exit(1);
769 }
770 spr_register(env, ivor_sprn[i], ivor_names[i],
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_generic, &spr_write_excp_vector,
773 0x00000000);
774 }
775 }
76a66253
JM		 776 spr_register(env, SPR_BOOKE_PID, "PID",
777 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 778 &spr_read_generic, &spr_write_booke_pid,
76a66253
JM		 779 0x00000000);
780 spr_register(env, SPR_BOOKE_TCR, "TCR",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_generic, &spr_write_booke_tcr,
783 0x00000000);
784 spr_register(env, SPR_BOOKE_TSR, "TSR",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_booke_tsr,
787 0x00000000);
788 /* Timer */
789 spr_register(env, SPR_DECR, "DECR",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_decr, &spr_write_decr,
792 0x00000000);
793 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
794 SPR_NOACCESS, SPR_NOACCESS,
795 SPR_NOACCESS, &spr_write_generic,
796 0x00000000);
797 /* SPRGs */
798 spr_register(env, SPR_USPRG0, "USPRG0",
799 &spr_read_generic, &spr_write_generic,
800 &spr_read_generic, &spr_write_generic,
801 0x00000000);
802 spr_register(env, SPR_SPRG4, "SPRG4",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_generic, &spr_write_generic,
805 0x00000000);
76a66253
JM		 806 spr_register(env, SPR_SPRG5, "SPRG5",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 0x00000000);
76a66253
JM		 810 spr_register(env, SPR_SPRG6, "SPRG6",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 0x00000000);
76a66253
JM		 814 spr_register(env, SPR_SPRG7, "SPRG7",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_generic, &spr_write_generic,
817 0x00000000);
0e3bf489
RK		 818 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_generic, &spr_write_generic,
821 0x00000000);
822 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_generic, &spr_write_generic,
825 0x00000000);
76a66253
JM		 826}
827
3e770bf7 828#if !defined(CONFIG_USER_ONLY)
a08eea67 829static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize,
01662f3e
AG		 830 uint32_t maxsize, uint32_t flags,
831 uint32_t nentries)
832{
833 return (assoc << TLBnCFG_ASSOC_SHIFT) |
834 (minsize << TLBnCFG_MINSIZE_SHIFT) |
835 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
836 flags | nentries;
837}
3e770bf7 838#endif /* !CONFIG_USER_ONLY */
01662f3e
AG		 839
840/* BookE 2.06 storage control registers */
a08eea67 841static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
d21ee633 842 uint32_t *tlbncfg, uint32_t mmucfg)
363be49c 843{
f2e63a42 844#if !defined(CONFIG_USER_ONLY)
b55266b5 845 const char *mas_names[8] = {
80d11f44
JM		 846 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
847 };
848 int mas_sprn[8] = {
849 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
850 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
851 };
852 int i;
853
363be49c 854 /* TLB assist registers */
80d11f44
JM		 855 for (i = 0; i < 8; i++) {
856 if (mas_mask & (1 << i)) {
857 spr_register(env, mas_sprn[i], mas_names[i],
858 SPR_NOACCESS, SPR_NOACCESS,
52e9612e
BL		 859 &spr_read_generic,
860 (i == 2 && (env->insns_flags & PPC_64B))
861 ? &spr_write_generic : &spr_write_generic32,
80d11f44
JM		 862 0x00000000);
863 }
864 }
363be49c
JM		 865 if (env->nb_pids > 1) {
866 spr_register(env, SPR_BOOKE_PID1, "PID1",
867 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 868 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 869 0x00000000);
870 }
871 if (env->nb_pids > 2) {
872 spr_register(env, SPR_BOOKE_PID2, "PID2",
873 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 874 &spr_read_generic, &spr_write_booke_pid,
363be49c
JM		 875 0x00000000);
876 }
50728199
RK		 877
878 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_generic, &spr_write_eplc,
881 0x00000000);
882 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_generic, &spr_write_epsc,
885 0x00000000);
886
65f9ee8d 887 spr_register(env, SPR_MMUCFG, "MMUCFG",
363be49c
JM		 888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
d21ee633 890 mmucfg);
363be49c
JM		 891 switch (env->nb_ways) {
892 case 4:
893 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, SPR_NOACCESS,
01662f3e 896 tlbncfg[3]);
363be49c
JM		 897 /* Fallthru */
898 case 3:
899 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
01662f3e 902 tlbncfg[2]);
363be49c
JM		 903 /* Fallthru */
904 case 2:
905 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, SPR_NOACCESS,
01662f3e 908 tlbncfg[1]);
363be49c
JM		 909 /* Fallthru */
910 case 1:
911 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
912 SPR_NOACCESS, SPR_NOACCESS,
913 &spr_read_generic, SPR_NOACCESS,
01662f3e 914 tlbncfg[0]);
363be49c
JM		 915 /* Fallthru */
916 case 0:
917 default:
918 break;
919 }
f2e63a42 920#endif
363be49c
JM		 921}
922
76a66253 923/* SPR specific to PowerPC 440 implementation */
a08eea67 924static void register_440_sprs(CPUPPCState *env)
76a66253
JM		 925{
926 /* Cache control */
76a66253
JM		 927 spr_register(env, SPR_440_DNV0, "DNV0",
928 SPR_NOACCESS, SPR_NOACCESS,
929 &spr_read_generic, &spr_write_generic,
930 0x00000000);
acf629eb 931
76a66253
JM		 932 spr_register(env, SPR_440_DNV1, "DNV1",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_generic, &spr_write_generic,
935 0x00000000);
acf629eb 936
76a66253
JM		 937 spr_register(env, SPR_440_DNV2, "DNV2",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 0x00000000);
acf629eb 941
76a66253
JM		 942 spr_register(env, SPR_440_DNV3, "DNV3",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
acf629eb 946
2662a059 947 spr_register(env, SPR_440_DTV0, "DTV0",
76a66253
JM		 948 SPR_NOACCESS, SPR_NOACCESS,
949 &spr_read_generic, &spr_write_generic,
950 0x00000000);
acf629eb 951
2662a059 952 spr_register(env, SPR_440_DTV1, "DTV1",
76a66253
JM		 953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_generic, &spr_write_generic,
955 0x00000000);
acf629eb 956
2662a059 957 spr_register(env, SPR_440_DTV2, "DTV2",
76a66253
JM		 958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
acf629eb 961
2662a059 962 spr_register(env, SPR_440_DTV3, "DTV3",
76a66253
JM		 963 SPR_NOACCESS, SPR_NOACCESS,
964 &spr_read_generic, &spr_write_generic,
965 0x00000000);
acf629eb 966
76a66253
JM		 967 spr_register(env, SPR_440_DVLIM, "DVLIM",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, &spr_write_generic,
970 0x00000000);
acf629eb 971
76a66253
JM		 972 spr_register(env, SPR_440_INV0, "INV0",
973 SPR_NOACCESS, SPR_NOACCESS,
974 &spr_read_generic, &spr_write_generic,
975 0x00000000);
acf629eb 976
76a66253
JM		 977 spr_register(env, SPR_440_INV1, "INV1",
978 SPR_NOACCESS, SPR_NOACCESS,
979 &spr_read_generic, &spr_write_generic,
980 0x00000000);
acf629eb 981
76a66253
JM		 982 spr_register(env, SPR_440_INV2, "INV2",
983 SPR_NOACCESS, SPR_NOACCESS,
984 &spr_read_generic, &spr_write_generic,
985 0x00000000);
acf629eb 986
76a66253
JM		 987 spr_register(env, SPR_440_INV3, "INV3",
988 SPR_NOACCESS, SPR_NOACCESS,
989 &spr_read_generic, &spr_write_generic,
990 0x00000000);
acf629eb 991
2662a059 992 spr_register(env, SPR_440_ITV0, "ITV0",
76a66253
JM		 993 SPR_NOACCESS, SPR_NOACCESS,
994 &spr_read_generic, &spr_write_generic,
995 0x00000000);
acf629eb 996
2662a059 997 spr_register(env, SPR_440_ITV1, "ITV1",
76a66253
JM		 998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, &spr_write_generic,
1000 0x00000000);
acf629eb 1001
2662a059 1002 spr_register(env, SPR_440_ITV2, "ITV2",
76a66253
JM		 1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
acf629eb 1006
2662a059 1007 spr_register(env, SPR_440_ITV3, "ITV3",
76a66253
JM		 1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
acf629eb 1011
76a66253
JM		 1012 spr_register(env, SPR_440_IVLIM, "IVLIM",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016 /* Cache debug */
2662a059 1017 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
76a66253
JM		 1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, SPR_NOACCESS,
1020 0x00000000);
acf629eb 1021
2662a059 1022 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
76a66253
JM		 1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, SPR_NOACCESS,
1025 0x00000000);
acf629eb 1026
2662a059 1027 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, SPR_NOACCESS,
1030 0x00000000);
acf629eb 1031
2662a059 1032 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
76a66253
JM		 1033 SPR_NOACCESS, SPR_NOACCESS,
1034 &spr_read_generic, SPR_NOACCESS,
1035 0x00000000);
acf629eb 1036
2662a059 1037 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
76a66253
JM		 1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, SPR_NOACCESS,
1040 0x00000000);
acf629eb 1041
76a66253
JM		 1042 spr_register(env, SPR_440_DBDR, "DBDR",
1043 SPR_NOACCESS, SPR_NOACCESS,
1044 &spr_read_generic, &spr_write_generic,
1045 0x00000000);
1046 /* Processor control */
1047 spr_register(env, SPR_4xx_CCR0, "CCR0",
1048 SPR_NOACCESS, SPR_NOACCESS,
1049 &spr_read_generic, &spr_write_generic,
1050 0x00000000);
1051 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1052 SPR_NOACCESS, SPR_NOACCESS,
1053 &spr_read_generic, SPR_NOACCESS,
1054 0x00000000);
1055 /* Storage control */
1056 spr_register(env, SPR_440_MMUCR, "MMUCR",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
49ed82b2
FR		 1060
1061 /* Processor identification */
1062 spr_register(env, SPR_BOOKE_PIR, "PIR",
1063 SPR_NOACCESS, SPR_NOACCESS,
1064 &spr_read_generic, &spr_write_pir,
1065 0x00000000);
1066
1067 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 0x00000000);
1071
1072 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1073 SPR_NOACCESS, SPR_NOACCESS,
1074 &spr_read_generic, &spr_write_generic,
1075 0x00000000);
1076
1077 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1078 SPR_NOACCESS, SPR_NOACCESS,
1079 &spr_read_generic, &spr_write_generic,
1080 0x00000000);
1081
1082 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1083 SPR_NOACCESS, SPR_NOACCESS,
1084 &spr_read_generic, &spr_write_generic,
1085 0x00000000);
76a66253
JM		 1086}
1087
1088/* SPR shared between PowerPC 40x implementations */
a08eea67 1089static void register_40x_sprs(CPUPPCState *env)
76a66253
JM		 1090{
1091 /* Cache */
5cbdb3a3 1092 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1093 spr_register(env, SPR_40x_DCCR, "DCCR",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
5cbdb3a3 1097 /* not emulated, as QEMU do not emulate caches */
76a66253
JM		 1098 spr_register(env, SPR_40x_ICCR, "ICCR",
1099 SPR_NOACCESS, SPR_NOACCESS,
1100 &spr_read_generic, &spr_write_generic,
1101 0x00000000);
5cbdb3a3 1102 /* not emulated, as QEMU do not emulate caches */
2662a059 1103 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
76a66253
JM		 1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, SPR_NOACCESS,
1106 0x00000000);
76a66253
JM		 1107 /* Exception */
1108 spr_register(env, SPR_40x_DEAR, "DEAR",
1109 SPR_NOACCESS, SPR_NOACCESS,
1110 &spr_read_generic, &spr_write_generic,
1111 0x00000000);
1112 spr_register(env, SPR_40x_ESR, "ESR",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 spr_register(env, SPR_40x_EVPR, "EVPR",
1117 SPR_NOACCESS, SPR_NOACCESS,
6f5d427d 1118 &spr_read_generic, &spr_write_excp_prefix,
76a66253
JM		 1119 0x00000000);
1120 spr_register(env, SPR_40x_SRR2, "SRR2",
1121 &spr_read_generic, &spr_write_generic,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 spr_register(env, SPR_40x_SRR3, "SRR3",
1125 &spr_read_generic, &spr_write_generic,
1126 &spr_read_generic, &spr_write_generic,
1127 0x00000000);
1128 /* Timers */
1129 spr_register(env, SPR_40x_PIT, "PIT",
1130 SPR_NOACCESS, SPR_NOACCESS,
1131 &spr_read_40x_pit, &spr_write_40x_pit,
1132 0x00000000);
1133 spr_register(env, SPR_40x_TCR, "TCR",
1134 SPR_NOACCESS, SPR_NOACCESS,
cbd8f17d 1135 &spr_read_generic, &spr_write_40x_tcr,
76a66253
JM		 1136 0x00000000);
1137 spr_register(env, SPR_40x_TSR, "TSR",
1138 SPR_NOACCESS, SPR_NOACCESS,
cbd8f17d 1139 &spr_read_generic, &spr_write_40x_tsr,
76a66253 1140 0x00000000);
2662a059
JM		 1141}
1142
1143/* SPR specific to PowerPC 405 implementation */
a08eea67 1144static void register_405_sprs(CPUPPCState *env)
2662a059
JM		 1145{
1146 /* MMU */
1147 spr_register(env, SPR_40x_PID, "PID",
76a66253 1148 SPR_NOACCESS, SPR_NOACCESS,
dd69d140 1149 &spr_read_generic, &spr_write_40x_pid,
76a66253 1150 0x00000000);
2662a059 1151 spr_register(env, SPR_4xx_CCR0, "CCR0",
76a66253
JM		 1152 SPR_NOACCESS, SPR_NOACCESS,
1153 &spr_read_generic, &spr_write_generic,
2662a059
JM		 1154 0x00700000);
1155 /* Debug interface */
76a66253
JM		 1156 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1157 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913 1158 &spr_read_generic, &spr_write_40x_dbcr0,
76a66253 1159 0x00000000);
acf629eb 1160
2662a059
JM		 1161 spr_register(env, SPR_405_DBCR1, "DBCR1",
1162 SPR_NOACCESS, SPR_NOACCESS,
1163 &spr_read_generic, &spr_write_generic,
1164 0x00000000);
acf629eb 1165
76a66253
JM		 1166 spr_register(env, SPR_40x_DBSR, "DBSR",
1167 SPR_NOACCESS, SPR_NOACCESS,
8ecc7913
JM		 1168 &spr_read_generic, &spr_write_clear,
1169 /* Last reset was system reset */
76a66253 1170 0x00000300);
acf629eb 1171
2662a059 1172 spr_register(env, SPR_40x_DAC1, "DAC1",
76a66253
JM		 1173 SPR_NOACCESS, SPR_NOACCESS,
1174 &spr_read_generic, &spr_write_generic,
1175 0x00000000);
2662a059 1176 spr_register(env, SPR_40x_DAC2, "DAC2",
76a66253
JM		 1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
acf629eb 1180
2662a059 1181 spr_register(env, SPR_405_DVC1, "DVC1",
76a66253
JM		 1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
2662a059 1184 0x00000000);
acf629eb 1185
2662a059 1186 spr_register(env, SPR_405_DVC2, "DVC2",
76a66253
JM		 1187 SPR_NOACCESS, SPR_NOACCESS,
1188 &spr_read_generic, &spr_write_generic,
1189 0x00000000);
acf629eb 1190
2662a059 1191 spr_register(env, SPR_40x_IAC1, "IAC1",
76a66253
JM		 1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
2662a059 1195 spr_register(env, SPR_40x_IAC2, "IAC2",
76a66253
JM		 1196 SPR_NOACCESS, SPR_NOACCESS,
1197 &spr_read_generic, &spr_write_generic,
1198 0x00000000);
acf629eb 1199
76a66253
JM		 1200 spr_register(env, SPR_405_IAC3, "IAC3",
1201 SPR_NOACCESS, SPR_NOACCESS,
1202 &spr_read_generic, &spr_write_generic,
1203 0x00000000);
acf629eb 1204
76a66253
JM		 1205 spr_register(env, SPR_405_IAC4, "IAC4",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_generic,
1208 0x00000000);
1209 /* Storage control */
76a66253
JM		 1210 spr_register(env, SPR_405_SLER, "SLER",
1211 SPR_NOACCESS, SPR_NOACCESS,
c294fc58 1212 &spr_read_generic, &spr_write_40x_sler,
76a66253 1213 0x00000000);
2662a059
JM		 1214 spr_register(env, SPR_40x_ZPR, "ZPR",
1215 SPR_NOACCESS, SPR_NOACCESS,
1216 &spr_read_generic, &spr_write_generic,
1217 0x00000000);
acf629eb 1218
76a66253
JM		 1219 spr_register(env, SPR_405_SU0R, "SU0R",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_generic,
1222 0x00000000);
1223 /* SPRG */
1224 spr_register(env, SPR_USPRG0, "USPRG0",
1225 &spr_read_ureg, SPR_NOACCESS,
1226 &spr_read_ureg, SPR_NOACCESS,
1227 0x00000000);
1228 spr_register(env, SPR_SPRG4, "SPRG4",
1229 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1230 &spr_read_generic, &spr_write_generic,
76a66253 1231 0x00000000);
76a66253
JM		 1232 spr_register(env, SPR_SPRG5, "SPRG5",
1233 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1234 spr_read_generic, &spr_write_generic,
76a66253 1235 0x00000000);
76a66253
JM		 1236 spr_register(env, SPR_SPRG6, "SPRG6",
1237 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1238 spr_read_generic, &spr_write_generic,
76a66253 1239 0x00000000);
76a66253
JM		 1240 spr_register(env, SPR_SPRG7, "SPRG7",
1241 SPR_NOACCESS, SPR_NOACCESS,
04f20795 1242 spr_read_generic, &spr_write_generic,
76a66253 1243 0x00000000);
acd1f788
FR		 1244
1245 /* Bus access control */
1246 /* not emulated, as QEMU never does speculative access */
1247 spr_register(env, SPR_40x_SGR, "SGR",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0xFFFFFFFF);
1251 /* not emulated, as QEMU do not emulate caches */
1252 spr_register(env, SPR_40x_DCWR, "DCWR",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1255 0x00000000);
76a66253
JM		 1256}
1257
a750fc0b 1258
a08eea67 1259static void register_5xx_8xx_sprs(CPUPPCState *env)
e1833e1f 1260{
80d11f44 1261 /* Exception processing */
d67d40ea
DG		 1262 spr_register_kvm(env, SPR_DSISR, "DSISR",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_generic, &spr_write_generic,
1265 KVM_REG_PPC_DSISR, 0x00000000);
1266 spr_register_kvm(env, SPR_DAR, "DAR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 KVM_REG_PPC_DAR, 0x00000000);
80d11f44
JM		 1270 /* Timer */
1271 spr_register(env, SPR_DECR, "DECR",
1272 SPR_NOACCESS, SPR_NOACCESS,
1273 &spr_read_decr, &spr_write_decr,
1274 0x00000000);
acf629eb 1275
80d11f44
JM		 1276 spr_register(env, SPR_MPC_EIE, "EIE",
1277 SPR_NOACCESS, SPR_NOACCESS,
1278 &spr_read_generic, &spr_write_generic,
1279 0x00000000);
acf629eb 1280
80d11f44
JM		 1281 spr_register(env, SPR_MPC_EID, "EID",
1282 SPR_NOACCESS, SPR_NOACCESS,
1283 &spr_read_generic, &spr_write_generic,
1284 0x00000000);
acf629eb 1285
80d11f44
JM		 1286 spr_register(env, SPR_MPC_NRI, "NRI",
1287 SPR_NOACCESS, SPR_NOACCESS,
1288 &spr_read_generic, &spr_write_generic,
1289 0x00000000);
acf629eb 1290
80d11f44
JM		 1291 spr_register(env, SPR_MPC_CMPA, "CMPA",
1292 SPR_NOACCESS, SPR_NOACCESS,
1293 &spr_read_generic, &spr_write_generic,
1294 0x00000000);
acf629eb 1295
80d11f44
JM		 1296 spr_register(env, SPR_MPC_CMPB, "CMPB",
1297 SPR_NOACCESS, SPR_NOACCESS,
1298 &spr_read_generic, &spr_write_generic,
1299 0x00000000);
acf629eb 1300
80d11f44
JM		 1301 spr_register(env, SPR_MPC_CMPC, "CMPC",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
acf629eb 1305
80d11f44
JM		 1306 spr_register(env, SPR_MPC_CMPD, "CMPD",
1307 SPR_NOACCESS, SPR_NOACCESS,
1308 &spr_read_generic, &spr_write_generic,
1309 0x00000000);
acf629eb 1310
80d11f44
JM		 1311 spr_register(env, SPR_MPC_ECR, "ECR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
acf629eb 1315
80d11f44
JM		 1316 spr_register(env, SPR_MPC_DER, "DER",
1317 SPR_NOACCESS, SPR_NOACCESS,
1318 &spr_read_generic, &spr_write_generic,
1319 0x00000000);
acf629eb 1320
80d11f44
JM		 1321 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_generic, &spr_write_generic,
1324 0x00000000);
acf629eb 1325
80d11f44
JM		 1326 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_generic, &spr_write_generic,
1329 0x00000000);
acf629eb 1330
80d11f44
JM		 1331 spr_register(env, SPR_MPC_CMPE, "CMPE",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_generic, &spr_write_generic,
1334 0x00000000);
acf629eb 1335
80d11f44
JM		 1336 spr_register(env, SPR_MPC_CMPF, "CMPF",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
acf629eb 1340
80d11f44
JM		 1341 spr_register(env, SPR_MPC_CMPG, "CMPG",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
acf629eb 1345
80d11f44
JM		 1346 spr_register(env, SPR_MPC_CMPH, "CMPH",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
acf629eb 1350
80d11f44
JM		 1351 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
1352 SPR_NOACCESS, SPR_NOACCESS,
1353 &spr_read_generic, &spr_write_generic,
1354 0x00000000);
acf629eb 1355
80d11f44
JM		 1356 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
acf629eb 1360
80d11f44
JM		 1361 spr_register(env, SPR_MPC_BAR, "BAR",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
acf629eb 1365
80d11f44
JM		 1366 spr_register(env, SPR_MPC_DPDR, "DPDR",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
acf629eb 1370
80d11f44
JM		 1371 spr_register(env, SPR_MPC_IMMR, "IMMR",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375}
1376
a08eea67 1377static void register_5xx_sprs(CPUPPCState *env)
80d11f44 1378{
80d11f44
JM		 1379 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
1380 SPR_NOACCESS, SPR_NOACCESS,
1381 &spr_read_generic, &spr_write_generic,
1382 0x00000000);
acf629eb 1383
80d11f44
JM		 1384 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
1385 SPR_NOACCESS, SPR_NOACCESS,
1386 &spr_read_generic, &spr_write_generic,
1387 0x00000000);
acf629eb 1388
80d11f44
JM		 1389 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
acf629eb 1393
80d11f44
JM		 1394 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
1395 SPR_NOACCESS, SPR_NOACCESS,
1396 &spr_read_generic, &spr_write_generic,
1397 0x00000000);
acf629eb 1398
80d11f44
JM		 1399 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
1400 SPR_NOACCESS, SPR_NOACCESS,
1401 &spr_read_generic, &spr_write_generic,
1402 0x00000000);
acf629eb 1403
80d11f44
JM		 1404 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
1405 SPR_NOACCESS, SPR_NOACCESS,
1406 &spr_read_generic, &spr_write_generic,
1407 0x00000000);
acf629eb 1408
80d11f44
JM		 1409 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
acf629eb 1413
80d11f44
JM		 1414 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
1415 SPR_NOACCESS, SPR_NOACCESS,
1416 &spr_read_generic, &spr_write_generic,
1417 0x00000000);
acf629eb 1418
80d11f44
JM		 1419 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
acf629eb 1423
80d11f44
JM		 1424 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
acf629eb 1428
80d11f44
JM		 1429 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
acf629eb 1433
80d11f44
JM		 1434 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
acf629eb 1438
80d11f44
JM		 1439 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
acf629eb 1443
80d11f44
JM		 1444 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
acf629eb 1448
80d11f44
JM		 1449 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
acf629eb 1453
80d11f44
JM		 1454 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
acf629eb 1458
80d11f44
JM		 1459 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
acf629eb 1463
80d11f44
JM		 1464 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
1465 SPR_NOACCESS, SPR_NOACCESS,
1466 &spr_read_generic, &spr_write_generic,
1467 0x00000000);
acf629eb 1468
80d11f44
JM		 1469 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_generic, &spr_write_generic,
1472 0x00000000);
acf629eb 1473
80d11f44
JM		 1474 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
1475 SPR_NOACCESS, SPR_NOACCESS,
1476 &spr_read_generic, &spr_write_generic,
1477 0x00000000);
acf629eb 1478
80d11f44
JM		 1479 spr_register(env, SPR_RCPU_FPECR, "FPECR",
1480 SPR_NOACCESS, SPR_NOACCESS,
1481 &spr_read_generic, &spr_write_generic,
1482 0x00000000);
1483}
1484
a08eea67 1485static void register_8xx_sprs(CPUPPCState *env)
80d11f44 1486{
acf629eb 1487
80d11f44
JM		 1488 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_generic,
1491 0x00000000);
acf629eb 1492
80d11f44
JM		 1493 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
acf629eb 1497
80d11f44
JM		 1498 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_generic, &spr_write_generic,
1501 0x00000000);
acf629eb 1502
80d11f44
JM		 1503 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
acf629eb 1507
80d11f44
JM		 1508 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
acf629eb 1512
80d11f44
JM		 1513 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
1514 SPR_NOACCESS, SPR_NOACCESS,
1515 &spr_read_generic, &spr_write_generic,
1516 0x00000000);
acf629eb 1517
80d11f44
JM		 1518 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
acf629eb 1522
80d11f44
JM		 1523 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 &spr_read_generic, &spr_write_generic,
1526 0x00000000);
acf629eb 1527
80d11f44
JM		 1528 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
1529 SPR_NOACCESS, SPR_NOACCESS,
1530 &spr_read_generic, &spr_write_generic,
1531 0x00000000);
acf629eb 1532
80d11f44
JM		 1533 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
1534 SPR_NOACCESS, SPR_NOACCESS,
1535 &spr_read_generic, &spr_write_generic,
1536 0x00000000);
acf629eb 1537
80d11f44
JM		 1538 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
acf629eb 1542
80d11f44
JM		 1543 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
acf629eb 1547
80d11f44
JM		 1548 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
acf629eb 1552
80d11f44
JM		 1553 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
acf629eb 1557
80d11f44
JM		 1558 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
acf629eb 1562
80d11f44
JM		 1563 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
acf629eb 1567
80d11f44
JM		 1568 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
acf629eb 1572
80d11f44
JM		 1573 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_generic,
1576 0x00000000);
acf629eb 1577
80d11f44
JM		 1578 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
acf629eb 1582
80d11f44
JM		 1583 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
acf629eb 1587
80d11f44
JM		 1588 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
acf629eb 1592
80d11f44
JM		 1593 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_generic,
1596 0x00000000);
acf629eb 1597
80d11f44
JM		 1598 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1601 0x00000000);
acf629eb 1602
80d11f44
JM		 1603 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
1604 SPR_NOACCESS, SPR_NOACCESS,
1605 &spr_read_generic, &spr_write_generic,
1606 0x00000000);
acf629eb 1607
80d11f44
JM		 1608 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1611 0x00000000);
1612}
1613
80d11f44
JM		 1614/*
1615 * AMR => SPR 29 (Power 2.04)
1616 * CTRL => SPR 136 (Power 2.04)
1617 * CTRL => SPR 152 (Power 2.04)
1618 * SCOMC => SPR 276 (64 bits ?)
1619 * SCOMD => SPR 277 (64 bits ?)
1620 * TBU40 => SPR 286 (Power 2.04 hypv)
1621 * HSPRG0 => SPR 304 (Power 2.04 hypv)
1622 * HSPRG1 => SPR 305 (Power 2.04 hypv)
1623 * HDSISR => SPR 306 (Power 2.04 hypv)
1624 * HDAR => SPR 307 (Power 2.04 hypv)
1625 * PURR => SPR 309 (Power 2.04 hypv)
1626 * HDEC => SPR 310 (Power 2.04 hypv)
1627 * HIOR => SPR 311 (hypv)
1628 * RMOR => SPR 312 (970)
1629 * HRMOR => SPR 313 (Power 2.04 hypv)
1630 * HSRR0 => SPR 314 (Power 2.04 hypv)
1631 * HSRR1 => SPR 315 (Power 2.04 hypv)
80d11f44 1632 * LPIDR => SPR 317 (970)
80d11f44
JM		 1633 * EPR => SPR 702 (Power 2.04 emb)
1634 * perf => 768-783 (Power 2.04)
1635 * perf => 784-799 (Power 2.04)
1636 * PPR => SPR 896 (Power 2.04)
80d11f44
JM		 1637 * DABRX => 1015 (Power 2.04 hypv)
1638 * FPECR => SPR 1022 (?)
1639 * ... and more (thermal management, performance counters, ...)
1640 */
1641
1642/*****************************************************************************/
1643/* Exception vectors models */
c364946d 1644static void init_excp_4xx_softmmu(CPUPPCState *env)
80d11f44
JM		 1645{
1646#if !defined(CONFIG_USER_ONLY)
1647 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
1648 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1649 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1650 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1651 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1652 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1653 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1654 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1655 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
1656 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
1657 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
1658 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
1659 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
1660 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
80d11f44
JM		 1661 env->ivor_mask = 0x0000FFF0UL;
1662 env->ivpr_mask = 0xFFFF0000UL;
1663 /* Hardware reset vector */
1664 env->hreset_vector = 0xFFFFFFFCUL;
1665#endif
1666}
1667
c364946d 1668static void init_excp_MPC5xx(CPUPPCState *env)
80d11f44
JM		 1669{
1670#if !defined(CONFIG_USER_ONLY)
1671 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1672 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1673 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1674 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1675 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
6328a3bb 1676 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
80d11f44
JM		 1677 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1678 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1679 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1680 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1681 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1682 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1683 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1684 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1685 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
80d11f44
JM		 1686 env->ivor_mask = 0x0000FFF0UL;
1687 env->ivpr_mask = 0xFFFF0000UL;
1688 /* Hardware reset vector */
09d9828a 1689 env->hreset_vector = 0x00000100UL;
80d11f44
JM		 1690#endif
1691}
1692
c364946d 1693static void init_excp_MPC8xx(CPUPPCState *env)
e1833e1f
JM		 1694{
1695#if !defined(CONFIG_USER_ONLY)
1696 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1697 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1698 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1699 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1700 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1701 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1702 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
6328a3bb 1703 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
e1833e1f 1704 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 1705 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
80d11f44
JM		 1706 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1707 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
1708 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
1709 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
1710 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
1711 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
1712 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
1713 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
1714 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
1715 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
1716 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
80d11f44
JM		 1717 env->ivor_mask = 0x0000FFF0UL;
1718 env->ivpr_mask = 0xFFFF0000UL;
1c27f8fb 1719 /* Hardware reset vector */
09d9828a 1720 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 1721#endif
1722}
1723
c364946d 1724static void init_excp_G2(CPUPPCState *env)
e1833e1f
JM		 1725{
1726#if !defined(CONFIG_USER_ONLY)
1727 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1728 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1729 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1730 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1731 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1732 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1733 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1734 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1735 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
80d11f44 1736 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
e1833e1f
JM		 1737 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1738 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
e1833e1f
JM		 1739 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1740 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1741 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1742 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1743 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
80d11f44 1744 /* Hardware reset vector */
09d9828a 1745 env->hreset_vector = 0x00000100UL;
80d11f44
JM		 1746#endif
1747}
1748
e9cd84b9 1749static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
80d11f44
JM		 1750{
1751#if !defined(CONFIG_USER_ONLY)
1752 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
1753 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1754 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1755 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1756 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1757 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1758 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1759 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1760 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1761 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1762 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1763 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1764 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1765 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1766 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1767 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1768 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
7fc1dc83
FR		 1769 /*
1770 * These two are the same IVOR as POWERPC_EXCP_VPU and
1771 * POWERPC_EXCP_VPUA. We deal with that when dispatching at
1772 * powerpc_excp().
1773 */
80d11f44
JM		 1774 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
1775 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
7fc1dc83 1776
80d11f44 1777 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
80d11f44 1778 env->ivor_mask = 0x0000FFF7UL;
e9cd84b9 1779 env->ivpr_mask = ivpr_mask;
80d11f44
JM		 1780 /* Hardware reset vector */
1781 env->hreset_vector = 0xFFFFFFFCUL;
1782#endif
1783}
1784
c364946d 1785static void init_excp_BookE(CPUPPCState *env)
80d11f44
JM		 1786{
1787#if !defined(CONFIG_USER_ONLY)
1788 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
1789 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
1790 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
1791 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
1792 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
1793 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
1794 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
1795 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
1796 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
1797 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
1798 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
1799 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
1800 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
1801 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
1802 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
1803 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
8412d112 1804 env->ivor_mask = 0x0000FFF0UL;
80d11f44
JM		 1805 env->ivpr_mask = 0xFFFF0000UL;
1806 /* Hardware reset vector */
1807 env->hreset_vector = 0xFFFFFFFCUL;
1808#endif
1809}
1810
c364946d 1811static void init_excp_603(CPUPPCState *env)
e1833e1f
JM		 1812{
1813#if !defined(CONFIG_USER_ONLY)
1814 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1815 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1816 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1817 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1818 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1819 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1820 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1821 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1822 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f
JM		 1823 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1824 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1825 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1826 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1827 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
1828 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1829 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb 1830 /* Hardware reset vector */
09d9828a 1831 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 1832#endif
1833}
1834
c364946d 1835static void init_excp_604(CPUPPCState *env)
e1833e1f
JM		 1836{
1837#if !defined(CONFIG_USER_ONLY)
1838 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1847 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1848 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1849 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1850 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1851 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1c27f8fb 1852 /* Hardware reset vector */
2d3eb7bf 1853 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 1854#endif
1855}
1856
c364946d 1857static void init_excp_7x0(CPUPPCState *env)
e1833e1f
JM		 1858{
1859#if !defined(CONFIG_USER_ONLY)
1860 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1861 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1862 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1863 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1864 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1865 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1866 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1867 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1868 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1869 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1870 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1871 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1872 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
bd928eba 1873 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
e1833e1f 1874 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 1875 /* Hardware reset vector */
09d9828a 1876 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 1877#endif
1878}
1879
c364946d 1880static void init_excp_750cl(CPUPPCState *env)
e1833e1f
JM		 1881{
1882#if !defined(CONFIG_USER_ONLY)
1883 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1884 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1885 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1886 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1887 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1888 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1889 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1890 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1891 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1892 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1893 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1894 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1895 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1896 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 1897 /* Hardware reset vector */
09d9828a 1898 env->hreset_vector = 0x00000100UL;
bd928eba
JM		 1899#endif
1900}
1901
c364946d 1902static void init_excp_750cx(CPUPPCState *env)
bd928eba
JM		 1903{
1904#if !defined(CONFIG_USER_ONLY)
1905 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1906 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1907 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1908 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1909 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1910 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1911 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1912 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1913 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1914 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1915 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1916 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1917 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
e1833e1f 1918 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 1919 /* Hardware reset vector */
09d9828a 1920 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 1921#endif
1922}
1923
7a3a6927 1924/* XXX: Check if this is correct */
c364946d 1925static void init_excp_7x5(CPUPPCState *env)
7a3a6927
JM		 1926{
1927#if !defined(CONFIG_USER_ONLY)
1928 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1929 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1930 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1931 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1932 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1933 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1934 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1935 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1936 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1937 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1938 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
bd928eba 1939 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
7a3a6927
JM		 1940 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
1941 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
1942 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
7a3a6927
JM		 1943 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1944 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
bd928eba 1945 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
7a3a6927 1946 /* Hardware reset vector */
09d9828a 1947 env->hreset_vector = 0x00000100UL;
7a3a6927
JM		 1948#endif
1949}
1950
c364946d 1951static void init_excp_7400(CPUPPCState *env)
e1833e1f
JM		 1952{
1953#if !defined(CONFIG_USER_ONLY)
1954 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1955 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1956 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1957 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1958 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1959 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1960 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1961 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1962 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1963 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1964 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1965 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1966 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1967 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1968 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1969 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1970 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
1c27f8fb 1971 /* Hardware reset vector */
09d9828a 1972 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 1973#endif
1974}
1975
c364946d 1976static void init_excp_7450(CPUPPCState *env)
e1833e1f
JM		 1977{
1978#if !defined(CONFIG_USER_ONLY)
1979 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
1980 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
1981 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
1982 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
1983 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
1984 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
1985 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
1986 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
1987 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
1988 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
1989 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
1990 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
1991 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
e1833e1f
JM		 1992 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
1993 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
1994 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
1c27f8fb 1995 /* Hardware reset vector */
09d9828a 1996 env->hreset_vector = 0x00000100UL;
e1833e1f
JM		 1997#endif
1998}
e1833e1f 1999
c364946d
DG		 2000#if defined(TARGET_PPC64)
2001static void init_excp_970(CPUPPCState *env)
e1833e1f
JM		 2002{
2003#if !defined(CONFIG_USER_ONLY)
2004 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2005 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2006 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2007 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2008 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2009 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2010 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2011 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2012 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2013 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2014 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
e1833e1f 2015 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
e1833e1f
JM		 2016 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2017 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2018 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2019 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2020 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2021 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
2022 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
2023 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
1c27f8fb
JM		 2024 /* Hardware reset vector */
2025 env->hreset_vector = 0x0000000000000100ULL;
e1833e1f
JM		 2026#endif
2027}
9d52e907 2028
c364946d 2029static void init_excp_POWER7(CPUPPCState *env)
9d52e907
DG		 2030{
2031#if !defined(CONFIG_USER_ONLY)
2032 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2033 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2034 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2035 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
2036 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2037 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
2038 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2039 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2040 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2041 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2042 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2043 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
2044 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2045 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
f03a1af5
BH		 2046 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00;
2047 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20;
2048 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40;
2049 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60;
9d52e907
DG		 2050 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2051 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
1f29871c 2052 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
9d52e907
DG		 2053 /* Hardware reset vector */
2054 env->hreset_vector = 0x0000000000000100ULL;
2055#endif
2056}
f03a1af5
BH		 2057
2058static void init_excp_POWER8(CPUPPCState *env)
2059{
2060 init_excp_POWER7(env);
2061
2062#if !defined(CONFIG_USER_ONLY)
2063 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00;
2064 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
2065 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
2066 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
cb76bbc4
DHB		 2067
2068 /* Userland exceptions without vector value in PowerISA v3.1 */
2069 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
2070 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
f03a1af5
BH		 2071#endif
2072}
2073
d8ce5fd6
BH		 2074static void init_excp_POWER9(CPUPPCState *env)
2075{
2076 init_excp_POWER8(env);
2077
2078#if !defined(CONFIG_USER_ONLY)
2079 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0;
8b7e6b07 2080 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000;
d8ce5fd6
BH		 2081#endif
2082}
2083
7d37b274
CLG		 2084static void init_excp_POWER10(CPUPPCState *env)
2085{
2086 init_excp_POWER9(env);
2087}
2088
e1833e1f
JM		 2089#endif
2090
c364946d 2091static int check_pow_hid0(CPUPPCState *env)
2f462816 2092{
1d28b5f6 2093 if (env->spr[SPR_HID0] & 0x00E00000) {
2f462816 2094 return 1;
1d28b5f6 2095 }
2f462816
JM		 2096
2097 return 0;
2098}
2099
c364946d 2100static int check_pow_hid0_74xx(CPUPPCState *env)
4e777442 2101{
1d28b5f6 2102 if (env->spr[SPR_HID0] & 0x00600000) {
4e777442 2103 return 1;
1d28b5f6 2104 }
4e777442
JM		 2105
2106 return 0;
2107}
2108
c364946d 2109static void init_proc_405(CPUPPCState *env)
80d11f44 2110{
a08eea67
BL		 2111 register_40x_sprs(env);
2112 register_405_sprs(env);
4ffb8c5e 2113 register_usprgh_sprs(env);
acd1f788 2114
80d11f44
JM		 2115 /* Memory management */
2116#if !defined(CONFIG_USER_ONLY)
2117 env->nb_tlb = 64;
2118 env->nb_ways = 1;
2119 env->id_tlbs = 0;
1c53accc 2120 env->tlb_type = TLB_EMB;
80d11f44
JM		 2121#endif
2122 init_excp_4xx_softmmu(env);
2123 env->dcache_line_size = 32;
2124 env->icache_line_size = 32;
2125 /* Allocate hardware IRQ controller */
db70b311 2126 ppc40x_irq_init(env_archcpu(env));
ddd1055b
FC		 2127
2128 SET_FIT_PERIOD(8, 12, 16, 20);
2129 SET_WDT_PERIOD(16, 20, 24, 28);
80d11f44
JM		 2130}
2131
7856e3a4
AF		 2132POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
2133{
ca5dff0a 2134 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2135 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2136
ca5dff0a 2137 dc->desc = "PowerPC 405";
7856e3a4
AF		 2138 pcc->init_proc = init_proc_405;
2139 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 2140 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2141 PPC_DCR | PPC_WRTEE |
2142 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
2143 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2144 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2145 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
2146 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
645d843c 2147 pcc->msr_mask = (1ull << MSR_WE) |
9df5a466
TM		 2148 (1ull << MSR_CE) |
2149 (1ull << MSR_EE) |
2150 (1ull << MSR_PR) |
2151 (1ull << MSR_FP) |
301e5d48 2152 (1ull << MSR_ME) |
9df5a466
TM		 2153 (1ull << MSR_DWE) |
2154 (1ull << MSR_DE) |
2155 (1ull << MSR_IR) |
2156 (1ull << MSR_DR);
ba9fd9f1
AF		 2157 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
2158 pcc->excp_model = POWERPC_EXCP_40x;
2159 pcc->bus_model = PPC_FLAGS_INPUT_405;
2160 pcc->bfd_mach = bfd_mach_ppc_403;
2161 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2162 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2163}
2164
c364946d 2165static void init_proc_440EP(CPUPPCState *env)
80d11f44 2166{
a08eea67
BL		 2167 register_BookE_sprs(env, 0x000000000000FFFFULL);
2168 register_440_sprs(env);
2169 register_usprgh_sprs(env);
acf629eb 2170
80d11f44
JM		 2171 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 &spr_read_generic, &spr_write_generic,
2178 0x00000000);
2179 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 &spr_read_generic, &spr_write_generic,
2182 0x00000000);
acf629eb 2183
80d11f44
JM		 2184 spr_register(env, SPR_440_CCR1, "CCR1",
2185 SPR_NOACCESS, SPR_NOACCESS,
2186 &spr_read_generic, &spr_write_generic,
2187 0x00000000);
2188 /* Memory management */
2189#if !defined(CONFIG_USER_ONLY)
2190 env->nb_tlb = 64;
2191 env->nb_ways = 1;
2192 env->id_tlbs = 0;
1c53accc 2193 env->tlb_type = TLB_EMB;
80d11f44
JM		 2194#endif
2195 init_excp_BookE(env);
2196 env->dcache_line_size = 32;
2197 env->icache_line_size = 32;
db70b311 2198 ppc40x_irq_init(env_archcpu(env));
ddd1055b
FC		 2199
2200 SET_FIT_PERIOD(12, 16, 20, 24);
2201 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 2202}
2203
7856e3a4
AF		 2204POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
2205{
ca5dff0a 2206 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2207 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2208
ca5dff0a 2209 dc->desc = "PowerPC 440 EP";
7856e3a4
AF		 2210 pcc->init_proc = init_proc_440EP;
2211 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 2212 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2213 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2214 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2215 PPC_FLOAT_STFIWX |
2216 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2217 PPC_CACHE | PPC_CACHE_ICBI |
2218 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2219 PPC_MEM_TLBSYNC | PPC_MFTB |
2220 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2221 PPC_440_SPEC;
81bb29ac
BZ		 2222 pcc->msr_mask = (1ull << MSR_POW) |
2223 (1ull << MSR_CE) |
2224 (1ull << MSR_EE) |
2225 (1ull << MSR_PR) |
2226 (1ull << MSR_FP) |
2227 (1ull << MSR_ME) |
2228 (1ull << MSR_FE0) |
2229 (1ull << MSR_DWE) |
2230 (1ull << MSR_DE) |
2231 (1ull << MSR_FE1) |
2232 (1ull << MSR_IR) |
2233 (1ull << MSR_DR);
2234 pcc->mmu_model = POWERPC_MMU_BOOKE;
2235 pcc->excp_model = POWERPC_EXCP_BOOKE;
2236 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2237 pcc->bfd_mach = bfd_mach_ppc_403;
2238 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2239 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
2240}
2241
2242POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
2243{
2244 DeviceClass *dc = DEVICE_CLASS(oc);
2245 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2246
2247 dc->desc = "PowerPC 460 EX";
2248 pcc->init_proc = init_proc_440EP;
2249 pcc->check_pow = check_pow_nocheck;
2250 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2251 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
2252 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
2253 PPC_FLOAT_STFIWX |
2254 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI |
2255 PPC_CACHE | PPC_CACHE_ICBI |
2256 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2257 PPC_MEM_TLBSYNC | PPC_MFTB |
2258 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2259 PPC_440_SPEC;
9df5a466
TM		 2260 pcc->msr_mask = (1ull << MSR_POW) |
2261 (1ull << MSR_CE) |
2262 (1ull << MSR_EE) |
2263 (1ull << MSR_PR) |
2264 (1ull << MSR_FP) |
2265 (1ull << MSR_ME) |
2266 (1ull << MSR_FE0) |
2267 (1ull << MSR_DWE) |
2268 (1ull << MSR_DE) |
2269 (1ull << MSR_FE1) |
2270 (1ull << MSR_IR) |
2271 (1ull << MSR_DR);
ba9fd9f1
AF		 2272 pcc->mmu_model = POWERPC_MMU_BOOKE;
2273 pcc->excp_model = POWERPC_EXCP_BOOKE;
2274 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2275 pcc->bfd_mach = bfd_mach_ppc_403;
2276 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2277 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2278}
2279
c364946d 2280static void init_proc_440GP(CPUPPCState *env)
80d11f44 2281{
a08eea67
BL		 2282 register_BookE_sprs(env, 0x000000000000FFFFULL);
2283 register_440_sprs(env);
2284 register_usprgh_sprs(env);
acf629eb 2285
80d11f44
JM		 2286 /* Memory management */
2287#if !defined(CONFIG_USER_ONLY)
2288 env->nb_tlb = 64;
2289 env->nb_ways = 1;
2290 env->id_tlbs = 0;
1c53accc 2291 env->tlb_type = TLB_EMB;
80d11f44
JM		 2292#endif
2293 init_excp_BookE(env);
2294 env->dcache_line_size = 32;
2295 env->icache_line_size = 32;
2296 /* XXX: TODO: allocate internal IRQ controller */
ddd1055b
FC		 2297
2298 SET_FIT_PERIOD(12, 16, 20, 24);
2299 SET_WDT_PERIOD(20, 24, 28, 32);
80d11f44
JM		 2300}
2301
7856e3a4
AF		 2302POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
2303{
ca5dff0a 2304 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2305 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2306
ca5dff0a 2307 dc->desc = "PowerPC 440 GP";
7856e3a4
AF		 2308 pcc->init_proc = init_proc_440GP;
2309 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 2310 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2311 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
2312 PPC_CACHE | PPC_CACHE_ICBI |
2313 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2314 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
2315 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
53116ebf 2316 PPC_440_SPEC;
9df5a466
TM		 2317 pcc->msr_mask = (1ull << MSR_POW) |
2318 (1ull << MSR_CE) |
2319 (1ull << MSR_EE) |
2320 (1ull << MSR_PR) |
2321 (1ull << MSR_FP) |
2322 (1ull << MSR_ME) |
2323 (1ull << MSR_FE0) |
2324 (1ull << MSR_DWE) |
2325 (1ull << MSR_DE) |
2326 (1ull << MSR_FE1) |
2327 (1ull << MSR_IR) |
2328 (1ull << MSR_DR);
ba9fd9f1
AF		 2329 pcc->mmu_model = POWERPC_MMU_BOOKE;
2330 pcc->excp_model = POWERPC_EXCP_BOOKE;
2331 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2332 pcc->bfd_mach = bfd_mach_ppc_403;
2333 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2334 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2335}
2336
c364946d 2337static void init_proc_440x5(CPUPPCState *env)
3fc6c082 2338{
a08eea67
BL		 2339 register_BookE_sprs(env, 0x000000000000FFFFULL);
2340 register_440_sprs(env);
2341 register_usprgh_sprs(env);
acf629eb 2342
80d11f44
JM		 2343 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2344 SPR_NOACCESS, SPR_NOACCESS,
2345 &spr_read_generic, &spr_write_generic,
2346 0x00000000);
2347 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 &spr_read_generic, &spr_write_generic,
2350 0x00000000);
2351 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2352 SPR_NOACCESS, SPR_NOACCESS,
2353 &spr_read_generic, &spr_write_generic,
2354 0x00000000);
acf629eb 2355
80d11f44 2356 spr_register(env, SPR_440_CCR1, "CCR1",
a750fc0b
JM		 2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_generic, &spr_write_generic,
2359 0x00000000);
2360 /* Memory management */
f2e63a42 2361#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 2362 env->nb_tlb = 64;
2363 env->nb_ways = 1;
2364 env->id_tlbs = 0;
1c53accc 2365 env->tlb_type = TLB_EMB;
f2e63a42 2366#endif
80d11f44 2367 init_excp_BookE(env);
d63001d1
JM		 2368 env->dcache_line_size = 32;
2369 env->icache_line_size = 32;
db70b311 2370 ppc40x_irq_init(env_archcpu(env));
ddd1055b
FC		 2371
2372 SET_FIT_PERIOD(12, 16, 20, 24);
2373 SET_WDT_PERIOD(20, 24, 28, 32);
3fc6c082
FB		 2374}
2375
7856e3a4
AF		 2376POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
2377{
ca5dff0a 2378 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2379 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2380
ca5dff0a 2381 dc->desc = "PowerPC 440x5";
7856e3a4
AF		 2382 pcc->init_proc = init_proc_440x5;
2383 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 2384 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2385 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2386 PPC_CACHE | PPC_CACHE_ICBI |
2387 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2388 PPC_MEM_TLBSYNC | PPC_MFTB |
2389 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2390 PPC_440_SPEC;
9df5a466
TM		 2391 pcc->msr_mask = (1ull << MSR_POW) |
2392 (1ull << MSR_CE) |
2393 (1ull << MSR_EE) |
2394 (1ull << MSR_PR) |
2395 (1ull << MSR_FP) |
2396 (1ull << MSR_ME) |
2397 (1ull << MSR_FE0) |
2398 (1ull << MSR_DWE) |
2399 (1ull << MSR_DE) |
2400 (1ull << MSR_FE1) |
2401 (1ull << MSR_IR) |
2402 (1ull << MSR_DR);
ba9fd9f1
AF		 2403 pcc->mmu_model = POWERPC_MMU_BOOKE;
2404 pcc->excp_model = POWERPC_EXCP_BOOKE;
2405 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2406 pcc->bfd_mach = bfd_mach_ppc_403;
2407 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2408 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2409}
2410
b8c867ed
PM		 2411POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
2412{
2413 DeviceClass *dc = DEVICE_CLASS(oc);
2414 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2415
2416 dc->desc = "PowerPC 440x5 with double precision FPU";
2417 pcc->init_proc = init_proc_440x5;
2418 pcc->check_pow = check_pow_nocheck;
2419 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2420 PPC_FLOAT | PPC_FLOAT_FSQRT |
2421 PPC_FLOAT_STFIWX |
2422 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
2423 PPC_CACHE | PPC_CACHE_ICBI |
2424 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2425 PPC_MEM_TLBSYNC | PPC_MFTB |
2426 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
2427 PPC_440_SPEC;
2428 pcc->insns_flags2 = PPC2_FP_CVT_S64;
9df5a466
TM		 2429 pcc->msr_mask = (1ull << MSR_POW) |
2430 (1ull << MSR_CE) |
2431 (1ull << MSR_EE) |
2432 (1ull << MSR_PR) |
2433 (1ull << MSR_FP) |
2434 (1ull << MSR_ME) |
2435 (1ull << MSR_FE0) |
2436 (1ull << MSR_DWE) |
2437 (1ull << MSR_DE) |
2438 (1ull << MSR_FE1) |
2439 (1ull << MSR_IR) |
2440 (1ull << MSR_DR);
ba9fd9f1
AF		 2441 pcc->mmu_model = POWERPC_MMU_BOOKE;
2442 pcc->excp_model = POWERPC_EXCP_BOOKE;
2443 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2444 pcc->bfd_mach = bfd_mach_ppc_403;
2445 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
2446 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2447}
2448
c364946d 2449static void init_proc_MPC5xx(CPUPPCState *env)
80d11f44 2450{
a08eea67
BL		 2451 register_5xx_8xx_sprs(env);
2452 register_5xx_sprs(env);
80d11f44
JM		 2453 init_excp_MPC5xx(env);
2454 env->dcache_line_size = 32;
2455 env->icache_line_size = 32;
2456 /* XXX: TODO: allocate internal IRQ controller */
2457}
2458
7856e3a4
AF		 2459POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
2460{
ca5dff0a 2461 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2462 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2463
ca5dff0a 2464 dc->desc = "Freescale 5xx cores (aka RCPU)";
7856e3a4
AF		 2465 pcc->init_proc = init_proc_MPC5xx;
2466 pcc->check_pow = check_pow_none;
53116ebf
AF		 2467 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2468 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2469 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
2470 PPC_MFTB;
9df5a466
TM		 2471 pcc->msr_mask = (1ull << MSR_ILE) |
2472 (1ull << MSR_EE) |
2473 (1ull << MSR_PR) |
2474 (1ull << MSR_FP) |
2475 (1ull << MSR_ME) |
2476 (1ull << MSR_FE0) |
2477 (1ull << MSR_SE) |
2478 (1ull << MSR_DE) |
2479 (1ull << MSR_FE1) |
2480 (1ull << MSR_EP) |
2481 (1ull << MSR_RI) |
2482 (1ull << MSR_LE);
ba9fd9f1 2483 pcc->mmu_model = POWERPC_MMU_REAL;
9323650f 2484 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 2485 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2486 pcc->bfd_mach = bfd_mach_ppc_505;
2487 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2488 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2489}
2490
c364946d 2491static void init_proc_MPC8xx(CPUPPCState *env)
80d11f44 2492{
a08eea67
BL		 2493 register_5xx_8xx_sprs(env);
2494 register_8xx_sprs(env);
80d11f44
JM		 2495 init_excp_MPC8xx(env);
2496 env->dcache_line_size = 32;
2497 env->icache_line_size = 32;
2498 /* XXX: TODO: allocate internal IRQ controller */
2499}
2500
7856e3a4
AF		 2501POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
2502{
ca5dff0a 2503 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2504 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2505
ca5dff0a 2506 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
7856e3a4
AF		 2507 pcc->init_proc = init_proc_MPC8xx;
2508 pcc->check_pow = check_pow_none;
53116ebf
AF		 2509 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
2510 PPC_MEM_EIEIO | PPC_MEM_SYNC |
2511 PPC_CACHE_ICBI | PPC_MFTB;
9df5a466
TM		 2512 pcc->msr_mask = (1ull << MSR_ILE) |
2513 (1ull << MSR_EE) |
2514 (1ull << MSR_PR) |
2515 (1ull << MSR_FP) |
2516 (1ull << MSR_ME) |
2517 (1ull << MSR_SE) |
2518 (1ull << MSR_DE) |
2519 (1ull << MSR_EP) |
2520 (1ull << MSR_IR) |
2521 (1ull << MSR_DR) |
2522 (1ull << MSR_RI) |
2523 (1ull << MSR_LE);
ba9fd9f1 2524 pcc->mmu_model = POWERPC_MMU_MPC8xx;
9323650f 2525 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 2526 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
2527 pcc->bfd_mach = bfd_mach_ppc_860;
2528 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
2529 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2530}
2531
80d11f44 2532/* Freescale 82xx cores (aka PowerQUICC-II) */
ca5dff0a 2533
c364946d 2534static void init_proc_G2(CPUPPCState *env)
3fc6c082 2535{
217781af 2536 register_non_embedded_sprs(env);
a08eea67 2537 register_sdr1_sprs(env);
a08eea67 2538 register_G2_sprs(env);
acf629eb 2539
a750fc0b 2540 /* Memory management */
a08eea67
BL		 2541 register_low_BATs(env);
2542 register_high_BATs(env);
2543 register_6xx_7xx_soft_tlb(env, 64, 2);
80d11f44 2544 init_excp_G2(env);
d63001d1
JM		 2545 env->dcache_line_size = 32;
2546 env->icache_line_size = 32;
80d11f44 2547 /* Allocate hardware IRQ controller */
db70b311 2548 ppc6xx_irq_init(env_archcpu(env));
3fc6c082 2549}
a750fc0b 2550
7856e3a4
AF		 2551POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
2552{
ca5dff0a 2553 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2554 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2555
ca5dff0a 2556 dc->desc = "PowerPC G2";
7856e3a4
AF		 2557 pcc->init_proc = init_proc_G2;
2558 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 2559 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2561 PPC_FLOAT_STFIWX |
2562 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2563 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2564 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2565 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 2566 pcc->msr_mask = (1ull << MSR_POW) |
2567 (1ull << MSR_TGPR) |
2568 (1ull << MSR_EE) |
2569 (1ull << MSR_PR) |
2570 (1ull << MSR_FP) |
2571 (1ull << MSR_ME) |
2572 (1ull << MSR_FE0) |
2573 (1ull << MSR_SE) |
2574 (1ull << MSR_DE) |
2575 (1ull << MSR_FE1) |
2576 (1ull << MSR_AL) |
2577 (1ull << MSR_EP) |
2578 (1ull << MSR_IR) |
2579 (1ull << MSR_DR) |
2580 (1ull << MSR_RI);
ba9fd9f1 2581 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
9323650f 2582 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 2583 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2584 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2585 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2586 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2587}
2588
7856e3a4
AF		 2589POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
2590{
ca5dff0a 2591 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2593
ca5dff0a 2594 dc->desc = "PowerPC G2LE";
363bd7d0 2595 pcc->init_proc = init_proc_G2;
7856e3a4 2596 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 2597 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
2598 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
2599 PPC_FLOAT_STFIWX |
2600 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
2601 PPC_MEM_SYNC | PPC_MEM_EIEIO |
2602 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
2603 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 2604 pcc->msr_mask = (1ull << MSR_POW) |
2605 (1ull << MSR_TGPR) |
2606 (1ull << MSR_ILE) |
2607 (1ull << MSR_EE) |
2608 (1ull << MSR_PR) |
2609 (1ull << MSR_FP) |
2610 (1ull << MSR_ME) |
2611 (1ull << MSR_FE0) |
2612 (1ull << MSR_SE) |
2613 (1ull << MSR_DE) |
2614 (1ull << MSR_FE1) |
2615 (1ull << MSR_AL) |
2616 (1ull << MSR_EP) |
2617 (1ull << MSR_IR) |
2618 (1ull << MSR_DR) |
2619 (1ull << MSR_RI) |
2620 (1ull << MSR_LE);
ba9fd9f1 2621 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
9323650f 2622 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 2623 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
2624 pcc->bfd_mach = bfd_mach_ppc_ec603e;
2625 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
2626 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2627}
2628
c364946d 2629static void init_proc_e200(CPUPPCState *env)
3fc6c082 2630{
a08eea67 2631 register_BookE_sprs(env, 0x000000070000FFFFULL);
acf629eb 2632
80d11f44 2633 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 2634 &spr_read_spefscr, &spr_write_spefscr,
2635 &spr_read_spefscr, &spr_write_spefscr,
e1833e1f 2636 0x00000000);
80d11f44 2637 /* Memory management */
a08eea67 2638 register_BookE206_sprs(env, 0x0000005D, NULL, 0);
4ffb8c5e 2639 register_usprgh_sprs(env);
acf629eb 2640
80d11f44 2641 spr_register(env, SPR_HID0, "HID0",
e1833e1f
JM		 2642 SPR_NOACCESS, SPR_NOACCESS,
2643 &spr_read_generic, &spr_write_generic,
2644 0x00000000);
acf629eb 2645
80d11f44 2646 spr_register(env, SPR_HID1, "HID1",
e1833e1f
JM		 2647 SPR_NOACCESS, SPR_NOACCESS,
2648 &spr_read_generic, &spr_write_generic,
2649 0x00000000);
acf629eb 2650
80d11f44 2651 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
e1833e1f
JM		 2652 SPR_NOACCESS, SPR_NOACCESS,
2653 &spr_read_generic, &spr_write_generic,
2654 0x00000000);
acf629eb 2655
80d11f44
JM		 2656 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
2657 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f 2658 &spr_read_generic, &spr_write_generic,
80d11f44 2659 0x00000000);
acf629eb 2660
80d11f44
JM		 2661 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
2662 SPR_NOACCESS, SPR_NOACCESS,
2663 &spr_read_generic, &spr_write_generic,
2664 0x00000000);
acf629eb 2665
80d11f44
JM		 2666 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
2667 SPR_NOACCESS, SPR_NOACCESS,
2668 &spr_read_generic, &spr_write_generic,
2669 0x00000000);
acf629eb 2670
80d11f44
JM		 2671 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
2672 SPR_NOACCESS, SPR_NOACCESS,
2673 &spr_read_generic, &spr_write_generic,
2674 0x00000000);
acf629eb 2675
80d11f44 2676 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
deb05c4c
AG		 2677 &spr_read_generic, SPR_NOACCESS,
2678 &spr_read_generic, SPR_NOACCESS,
80d11f44 2679 0x00000000);
acf629eb 2680
80d11f44
JM		 2681 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2682 SPR_NOACCESS, SPR_NOACCESS,
2683 &spr_read_generic, &spr_write_generic,
2684 0x00000000);
acf629eb 2685
80d11f44
JM		 2686 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
2687 SPR_NOACCESS, SPR_NOACCESS,
2688 &spr_read_generic, &spr_write_generic,
2689 0x00000000);
acf629eb 2690
80d11f44
JM		 2691 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2692 SPR_NOACCESS, SPR_NOACCESS,
2693 &spr_read_generic, &spr_write_generic,
2694 0x00000000);
acf629eb 2695
80d11f44
JM		 2696 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2697 SPR_NOACCESS, SPR_NOACCESS,
2698 &spr_read_generic, &spr_write_generic,
2699 0x00000000);
acf629eb 2700
80d11f44
JM		 2701 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
2702 SPR_NOACCESS, SPR_NOACCESS,
2703 &spr_read_generic, &spr_write_generic,
2704 0x00000000);
acf629eb 2705
80d11f44
JM		 2706 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
2707 SPR_NOACCESS, SPR_NOACCESS,
2708 &spr_read_generic, &spr_write_generic,
2709 0x00000000);
acf629eb 2710
01662f3e
AG		 2711 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2712 SPR_NOACCESS, SPR_NOACCESS,
2713 &spr_read_generic, &spr_write_generic,
2714 0x00000000); /* TOFIX */
80d11f44
JM		 2715 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
2716 SPR_NOACCESS, SPR_NOACCESS,
2717 &spr_read_generic, &spr_write_generic,
2718 0x00000000);
2719 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
2720 SPR_NOACCESS, SPR_NOACCESS,
e1833e1f
JM		 2721 &spr_read_generic, &spr_write_generic,
2722 0x00000000);
f2e63a42 2723#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 2724 env->nb_tlb = 64;
2725 env->nb_ways = 1;
2726 env->id_tlbs = 0;
1c53accc 2727 env->tlb_type = TLB_EMB;
f2e63a42 2728#endif
e9cd84b9 2729 init_excp_e200(env, 0xFFFF0000UL);
d63001d1
JM		 2730 env->dcache_line_size = 32;
2731 env->icache_line_size = 32;
e1833e1f 2732 /* XXX: TODO: allocate internal IRQ controller */
3fc6c082 2733}
a750fc0b 2734
7856e3a4
AF		 2735POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
2736{
ca5dff0a 2737 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 2738 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2739
ca5dff0a 2740 dc->desc = "e200 core";
7856e3a4
AF		 2741 pcc->init_proc = init_proc_e200;
2742 pcc->check_pow = check_pow_hid0;
1d28b5f6
DG		 2743 /*
2744 * XXX: unimplemented instructions:
53116ebf
AF		 2745 * dcblc
2746 * dcbtlst
2747 * dcbtstls
2748 * icblc
2749 * icbtls
2750 * tlbivax
2751 * all SPE multiply-accumulate instructions
2752 */
2753 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
2754 PPC_SPE | PPC_SPE_SINGLE |
2755 PPC_WRTEE | PPC_RFDI |
2756 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
2757 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
2758 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
2759 PPC_BOOKE;
9df5a466
TM		 2760 pcc->msr_mask = (1ull << MSR_UCLE) |
2761 (1ull << MSR_SPE) |
2762 (1ull << MSR_POW) |
2763 (1ull << MSR_CE) |
2764 (1ull << MSR_EE) |
2765 (1ull << MSR_PR) |
2766 (1ull << MSR_FP) |
2767 (1ull << MSR_ME) |
2768 (1ull << MSR_FE0) |
2769 (1ull << MSR_DWE) |
2770 (1ull << MSR_DE) |
2771 (1ull << MSR_FE1) |
2772 (1ull << MSR_IR) |
2773 (1ull << MSR_DR);
ba9fd9f1
AF		 2774 pcc->mmu_model = POWERPC_MMU_BOOKE206;
2775 pcc->excp_model = POWERPC_EXCP_BOOKE;
2776 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
2777 pcc->bfd_mach = bfd_mach_ppc_860;
2778 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
2779 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
2780 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 2781}
2782
f7aa5583
VS		 2783enum fsl_e500_version {
2784 fsl_e500v1,
2785 fsl_e500v2,
2786 fsl_e500mc,
b81ccf8a 2787 fsl_e5500,
54a50dae 2788 fsl_e6500,
f7aa5583
VS		 2789};
2790
c364946d 2791static void init_proc_e500(CPUPPCState *env, int version)
80d11f44 2792{
01662f3e 2793 uint32_t tlbncfg[2];
b81ccf8a 2794 uint64_t ivor_mask;
e9cd84b9 2795 uint64_t ivpr_mask = 0xFFFF0000ULL;
a496e8ee
AG		 2796 uint32_t l1cfg0 = 0x3800 /* 8 ways */
2797 | 0x0020; /* 32 kb */
d2ea2bf7
AG		 2798 uint32_t l1cfg1 = 0x3800 /* 8 ways */
2799 | 0x0020; /* 32 kb */
d21ee633 2800 uint32_t mmucfg = 0;
01662f3e
AG		 2801#if !defined(CONFIG_USER_ONLY)
2802 int i;
2803#endif
2804
01662f3e
AG		 2805 /*
2806 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
2807 * complain when accessing them.
a08eea67 2808 * register_BookE_sprs(env, 0x0000000F0000FD7FULL);
01662f3e 2809 */
b81ccf8a 2810 switch (version) {
1d28b5f6
DG		 2811 case fsl_e500v1:
2812 case fsl_e500v2:
2813 default:
2814 ivor_mask = 0x0000000F0000FFFFULL;
2815 break;
2816 case fsl_e500mc:
2817 case fsl_e5500:
2818 ivor_mask = 0x000003FE0000FFFFULL;
2819 break;
2820 case fsl_e6500:
2821 ivor_mask = 0x000003FF0000FFFFULL;
2822 break;
2c9732db 2823 }
a08eea67 2824 register_BookE_sprs(env, ivor_mask);
2a48d83d
FR		 2825
2826 spr_register(env, SPR_USPRG3, "USPRG3",
2827 &spr_read_ureg, SPR_NOACCESS,
2828 &spr_read_ureg, SPR_NOACCESS,
2829 0x00000000);
2830
80d11f44
JM		 2831 /* Processor identification */
2832 spr_register(env, SPR_BOOKE_PIR, "PIR",
2833 SPR_NOACCESS, SPR_NOACCESS,
2834 &spr_read_generic, &spr_write_pir,
2835 0x00000000);
acf629eb 2836
80d11f44 2837 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
d34defbc
AJ		 2838 &spr_read_spefscr, &spr_write_spefscr,
2839 &spr_read_spefscr, &spr_write_spefscr,
80d11f44 2840 0x00000000);
892c587f 2841#if !defined(CONFIG_USER_ONLY)
80d11f44 2842 /* Memory management */
80d11f44 2843 env->nb_pids = 3;
01662f3e
AG		 2844 env->nb_ways = 2;
2845 env->id_tlbs = 0;
2846 switch (version) {
f7aa5583 2847 case fsl_e500v1:
a08eea67
BL		 2848 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256);
2849 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
01662f3e 2850 break;
f7aa5583 2851 case fsl_e500v2:
a08eea67
BL		 2852 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2853 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
f7aa5583
VS		 2854 break;
2855 case fsl_e500mc:
b81ccf8a 2856 case fsl_e5500:
a08eea67
BL		 2857 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512);
2858 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
892c587f 2859 break;
54a50dae
KF		 2860 case fsl_e6500:
2861 mmucfg = 0x6510B45;
2862 env->nb_pids = 1;
2863 tlbncfg[0] = 0x08052400;
2864 tlbncfg[1] = 0x40028040;
2865 break;
892c587f 2866 default:
db70b311 2867 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
1d28b5f6 2868 env->spr[SPR_PVR]);
892c587f
AG		 2869 }
2870#endif
2871 /* Cache sizes */
2872 switch (version) {
2873 case fsl_e500v1:
2874 case fsl_e500v2:
2875 env->dcache_line_size = 32;
2876 env->icache_line_size = 32;
2877 break;
2878 case fsl_e500mc:
b81ccf8a 2879 case fsl_e5500:
f7aa5583
VS		 2880 env->dcache_line_size = 64;
2881 env->icache_line_size = 64;
a496e8ee 2882 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
d2ea2bf7 2883 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
01662f3e 2884 break;
54a50dae
KF		 2885 case fsl_e6500:
2886 env->dcache_line_size = 32;
2887 env->icache_line_size = 32;
2888 l1cfg0 |= 0x0F83820;
2889 l1cfg1 |= 0x0B83820;
2890 break;
01662f3e 2891 default:
db70b311 2892 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n",
1d28b5f6 2893 env->spr[SPR_PVR]);
01662f3e 2894 }
a08eea67 2895 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
4ffb8c5e 2896 register_usprgh_sprs(env);
acf629eb 2897
80d11f44
JM		 2898 spr_register(env, SPR_HID0, "HID0",
2899 SPR_NOACCESS, SPR_NOACCESS,
2900 &spr_read_generic, &spr_write_generic,
2901 0x00000000);
acf629eb 2902
80d11f44
JM		 2903 spr_register(env, SPR_HID1, "HID1",
2904 SPR_NOACCESS, SPR_NOACCESS,
2905 &spr_read_generic, &spr_write_generic,
2906 0x00000000);
acf629eb 2907
80d11f44
JM		 2908 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
2909 SPR_NOACCESS, SPR_NOACCESS,
2910 &spr_read_generic, &spr_write_generic,
2911 0x00000000);
acf629eb 2912
80d11f44
JM		 2913 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
2914 SPR_NOACCESS, SPR_NOACCESS,
2915 &spr_read_generic, &spr_write_generic,
2916 0x00000000);
acf629eb 2917
80d11f44
JM		 2918 spr_register(env, SPR_Exxx_MCAR, "MCAR",
2919 SPR_NOACCESS, SPR_NOACCESS,
2920 &spr_read_generic, &spr_write_generic,
2921 0x00000000);
acf629eb 2922
a750fc0b
JM		 2923 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
2924 SPR_NOACCESS, SPR_NOACCESS,
2925 &spr_read_generic, &spr_write_generic,
2926 0x00000000);
acf629eb 2927
80d11f44 2928 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
a750fc0b
JM		 2929 SPR_NOACCESS, SPR_NOACCESS,
2930 &spr_read_generic, &spr_write_generic,
2931 0x00000000);
acf629eb 2932
80d11f44 2933 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
a750fc0b
JM		 2934 SPR_NOACCESS, SPR_NOACCESS,
2935 &spr_read_generic, &spr_write_generic,
2936 0x00000000);
acf629eb 2937
80d11f44 2938 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
deb05c4c
AG		 2939 &spr_read_generic, SPR_NOACCESS,
2940 &spr_read_generic, SPR_NOACCESS,
a496e8ee 2941 l1cfg0);
d2ea2bf7
AG		 2942 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
2943 &spr_read_generic, SPR_NOACCESS,
2944 &spr_read_generic, SPR_NOACCESS,
2945 l1cfg1);
80d11f44
JM		 2946 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
2947 SPR_NOACCESS, SPR_NOACCESS,
01662f3e 2948 &spr_read_generic, &spr_write_e500_l1csr0,
80d11f44 2949 0x00000000);
80d11f44
JM		 2950 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
2951 SPR_NOACCESS, SPR_NOACCESS,
ea71258d 2952 &spr_read_generic, &spr_write_e500_l1csr1,
80d11f44 2953 0x00000000);
298091f8
BM		 2954 if (version != fsl_e500v1 && version != fsl_e500v2) {
2955 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
2956 SPR_NOACCESS, SPR_NOACCESS,
2957 &spr_read_generic, &spr_write_e500_l2csr0,
2958 0x00000000);
2959 }
80d11f44
JM		 2960 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
2961 SPR_NOACCESS, SPR_NOACCESS,
2962 &spr_read_generic, &spr_write_generic,
2963 0x00000000);
2964 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
2965 SPR_NOACCESS, SPR_NOACCESS,
a750fc0b
JM		 2966 &spr_read_generic, &spr_write_generic,
2967 0x00000000);
01662f3e
AG		 2968 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
2969 SPR_NOACCESS, SPR_NOACCESS,
2970 &spr_read_generic, &spr_write_booke206_mmucsr0,
2971 0x00000000);
b81ccf8a
AG		 2972 spr_register(env, SPR_BOOKE_EPR, "EPR",
2973 SPR_NOACCESS, SPR_NOACCESS,
68c2dd70 2974 &spr_read_generic, SPR_NOACCESS,
b81ccf8a
AG		 2975 0x00000000);
2976 /* XXX better abstract into Emb.xxx features */
54a50dae 2977 if ((version == fsl_e5500) || (version == fsl_e6500)) {
b81ccf8a
AG		 2978 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
2979 SPR_NOACCESS, SPR_NOACCESS,
2980 &spr_read_generic, &spr_write_generic,
2981 0x00000000);
2982 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
2983 SPR_NOACCESS, SPR_NOACCESS,
2984 &spr_read_mas73, &spr_write_mas73,
2985 0x00000000);
2986 ivpr_mask = (target_ulong)~0xFFFFULL;
2987 }
01662f3e 2988
54a50dae 2989 if (version == fsl_e6500) {
54a50dae
KF		 2990 /* Thread identification */
2991 spr_register(env, SPR_TIR, "TIR",
2992 SPR_NOACCESS, SPR_NOACCESS,
2993 &spr_read_generic, SPR_NOACCESS,
2994 0x00000000);
2995 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS",
2996 SPR_NOACCESS, SPR_NOACCESS,
2997 &spr_read_generic, SPR_NOACCESS,
2998 0x00000004);
2999 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS",
3000 SPR_NOACCESS, SPR_NOACCESS,
3001 &spr_read_generic, SPR_NOACCESS,
3002 0x7FFFFFFC);
3003 }
3004
f2e63a42 3005#if !defined(CONFIG_USER_ONLY)
01662f3e 3006 env->nb_tlb = 0;
1c53accc 3007 env->tlb_type = TLB_MAS;
01662f3e
AG		 3008 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
3009 env->nb_tlb += booke206_tlb_size(env, i);
3010 }
f2e63a42 3011#endif
01662f3e 3012
e9cd84b9 3013 init_excp_e200(env, ivpr_mask);
9fdc60bf 3014 /* Allocate hardware IRQ controller */
db70b311 3015 ppce500_irq_init(env_archcpu(env));
3fc6c082 3016}
a750fc0b 3017
01662f3e
AG		 3018static void init_proc_e500v1(CPUPPCState *env)
3019{
f7aa5583 3020 init_proc_e500(env, fsl_e500v1);
01662f3e
AG		 3021}
3022
7856e3a4
AF		 3023POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
3024{
ca5dff0a 3025 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3026 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3027
ca5dff0a 3028 dc->desc = "e500v1 core";
7856e3a4
AF		 3029 pcc->init_proc = init_proc_e500v1;
3030 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3031 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3032 PPC_SPE | PPC_SPE_SINGLE |
3033 PPC_WRTEE | PPC_RFDI |
3034 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3035 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3036 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3037 pcc->insns_flags2 = PPC2_BOOKE206;
9df5a466
TM		 3038 pcc->msr_mask = (1ull << MSR_UCLE) |
3039 (1ull << MSR_SPE) |
3040 (1ull << MSR_POW) |
3041 (1ull << MSR_CE) |
3042 (1ull << MSR_EE) |
3043 (1ull << MSR_PR) |
3044 (1ull << MSR_FP) |
3045 (1ull << MSR_ME) |
3046 (1ull << MSR_FE0) |
3047 (1ull << MSR_DWE) |
3048 (1ull << MSR_DE) |
3049 (1ull << MSR_FE1) |
3050 (1ull << MSR_IR) |
3051 (1ull << MSR_DR);
ba9fd9f1
AF		 3052 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3053 pcc->excp_model = POWERPC_EXCP_BOOKE;
3054 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3055 pcc->bfd_mach = bfd_mach_ppc_860;
3056 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3057 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3058 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3059}
3060
01662f3e
AG		 3061static void init_proc_e500v2(CPUPPCState *env)
3062{
f7aa5583
VS		 3063 init_proc_e500(env, fsl_e500v2);
3064}
3065
7856e3a4
AF		 3066POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
3067{
ca5dff0a 3068 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3069 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3070
ca5dff0a 3071 dc->desc = "e500v2 core";
7856e3a4
AF		 3072 pcc->init_proc = init_proc_e500v2;
3073 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3074 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
3075 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
3076 PPC_WRTEE | PPC_RFDI |
3077 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3078 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3079 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3080 pcc->insns_flags2 = PPC2_BOOKE206;
9df5a466
TM		 3081 pcc->msr_mask = (1ull << MSR_UCLE) |
3082 (1ull << MSR_SPE) |
3083 (1ull << MSR_POW) |
3084 (1ull << MSR_CE) |
3085 (1ull << MSR_EE) |
3086 (1ull << MSR_PR) |
3087 (1ull << MSR_FP) |
3088 (1ull << MSR_ME) |
3089 (1ull << MSR_FE0) |
3090 (1ull << MSR_DWE) |
3091 (1ull << MSR_DE) |
3092 (1ull << MSR_FE1) |
3093 (1ull << MSR_IR) |
3094 (1ull << MSR_DR);
ba9fd9f1
AF		 3095 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3096 pcc->excp_model = POWERPC_EXCP_BOOKE;
3097 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3098 pcc->bfd_mach = bfd_mach_ppc_860;
3099 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
3100 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
3101 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3102}
3103
f7aa5583
VS		 3104static void init_proc_e500mc(CPUPPCState *env)
3105{
3106 init_proc_e500(env, fsl_e500mc);
01662f3e
AG		 3107}
3108
7856e3a4
AF		 3109POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
3110{
ca5dff0a 3111 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3112 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3113
ca5dff0a 3114 dc->desc = "e500mc core";
7856e3a4
AF		 3115 pcc->init_proc = init_proc_e500mc;
3116 pcc->check_pow = check_pow_none;
2fff4bad 3117 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
53116ebf
AF		 3118 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3119 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3120 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3121 PPC_FLOAT | PPC_FLOAT_FRES |
3122 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3123 PPC_FLOAT_STFIWX | PPC_WAIT |
3124 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
3125 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
9df5a466
TM		 3126 pcc->msr_mask = (1ull << MSR_GS) |
3127 (1ull << MSR_UCLE) |
3128 (1ull << MSR_CE) |
3129 (1ull << MSR_EE) |
3130 (1ull << MSR_PR) |
3131 (1ull << MSR_FP) |
3132 (1ull << MSR_ME) |
3133 (1ull << MSR_FE0) |
3134 (1ull << MSR_DE) |
3135 (1ull << MSR_FE1) |
3136 (1ull << MSR_IR) |
3137 (1ull << MSR_DR) |
3138 (1ull << MSR_PX) |
3139 (1ull << MSR_RI);
ba9fd9f1
AF		 3140 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3141 pcc->excp_model = POWERPC_EXCP_BOOKE;
3142 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3143 /* FIXME: figure out the correct flag for e500mc */
3144 pcc->bfd_mach = bfd_mach_ppc_e500;
3145 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3146 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3147}
3148
b81ccf8a
AG		 3149#ifdef TARGET_PPC64
3150static void init_proc_e5500(CPUPPCState *env)
3151{
3152 init_proc_e500(env, fsl_e5500);
3153}
7856e3a4
AF		 3154
3155POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
3156{
ca5dff0a 3157 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3158 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3159
ca5dff0a 3160 dc->desc = "e5500 core";
7856e3a4
AF		 3161 pcc->init_proc = init_proc_e5500;
3162 pcc->check_pow = check_pow_none;
2fff4bad 3163 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
53116ebf
AF		 3164 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3165 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3166 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3167 PPC_FLOAT | PPC_FLOAT_FRES |
3168 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3169 PPC_FLOAT_STFIWX | PPC_WAIT |
3170 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3171 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
78ee6bd0 3172 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
4171853c 3173 PPC2_FP_CVT_S64;
9df5a466
TM		 3174 pcc->msr_mask = (1ull << MSR_CM) |
3175 (1ull << MSR_GS) |
3176 (1ull << MSR_UCLE) |
3177 (1ull << MSR_CE) |
3178 (1ull << MSR_EE) |
3179 (1ull << MSR_PR) |
3180 (1ull << MSR_FP) |
3181 (1ull << MSR_ME) |
3182 (1ull << MSR_FE0) |
3183 (1ull << MSR_DE) |
3184 (1ull << MSR_FE1) |
3185 (1ull << MSR_IR) |
3186 (1ull << MSR_DR) |
3187 (1ull << MSR_PX) |
3188 (1ull << MSR_RI);
ba9fd9f1
AF		 3189 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3190 pcc->excp_model = POWERPC_EXCP_BOOKE;
3191 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3192 /* FIXME: figure out the correct flag for e5500 */
3193 pcc->bfd_mach = bfd_mach_ppc_e500;
3194 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3195 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4 3196}
54a50dae
KF		 3197
3198static void init_proc_e6500(CPUPPCState *env)
3199{
3200 init_proc_e500(env, fsl_e6500);
3201}
3202
3203POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
3204{
3205 DeviceClass *dc = DEVICE_CLASS(oc);
3206 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3207
3208 dc->desc = "e6500 core";
3209 pcc->init_proc = init_proc_e6500;
3210 pcc->check_pow = check_pow_none;
3211 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB |
3212 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
3213 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
3214 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3215 PPC_FLOAT | PPC_FLOAT_FRES |
3216 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
3217 PPC_FLOAT_STFIWX | PPC_WAIT |
3218 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
3219 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC;
78ee6bd0 3220 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 |
54a50dae
KF		 3221 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206;
3222 pcc->msr_mask = (1ull << MSR_CM) |
3223 (1ull << MSR_GS) |
3224 (1ull << MSR_UCLE) |
3225 (1ull << MSR_CE) |
3226 (1ull << MSR_EE) |
3227 (1ull << MSR_PR) |
3228 (1ull << MSR_FP) |
3229 (1ull << MSR_ME) |
3230 (1ull << MSR_FE0) |
3231 (1ull << MSR_DE) |
3232 (1ull << MSR_FE1) |
3233 (1ull << MSR_IS) |
3234 (1ull << MSR_DS) |
3235 (1ull << MSR_PX) |
3236 (1ull << MSR_RI) |
3237 (1ull << MSR_VR);
3238 pcc->mmu_model = POWERPC_MMU_BOOKE206;
3239 pcc->excp_model = POWERPC_EXCP_BOOKE;
3240 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3241 pcc->bfd_mach = bfd_mach_ppc_e500;
3242 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3243 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE;
3244}
3245
b81ccf8a
AG		 3246#endif
3247
a750fc0b 3248/* Non-embedded PowerPC */
c364946d 3249static void init_proc_603(CPUPPCState *env)
a750fc0b 3250{
217781af 3251 register_non_embedded_sprs(env);
a08eea67
BL		 3252 register_sdr1_sprs(env);
3253 register_603_sprs(env);
acf629eb 3254
a750fc0b 3255 /* Memory management */
a08eea67
BL		 3256 register_low_BATs(env);
3257 register_6xx_7xx_soft_tlb(env, 64, 2);
e1833e1f 3258 init_excp_603(env);
d63001d1
JM		 3259 env->dcache_line_size = 32;
3260 env->icache_line_size = 32;
a750fc0b 3261 /* Allocate hardware IRQ controller */
db70b311 3262 ppc6xx_irq_init(env_archcpu(env));
3fc6c082
FB		 3263}
3264
7856e3a4
AF		 3265POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
3266{
ca5dff0a 3267 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3268 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3269
ca5dff0a 3270 dc->desc = "PowerPC 603";
7856e3a4
AF		 3271 pcc->init_proc = init_proc_603;
3272 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3273 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3274 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3275 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3276 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3277 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3278 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3279 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3280 pcc->msr_mask = (1ull << MSR_POW) |
3281 (1ull << MSR_TGPR) |
3282 (1ull << MSR_ILE) |
3283 (1ull << MSR_EE) |
3284 (1ull << MSR_PR) |
3285 (1ull << MSR_FP) |
3286 (1ull << MSR_ME) |
3287 (1ull << MSR_FE0) |
3288 (1ull << MSR_SE) |
3289 (1ull << MSR_DE) |
3290 (1ull << MSR_FE1) |
3291 (1ull << MSR_EP) |
3292 (1ull << MSR_IR) |
3293 (1ull << MSR_DR) |
3294 (1ull << MSR_RI) |
3295 (1ull << MSR_LE);
ba9fd9f1 3296 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
9323650f 3297 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 3298 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3299 pcc->bfd_mach = bfd_mach_ppc_603;
3300 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3301 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3302}
3303
7856e3a4
AF		 3304POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
3305{
ca5dff0a 3306 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3307 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3308
ca5dff0a 3309 dc->desc = "PowerPC 603e";
fd77f757 3310 pcc->init_proc = init_proc_603;
7856e3a4 3311 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3312 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3313 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3314 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3315 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3316 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3317 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3318 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3319 pcc->msr_mask = (1ull << MSR_POW) |
3320 (1ull << MSR_TGPR) |
3321 (1ull << MSR_ILE) |
3322 (1ull << MSR_EE) |
3323 (1ull << MSR_PR) |
3324 (1ull << MSR_FP) |
3325 (1ull << MSR_ME) |
3326 (1ull << MSR_FE0) |
3327 (1ull << MSR_SE) |
3328 (1ull << MSR_DE) |
3329 (1ull << MSR_FE1) |
3330 (1ull << MSR_EP) |
3331 (1ull << MSR_IR) |
3332 (1ull << MSR_DR) |
3333 (1ull << MSR_RI) |
3334 (1ull << MSR_LE);
ba9fd9f1 3335 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
9323650f 3336 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 3337 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3338 pcc->bfd_mach = bfd_mach_ppc_ec603e;
3339 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3340 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3341}
3342
9f33f3d8
FR		 3343static void init_proc_e300(CPUPPCState *env)
3344{
3345 init_proc_603(env);
3346 register_e300_sprs(env);
3347}
3348
3349POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
3350{
3351 DeviceClass *dc = DEVICE_CLASS(oc);
3352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3353
3354 dc->desc = "e300 core";
3355 pcc->init_proc = init_proc_e300;
3356 pcc->check_pow = check_pow_hid0;
3357 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3358 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3359 PPC_FLOAT_STFIWX |
3360 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3361 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3362 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
3363 PPC_SEGMENT | PPC_EXTERN;
3364 pcc->msr_mask = (1ull << MSR_POW) |
3365 (1ull << MSR_TGPR) |
3366 (1ull << MSR_ILE) |
3367 (1ull << MSR_EE) |
3368 (1ull << MSR_PR) |
3369 (1ull << MSR_FP) |
3370 (1ull << MSR_ME) |
3371 (1ull << MSR_FE0) |
3372 (1ull << MSR_SE) |
3373 (1ull << MSR_DE) |
3374 (1ull << MSR_FE1) |
3375 (1ull << MSR_AL) |
3376 (1ull << MSR_EP) |
3377 (1ull << MSR_IR) |
3378 (1ull << MSR_DR) |
3379 (1ull << MSR_RI) |
3380 (1ull << MSR_LE);
3381 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
3382 pcc->excp_model = POWERPC_EXCP_6xx;
3383 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3384 pcc->bfd_mach = bfd_mach_ppc_603;
3385 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
3386 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
3387}
3388
c364946d 3389static void init_proc_604(CPUPPCState *env)
a750fc0b 3390{
217781af 3391 register_non_embedded_sprs(env);
a08eea67
BL		 3392 register_sdr1_sprs(env);
3393 register_604_sprs(env);
20f6fb99 3394
082c6681 3395 /* Memory management */
a08eea67 3396 register_low_BATs(env);
082c6681
JM		 3397 init_excp_604(env);
3398 env->dcache_line_size = 32;
3399 env->icache_line_size = 32;
3400 /* Allocate hardware IRQ controller */
db70b311 3401 ppc6xx_irq_init(env_archcpu(env));
082c6681
JM		 3402}
3403
7856e3a4
AF		 3404POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
3405{
ca5dff0a 3406 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3407 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3408
ca5dff0a 3409 dc->desc = "PowerPC 604";
7856e3a4
AF		 3410 pcc->init_proc = init_proc_604;
3411 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3412 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3413 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3414 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3415 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3416 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3417 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3418 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3419 pcc->msr_mask = (1ull << MSR_POW) |
3420 (1ull << MSR_ILE) |
3421 (1ull << MSR_EE) |
3422 (1ull << MSR_PR) |
3423 (1ull << MSR_FP) |
3424 (1ull << MSR_ME) |
3425 (1ull << MSR_FE0) |
3426 (1ull << MSR_SE) |
3427 (1ull << MSR_DE) |
3428 (1ull << MSR_FE1) |
3429 (1ull << MSR_EP) |
3430 (1ull << MSR_IR) |
3431 (1ull << MSR_DR) |
3432 (1ull << MSR_PMM) |
3433 (1ull << MSR_RI) |
3434 (1ull << MSR_LE);
ba9fd9f1 3435 pcc->mmu_model = POWERPC_MMU_32B;
9323650f 3436 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 3437 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3438 pcc->bfd_mach = bfd_mach_ppc_604;
3439 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3440 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3441}
3442
c364946d 3443static void init_proc_604E(CPUPPCState *env)
082c6681 3444{
0df0ca16 3445 init_proc_604(env);
3b18ec76 3446 register_604e_sprs(env);
a750fc0b
JM		 3447}
3448
7856e3a4
AF		 3449POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
3450{
ca5dff0a 3451 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3452 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3453
ca5dff0a 3454 dc->desc = "PowerPC 604E";
7856e3a4
AF		 3455 pcc->init_proc = init_proc_604E;
3456 pcc->check_pow = check_pow_nocheck;
53116ebf
AF		 3457 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3458 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3459 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3460 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3461 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3462 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3463 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3464 pcc->msr_mask = (1ull << MSR_POW) |
3465 (1ull << MSR_ILE) |
3466 (1ull << MSR_EE) |
3467 (1ull << MSR_PR) |
3468 (1ull << MSR_FP) |
3469 (1ull << MSR_ME) |
3470 (1ull << MSR_FE0) |
3471 (1ull << MSR_SE) |
3472 (1ull << MSR_DE) |
3473 (1ull << MSR_FE1) |
3474 (1ull << MSR_EP) |
3475 (1ull << MSR_IR) |
3476 (1ull << MSR_DR) |
3477 (1ull << MSR_PMM) |
3478 (1ull << MSR_RI) |
3479 (1ull << MSR_LE);
ba9fd9f1 3480 pcc->mmu_model = POWERPC_MMU_32B;
9323650f 3481 pcc->excp_model = POWERPC_EXCP_6xx;
ba9fd9f1
AF		 3482 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3483 pcc->bfd_mach = bfd_mach_ppc_604;
3484 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3485 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3486}
3487
c364946d 3488static void init_proc_740(CPUPPCState *env)
a750fc0b 3489{
217781af 3490 register_non_embedded_sprs(env);
a08eea67
BL		 3491 register_sdr1_sprs(env);
3492 register_7xx_sprs(env);
a750fc0b 3493 /* Thermal management */
a08eea67 3494 register_thrm_sprs(env);
acf629eb 3495
a750fc0b 3496 /* Memory management */
a08eea67 3497 register_low_BATs(env);
e1833e1f 3498 init_excp_7x0(env);
d63001d1
JM		 3499 env->dcache_line_size = 32;
3500 env->icache_line_size = 32;
a750fc0b 3501 /* Allocate hardware IRQ controller */
db70b311 3502 ppc6xx_irq_init(env_archcpu(env));
a750fc0b
JM		 3503}
3504
7856e3a4
AF		 3505POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
3506{
ca5dff0a 3507 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3508 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3509
ca5dff0a 3510 dc->desc = "PowerPC 740";
7856e3a4
AF		 3511 pcc->init_proc = init_proc_740;
3512 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3513 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3514 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3515 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3516 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3517 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3518 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3519 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3520 pcc->msr_mask = (1ull << MSR_POW) |
3521 (1ull << MSR_ILE) |
3522 (1ull << MSR_EE) |
3523 (1ull << MSR_PR) |
3524 (1ull << MSR_FP) |
3525 (1ull << MSR_ME) |
3526 (1ull << MSR_FE0) |
3527 (1ull << MSR_SE) |
3528 (1ull << MSR_DE) |
3529 (1ull << MSR_FE1) |
3530 (1ull << MSR_EP) |
3531 (1ull << MSR_IR) |
3532 (1ull << MSR_DR) |
3533 (1ull << MSR_PMM) |
3534 (1ull << MSR_RI) |
3535 (1ull << MSR_LE);
ba9fd9f1 3536 pcc->mmu_model = POWERPC_MMU_32B;
fd7dc4bb 3537 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 3538 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3539 pcc->bfd_mach = bfd_mach_ppc_750;
3540 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3541 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3542}
3543
c364946d 3544static void init_proc_750(CPUPPCState *env)
bd928eba 3545{
217781af 3546 register_non_embedded_sprs(env);
a08eea67
BL		 3547 register_sdr1_sprs(env);
3548 register_7xx_sprs(env);
acf629eb 3549
bd928eba
JM		 3550 spr_register(env, SPR_L2CR, "L2CR",
3551 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 3552 &spr_read_generic, spr_access_nop,
bd928eba 3553 0x00000000);
bd928eba 3554 /* Thermal management */
a08eea67 3555 register_thrm_sprs(env);
acf629eb 3556
bd928eba 3557 /* Memory management */
a08eea67 3558 register_low_BATs(env);
1d28b5f6
DG		 3559 /*
3560 * XXX: high BATs are also present but are known to be bugged on
bd928eba
JM		 3561 * die version 1.x
3562 */
3563 init_excp_7x0(env);
3564 env->dcache_line_size = 32;
3565 env->icache_line_size = 32;
3566 /* Allocate hardware IRQ controller */
db70b311 3567 ppc6xx_irq_init(env_archcpu(env));
bd928eba
JM		 3568}
3569
7856e3a4
AF		 3570POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
3571{
ca5dff0a 3572 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3573 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3574
ca5dff0a 3575 dc->desc = "PowerPC 750";
7856e3a4
AF		 3576 pcc->init_proc = init_proc_750;
3577 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3578 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3579 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3580 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3581 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3582 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3583 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3584 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3585 pcc->msr_mask = (1ull << MSR_POW) |
3586 (1ull << MSR_ILE) |
3587 (1ull << MSR_EE) |
3588 (1ull << MSR_PR) |
3589 (1ull << MSR_FP) |
3590 (1ull << MSR_ME) |
3591 (1ull << MSR_FE0) |
3592 (1ull << MSR_SE) |
3593 (1ull << MSR_DE) |
3594 (1ull << MSR_FE1) |
3595 (1ull << MSR_EP) |
3596 (1ull << MSR_IR) |
3597 (1ull << MSR_DR) |
3598 (1ull << MSR_PMM) |
3599 (1ull << MSR_RI) |
3600 (1ull << MSR_LE);
ba9fd9f1 3601 pcc->mmu_model = POWERPC_MMU_32B;
fd7dc4bb 3602 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 3603 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3604 pcc->bfd_mach = bfd_mach_ppc_750;
3605 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3606 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3607}
3608
c364946d 3609static void init_proc_750cl(CPUPPCState *env)
bd928eba 3610{
217781af 3611 register_non_embedded_sprs(env);
a08eea67
BL		 3612 register_sdr1_sprs(env);
3613 register_7xx_sprs(env);
acf629eb 3614
bd928eba
JM		 3615 spr_register(env, SPR_L2CR, "L2CR",
3616 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 3617 &spr_read_generic, spr_access_nop,
bd928eba 3618 0x00000000);
bd928eba
JM		 3619 /* Thermal management */
3620 /* Those registers are fake on 750CL */
3621 spr_register(env, SPR_THRM1, "THRM1",
3622 SPR_NOACCESS, SPR_NOACCESS,
3623 &spr_read_generic, &spr_write_generic,
3624 0x00000000);
3625 spr_register(env, SPR_THRM2, "THRM2",
3626 SPR_NOACCESS, SPR_NOACCESS,
3627 &spr_read_generic, &spr_write_generic,
3628 0x00000000);
3629 spr_register(env, SPR_THRM3, "THRM3",
3630 SPR_NOACCESS, SPR_NOACCESS,
3631 &spr_read_generic, &spr_write_generic,
3632 0x00000000);
acf629eb 3633
bd928eba
JM		 3634 spr_register(env, SPR_750_TDCL, "TDCL",
3635 SPR_NOACCESS, SPR_NOACCESS,
3636 &spr_read_generic, &spr_write_generic,
3637 0x00000000);
3638 spr_register(env, SPR_750_TDCH, "TDCH",
3639 SPR_NOACCESS, SPR_NOACCESS,
3640 &spr_read_generic, &spr_write_generic,
3641 0x00000000);
3642 /* DMA */
bd928eba
JM		 3643 spr_register(env, SPR_750_WPAR, "WPAR",
3644 SPR_NOACCESS, SPR_NOACCESS,
3645 &spr_read_generic, &spr_write_generic,
3646 0x00000000);
3647 spr_register(env, SPR_750_DMAL, "DMAL",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 spr_register(env, SPR_750_DMAU, "DMAU",
3652 SPR_NOACCESS, SPR_NOACCESS,
3653 &spr_read_generic, &spr_write_generic,
3654 0x00000000);
3655 /* Hardware implementation registers */
bd928eba
JM		 3656 spr_register(env, SPR_750CL_HID2, "HID2",
3657 SPR_NOACCESS, SPR_NOACCESS,
3658 &spr_read_generic, &spr_write_generic,
3659 0x00000000);
acf629eb 3660
bd928eba
JM		 3661 spr_register(env, SPR_750CL_HID4, "HID4",
3662 SPR_NOACCESS, SPR_NOACCESS,
3663 &spr_read_generic, &spr_write_generic,
3664 0x00000000);
3665 /* Quantization registers */
bd928eba
JM		 3666 spr_register(env, SPR_750_GQR0, "GQR0",
3667 SPR_NOACCESS, SPR_NOACCESS,
3668 &spr_read_generic, &spr_write_generic,
3669 0x00000000);
acf629eb 3670
bd928eba
JM		 3671 spr_register(env, SPR_750_GQR1, "GQR1",
3672 SPR_NOACCESS, SPR_NOACCESS,
3673 &spr_read_generic, &spr_write_generic,
3674 0x00000000);
acf629eb 3675
bd928eba
JM		 3676 spr_register(env, SPR_750_GQR2, "GQR2",
3677 SPR_NOACCESS, SPR_NOACCESS,
3678 &spr_read_generic, &spr_write_generic,
3679 0x00000000);
acf629eb 3680
bd928eba
JM		 3681 spr_register(env, SPR_750_GQR3, "GQR3",
3682 SPR_NOACCESS, SPR_NOACCESS,
3683 &spr_read_generic, &spr_write_generic,
3684 0x00000000);
acf629eb 3685
bd928eba
JM		 3686 spr_register(env, SPR_750_GQR4, "GQR4",
3687 SPR_NOACCESS, SPR_NOACCESS,
3688 &spr_read_generic, &spr_write_generic,
3689 0x00000000);
acf629eb 3690
bd928eba
JM		 3691 spr_register(env, SPR_750_GQR5, "GQR5",
3692 SPR_NOACCESS, SPR_NOACCESS,
3693 &spr_read_generic, &spr_write_generic,
3694 0x00000000);
acf629eb 3695
bd928eba
JM		 3696 spr_register(env, SPR_750_GQR6, "GQR6",
3697 SPR_NOACCESS, SPR_NOACCESS,
3698 &spr_read_generic, &spr_write_generic,
3699 0x00000000);
acf629eb 3700
bd928eba
JM		 3701 spr_register(env, SPR_750_GQR7, "GQR7",
3702 SPR_NOACCESS, SPR_NOACCESS,
3703 &spr_read_generic, &spr_write_generic,
3704 0x00000000);
3705 /* Memory management */
a08eea67 3706 register_low_BATs(env);
bd928eba 3707 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
a08eea67 3708 register_high_BATs(env);
bd928eba
JM		 3709 init_excp_750cl(env);
3710 env->dcache_line_size = 32;
3711 env->icache_line_size = 32;
3712 /* Allocate hardware IRQ controller */
db70b311 3713 ppc6xx_irq_init(env_archcpu(env));
bd928eba
JM		 3714}
3715
7856e3a4
AF		 3716POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
3717{
ca5dff0a 3718 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3719 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3720
ca5dff0a 3721 dc->desc = "PowerPC 750 CL";
7856e3a4
AF		 3722 pcc->init_proc = init_proc_750cl;
3723 pcc->check_pow = check_pow_hid0;
1d28b5f6
DG		 3724 /*
3725 * XXX: not implemented:
53116ebf
AF		 3726 * cache lock instructions:
3727 * dcbz_l
3728 * floating point paired instructions
3729 * psq_lux
3730 * psq_lx
3731 * psq_stux
3732 * psq_stx
3733 * ps_abs
3734 * ps_add
3735 * ps_cmpo0
3736 * ps_cmpo1
3737 * ps_cmpu0
3738 * ps_cmpu1
3739 * ps_div
3740 * ps_madd
3741 * ps_madds0
3742 * ps_madds1
3743 * ps_merge00
3744 * ps_merge01
3745 * ps_merge10
3746 * ps_merge11
3747 * ps_mr
3748 * ps_msub
3749 * ps_mul
3750 * ps_muls0
3751 * ps_muls1
3752 * ps_nabs
3753 * ps_neg
3754 * ps_nmadd
3755 * ps_nmsub
3756 * ps_res
3757 * ps_rsqrte
3758 * ps_sel
3759 * ps_sub
3760 * ps_sum0
3761 * ps_sum1
3762 */
3763 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3765 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3766 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3767 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3768 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3769 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3770 pcc->msr_mask = (1ull << MSR_POW) |
3771 (1ull << MSR_ILE) |
3772 (1ull << MSR_EE) |
3773 (1ull << MSR_PR) |
3774 (1ull << MSR_FP) |
3775 (1ull << MSR_ME) |
3776 (1ull << MSR_FE0) |
3777 (1ull << MSR_SE) |
3778 (1ull << MSR_DE) |
3779 (1ull << MSR_FE1) |
3780 (1ull << MSR_EP) |
3781 (1ull << MSR_IR) |
3782 (1ull << MSR_DR) |
3783 (1ull << MSR_PMM) |
3784 (1ull << MSR_RI) |
3785 (1ull << MSR_LE);
ba9fd9f1 3786 pcc->mmu_model = POWERPC_MMU_32B;
fd7dc4bb 3787 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 3788 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3789 pcc->bfd_mach = bfd_mach_ppc_750;
3790 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3791 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3792}
3793
c364946d 3794static void init_proc_750cx(CPUPPCState *env)
bd928eba 3795{
217781af 3796 register_non_embedded_sprs(env);
a08eea67
BL		 3797 register_sdr1_sprs(env);
3798 register_7xx_sprs(env);
acf629eb 3799
bd928eba
JM		 3800 spr_register(env, SPR_L2CR, "L2CR",
3801 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 3802 &spr_read_generic, spr_access_nop,
bd928eba 3803 0x00000000);
bd928eba 3804 /* Thermal management */
a08eea67 3805 register_thrm_sprs(env);
acf629eb 3806
bd928eba
JM		 3807 spr_register(env, SPR_SDA, "SDA",
3808 SPR_NOACCESS, SPR_NOACCESS,
3809 &spr_read_generic, &spr_write_generic,
3810 0x00000000);
acf629eb 3811
bd928eba 3812 /* Memory management */
a08eea67 3813 register_low_BATs(env);
4e777442 3814 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
a08eea67 3815 register_high_BATs(env);
bd928eba
JM		 3816 init_excp_750cx(env);
3817 env->dcache_line_size = 32;
3818 env->icache_line_size = 32;
3819 /* Allocate hardware IRQ controller */
db70b311 3820 ppc6xx_irq_init(env_archcpu(env));
bd928eba
JM		 3821}
3822
7856e3a4
AF		 3823POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
3824{
ca5dff0a 3825 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3826 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3827
ca5dff0a 3828 dc->desc = "PowerPC 750CX";
7856e3a4
AF		 3829 pcc->init_proc = init_proc_750cx;
3830 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3831 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3832 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3833 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3834 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3835 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3836 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3837 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3838 pcc->msr_mask = (1ull << MSR_POW) |
3839 (1ull << MSR_ILE) |
3840 (1ull << MSR_EE) |
3841 (1ull << MSR_PR) |
3842 (1ull << MSR_FP) |
3843 (1ull << MSR_ME) |
3844 (1ull << MSR_FE0) |
3845 (1ull << MSR_SE) |
3846 (1ull << MSR_DE) |
3847 (1ull << MSR_FE1) |
3848 (1ull << MSR_EP) |
3849 (1ull << MSR_IR) |
3850 (1ull << MSR_DR) |
3851 (1ull << MSR_PMM) |
3852 (1ull << MSR_RI) |
3853 (1ull << MSR_LE);
ba9fd9f1 3854 pcc->mmu_model = POWERPC_MMU_32B;
fd7dc4bb 3855 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 3856 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3857 pcc->bfd_mach = bfd_mach_ppc_750;
3858 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3859 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3860}
3861
c364946d 3862static void init_proc_750fx(CPUPPCState *env)
a750fc0b 3863{
217781af 3864 register_non_embedded_sprs(env);
a08eea67
BL		 3865 register_sdr1_sprs(env);
3866 register_7xx_sprs(env);
acf629eb 3867
bd928eba
JM		 3868 spr_register(env, SPR_L2CR, "L2CR",
3869 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 3870 &spr_read_generic, spr_access_nop,
bd928eba 3871 0x00000000);
a750fc0b 3872 /* Thermal management */
a08eea67 3873 register_thrm_sprs(env);
acf629eb 3874
bd928eba
JM		 3875 spr_register(env, SPR_750_THRM4, "THRM4",
3876 SPR_NOACCESS, SPR_NOACCESS,
3877 &spr_read_generic, &spr_write_generic,
3878 0x00000000);
a750fc0b 3879 /* Hardware implementation registers */
bd928eba 3880 spr_register(env, SPR_750FX_HID2, "HID2",
a750fc0b
JM		 3881 SPR_NOACCESS, SPR_NOACCESS,
3882 &spr_read_generic, &spr_write_generic,
3883 0x00000000);
3884 /* Memory management */
a08eea67 3885 register_low_BATs(env);
a750fc0b 3886 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
a08eea67 3887 register_high_BATs(env);
bd928eba 3888 init_excp_7x0(env);
d63001d1
JM		 3889 env->dcache_line_size = 32;
3890 env->icache_line_size = 32;
a750fc0b 3891 /* Allocate hardware IRQ controller */
db70b311 3892 ppc6xx_irq_init(env_archcpu(env));
a750fc0b
JM		 3893}
3894
7856e3a4
AF		 3895POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
3896{
ca5dff0a 3897 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3898 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3899
ca5dff0a 3900 dc->desc = "PowerPC 750FX";
7856e3a4
AF		 3901 pcc->init_proc = init_proc_750fx;
3902 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3903 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3904 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3905 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3906 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3907 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3908 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3909 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3910 pcc->msr_mask = (1ull << MSR_POW) |
3911 (1ull << MSR_ILE) |
3912 (1ull << MSR_EE) |
3913 (1ull << MSR_PR) |
3914 (1ull << MSR_FP) |
3915 (1ull << MSR_ME) |
3916 (1ull << MSR_FE0) |
3917 (1ull << MSR_SE) |
3918 (1ull << MSR_DE) |
3919 (1ull << MSR_FE1) |
3920 (1ull << MSR_EP) |
3921 (1ull << MSR_IR) |
3922 (1ull << MSR_DR) |
3923 (1ull << MSR_PMM) |
3924 (1ull << MSR_RI) |
3925 (1ull << MSR_LE);
ba9fd9f1 3926 pcc->mmu_model = POWERPC_MMU_32B;
fd7dc4bb 3927 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 3928 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
3929 pcc->bfd_mach = bfd_mach_ppc_750;
3930 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
3931 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 3932}
3933
c364946d 3934static void init_proc_750gx(CPUPPCState *env)
bd928eba 3935{
217781af 3936 register_non_embedded_sprs(env);
a08eea67
BL		 3937 register_sdr1_sprs(env);
3938 register_7xx_sprs(env);
acf629eb 3939
bd928eba
JM		 3940 spr_register(env, SPR_L2CR, "L2CR",
3941 SPR_NOACCESS, SPR_NOACCESS,
9633fcc6 3942 &spr_read_generic, spr_access_nop,
bd928eba 3943 0x00000000);
bd928eba 3944 /* Thermal management */
a08eea67 3945 register_thrm_sprs(env);
acf629eb 3946
bd928eba
JM		 3947 spr_register(env, SPR_750_THRM4, "THRM4",
3948 SPR_NOACCESS, SPR_NOACCESS,
3949 &spr_read_generic, &spr_write_generic,
3950 0x00000000);
3951 /* Hardware implementation registers */
bd928eba
JM		 3952 spr_register(env, SPR_750FX_HID2, "HID2",
3953 SPR_NOACCESS, SPR_NOACCESS,
3954 &spr_read_generic, &spr_write_generic,
3955 0x00000000);
3956 /* Memory management */
a08eea67 3957 register_low_BATs(env);
bd928eba 3958 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
a08eea67 3959 register_high_BATs(env);
bd928eba
JM		 3960 init_excp_7x0(env);
3961 env->dcache_line_size = 32;
3962 env->icache_line_size = 32;
3963 /* Allocate hardware IRQ controller */
db70b311 3964 ppc6xx_irq_init(env_archcpu(env));
bd928eba
JM		 3965}
3966
7856e3a4
AF		 3967POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
3968{
ca5dff0a 3969 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 3970 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3971
ca5dff0a 3972 dc->desc = "PowerPC 750GX";
7856e3a4
AF		 3973 pcc->init_proc = init_proc_750gx;
3974 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 3975 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3976 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
3977 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
3978 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
3979 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3980 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
3981 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 3982 pcc->msr_mask = (1ull << MSR_POW) |
3983 (1ull << MSR_ILE) |
3984 (1ull << MSR_EE) |
3985 (1ull << MSR_PR) |
3986 (1ull << MSR_FP) |
3987 (1ull << MSR_ME) |
3988 (1ull << MSR_FE0) |
3989 (1ull << MSR_SE) |
3990 (1ull << MSR_DE) |
3991 (1ull << MSR_FE1) |
3992 (1ull << MSR_EP) |
3993 (1ull << MSR_IR) |
3994 (1ull << MSR_DR) |
3995 (1ull << MSR_PMM) |
3996 (1ull << MSR_RI) |
3997 (1ull << MSR_LE);
ba9fd9f1 3998 pcc->mmu_model = POWERPC_MMU_32B;
fd7dc4bb 3999 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 4000 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4001 pcc->bfd_mach = bfd_mach_ppc_750;
4002 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4003 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4004}
4005
c364946d 4006static void init_proc_745(CPUPPCState *env)
bd928eba 4007{
217781af 4008 register_non_embedded_sprs(env);
a08eea67
BL		 4009 register_sdr1_sprs(env);
4010 register_7xx_sprs(env);
a5d1120b 4011 register_745_sprs(env);
bd928eba 4012 /* Thermal management */
a08eea67 4013 register_thrm_sprs(env);
acf629eb 4014
bd928eba 4015 /* Memory management */
a08eea67
BL		 4016 register_low_BATs(env);
4017 register_high_BATs(env);
4018 register_6xx_7xx_soft_tlb(env, 64, 2);
bd928eba
JM		 4019 init_excp_7x5(env);
4020 env->dcache_line_size = 32;
4021 env->icache_line_size = 32;
4022 /* Allocate hardware IRQ controller */
db70b311 4023 ppc6xx_irq_init(env_archcpu(env));
bd928eba
JM		 4024}
4025
7856e3a4
AF		 4026POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
4027{
ca5dff0a 4028 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4029 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4030
ca5dff0a 4031 dc->desc = "PowerPC 745";
7856e3a4
AF		 4032 pcc->init_proc = init_proc_745;
4033 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4034 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4035 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4036 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4037 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4038 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4039 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4040 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 4041 pcc->msr_mask = (1ull << MSR_POW) |
4042 (1ull << MSR_ILE) |
4043 (1ull << MSR_EE) |
4044 (1ull << MSR_PR) |
4045 (1ull << MSR_FP) |
4046 (1ull << MSR_ME) |
4047 (1ull << MSR_FE0) |
4048 (1ull << MSR_SE) |
4049 (1ull << MSR_DE) |
4050 (1ull << MSR_FE1) |
4051 (1ull << MSR_EP) |
4052 (1ull << MSR_IR) |
4053 (1ull << MSR_DR) |
4054 (1ull << MSR_PMM) |
4055 (1ull << MSR_RI) |
4056 (1ull << MSR_LE);
ba9fd9f1 4057 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
fd7dc4bb 4058 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 4059 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4060 pcc->bfd_mach = bfd_mach_ppc_750;
4061 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4062 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4063}
4064
c364946d 4065static void init_proc_755(CPUPPCState *env)
a750fc0b 4066{
c1f21577 4067 init_proc_745(env);
28930245 4068 register_755_sprs(env);
a750fc0b
JM		 4069}
4070
7856e3a4
AF		 4071POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
4072{
ca5dff0a 4073 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4074 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4075
ca5dff0a 4076 dc->desc = "PowerPC 755";
7856e3a4
AF		 4077 pcc->init_proc = init_proc_755;
4078 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4079 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4080 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4081 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4082 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4083 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4084 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4085 PPC_SEGMENT | PPC_EXTERN;
9df5a466
TM		 4086 pcc->msr_mask = (1ull << MSR_POW) |
4087 (1ull << MSR_ILE) |
4088 (1ull << MSR_EE) |
4089 (1ull << MSR_PR) |
4090 (1ull << MSR_FP) |
4091 (1ull << MSR_ME) |
4092 (1ull << MSR_FE0) |
4093 (1ull << MSR_SE) |
4094 (1ull << MSR_DE) |
4095 (1ull << MSR_FE1) |
4096 (1ull << MSR_EP) |
4097 (1ull << MSR_IR) |
4098 (1ull << MSR_DR) |
4099 (1ull << MSR_PMM) |
4100 (1ull << MSR_RI) |
4101 (1ull << MSR_LE);
ba9fd9f1 4102 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
fd7dc4bb 4103 pcc->excp_model = POWERPC_EXCP_7xx;
ba9fd9f1
AF		 4104 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4105 pcc->bfd_mach = bfd_mach_ppc_750;
4106 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4107 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4108}
4109
c364946d 4110static void init_proc_7400(CPUPPCState *env)
a750fc0b 4111{
217781af 4112 register_non_embedded_sprs(env);
a08eea67 4113 register_sdr1_sprs(env);
a08eea67 4114 register_74xx_sprs(env);
f350982f 4115 vscr_init(env, 0x00010000);
acf629eb 4116
4e777442
JM		 4117 spr_register(env, SPR_UBAMR, "UBAMR",
4118 &spr_read_ureg, SPR_NOACCESS,
4119 &spr_read_ureg, SPR_NOACCESS,
4120 0x00000000);
acf629eb 4121
4e777442
JM		 4122 spr_register(env, SPR_MSSCR1, "MSSCR1",
4123 SPR_NOACCESS, SPR_NOACCESS,
4124 &spr_read_generic, &spr_write_generic,
4125 0x00000000);
a750fc0b 4126 /* Thermal management */
a08eea67 4127 register_thrm_sprs(env);
a750fc0b 4128 /* Memory management */
a08eea67 4129 register_low_BATs(env);
e1833e1f 4130 init_excp_7400(env);
d63001d1
JM		 4131 env->dcache_line_size = 32;
4132 env->icache_line_size = 32;
a750fc0b 4133 /* Allocate hardware IRQ controller */
db70b311 4134 ppc6xx_irq_init(env_archcpu(env));
a750fc0b
JM		 4135}
4136
7856e3a4
AF		 4137POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
4138{
ca5dff0a 4139 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4140 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4141
ca5dff0a 4142 dc->desc = "PowerPC 7400 (aka G4)";
7856e3a4
AF		 4143 pcc->init_proc = init_proc_7400;
4144 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4145 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4146 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4147 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4148 PPC_FLOAT_STFIWX |
4149 PPC_CACHE | PPC_CACHE_ICBI |
4150 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4151 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4152 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4153 PPC_MEM_TLBIA |
4154 PPC_SEGMENT | PPC_EXTERN |
4155 PPC_ALTIVEC;
9df5a466
TM		 4156 pcc->msr_mask = (1ull << MSR_VR) |
4157 (1ull << MSR_POW) |
4158 (1ull << MSR_ILE) |
4159 (1ull << MSR_EE) |
4160 (1ull << MSR_PR) |
4161 (1ull << MSR_FP) |
4162 (1ull << MSR_ME) |
4163 (1ull << MSR_FE0) |
4164 (1ull << MSR_SE) |
4165 (1ull << MSR_DE) |
4166 (1ull << MSR_FE1) |
4167 (1ull << MSR_EP) |
4168 (1ull << MSR_IR) |
4169 (1ull << MSR_DR) |
4170 (1ull << MSR_PMM) |
4171 (1ull << MSR_RI) |
4172 (1ull << MSR_LE);
ba9fd9f1
AF		 4173 pcc->mmu_model = POWERPC_MMU_32B;
4174 pcc->excp_model = POWERPC_EXCP_74xx;
4175 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4176 pcc->bfd_mach = bfd_mach_ppc_7400;
4177 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4178 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4179 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4180}
4181
c364946d 4182static void init_proc_7410(CPUPPCState *env)
a750fc0b 4183{
217781af 4184 register_non_embedded_sprs(env);
a08eea67 4185 register_sdr1_sprs(env);
a08eea67 4186 register_74xx_sprs(env);
f350982f 4187 vscr_init(env, 0x00010000);
acf629eb 4188
4e777442
JM		 4189 spr_register(env, SPR_UBAMR, "UBAMR",
4190 &spr_read_ureg, SPR_NOACCESS,
4191 &spr_read_ureg, SPR_NOACCESS,
4192 0x00000000);
a750fc0b 4193 /* Thermal management */
a08eea67 4194 register_thrm_sprs(env);
a750fc0b 4195 /* L2PMCR */
acf629eb 4196
a750fc0b
JM		 4197 spr_register(env, SPR_L2PMCR, "L2PMCR",
4198 SPR_NOACCESS, SPR_NOACCESS,
4199 &spr_read_generic, &spr_write_generic,
4200 0x00000000);
4201 /* LDSTDB */
acf629eb 4202
a750fc0b
JM		 4203 spr_register(env, SPR_LDSTDB, "LDSTDB",
4204 SPR_NOACCESS, SPR_NOACCESS,
4205 &spr_read_generic, &spr_write_generic,
4206 0x00000000);
4207 /* Memory management */
a08eea67 4208 register_low_BATs(env);
e1833e1f 4209 init_excp_7400(env);
d63001d1
JM		 4210 env->dcache_line_size = 32;
4211 env->icache_line_size = 32;
a750fc0b 4212 /* Allocate hardware IRQ controller */
db70b311 4213 ppc6xx_irq_init(env_archcpu(env));
a750fc0b
JM		 4214}
4215
7856e3a4
AF		 4216POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
4217{
ca5dff0a 4218 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4219 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4220
ca5dff0a 4221 dc->desc = "PowerPC 7410 (aka G4)";
7856e3a4
AF		 4222 pcc->init_proc = init_proc_7410;
4223 pcc->check_pow = check_pow_hid0;
53116ebf
AF		 4224 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4225 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4226 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4227 PPC_FLOAT_STFIWX |
4228 PPC_CACHE | PPC_CACHE_ICBI |
4229 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4230 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4232 PPC_MEM_TLBIA |
4233 PPC_SEGMENT | PPC_EXTERN |
4234 PPC_ALTIVEC;
9df5a466
TM		 4235 pcc->msr_mask = (1ull << MSR_VR) |
4236 (1ull << MSR_POW) |
4237 (1ull << MSR_ILE) |
4238 (1ull << MSR_EE) |
4239 (1ull << MSR_PR) |
4240 (1ull << MSR_FP) |
4241 (1ull << MSR_ME) |
4242 (1ull << MSR_FE0) |
4243 (1ull << MSR_SE) |
4244 (1ull << MSR_DE) |
4245 (1ull << MSR_FE1) |
4246 (1ull << MSR_EP) |
4247 (1ull << MSR_IR) |
4248 (1ull << MSR_DR) |
4249 (1ull << MSR_PMM) |
4250 (1ull << MSR_RI) |
4251 (1ull << MSR_LE);
ba9fd9f1
AF		 4252 pcc->mmu_model = POWERPC_MMU_32B;
4253 pcc->excp_model = POWERPC_EXCP_74xx;
4254 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4255 pcc->bfd_mach = bfd_mach_ppc_7400;
4256 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4257 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4258 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4259}
4260
c364946d 4261static void init_proc_7440(CPUPPCState *env)
a750fc0b 4262{
217781af 4263 register_non_embedded_sprs(env);
a08eea67 4264 register_sdr1_sprs(env);
a08eea67 4265 register_74xx_sprs(env);
f350982f 4266 vscr_init(env, 0x00010000);
acf629eb 4267
4e777442
JM		 4268 spr_register(env, SPR_UBAMR, "UBAMR",
4269 &spr_read_ureg, SPR_NOACCESS,
4270 &spr_read_ureg, SPR_NOACCESS,
4271 0x00000000);
a750fc0b 4272 /* LDSTCR */
a750fc0b
JM		 4273 spr_register(env, SPR_LDSTCR, "LDSTCR",
4274 SPR_NOACCESS, SPR_NOACCESS,
4275 &spr_read_generic, &spr_write_generic,
4276 0x00000000);
4277 /* ICTRL */
a750fc0b
JM		 4278 spr_register(env, SPR_ICTRL, "ICTRL",
4279 SPR_NOACCESS, SPR_NOACCESS,
4280 &spr_read_generic, &spr_write_generic,
4281 0x00000000);
4282 /* MSSSR0 */
4283 spr_register(env, SPR_MSSSR0, "MSSSR0",
4284 SPR_NOACCESS, SPR_NOACCESS,
4285 &spr_read_generic, &spr_write_generic,
4286 0x00000000);
4287 /* PMC */
cb8b8bf8 4288 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 4289 SPR_NOACCESS, SPR_NOACCESS,
4290 &spr_read_generic, &spr_write_generic,
4291 0x00000000);
acf629eb 4292
cb8b8bf8 4293 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 4294 &spr_read_ureg, SPR_NOACCESS,
4295 &spr_read_ureg, SPR_NOACCESS,
4296 0x00000000);
acf629eb 4297
cb8b8bf8 4298 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 4299 SPR_NOACCESS, SPR_NOACCESS,
4300 &spr_read_generic, &spr_write_generic,
4301 0x00000000);
acf629eb 4302
cb8b8bf8 4303 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 4304 &spr_read_ureg, SPR_NOACCESS,
4305 &spr_read_ureg, SPR_NOACCESS,
4306 0x00000000);
4307 /* Memory management */
a08eea67 4308 register_low_BATs(env);
1c27f8fb 4309 init_excp_7450(env);
d63001d1
JM		 4310 env->dcache_line_size = 32;
4311 env->icache_line_size = 32;
a750fc0b 4312 /* Allocate hardware IRQ controller */
db70b311 4313 ppc6xx_irq_init(env_archcpu(env));
a750fc0b 4314}
a750fc0b 4315
7856e3a4
AF		 4316POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
4317{
ca5dff0a 4318 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4319 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4320
ca5dff0a 4321 dc->desc = "PowerPC 7440 (aka G4)";
7856e3a4
AF		 4322 pcc->init_proc = init_proc_7440;
4323 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 4324 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4325 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4326 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4327 PPC_FLOAT_STFIWX |
4328 PPC_CACHE | PPC_CACHE_ICBI |
4329 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4330 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4331 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
1da666cd 4332 PPC_MEM_TLBIA |
53116ebf
AF		 4333 PPC_SEGMENT | PPC_EXTERN |
4334 PPC_ALTIVEC;
9df5a466
TM		 4335 pcc->msr_mask = (1ull << MSR_VR) |
4336 (1ull << MSR_POW) |
4337 (1ull << MSR_ILE) |
4338 (1ull << MSR_EE) |
4339 (1ull << MSR_PR) |
4340 (1ull << MSR_FP) |
4341 (1ull << MSR_ME) |
4342 (1ull << MSR_FE0) |
4343 (1ull << MSR_SE) |
4344 (1ull << MSR_DE) |
4345 (1ull << MSR_FE1) |
4346 (1ull << MSR_EP) |
4347 (1ull << MSR_IR) |
4348 (1ull << MSR_DR) |
4349 (1ull << MSR_PMM) |
4350 (1ull << MSR_RI) |
4351 (1ull << MSR_LE);
1da666cd 4352 pcc->mmu_model = POWERPC_MMU_32B;
ba9fd9f1
AF		 4353 pcc->excp_model = POWERPC_EXCP_74xx;
4354 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4355 pcc->bfd_mach = bfd_mach_ppc_7400;
4356 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4357 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4358 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4359}
4360
c364946d 4361static void init_proc_7450(CPUPPCState *env)
a750fc0b 4362{
217781af 4363 register_non_embedded_sprs(env);
a08eea67 4364 register_sdr1_sprs(env);
a08eea67 4365 register_74xx_sprs(env);
f350982f 4366 vscr_init(env, 0x00010000);
a750fc0b 4367 /* Level 3 cache control */
a08eea67 4368 register_l3_ctrl(env);
4e777442 4369 /* L3ITCR1 */
4e777442
JM		 4370 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4371 SPR_NOACCESS, SPR_NOACCESS,
4372 &spr_read_generic, &spr_write_generic,
4373 0x00000000);
4374 /* L3ITCR2 */
4e777442
JM		 4375 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4376 SPR_NOACCESS, SPR_NOACCESS,
4377 &spr_read_generic, &spr_write_generic,
4378 0x00000000);
4379 /* L3ITCR3 */
4e777442
JM		 4380 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4381 SPR_NOACCESS, SPR_NOACCESS,
4382 &spr_read_generic, &spr_write_generic,
4383 0x00000000);
4384 /* L3OHCR */
4e777442
JM		 4385 spr_register(env, SPR_L3OHCR, "L3OHCR",
4386 SPR_NOACCESS, SPR_NOACCESS,
4387 &spr_read_generic, &spr_write_generic,
4388 0x00000000);
acf629eb 4389
4e777442
JM		 4390 spr_register(env, SPR_UBAMR, "UBAMR",
4391 &spr_read_ureg, SPR_NOACCESS,
4392 &spr_read_ureg, SPR_NOACCESS,
4393 0x00000000);
a750fc0b 4394 /* LDSTCR */
a750fc0b
JM		 4395 spr_register(env, SPR_LDSTCR, "LDSTCR",
4396 SPR_NOACCESS, SPR_NOACCESS,
4397 &spr_read_generic, &spr_write_generic,
4398 0x00000000);
4399 /* ICTRL */
a750fc0b
JM		 4400 spr_register(env, SPR_ICTRL, "ICTRL",
4401 SPR_NOACCESS, SPR_NOACCESS,
4402 &spr_read_generic, &spr_write_generic,
4403 0x00000000);
4404 /* MSSSR0 */
4405 spr_register(env, SPR_MSSSR0, "MSSSR0",
4406 SPR_NOACCESS, SPR_NOACCESS,
4407 &spr_read_generic, &spr_write_generic,
4408 0x00000000);
4409 /* PMC */
cb8b8bf8 4410 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 4411 SPR_NOACCESS, SPR_NOACCESS,
4412 &spr_read_generic, &spr_write_generic,
4413 0x00000000);
acf629eb 4414
cb8b8bf8 4415 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 4416 &spr_read_ureg, SPR_NOACCESS,
4417 &spr_read_ureg, SPR_NOACCESS,
4418 0x00000000);
acf629eb 4419
cb8b8bf8 4420 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 4421 SPR_NOACCESS, SPR_NOACCESS,
4422 &spr_read_generic, &spr_write_generic,
4423 0x00000000);
acf629eb 4424
cb8b8bf8 4425 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 4426 &spr_read_ureg, SPR_NOACCESS,
4427 &spr_read_ureg, SPR_NOACCESS,
4428 0x00000000);
4429 /* Memory management */
a08eea67 4430 register_low_BATs(env);
e1833e1f 4431 init_excp_7450(env);
d63001d1
JM		 4432 env->dcache_line_size = 32;
4433 env->icache_line_size = 32;
a750fc0b 4434 /* Allocate hardware IRQ controller */
db70b311 4435 ppc6xx_irq_init(env_archcpu(env));
a750fc0b 4436}
a750fc0b 4437
7856e3a4
AF		 4438POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
4439{
ca5dff0a 4440 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4442
ca5dff0a 4443 dc->desc = "PowerPC 7450 (aka G4)";
7856e3a4
AF		 4444 pcc->init_proc = init_proc_7450;
4445 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 4446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4447 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4448 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4449 PPC_FLOAT_STFIWX |
4450 PPC_CACHE | PPC_CACHE_ICBI |
4451 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4452 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4453 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
1da666cd 4454 PPC_MEM_TLBIA |
53116ebf
AF		 4455 PPC_SEGMENT | PPC_EXTERN |
4456 PPC_ALTIVEC;
9df5a466
TM		 4457 pcc->msr_mask = (1ull << MSR_VR) |
4458 (1ull << MSR_POW) |
4459 (1ull << MSR_ILE) |
4460 (1ull << MSR_EE) |
4461 (1ull << MSR_PR) |
4462 (1ull << MSR_FP) |
4463 (1ull << MSR_ME) |
4464 (1ull << MSR_FE0) |
4465 (1ull << MSR_SE) |
4466 (1ull << MSR_DE) |
4467 (1ull << MSR_FE1) |
4468 (1ull << MSR_EP) |
4469 (1ull << MSR_IR) |
4470 (1ull << MSR_DR) |
4471 (1ull << MSR_PMM) |
4472 (1ull << MSR_RI) |
4473 (1ull << MSR_LE);
1da666cd 4474 pcc->mmu_model = POWERPC_MMU_32B;
ba9fd9f1
AF		 4475 pcc->excp_model = POWERPC_EXCP_74xx;
4476 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4477 pcc->bfd_mach = bfd_mach_ppc_7400;
4478 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4479 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4480 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4481}
4482
c364946d 4483static void init_proc_7445(CPUPPCState *env)
a750fc0b 4484{
217781af 4485 register_non_embedded_sprs(env);
a08eea67 4486 register_sdr1_sprs(env);
a08eea67 4487 register_74xx_sprs(env);
f350982f 4488 vscr_init(env, 0x00010000);
a750fc0b 4489 /* LDSTCR */
a750fc0b
JM		 4490 spr_register(env, SPR_LDSTCR, "LDSTCR",
4491 SPR_NOACCESS, SPR_NOACCESS,
4492 &spr_read_generic, &spr_write_generic,
4493 0x00000000);
4494 /* ICTRL */
a750fc0b
JM		 4495 spr_register(env, SPR_ICTRL, "ICTRL",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499 /* MSSSR0 */
4500 spr_register(env, SPR_MSSSR0, "MSSSR0",
4501 SPR_NOACCESS, SPR_NOACCESS,
4502 &spr_read_generic, &spr_write_generic,
4503 0x00000000);
4504 /* PMC */
cb8b8bf8 4505 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 4506 SPR_NOACCESS, SPR_NOACCESS,
4507 &spr_read_generic, &spr_write_generic,
4508 0x00000000);
acf629eb 4509
cb8b8bf8 4510 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 4511 &spr_read_ureg, SPR_NOACCESS,
4512 &spr_read_ureg, SPR_NOACCESS,
4513 0x00000000);
acf629eb 4514
cb8b8bf8 4515 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 4516 SPR_NOACCESS, SPR_NOACCESS,
4517 &spr_read_generic, &spr_write_generic,
4518 0x00000000);
acf629eb 4519
cb8b8bf8 4520 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 4521 &spr_read_ureg, SPR_NOACCESS,
4522 &spr_read_ureg, SPR_NOACCESS,
4523 0x00000000);
4524 /* SPRGs */
4525 spr_register(env, SPR_SPRG4, "SPRG4",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 spr_register(env, SPR_USPRG4, "USPRG4",
4530 &spr_read_ureg, SPR_NOACCESS,
4531 &spr_read_ureg, SPR_NOACCESS,
4532 0x00000000);
4533 spr_register(env, SPR_SPRG5, "SPRG5",
4534 SPR_NOACCESS, SPR_NOACCESS,
4535 &spr_read_generic, &spr_write_generic,
4536 0x00000000);
4537 spr_register(env, SPR_USPRG5, "USPRG5",
4538 &spr_read_ureg, SPR_NOACCESS,
4539 &spr_read_ureg, SPR_NOACCESS,
4540 0x00000000);
4541 spr_register(env, SPR_SPRG6, "SPRG6",
4542 SPR_NOACCESS, SPR_NOACCESS,
4543 &spr_read_generic, &spr_write_generic,
4544 0x00000000);
4545 spr_register(env, SPR_USPRG6, "USPRG6",
4546 &spr_read_ureg, SPR_NOACCESS,
4547 &spr_read_ureg, SPR_NOACCESS,
4548 0x00000000);
4549 spr_register(env, SPR_SPRG7, "SPRG7",
4550 SPR_NOACCESS, SPR_NOACCESS,
4551 &spr_read_generic, &spr_write_generic,
4552 0x00000000);
4553 spr_register(env, SPR_USPRG7, "USPRG7",
4554 &spr_read_ureg, SPR_NOACCESS,
4555 &spr_read_ureg, SPR_NOACCESS,
4556 0x00000000);
4557 /* Memory management */
a08eea67
BL		 4558 register_low_BATs(env);
4559 register_high_BATs(env);
e1833e1f 4560 init_excp_7450(env);
d63001d1
JM		 4561 env->dcache_line_size = 32;
4562 env->icache_line_size = 32;
a750fc0b 4563 /* Allocate hardware IRQ controller */
db70b311 4564 ppc6xx_irq_init(env_archcpu(env));
a750fc0b 4565}
a750fc0b 4566
7856e3a4
AF		 4567POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
4568{
ca5dff0a 4569 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4570 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4571
ca5dff0a 4572 dc->desc = "PowerPC 7445 (aka G4)";
7856e3a4
AF		 4573 pcc->init_proc = init_proc_7445;
4574 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 4575 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4576 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4577 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4578 PPC_FLOAT_STFIWX |
4579 PPC_CACHE | PPC_CACHE_ICBI |
4580 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4581 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4582 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
1da666cd 4583 PPC_MEM_TLBIA |
53116ebf
AF		 4584 PPC_SEGMENT | PPC_EXTERN |
4585 PPC_ALTIVEC;
9df5a466
TM		 4586 pcc->msr_mask = (1ull << MSR_VR) |
4587 (1ull << MSR_POW) |
4588 (1ull << MSR_ILE) |
4589 (1ull << MSR_EE) |
4590 (1ull << MSR_PR) |
4591 (1ull << MSR_FP) |
4592 (1ull << MSR_ME) |
4593 (1ull << MSR_FE0) |
4594 (1ull << MSR_SE) |
4595 (1ull << MSR_DE) |
4596 (1ull << MSR_FE1) |
4597 (1ull << MSR_EP) |
4598 (1ull << MSR_IR) |
4599 (1ull << MSR_DR) |
4600 (1ull << MSR_PMM) |
4601 (1ull << MSR_RI) |
4602 (1ull << MSR_LE);
1da666cd 4603 pcc->mmu_model = POWERPC_MMU_32B;
ba9fd9f1
AF		 4604 pcc->excp_model = POWERPC_EXCP_74xx;
4605 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4606 pcc->bfd_mach = bfd_mach_ppc_7400;
4607 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4608 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4609 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4610}
4611
c364946d 4612static void init_proc_7455(CPUPPCState *env)
a750fc0b 4613{
217781af 4614 register_non_embedded_sprs(env);
a08eea67 4615 register_sdr1_sprs(env);
a08eea67 4616 register_74xx_sprs(env);
f350982f 4617 vscr_init(env, 0x00010000);
a750fc0b 4618 /* Level 3 cache control */
a08eea67 4619 register_l3_ctrl(env);
a750fc0b 4620 /* LDSTCR */
a750fc0b
JM		 4621 spr_register(env, SPR_LDSTCR, "LDSTCR",
4622 SPR_NOACCESS, SPR_NOACCESS,
4623 &spr_read_generic, &spr_write_generic,
4624 0x00000000);
4625 /* ICTRL */
a750fc0b
JM		 4626 spr_register(env, SPR_ICTRL, "ICTRL",
4627 SPR_NOACCESS, SPR_NOACCESS,
4628 &spr_read_generic, &spr_write_generic,
4629 0x00000000);
4630 /* MSSSR0 */
4631 spr_register(env, SPR_MSSSR0, "MSSSR0",
4632 SPR_NOACCESS, SPR_NOACCESS,
4633 &spr_read_generic, &spr_write_generic,
4634 0x00000000);
4635 /* PMC */
cb8b8bf8 4636 spr_register(env, SPR_7XX_PMC5, "PMC5",
a750fc0b
JM		 4637 SPR_NOACCESS, SPR_NOACCESS,
4638 &spr_read_generic, &spr_write_generic,
4639 0x00000000);
acf629eb 4640
cb8b8bf8 4641 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
a750fc0b
JM		 4642 &spr_read_ureg, SPR_NOACCESS,
4643 &spr_read_ureg, SPR_NOACCESS,
4644 0x00000000);
acf629eb 4645
cb8b8bf8 4646 spr_register(env, SPR_7XX_PMC6, "PMC6",
a750fc0b
JM		 4647 SPR_NOACCESS, SPR_NOACCESS,
4648 &spr_read_generic, &spr_write_generic,
4649 0x00000000);
acf629eb 4650
cb8b8bf8 4651 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
a750fc0b
JM		 4652 &spr_read_ureg, SPR_NOACCESS,
4653 &spr_read_ureg, SPR_NOACCESS,
4654 0x00000000);
4655 /* SPRGs */
4656 spr_register(env, SPR_SPRG4, "SPRG4",
4657 SPR_NOACCESS, SPR_NOACCESS,
4658 &spr_read_generic, &spr_write_generic,
4659 0x00000000);
4660 spr_register(env, SPR_USPRG4, "USPRG4",
4661 &spr_read_ureg, SPR_NOACCESS,
4662 &spr_read_ureg, SPR_NOACCESS,
4663 0x00000000);
4664 spr_register(env, SPR_SPRG5, "SPRG5",
4665 SPR_NOACCESS, SPR_NOACCESS,
4666 &spr_read_generic, &spr_write_generic,
4667 0x00000000);
4668 spr_register(env, SPR_USPRG5, "USPRG5",
4669 &spr_read_ureg, SPR_NOACCESS,
4670 &spr_read_ureg, SPR_NOACCESS,
4671 0x00000000);
4672 spr_register(env, SPR_SPRG6, "SPRG6",
4673 SPR_NOACCESS, SPR_NOACCESS,
4674 &spr_read_generic, &spr_write_generic,
4675 0x00000000);
4676 spr_register(env, SPR_USPRG6, "USPRG6",
4677 &spr_read_ureg, SPR_NOACCESS,
4678 &spr_read_ureg, SPR_NOACCESS,
4679 0x00000000);
4680 spr_register(env, SPR_SPRG7, "SPRG7",
4681 SPR_NOACCESS, SPR_NOACCESS,
4682 &spr_read_generic, &spr_write_generic,
4683 0x00000000);
4684 spr_register(env, SPR_USPRG7, "USPRG7",
4685 &spr_read_ureg, SPR_NOACCESS,
4686 &spr_read_ureg, SPR_NOACCESS,
4687 0x00000000);
4688 /* Memory management */
a08eea67
BL		 4689 register_low_BATs(env);
4690 register_high_BATs(env);
e1833e1f 4691 init_excp_7450(env);
d63001d1
JM		 4692 env->dcache_line_size = 32;
4693 env->icache_line_size = 32;
a750fc0b 4694 /* Allocate hardware IRQ controller */
db70b311 4695 ppc6xx_irq_init(env_archcpu(env));
a750fc0b 4696}
a750fc0b 4697
7856e3a4
AF		 4698POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
4699{
ca5dff0a 4700 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4701 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4702
ca5dff0a 4703 dc->desc = "PowerPC 7455 (aka G4)";
7856e3a4
AF		 4704 pcc->init_proc = init_proc_7455;
4705 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 4706 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4707 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4708 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4709 PPC_FLOAT_STFIWX |
4710 PPC_CACHE | PPC_CACHE_ICBI |
4711 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4712 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4713 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
1da666cd 4714 PPC_MEM_TLBIA |
53116ebf
AF		 4715 PPC_SEGMENT | PPC_EXTERN |
4716 PPC_ALTIVEC;
9df5a466
TM		 4717 pcc->msr_mask = (1ull << MSR_VR) |
4718 (1ull << MSR_POW) |
4719 (1ull << MSR_ILE) |
4720 (1ull << MSR_EE) |
4721 (1ull << MSR_PR) |
4722 (1ull << MSR_FP) |
4723 (1ull << MSR_ME) |
4724 (1ull << MSR_FE0) |
4725 (1ull << MSR_SE) |
4726 (1ull << MSR_DE) |
4727 (1ull << MSR_FE1) |
4728 (1ull << MSR_EP) |
4729 (1ull << MSR_IR) |
4730 (1ull << MSR_DR) |
4731 (1ull << MSR_PMM) |
4732 (1ull << MSR_RI) |
4733 (1ull << MSR_LE);
1da666cd 4734 pcc->mmu_model = POWERPC_MMU_32B;
ba9fd9f1
AF		 4735 pcc->excp_model = POWERPC_EXCP_74xx;
4736 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4737 pcc->bfd_mach = bfd_mach_ppc_7400;
4738 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4739 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4740 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4741}
4742
c364946d 4743static void init_proc_7457(CPUPPCState *env)
4e777442 4744{
217781af 4745 register_non_embedded_sprs(env);
a08eea67 4746 register_sdr1_sprs(env);
a08eea67 4747 register_74xx_sprs(env);
f350982f 4748 vscr_init(env, 0x00010000);
4e777442 4749 /* Level 3 cache control */
a08eea67 4750 register_l3_ctrl(env);
4e777442 4751 /* L3ITCR1 */
4e777442
JM		 4752 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
4753 SPR_NOACCESS, SPR_NOACCESS,
4754 &spr_read_generic, &spr_write_generic,
4755 0x00000000);
4756 /* L3ITCR2 */
4e777442
JM		 4757 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
4758 SPR_NOACCESS, SPR_NOACCESS,
4759 &spr_read_generic, &spr_write_generic,
4760 0x00000000);
4761 /* L3ITCR3 */
4e777442
JM		 4762 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
4763 SPR_NOACCESS, SPR_NOACCESS,
4764 &spr_read_generic, &spr_write_generic,
4765 0x00000000);
4766 /* L3OHCR */
4e777442
JM		 4767 spr_register(env, SPR_L3OHCR, "L3OHCR",
4768 SPR_NOACCESS, SPR_NOACCESS,
4769 &spr_read_generic, &spr_write_generic,
4770 0x00000000);
4771 /* LDSTCR */
4e777442
JM		 4772 spr_register(env, SPR_LDSTCR, "LDSTCR",
4773 SPR_NOACCESS, SPR_NOACCESS,
4774 &spr_read_generic, &spr_write_generic,
4775 0x00000000);
4776 /* ICTRL */
4e777442
JM		 4777 spr_register(env, SPR_ICTRL, "ICTRL",
4778 SPR_NOACCESS, SPR_NOACCESS,
4779 &spr_read_generic, &spr_write_generic,
4780 0x00000000);
4781 /* MSSSR0 */
4e777442
JM		 4782 spr_register(env, SPR_MSSSR0, "MSSSR0",
4783 SPR_NOACCESS, SPR_NOACCESS,
4784 &spr_read_generic, &spr_write_generic,
4785 0x00000000);
4786 /* PMC */
cb8b8bf8 4787 spr_register(env, SPR_7XX_PMC5, "PMC5",
4e777442
JM		 4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
acf629eb 4791
cb8b8bf8 4792 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
4e777442
JM		 4793 &spr_read_ureg, SPR_NOACCESS,
4794 &spr_read_ureg, SPR_NOACCESS,
4795 0x00000000);
acf629eb 4796
cb8b8bf8 4797 spr_register(env, SPR_7XX_PMC6, "PMC6",
4e777442
JM		 4798 SPR_NOACCESS, SPR_NOACCESS,
4799 &spr_read_generic, &spr_write_generic,
4800 0x00000000);
acf629eb 4801
cb8b8bf8 4802 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
4e777442
JM		 4803 &spr_read_ureg, SPR_NOACCESS,
4804 &spr_read_ureg, SPR_NOACCESS,
4805 0x00000000);
4806 /* SPRGs */
4807 spr_register(env, SPR_SPRG4, "SPRG4",
4808 SPR_NOACCESS, SPR_NOACCESS,
4809 &spr_read_generic, &spr_write_generic,
4810 0x00000000);
4811 spr_register(env, SPR_USPRG4, "USPRG4",
4812 &spr_read_ureg, SPR_NOACCESS,
4813 &spr_read_ureg, SPR_NOACCESS,
4814 0x00000000);
4815 spr_register(env, SPR_SPRG5, "SPRG5",
4816 SPR_NOACCESS, SPR_NOACCESS,
4817 &spr_read_generic, &spr_write_generic,
4818 0x00000000);
4819 spr_register(env, SPR_USPRG5, "USPRG5",
4820 &spr_read_ureg, SPR_NOACCESS,
4821 &spr_read_ureg, SPR_NOACCESS,
4822 0x00000000);
4823 spr_register(env, SPR_SPRG6, "SPRG6",
4824 SPR_NOACCESS, SPR_NOACCESS,
4825 &spr_read_generic, &spr_write_generic,
4826 0x00000000);
4827 spr_register(env, SPR_USPRG6, "USPRG6",
4828 &spr_read_ureg, SPR_NOACCESS,
4829 &spr_read_ureg, SPR_NOACCESS,
4830 0x00000000);
4831 spr_register(env, SPR_SPRG7, "SPRG7",
4832 SPR_NOACCESS, SPR_NOACCESS,
4833 &spr_read_generic, &spr_write_generic,
4834 0x00000000);
4835 spr_register(env, SPR_USPRG7, "USPRG7",
4836 &spr_read_ureg, SPR_NOACCESS,
4837 &spr_read_ureg, SPR_NOACCESS,
4838 0x00000000);
4839 /* Memory management */
a08eea67
BL		 4840 register_low_BATs(env);
4841 register_high_BATs(env);
4e777442
JM		 4842 init_excp_7450(env);
4843 env->dcache_line_size = 32;
4844 env->icache_line_size = 32;
4845 /* Allocate hardware IRQ controller */
db70b311 4846 ppc6xx_irq_init(env_archcpu(env));
4e777442
JM		 4847}
4848
7856e3a4
AF		 4849POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
4850{
ca5dff0a 4851 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 4852 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4853
ca5dff0a 4854 dc->desc = "PowerPC 7457 (aka G4)";
7856e3a4
AF		 4855 pcc->init_proc = init_proc_7457;
4856 pcc->check_pow = check_pow_hid0_74xx;
53116ebf
AF		 4857 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4858 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4859 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4860 PPC_FLOAT_STFIWX |
4861 PPC_CACHE | PPC_CACHE_ICBI |
4862 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4863 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4864 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
1da666cd 4865 PPC_MEM_TLBIA |
53116ebf
AF		 4866 PPC_SEGMENT | PPC_EXTERN |
4867 PPC_ALTIVEC;
9df5a466
TM		 4868 pcc->msr_mask = (1ull << MSR_VR) |
4869 (1ull << MSR_POW) |
4870 (1ull << MSR_ILE) |
4871 (1ull << MSR_EE) |
4872 (1ull << MSR_PR) |
4873 (1ull << MSR_FP) |
4874 (1ull << MSR_ME) |
4875 (1ull << MSR_FE0) |
4876 (1ull << MSR_SE) |
4877 (1ull << MSR_DE) |
4878 (1ull << MSR_FE1) |
4879 (1ull << MSR_EP) |
4880 (1ull << MSR_IR) |
4881 (1ull << MSR_DR) |
4882 (1ull << MSR_PMM) |
4883 (1ull << MSR_RI) |
4884 (1ull << MSR_LE);
1da666cd 4885 pcc->mmu_model = POWERPC_MMU_32B;
ba9fd9f1
AF		 4886 pcc->excp_model = POWERPC_EXCP_74xx;
4887 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4888 pcc->bfd_mach = bfd_mach_ppc_7400;
4889 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
4890 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
4891 POWERPC_FLAG_BUS_CLK;
7856e3a4
AF		 4892}
4893
c364946d 4894static void init_proc_e600(CPUPPCState *env)
7162bdea 4895{
217781af 4896 register_non_embedded_sprs(env);
a08eea67 4897 register_sdr1_sprs(env);
a08eea67 4898 register_74xx_sprs(env);
f350982f 4899 vscr_init(env, 0x00010000);
acf629eb 4900
7162bdea
JG		 4901 spr_register(env, SPR_UBAMR, "UBAMR",
4902 &spr_read_ureg, SPR_NOACCESS,
4903 &spr_read_ureg, SPR_NOACCESS,
4904 0x00000000);
acf629eb 4905
7162bdea
JG		 4906 spr_register(env, SPR_LDSTCR, "LDSTCR",
4907 SPR_NOACCESS, SPR_NOACCESS,
4908 &spr_read_generic, &spr_write_generic,
4909 0x00000000);
acf629eb 4910
7162bdea
JG		 4911 spr_register(env, SPR_ICTRL, "ICTRL",
4912 SPR_NOACCESS, SPR_NOACCESS,
4913 &spr_read_generic, &spr_write_generic,
4914 0x00000000);
acf629eb 4915
7162bdea
JG		 4916 spr_register(env, SPR_MSSSR0, "MSSSR0",
4917 SPR_NOACCESS, SPR_NOACCESS,
4918 &spr_read_generic, &spr_write_generic,
4919 0x00000000);
acf629eb 4920
cb8b8bf8 4921 spr_register(env, SPR_7XX_PMC5, "PMC5",
7162bdea
JG		 4922 SPR_NOACCESS, SPR_NOACCESS,
4923 &spr_read_generic, &spr_write_generic,
4924 0x00000000);
acf629eb 4925
cb8b8bf8 4926 spr_register(env, SPR_7XX_UPMC5, "UPMC5",
7162bdea
JG		 4927 &spr_read_ureg, SPR_NOACCESS,
4928 &spr_read_ureg, SPR_NOACCESS,
4929 0x00000000);
acf629eb 4930
cb8b8bf8 4931 spr_register(env, SPR_7XX_PMC6, "PMC6",
7162bdea
JG		 4932 SPR_NOACCESS, SPR_NOACCESS,
4933 &spr_read_generic, &spr_write_generic,
4934 0x00000000);
acf629eb 4935
cb8b8bf8 4936 spr_register(env, SPR_7XX_UPMC6, "UPMC6",
7162bdea
JG		 4937 &spr_read_ureg, SPR_NOACCESS,
4938 &spr_read_ureg, SPR_NOACCESS,
4939 0x00000000);
4940 /* SPRGs */
4941 spr_register(env, SPR_SPRG4, "SPRG4",
4942 SPR_NOACCESS, SPR_NOACCESS,
4943 &spr_read_generic, &spr_write_generic,
4944 0x00000000);
4945 spr_register(env, SPR_USPRG4, "USPRG4",
4946 &spr_read_ureg, SPR_NOACCESS,
4947 &spr_read_ureg, SPR_NOACCESS,
4948 0x00000000);
4949 spr_register(env, SPR_SPRG5, "SPRG5",
4950 SPR_NOACCESS, SPR_NOACCESS,
4951 &spr_read_generic, &spr_write_generic,
4952 0x00000000);
4953 spr_register(env, SPR_USPRG5, "USPRG5",
4954 &spr_read_ureg, SPR_NOACCESS,
4955 &spr_read_ureg, SPR_NOACCESS,
4956 0x00000000);
4957 spr_register(env, SPR_SPRG6, "SPRG6",
4958 SPR_NOACCESS, SPR_NOACCESS,
4959 &spr_read_generic, &spr_write_generic,
4960 0x00000000);
4961 spr_register(env, SPR_USPRG6, "USPRG6",
4962 &spr_read_ureg, SPR_NOACCESS,
4963 &spr_read_ureg, SPR_NOACCESS,
4964 0x00000000);
4965 spr_register(env, SPR_SPRG7, "SPRG7",
4966 SPR_NOACCESS, SPR_NOACCESS,
4967 &spr_read_generic, &spr_write_generic,
4968 0x00000000);
4969 spr_register(env, SPR_USPRG7, "USPRG7",
4970 &spr_read_ureg, SPR_NOACCESS,
4971 &spr_read_ureg, SPR_NOACCESS,
4972 0x00000000);
4973 /* Memory management */
a08eea67
BL		 4974 register_low_BATs(env);
4975 register_high_BATs(env);
7162bdea
JG		 4976 init_excp_7450(env);
4977 env->dcache_line_size = 32;
4978 env->icache_line_size = 32;
4979 /* Allocate hardware IRQ controller */
db70b311 4980 ppc6xx_irq_init(env_archcpu(env));
7162bdea
JG		 4981}
4982
4983POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
4984{
4985 DeviceClass *dc = DEVICE_CLASS(oc);
4986 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4987
4988 dc->desc = "PowerPC e600";
4989 pcc->init_proc = init_proc_e600;
4990 pcc->check_pow = check_pow_hid0_74xx;
4991 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4992 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4993 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4994 PPC_FLOAT_STFIWX |
4995 PPC_CACHE | PPC_CACHE_ICBI |
4996 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
4997 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4998 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
b137fb72 4999 PPC_MEM_TLBIA |
7162bdea
JG		 5000 PPC_SEGMENT | PPC_EXTERN |
5001 PPC_ALTIVEC;
5002 pcc->insns_flags2 = PPC_NONE;
9df5a466
TM		 5003 pcc->msr_mask = (1ull << MSR_VR) |
5004 (1ull << MSR_POW) |
5005 (1ull << MSR_ILE) |
5006 (1ull << MSR_EE) |
5007 (1ull << MSR_PR) |
5008 (1ull << MSR_FP) |
5009 (1ull << MSR_ME) |
5010 (1ull << MSR_FE0) |
5011 (1ull << MSR_SE) |
5012 (1ull << MSR_DE) |
5013 (1ull << MSR_FE1) |
5014 (1ull << MSR_EP) |
5015 (1ull << MSR_IR) |
5016 (1ull << MSR_DR) |
5017 (1ull << MSR_PMM) |
5018 (1ull << MSR_RI) |
5019 (1ull << MSR_LE);
7162bdea 5020 pcc->mmu_model = POWERPC_MMU_32B;
7162bdea
JG		 5021 pcc->excp_model = POWERPC_EXCP_74xx;
5022 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5023 pcc->bfd_mach = bfd_mach_ppc_7400;
5024 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5025 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5026 POWERPC_FLAG_BUS_CLK;
5027}
5028
c364946d 5029#if defined(TARGET_PPC64)
417bf010
JM		 5030#if defined(CONFIG_USER_ONLY)
5031#define POWERPC970_HID5_INIT 0x00000080
5032#else
5033#define POWERPC970_HID5_INIT 0x00000000
5034#endif
5035
c364946d 5036static int check_pow_970(CPUPPCState *env)
2f462816 5037{
bbc01ca7 5038 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) {
2f462816 5039 return 1;
bbc01ca7 5040 }
2f462816
JM		 5041
5042 return 0;
5043}
5044
a08eea67 5045static void register_970_hid_sprs(CPUPPCState *env)
a750fc0b 5046{
a750fc0b 5047 /* Hardware implementation registers */
a750fc0b
JM		 5048 spr_register(env, SPR_HID0, "HID0",
5049 SPR_NOACCESS, SPR_NOACCESS,
06403421 5050 &spr_read_generic, &spr_write_clear,
d63001d1 5051 0x60000000);
a750fc0b
JM		 5052 spr_register(env, SPR_HID1, "HID1",
5053 SPR_NOACCESS, SPR_NOACCESS,
5054 &spr_read_generic, &spr_write_generic,
5055 0x00000000);
e57448f1
JM		 5056 spr_register(env, SPR_970_HID5, "HID5",
5057 SPR_NOACCESS, SPR_NOACCESS,
5058 &spr_read_generic, &spr_write_generic,
417bf010 5059 POWERPC970_HID5_INIT);
42382f62
AK		 5060}
5061
a08eea67 5062static void register_970_hior_sprs(CPUPPCState *env)
42382f62 5063{
12de9a39
JM		 5064 spr_register(env, SPR_HIOR, "SPR_HIOR",
5065 SPR_NOACCESS, SPR_NOACCESS,
2adab7d6
BS		 5066 &spr_read_hior, &spr_write_hior,
5067 0x00000000);
42382f62 5068}
7856e3a4 5069
a08eea67 5070static void register_book3s_ctrl_sprs(CPUPPCState *env)
42382f62 5071{
4e98d8cf
BS		 5072 spr_register(env, SPR_CTRL, "SPR_CTRL",
5073 SPR_NOACCESS, SPR_NOACCESS,
7aeac354 5074 SPR_NOACCESS, &spr_write_CTRL,
4e98d8cf
BS		 5075 0x00000000);
5076 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
eb16dd9c
AK		 5077 &spr_read_ureg, SPR_NOACCESS,
5078 &spr_read_ureg, SPR_NOACCESS,
4e98d8cf 5079 0x00000000);
42382f62
AK		 5080}
5081
a08eea67 5082static void register_book3s_altivec_sprs(CPUPPCState *env)
42382f62
AK		 5083{
5084 if (!(env->insns_flags & PPC_ALTIVEC)) {
5085 return;
5086 }
5087
7303f83d
AK		 5088 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE",
5089 &spr_read_generic, &spr_write_generic,
5090 &spr_read_generic, &spr_write_generic,
5091 KVM_REG_PPC_VRSAVE, 0x00000000);
42382f62 5092
42382f62
AK		 5093}
5094
a08eea67 5095static void register_book3s_dbg_sprs(CPUPPCState *env)
fd51ff63 5096{
cd9adfdd
AK		 5097 /*
5098 * TODO: different specs define different scopes for these,
5099 * will have to address this:
5100 * 970: super/write and super/read
5101 * powerisa 2.03..2.04: hypv/write and super/read.
5102 * powerisa 2.05 and newer: hypv/write and hypv/read.
5103 */
fd51ff63
AK		 5104 spr_register_kvm(env, SPR_DABR, "DABR",
5105 SPR_NOACCESS, SPR_NOACCESS,
5106 &spr_read_generic, &spr_write_generic,
5107 KVM_REG_PPC_DABR, 0x00000000);
cd9adfdd
AK		 5108 spr_register_kvm(env, SPR_DABRX, "DABRX",
5109 SPR_NOACCESS, SPR_NOACCESS,
5110 &spr_read_generic, &spr_write_generic,
5111 KVM_REG_PPC_DABRX, 0x00000000);
fd51ff63
AK		 5112}
5113
a08eea67 5114static void register_book3s_207_dbg_sprs(CPUPPCState *env)
f401dd32 5115{
a7913d5e 5116 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0",
f401dd32
BH		 5117 SPR_NOACCESS, SPR_NOACCESS,
5118 SPR_NOACCESS, SPR_NOACCESS,
5119 &spr_read_generic, &spr_write_generic,
5120 KVM_REG_PPC_DAWR, 0x00000000);
a7913d5e 5121 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0",
f401dd32
BH		 5122 SPR_NOACCESS, SPR_NOACCESS,
5123 SPR_NOACCESS, SPR_NOACCESS,
5124 &spr_read_generic, &spr_write_generic,
5125 KVM_REG_PPC_DAWRX, 0x00000000);
eb5ceb4d
BH		 5126 spr_register_kvm_hv(env, SPR_CIABR, "CIABR",
5127 SPR_NOACCESS, SPR_NOACCESS,
5128 SPR_NOACCESS, SPR_NOACCESS,
5129 &spr_read_generic, &spr_write_generic,
5130 KVM_REG_PPC_CIABR, 0x00000000);
f401dd32
BH		 5131}
5132
a08eea67 5133static void register_970_dbg_sprs(CPUPPCState *env)
fd51ff63
AK		 5134{
5135 /* Breakpoints */
5136 spr_register(env, SPR_IABR, "IABR",
5137 SPR_NOACCESS, SPR_NOACCESS,
5138 &spr_read_generic, &spr_write_generic,
5139 0x00000000);
5140}
5141
a08eea67 5142static void register_book3s_pmu_sup_sprs(CPUPPCState *env)
fd51ff63 5143{
83cc6f8c
AK		 5144 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0",
5145 SPR_NOACCESS, SPR_NOACCESS,
c2eff582
DHB		 5146 &spr_read_generic, &spr_write_MMCR0,
5147 KVM_REG_PPC_MMCR0, 0x80000000);
83cc6f8c
AK		 5148 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1",
5149 SPR_NOACCESS, SPR_NOACCESS,
a6f91249 5150 &spr_read_generic, &spr_write_MMCR1,
83cc6f8c
AK		 5151 KVM_REG_PPC_MMCR1, 0x00000000);
5152 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA",
5153 SPR_NOACCESS, SPR_NOACCESS,
5154 &spr_read_generic, &spr_write_generic,
5155 KVM_REG_PPC_MMCRA, 0x00000000);
5156 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1",
5157 SPR_NOACCESS, SPR_NOACCESS,
308b9fad 5158 &spr_read_PMC, &spr_write_PMC,
83cc6f8c
AK		 5159 KVM_REG_PPC_PMC1, 0x00000000);
5160 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2",
5161 SPR_NOACCESS, SPR_NOACCESS,
308b9fad 5162 &spr_read_PMC, &spr_write_PMC,
83cc6f8c
AK		 5163 KVM_REG_PPC_PMC2, 0x00000000);
5164 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3",
5165 SPR_NOACCESS, SPR_NOACCESS,
308b9fad 5166 &spr_read_PMC, &spr_write_PMC,
83cc6f8c
AK		 5167 KVM_REG_PPC_PMC3, 0x00000000);
5168 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4",
5169 SPR_NOACCESS, SPR_NOACCESS,
308b9fad 5170 &spr_read_PMC, &spr_write_PMC,
83cc6f8c
AK		 5171 KVM_REG_PPC_PMC4, 0x00000000);
5172 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5",
5173 SPR_NOACCESS, SPR_NOACCESS,
308b9fad 5174 &spr_read_PMC, &spr_write_PMC,
83cc6f8c
AK		 5175 KVM_REG_PPC_PMC5, 0x00000000);
5176 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6",
5177 SPR_NOACCESS, SPR_NOACCESS,
308b9fad 5178 &spr_read_PMC, &spr_write_PMC,
83cc6f8c
AK		 5179 KVM_REG_PPC_PMC6, 0x00000000);
5180 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR",
5181 SPR_NOACCESS, SPR_NOACCESS,
5182 &spr_read_generic, &spr_write_generic,
5183 KVM_REG_PPC_SIAR, 0x00000000);
5184 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR",
5185 SPR_NOACCESS, SPR_NOACCESS,
5186 &spr_read_generic, &spr_write_generic,
5187 KVM_REG_PPC_SDAR, 0x00000000);
fd51ff63
AK		 5188}
5189
a08eea67 5190static void register_book3s_pmu_user_sprs(CPUPPCState *env)
fd51ff63
AK		 5191{
5192 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0",
565cb109 5193 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg,
fd51ff63 5194 &spr_read_ureg, &spr_write_ureg,
c2eff582 5195 0x80000000);
fd51ff63
AK		 5196 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1",
5197 &spr_read_ureg, SPR_NOACCESS,
5198 &spr_read_ureg, &spr_write_ureg,
5199 0x00000000);
077850b0
AK		 5200 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA",
5201 &spr_read_ureg, SPR_NOACCESS,
5202 &spr_read_ureg, &spr_write_ureg,
5203 0x00000000);
fd51ff63 5204 spr_register(env, SPR_POWER_UPMC1, "UPMC1",
cedf7069 5205 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
fd51ff63
AK		 5206 &spr_read_ureg, &spr_write_ureg,
5207 0x00000000);
5208 spr_register(env, SPR_POWER_UPMC2, "UPMC2",
cedf7069 5209 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
fd51ff63
AK		 5210 &spr_read_ureg, &spr_write_ureg,
5211 0x00000000);
5212 spr_register(env, SPR_POWER_UPMC3, "UPMC3",
cedf7069 5213 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
fd51ff63
AK		 5214 &spr_read_ureg, &spr_write_ureg,
5215 0x00000000);
5216 spr_register(env, SPR_POWER_UPMC4, "UPMC4",
cedf7069 5217 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg,
fd51ff63
AK		 5218 &spr_read_ureg, &spr_write_ureg,
5219 0x00000000);
077850b0 5220 spr_register(env, SPR_POWER_UPMC5, "UPMC5",
cedf7069 5221 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
077850b0
AK		 5222 &spr_read_ureg, &spr_write_ureg,
5223 0x00000000);
5224 spr_register(env, SPR_POWER_UPMC6, "UPMC6",
cedf7069 5225 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg,
077850b0
AK		 5226 &spr_read_ureg, &spr_write_ureg,
5227 0x00000000);
fd51ff63
AK		 5228 spr_register(env, SPR_POWER_USIAR, "USIAR",
5229 &spr_read_ureg, SPR_NOACCESS,
5230 &spr_read_ureg, &spr_write_ureg,
5231 0x00000000);
077850b0
AK		 5232 spr_register(env, SPR_POWER_USDAR, "USDAR",
5233 &spr_read_ureg, SPR_NOACCESS,
5234 &spr_read_ureg, &spr_write_ureg,
5235 0x00000000);
fd51ff63
AK		 5236}
5237
a08eea67 5238static void register_970_pmu_sup_sprs(CPUPPCState *env)
c36c97f8 5239{
83cc6f8c
AK		 5240 spr_register_kvm(env, SPR_970_PMC7, "PMC7",
5241 SPR_NOACCESS, SPR_NOACCESS,
5242 &spr_read_generic, &spr_write_generic,
5243 KVM_REG_PPC_PMC7, 0x00000000);
5244 spr_register_kvm(env, SPR_970_PMC8, "PMC8",
5245 SPR_NOACCESS, SPR_NOACCESS,
5246 &spr_read_generic, &spr_write_generic,
5247 KVM_REG_PPC_PMC8, 0x00000000);
c36c97f8
AK		 5248}
5249
a08eea67 5250static void register_970_pmu_user_sprs(CPUPPCState *env)
c36c97f8
AK		 5251{
5252 spr_register(env, SPR_970_UPMC7, "UPMC7",
5253 &spr_read_ureg, SPR_NOACCESS,
5254 &spr_read_ureg, &spr_write_ureg,
5255 0x00000000);
5256 spr_register(env, SPR_970_UPMC8, "UPMC8",
5257 &spr_read_ureg, SPR_NOACCESS,
5258 &spr_read_ureg, &spr_write_ureg,
5259 0x00000000);
5260}
5261
a08eea67 5262static void register_power8_pmu_sup_sprs(CPUPPCState *env)
70c53407
AK		 5263{
5264 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2",
5265 SPR_NOACCESS, SPR_NOACCESS,
5266 &spr_read_generic, &spr_write_generic,
5267 KVM_REG_PPC_MMCR2, 0x00000000);
5268 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 KVM_REG_PPC_MMCRS, 0x00000000);
14646457
BH		 5272 spr_register_kvm(env, SPR_POWER_SIER, "SIER",
5273 SPR_NOACCESS, SPR_NOACCESS,
5274 &spr_read_generic, &spr_write_generic,
5275 KVM_REG_PPC_SIER, 0x00000000);
5276 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1",
5277 SPR_NOACCESS, SPR_NOACCESS,
5278 &spr_read_generic, &spr_write_generic,
5279 KVM_REG_PPC_SPMC1, 0x00000000);
5280 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2",
5281 SPR_NOACCESS, SPR_NOACCESS,
5282 &spr_read_generic, &spr_write_generic,
5283 KVM_REG_PPC_SPMC2, 0x00000000);
5284 spr_register_kvm(env, SPR_TACR, "TACR",
5285 SPR_NOACCESS, SPR_NOACCESS,
5286 &spr_read_generic, &spr_write_generic,
5287 KVM_REG_PPC_TACR, 0x00000000);
5288 spr_register_kvm(env, SPR_TCSCR, "TCSCR",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 KVM_REG_PPC_TCSCR, 0x00000000);
5292 spr_register_kvm(env, SPR_CSIGR, "CSIGR",
5293 SPR_NOACCESS, SPR_NOACCESS,
5294 &spr_read_generic, &spr_write_generic,
5295 KVM_REG_PPC_CSIGR, 0x00000000);
70c53407
AK		 5296}
5297
a08eea67 5298static void register_power8_pmu_user_sprs(CPUPPCState *env)
70c53407
AK		 5299{
5300 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2",
7b3ecf16 5301 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg,
70c53407
AK		 5302 &spr_read_ureg, &spr_write_ureg,
5303 0x00000000);
14646457
BH		 5304 spr_register(env, SPR_POWER_USIER, "USIER",
5305 &spr_read_generic, SPR_NOACCESS,
5306 &spr_read_generic, &spr_write_generic,
5307 0x00000000);
70c53407
AK		 5308}
5309
a08eea67 5310static void register_power5p_ear_sprs(CPUPPCState *env)
fd51ff63
AK		 5311{
5312 /* External access control */
5313 spr_register(env, SPR_EAR, "EAR",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 0x00000000);
5317}
5318
a08eea67 5319static void register_power5p_tb_sprs(CPUPPCState *env)
f0ec31b1
SJS		 5320{
5321 /* TBU40 (High 40 bits of the Timebase register */
5322 spr_register_hv(env, SPR_TBU40, "TBU40",
5323 SPR_NOACCESS, SPR_NOACCESS,
5324 SPR_NOACCESS, SPR_NOACCESS,
5325 SPR_NOACCESS, &spr_write_tbu40,
5326 0x00000000);
5327}
5328
a08eea67 5329static void register_970_lpar_sprs(CPUPPCState *env)
4b3fc377
BH		 5330{
5331#if !defined(CONFIG_USER_ONLY)
19acd4b6
DG		 5332 /*
5333 * PPC970: HID4 covers things later controlled by the LPCR and
5334 * RMOR in later CPUs, but with a different encoding. We only
5335 * support the 970 in "Apple mode" which has all hypervisor
5336 * facilities disabled by strapping, so we can basically just
5337 * ignore it
5338 */
4b3fc377
BH		 5339 spr_register(env, SPR_970_HID4, "HID4",
5340 SPR_NOACCESS, SPR_NOACCESS,
19acd4b6 5341 &spr_read_generic, &spr_write_generic,
4b3fc377
BH		 5342 0x00000000);
5343#endif
5344}
5345
a08eea67 5346static void register_power5p_lpar_sprs(CPUPPCState *env)
4b3fc377
BH		 5347{
5348#if !defined(CONFIG_USER_ONLY)
5349 /* Logical partitionning */
635dff20
BH		 5350 spr_register_kvm_hv(env, SPR_LPCR, "LPCR",
5351 SPR_NOACCESS, SPR_NOACCESS,
5352 SPR_NOACCESS, SPR_NOACCESS,
5353 &spr_read_generic, &spr_write_lpcr,
5354 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1);
4b236b62
BH		 5355 spr_register_hv(env, SPR_HDEC, "HDEC",
5356 SPR_NOACCESS, SPR_NOACCESS,
5357 SPR_NOACCESS, SPR_NOACCESS,
5358 &spr_read_hdecr, &spr_write_hdecr, 0);
8eeb330c 5359#endif
4b3fc377 5360}
8eeb330c 5361
a08eea67 5362static void register_book3s_ids_sprs(CPUPPCState *env)
e61716aa 5363{
8eeb330c
BH		 5364 /* FIXME: Will need to deal with thread vs core only SPRs */
5365
e61716aa 5366 /* Processor identification */
8eeb330c 5367 spr_register_hv(env, SPR_PIR, "PIR",
e61716aa 5368 SPR_NOACCESS, SPR_NOACCESS,
bfda32a8 5369 &spr_read_generic, SPR_NOACCESS,
8eeb330c
BH		 5370 &spr_read_generic, NULL,
5371 0x00000000);
5372 spr_register_hv(env, SPR_HID0, "HID0",
5373 SPR_NOACCESS, SPR_NOACCESS,
5374 SPR_NOACCESS, SPR_NOACCESS,
5375 &spr_read_generic, &spr_write_generic,
5376 0x00000000);
5377 spr_register_hv(env, SPR_TSCR, "TSCR",
5378 SPR_NOACCESS, SPR_NOACCESS,
5379 SPR_NOACCESS, SPR_NOACCESS,
5380 &spr_read_generic, &spr_write_generic,
5381 0x00000000);
5382 spr_register_hv(env, SPR_HMER, "HMER",
5383 SPR_NOACCESS, SPR_NOACCESS,
5384 SPR_NOACCESS, SPR_NOACCESS,
5385 &spr_read_generic, &spr_write_hmer,
5386 0x00000000);
5387 spr_register_hv(env, SPR_HMEER, "HMEER",
5388 SPR_NOACCESS, SPR_NOACCESS,
5389 SPR_NOACCESS, SPR_NOACCESS,
5390 &spr_read_generic, &spr_write_generic,
5391 0x00000000);
5392 spr_register_hv(env, SPR_TFMR, "TFMR",
5393 SPR_NOACCESS, SPR_NOACCESS,
5394 SPR_NOACCESS, SPR_NOACCESS,
5395 &spr_read_generic, &spr_write_generic,
5396 0x00000000);
5397 spr_register_hv(env, SPR_LPIDR, "LPIDR",
5398 SPR_NOACCESS, SPR_NOACCESS,
5399 SPR_NOACCESS, SPR_NOACCESS,
c4dae9cd 5400 &spr_read_generic, &spr_write_lpidr,
8eeb330c
BH		 5401 0x00000000);
5402 spr_register_hv(env, SPR_HFSCR, "HFSCR",
5403 SPR_NOACCESS, SPR_NOACCESS,
5404 SPR_NOACCESS, SPR_NOACCESS,
5405 &spr_read_generic, &spr_write_generic,
5406 0x00000000);
5407 spr_register_hv(env, SPR_MMCRC, "MMCRC",
5408 SPR_NOACCESS, SPR_NOACCESS,
5409 SPR_NOACCESS, SPR_NOACCESS,
5410 &spr_read_generic, &spr_write_generic,
5411 0x00000000);
5412 spr_register_hv(env, SPR_MMCRH, "MMCRH",
5413 SPR_NOACCESS, SPR_NOACCESS,
5414 SPR_NOACCESS, SPR_NOACCESS,
5415 &spr_read_generic, &spr_write_generic,
5416 0x00000000);
5417 spr_register_hv(env, SPR_HSPRG0, "HSPRG0",
5418 SPR_NOACCESS, SPR_NOACCESS,
5419 SPR_NOACCESS, SPR_NOACCESS,
5420 &spr_read_generic, &spr_write_generic,
5421 0x00000000);
5422 spr_register_hv(env, SPR_HSPRG1, "HSPRG1",
5423 SPR_NOACCESS, SPR_NOACCESS,
5424 SPR_NOACCESS, SPR_NOACCESS,
5425 &spr_read_generic, &spr_write_generic,
5426 0x00000000);
5427 spr_register_hv(env, SPR_HSRR0, "HSRR0",
5428 SPR_NOACCESS, SPR_NOACCESS,
5429 SPR_NOACCESS, SPR_NOACCESS,
5430 &spr_read_generic, &spr_write_generic,
5431 0x00000000);
5432 spr_register_hv(env, SPR_HSRR1, "HSRR1",
5433 SPR_NOACCESS, SPR_NOACCESS,
5434 SPR_NOACCESS, SPR_NOACCESS,
5435 &spr_read_generic, &spr_write_generic,
5436 0x00000000);
5437 spr_register_hv(env, SPR_HDAR, "HDAR",
5438 SPR_NOACCESS, SPR_NOACCESS,
5439 SPR_NOACCESS, SPR_NOACCESS,
5440 &spr_read_generic, &spr_write_generic,
5441 0x00000000);
5442 spr_register_hv(env, SPR_HDSISR, "HDSISR",
5443 SPR_NOACCESS, SPR_NOACCESS,
5444 SPR_NOACCESS, SPR_NOACCESS,
5445 &spr_read_generic, &spr_write_generic,
5446 0x00000000);
51671009 5447 spr_register_hv(env, SPR_HRMOR, "HRMOR",
8eeb330c
BH		 5448 SPR_NOACCESS, SPR_NOACCESS,
5449 SPR_NOACCESS, SPR_NOACCESS,
5450 &spr_read_generic, &spr_write_generic,
5451 0x00000000);
51671009
DG		 5452}
5453
a08eea67 5454static void register_rmor_sprs(CPUPPCState *env)
51671009
DG		 5455{
5456 spr_register_hv(env, SPR_RMOR, "RMOR",
8eeb330c
BH		 5457 SPR_NOACCESS, SPR_NOACCESS,
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
e61716aa
AK		 5460 0x00000000);
5461}
5462
a08eea67 5463static void register_power8_ids_sprs(CPUPPCState *env)
d1a721ab
AK		 5464{
5465 /* Thread identification */
5466 spr_register(env, SPR_TIR, "TIR",
5467 SPR_NOACCESS, SPR_NOACCESS,
5468 &spr_read_generic, SPR_NOACCESS,
5469 0x00000000);
5470}
5471
a08eea67 5472static void register_book3s_purr_sprs(CPUPPCState *env)
e61716aa
AK		 5473{
5474#if !defined(CONFIG_USER_ONLY)
5475 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
5cc7e69f
SJS		 5476 spr_register_kvm_hv(env, SPR_PURR, "PURR",
5477 &spr_read_purr, SPR_NOACCESS,
5478 &spr_read_purr, SPR_NOACCESS,
5479 &spr_read_purr, &spr_write_purr,
5480 KVM_REG_PPC_PURR, 0x00000000);
5481 spr_register_kvm_hv(env, SPR_SPURR, "SPURR",
5482 &spr_read_purr, SPR_NOACCESS,
5483 &spr_read_purr, SPR_NOACCESS,
5484 &spr_read_purr, &spr_write_purr,
5485 KVM_REG_PPC_SPURR, 0x00000000);
e61716aa
AK		 5486#endif
5487}
5488
a08eea67 5489static void register_power6_dbg_sprs(CPUPPCState *env)
5db7d4fa
AK		 5490{
5491#if !defined(CONFIG_USER_ONLY)
5492 spr_register(env, SPR_CFAR, "SPR_CFAR",
5493 SPR_NOACCESS, SPR_NOACCESS,
5494 &spr_read_cfar, &spr_write_cfar,
5495 0x00000000);
5496#endif
5497}
5498
a08eea67 5499static void register_power5p_common_sprs(CPUPPCState *env)
5db7d4fa 5500{
7303f83d
AK		 5501 spr_register_kvm(env, SPR_PPR, "PPR",
5502 &spr_read_generic, &spr_write_generic,
5503 &spr_read_generic, &spr_write_generic,
5504 KVM_REG_PPC_PPR, 0x00000000);
5db7d4fa
AK		 5505}
5506
a08eea67 5507static void register_power6_common_sprs(CPUPPCState *env)
5db7d4fa
AK		 5508{
5509#if !defined(CONFIG_USER_ONLY)
5510 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
5511 SPR_NOACCESS, SPR_NOACCESS,
5512 &spr_read_generic, &spr_write_generic,
5513 KVM_REG_PPC_DSCR, 0x00000000);
5514#endif
5515 /*
5516 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
6b375544 5517 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access.
5db7d4fa 5518 */
6b375544 5519 spr_register_hv(env, SPR_PCR, "PCR",
5db7d4fa
AK		 5520 SPR_NOACCESS, SPR_NOACCESS,
5521 SPR_NOACCESS, SPR_NOACCESS,
6b375544 5522 &spr_read_generic, &spr_write_pcr,
5db7d4fa
AK		 5523 0x00000000);
5524}
5525
a08eea67 5526static void register_power8_tce_address_control_sprs(CPUPPCState *env)
768167ab 5527{
1e440cbc
TH		 5528 spr_register_kvm(env, SPR_TAR, "TAR",
5529 &spr_read_tar, &spr_write_tar,
5530 &spr_read_generic, &spr_write_generic,
5531 KVM_REG_PPC_TAR, 0x00000000);
768167ab
AK		 5532}
5533
a08eea67 5534static void register_power8_tm_sprs(CPUPPCState *env)
cdcdda27
AK		 5535{
5536 spr_register_kvm(env, SPR_TFHAR, "TFHAR",
5537 &spr_read_tm, &spr_write_tm,
5538 &spr_read_tm, &spr_write_tm,
5539 KVM_REG_PPC_TFHAR, 0x00000000);
5540 spr_register_kvm(env, SPR_TFIAR, "TFIAR",
5541 &spr_read_tm, &spr_write_tm,
5542 &spr_read_tm, &spr_write_tm,
5543 KVM_REG_PPC_TFIAR, 0x00000000);
5544 spr_register_kvm(env, SPR_TEXASR, "TEXASR",
5545 &spr_read_tm, &spr_write_tm,
5546 &spr_read_tm, &spr_write_tm,
5547 KVM_REG_PPC_TEXASR, 0x00000000);
5548 spr_register(env, SPR_TEXASRU, "TEXASRU",
5549 &spr_read_tm_upper32, &spr_write_tm_upper32,
5550 &spr_read_tm_upper32, &spr_write_tm_upper32,
5551 0x00000000);
5552}
5553
a08eea67 5554static void register_power8_ebb_sprs(CPUPPCState *env)
4ee4a03b
AK		 5555{
5556 spr_register(env, SPR_BESCRS, "BESCRS",
5557 &spr_read_ebb, &spr_write_ebb,
5558 &spr_read_generic, &spr_write_generic,
5559 0x00000000);
5560 spr_register(env, SPR_BESCRSU, "BESCRSU",
5561 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5562 &spr_read_prev_upper32, &spr_write_prev_upper32,
5563 0x00000000);
5564 spr_register(env, SPR_BESCRR, "BESCRR",
5565 &spr_read_ebb, &spr_write_ebb,
5566 &spr_read_generic, &spr_write_generic,
5567 0x00000000);
5568 spr_register(env, SPR_BESCRRU, "BESCRRU",
5569 &spr_read_ebb_upper32, &spr_write_ebb_upper32,
5570 &spr_read_prev_upper32, &spr_write_prev_upper32,
5571 0x00000000);
5572 spr_register_kvm(env, SPR_EBBHR, "EBBHR",
5573 &spr_read_ebb, &spr_write_ebb,
5574 &spr_read_generic, &spr_write_generic,
5575 KVM_REG_PPC_EBBHR, 0x00000000);
5576 spr_register_kvm(env, SPR_EBBRR, "EBBRR",
5577 &spr_read_ebb, &spr_write_ebb,
5578 &spr_read_generic, &spr_write_generic,
5579 KVM_REG_PPC_EBBRR, 0x00000000);
5580 spr_register_kvm(env, SPR_BESCR, "BESCR",
5581 &spr_read_ebb, &spr_write_ebb,
5582 &spr_read_generic, &spr_write_generic,
5583 KVM_REG_PPC_BESCR, 0x00000000);
5584}
5585
3ba55e39 5586/* Virtual Time Base */
a08eea67 5587static void register_vtb_sprs(CPUPPCState *env)
3ba55e39 5588{
5d62725b
SJS		 5589 spr_register_kvm_hv(env, SPR_VTB, "VTB",
5590 SPR_NOACCESS, SPR_NOACCESS,
5591 &spr_read_vtb, SPR_NOACCESS,
5592 &spr_read_vtb, &spr_write_vtb,
5593 KVM_REG_PPC_VTB, 0x00000000);
3ba55e39
CB		 5594}
5595
a08eea67 5596static void register_power8_fscr_sprs(CPUPPCState *env)
7019cb3d 5597{
45ed0be1
AK		 5598#if defined(CONFIG_USER_ONLY)
5599 target_ulong initval = 1ULL << FSCR_TAR;
5600#else
5601 target_ulong initval = 0;
5602#endif
7019cb3d
AK		 5603 spr_register_kvm(env, SPR_FSCR, "FSCR",
5604 SPR_NOACCESS, SPR_NOACCESS,
5605 &spr_read_generic, &spr_write_generic,
45ed0be1 5606 KVM_REG_PPC_FSCR, initval);
7019cb3d
AK		 5607}
5608
a08eea67 5609static void register_power8_pspb_sprs(CPUPPCState *env)
d6f1445f
TH		 5610{
5611 spr_register_kvm(env, SPR_PSPB, "PSPB",
5612 SPR_NOACCESS, SPR_NOACCESS,
5613 &spr_read_generic, &spr_write_generic32,
5614 KVM_REG_PPC_PSPB, 0);
5615}
5616
a08eea67 5617static void register_power8_dpdes_sprs(CPUPPCState *env)
cfc61ba6
AK		 5618{
5619#if !defined(CONFIG_USER_ONLY)
5620 /* Directed Privileged Door-bell Exception State, used for IPI */
5ba7ba1d
CLG		 5621 spr_register_kvm_hv(env, SPR_DPDES, "DPDES",
5622 SPR_NOACCESS, SPR_NOACCESS,
5623 &spr_read_dpdes, SPR_NOACCESS,
5624 &spr_read_dpdes, &spr_write_dpdes,
5625 KVM_REG_PPC_DPDES, 0x00000000);
cfc61ba6
AK		 5626#endif
5627}
5628
a08eea67 5629static void register_power8_ic_sprs(CPUPPCState *env)
21a558be
BH		 5630{
5631#if !defined(CONFIG_USER_ONLY)
5632 spr_register_hv(env, SPR_IC, "IC",
5633 SPR_NOACCESS, SPR_NOACCESS,
5634 &spr_read_generic, SPR_NOACCESS,
5635 &spr_read_generic, &spr_write_generic,
5636 0);
9d0e5c8c
CLG		 5637#endif
5638}
5639
a08eea67 5640static void register_power8_book4_sprs(CPUPPCState *env)
9d0e5c8c
CLG		 5641{
5642 /* Add a number of P8 book4 registers */
5643#if !defined(CONFIG_USER_ONLY)
9c1cf38d
BH		 5644 spr_register_kvm(env, SPR_ACOP, "ACOP",
5645 SPR_NOACCESS, SPR_NOACCESS,
5646 &spr_read_generic, &spr_write_generic,
5647 KVM_REG_PPC_ACOP, 0);
5648 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5649 SPR_NOACCESS, SPR_NOACCESS,
31b2b0f8 5650 &spr_read_generic, &spr_write_pidr,
9c1cf38d
BH		 5651 KVM_REG_PPC_PID, 0);
5652 spr_register_kvm(env, SPR_WORT, "WORT",
5653 SPR_NOACCESS, SPR_NOACCESS,
5654 &spr_read_generic, &spr_write_generic,
5655 KVM_REG_PPC_WORT, 0);
21a558be
BH		 5656#endif
5657}
5658
a08eea67 5659static void register_power7_book4_sprs(CPUPPCState *env)
8eb0f563
BH		 5660{
5661 /* Add a number of P7 book4 registers */
5662#if !defined(CONFIG_USER_ONLY)
5663 spr_register_kvm(env, SPR_ACOP, "ACOP",
5664 SPR_NOACCESS, SPR_NOACCESS,
5665 &spr_read_generic, &spr_write_generic,
5666 KVM_REG_PPC_ACOP, 0);
5667 spr_register_kvm(env, SPR_BOOKS_PID, "PID",
5668 SPR_NOACCESS, SPR_NOACCESS,
5669 &spr_read_generic, &spr_write_generic,
5670 KVM_REG_PPC_PID, 0);
5671#endif
5672}
5673
a08eea67 5674static void register_power8_rpr_sprs(CPUPPCState *env)
8eeb330c
BH		 5675{
5676#if !defined(CONFIG_USER_ONLY)
5677 spr_register_hv(env, SPR_RPR, "RPR",
5678 SPR_NOACCESS, SPR_NOACCESS,
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic,
5681 0x00000103070F1F3F);
5682#endif
5683}
5684
a08eea67 5685static void register_power9_mmu_sprs(CPUPPCState *env)
4a7518e0
CLG		 5686{
5687#if !defined(CONFIG_USER_ONLY)
5688 /* Partition Table Control */
56de52ca
SJS		 5689 spr_register_kvm_hv(env, SPR_PTCR, "PTCR",
5690 SPR_NOACCESS, SPR_NOACCESS,
5691 SPR_NOACCESS, SPR_NOACCESS,
5692 &spr_read_generic, &spr_write_ptcr,
5693 KVM_REG_PPC_PTCR, 0x00000000);
32d0f0d8
SJS		 5694 /* Address Segment Descriptor Register */
5695 spr_register_hv(env, SPR_ASDR, "ASDR",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 SPR_NOACCESS, SPR_NOACCESS,
5698 &spr_read_generic, &spr_write_generic,
5699 0x0000000000000000);
4a7518e0
CLG		 5700#endif
5701}
5702
903f84eb
VC		 5703static void register_power10_hash_sprs(CPUPPCState *env)
5704{
5705 /*
5706 * it's the OS responsability to generate a random value for the registers
5707 * in each process' context. So, initialize it with 0 here.
5708 */
5709 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0;
5710#if defined(CONFIG_USER_ONLY)
5711 /* in linux-user, setup the hash register with a random value */
5712 GRand *rand = g_rand_new();
5713 hashkeyr_initial_value =
5714 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5715 hashpkeyr_initial_value =
5716 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand);
5717 g_rand_free(rand);
5718#endif
5719 spr_register(env, SPR_HASHKEYR, "HASHKEYR",
5720 SPR_NOACCESS, SPR_NOACCESS,
5721 &spr_read_generic, &spr_write_generic,
5722 hashkeyr_initial_value);
5723 spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR",
5724 SPR_NOACCESS, SPR_NOACCESS,
5725 SPR_NOACCESS, SPR_NOACCESS,
5726 &spr_read_generic, &spr_write_generic,
5727 hashpkeyr_initial_value);
5728}
5729
8f2e9d40
DHB		 5730/*
5731 * Initialize PMU counter overflow timers for Power8 and
5732 * newer Power chips when using TCG.
5733 */
5734static void init_tcg_pmu_power8(CPUPPCState *env)
5735{
8f2e9d40 5736 /* Init PMU overflow timers */
33edcde7 5737 if (tcg_enabled()) {
8f2e9d40
DHB		 5738 cpu_ppc_pmu_init(env);
5739 }
8f2e9d40
DHB		 5740}
5741
4f4f28ff 5742static void init_proc_book3s_common(CPUPPCState *env)
42382f62 5743{
217781af 5744 register_non_embedded_sprs(env);
a08eea67
BL		 5745 register_book3s_altivec_sprs(env);
5746 register_book3s_pmu_sup_sprs(env);
5747 register_book3s_pmu_user_sprs(env);
5748 register_book3s_ctrl_sprs(env);
f350982f
BL		 5749 /*
5750 * Can't find information on what this should be on reset. This
5751 * value is the one used by 74xx processors.
5752 */
5753 vscr_init(env, 0x00010000);
2a48d83d
FR		 5754
5755 spr_register(env, SPR_USPRG3, "USPRG3",
5756 &spr_read_ureg, SPR_NOACCESS,
5757 &spr_read_ureg, SPR_NOACCESS,
5758 0x00000000);
4f4f28ff 5759}
fd51ff63 5760
4f4f28ff
SJS		 5761static void init_proc_970(CPUPPCState *env)
5762{
5763 /* Common Registers */
5764 init_proc_book3s_common(env);
a08eea67
BL		 5765 register_sdr1_sprs(env);
5766 register_book3s_dbg_sprs(env);
4f4f28ff
SJS		 5767
5768 /* 970 Specific Registers */
a08eea67
BL		 5769 register_970_hid_sprs(env);
5770 register_970_hior_sprs(env);
5771 register_low_BATs(env);
5772 register_970_pmu_sup_sprs(env);
5773 register_970_pmu_user_sprs(env);
5774 register_970_lpar_sprs(env);
5775 register_970_dbg_sprs(env);
4f4f28ff
SJS		 5776
5777 /* env variables */
d63001d1
JM		 5778 env->dcache_line_size = 128;
5779 env->icache_line_size = 128;
a750fc0b 5780
4f4f28ff
SJS		 5781 /* Allocate hardware IRQ controller */
5782 init_excp_970(env);
db70b311 5783 ppc970_irq_init(env_archcpu(env));
7488d481
AK		 5784}
5785
bbc01ca7 5786POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7856e3a4 5787{
ca5dff0a 5788 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4
AF		 5789 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5790
bbc01ca7
AK		 5791 dc->desc = "PowerPC 970";
5792 pcc->init_proc = init_proc_970;
5793 pcc->check_pow = check_pow_970;
53116ebf
AF		 5794 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5795 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5796 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5797 PPC_FLOAT_STFIWX |
5798 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5799 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5800 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5801 PPC_64B | PPC_ALTIVEC |
5802 PPC_SEGMENT_64B | PPC_SLBI;
03abfd90 5803 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
9df5a466
TM		 5804 pcc->msr_mask = (1ull << MSR_SF) |
5805 (1ull << MSR_VR) |
5806 (1ull << MSR_POW) |
5807 (1ull << MSR_EE) |
5808 (1ull << MSR_PR) |
5809 (1ull << MSR_FP) |
5810 (1ull << MSR_ME) |
5811 (1ull << MSR_FE0) |
5812 (1ull << MSR_SE) |
5813 (1ull << MSR_DE) |
5814 (1ull << MSR_FE1) |
5815 (1ull << MSR_IR) |
5816 (1ull << MSR_DR) |
5817 (1ull << MSR_PMM) |
5818 (1ull << MSR_RI);
ba9fd9f1 5819 pcc->mmu_model = POWERPC_MMU_64B;
b632a148 5820#if defined(CONFIG_SOFTMMU)
21e405f1 5821 pcc->hash64_opts = &ppc_hash64_opts_basic;
b632a148 5822#endif
ba9fd9f1
AF		 5823 pcc->excp_model = POWERPC_EXCP_970;
5824 pcc->bus_model = PPC_FLAGS_INPUT_970;
5825 pcc->bfd_mach = bfd_mach_ppc64;
5826 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5827 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5828 POWERPC_FLAG_BUS_CLK;
06f6e124
AG		 5829 pcc->l1_dcache_size = 0x8000;
5830 pcc->l1_icache_size = 0x10000;
7856e3a4
AF		 5831}
5832
35ebcb2b
AF		 5833static void init_proc_power5plus(CPUPPCState *env)
5834{
4f4f28ff
SJS		 5835 /* Common Registers */
5836 init_proc_book3s_common(env);
a08eea67
BL		 5837 register_sdr1_sprs(env);
5838 register_book3s_dbg_sprs(env);
4f4f28ff
SJS		 5839
5840 /* POWER5+ Specific Registers */
a08eea67
BL		 5841 register_970_hid_sprs(env);
5842 register_970_hior_sprs(env);
5843 register_low_BATs(env);
5844 register_970_pmu_sup_sprs(env);
5845 register_970_pmu_user_sprs(env);
5846 register_power5p_common_sprs(env);
5847 register_power5p_lpar_sprs(env);
5848 register_power5p_ear_sprs(env);
5849 register_power5p_tb_sprs(env);
4f4f28ff
SJS		 5850
5851 /* env variables */
4f4f28ff
SJS		 5852 env->dcache_line_size = 128;
5853 env->icache_line_size = 128;
5854
5855 /* Allocate hardware IRQ controller */
5856 init_excp_970(env);
db70b311 5857 ppc970_irq_init(env_archcpu(env));
35ebcb2b
AF		 5858}
5859
5860POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
5861{
5862 DeviceClass *dc = DEVICE_CLASS(oc);
5863 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5864
793826cd 5865 dc->fw_name = "PowerPC,POWER5";
35ebcb2b
AF		 5866 dc->desc = "POWER5+";
5867 pcc->init_proc = init_proc_power5plus;
90618f4f 5868 pcc->check_pow = check_pow_970;
35ebcb2b
AF		 5869 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5870 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5871 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5872 PPC_FLOAT_STFIWX |
91137619 5873 PPC_FLOAT_EXT |
35ebcb2b
AF		 5874 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5875 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5876 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5877 PPC_64B |
23ab6d88 5878 PPC_POPCNTB |
35ebcb2b 5879 PPC_SEGMENT_64B | PPC_SLBI;
03abfd90 5880 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC;
9df5a466
TM		 5881 pcc->msr_mask = (1ull << MSR_SF) |
5882 (1ull << MSR_VR) |
5883 (1ull << MSR_POW) |
5884 (1ull << MSR_EE) |
5885 (1ull << MSR_PR) |
5886 (1ull << MSR_FP) |
5887 (1ull << MSR_ME) |
5888 (1ull << MSR_FE0) |
5889 (1ull << MSR_SE) |
5890 (1ull << MSR_DE) |
5891 (1ull << MSR_FE1) |
5892 (1ull << MSR_IR) |
5893 (1ull << MSR_DR) |
5894 (1ull << MSR_PMM) |
5895 (1ull << MSR_RI);
e232eccc
DG		 5896 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 |
5897 LPCR_RMI | LPCR_HDICE;
aa4bb587 5898 pcc->mmu_model = POWERPC_MMU_2_03;
35ebcb2b 5899#if defined(CONFIG_SOFTMMU)
21e405f1 5900 pcc->hash64_opts = &ppc_hash64_opts_basic;
a8dafa52 5901 pcc->lrg_decr_bits = 32;
35ebcb2b
AF		 5902#endif
5903 pcc->excp_model = POWERPC_EXCP_970;
5904 pcc->bus_model = PPC_FLAGS_INPUT_970;
5905 pcc->bfd_mach = bfd_mach_ppc64;
5906 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5907 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5908 POWERPC_FLAG_BUS_CLK;
06f6e124
AG		 5909 pcc->l1_dcache_size = 0x8000;
5910 pcc->l1_icache_size = 0x10000;
35ebcb2b
AF		 5911}
5912
c364946d 5913static void init_proc_POWER7(CPUPPCState *env)
9d52e907 5914{
4f4f28ff
SJS		 5915 /* Common Registers */
5916 init_proc_book3s_common(env);
a08eea67
BL		 5917 register_sdr1_sprs(env);
5918 register_book3s_dbg_sprs(env);
4f4f28ff
SJS		 5919
5920 /* POWER7 Specific Registers */
a08eea67
BL		 5921 register_book3s_ids_sprs(env);
5922 register_rmor_sprs(env);
5923 register_amr_sprs(env);
5924 register_book3s_purr_sprs(env);
5925 register_power5p_common_sprs(env);
5926 register_power5p_lpar_sprs(env);
5927 register_power5p_ear_sprs(env);
5928 register_power5p_tb_sprs(env);
5929 register_power6_common_sprs(env);
5930 register_power6_dbg_sprs(env);
5931 register_power7_book4_sprs(env);
4f4f28ff
SJS		 5932
5933 /* env variables */
4f4f28ff
SJS		 5934 env->dcache_line_size = 128;
5935 env->icache_line_size = 128;
5936
5937 /* Allocate hardware IRQ controller */
5938 init_excp_POWER7(env);
db70b311 5939 ppcPOWER7_irq_init(env_archcpu(env));
9d52e907 5940}
9d52e907 5941
21d3a78e 5942static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
03ae4133 5943{
21d3a78e
NP		 5944 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
5945 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
5946
5947 if (!best) {
5948 if (base == CPU_POWERPC_POWER7_BASE) {
5949 return true;
5950 }
5951 if (base == CPU_POWERPC_POWER7P_BASE) {
5952 return true;
5953 }
03ae4133 5954 }
21d3a78e
NP		 5955
5956 if (base != pcc_base) {
5957 return false;
03ae4133 5958 }
21d3a78e
NP		 5959
5960 return true;
03ae4133
AK		 5961}
5962
7778a575
BH		 5963static bool cpu_has_work_POWER7(CPUState *cs)
5964{
5965 PowerPCCPU *cpu = POWERPC_CPU(cs);
5966 CPUPPCState *env = &cpu->env;
5967
5968 if (cs->halted) {
5969 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
5970 return false;
5971 }
5972 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
5973 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) {
5974 return true;
5975 }
5976 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
5977 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) {
5978 return true;
5979 }
5980 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
5981 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
5982 return true;
5983 }
5984 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
5985 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) {
5986 return true;
5987 }
5988 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
5989 return true;
5990 }
5991 return false;
5992 } else {
0939b8f8
VC		 5993 return FIELD_EX64(env->msr, MSR, EE) &&
5994 (cs->interrupt_request & CPU_INTERRUPT_HARD);
7778a575
BH		 5995 }
5996}
5997
7856e3a4
AF		 5998POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
5999{
ca5dff0a 6000 DeviceClass *dc = DEVICE_CLASS(oc);
7856e3a4 6001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7778a575 6002 CPUClass *cc = CPU_CLASS(oc);
7856e3a4 6003
793826cd 6004 dc->fw_name = "PowerPC,POWER7";
ca5dff0a 6005 dc->desc = "POWER7";
03ae4133 6006 pcc->pvr_match = ppc_pvr_match_power7;
8cd2ce7a
TH		 6007 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
6008 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
7856e3a4
AF		 6009 pcc->init_proc = init_proc_POWER7;
6010 pcc->check_pow = check_pow_nocheck;
7778a575 6011 cc->has_work = cpu_has_work_POWER7;
e71ec2e9 6012 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
53116ebf
AF		 6013 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6014 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
ce8ca30b 6015 PPC_FLOAT_FRSQRTES |
53116ebf 6016 PPC_FLOAT_STFIWX |
c7386080 6017 PPC_FLOAT_EXT |
53116ebf
AF		 6018 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6019 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6020 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
dfdd3e43 6021 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
53116ebf 6022 PPC_SEGMENT_64B | PPC_SLBI |
b7815375
BH		 6023 PPC_POPCNTB | PPC_POPCNTWD |
6024 PPC_CILDST;
86ba37ed 6025 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
1fa6c533 6026 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
29a0e4e9 6027 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7778a575 6028 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
4dc5f8ab 6029 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
9df5a466
TM		 6030 pcc->msr_mask = (1ull << MSR_SF) |
6031 (1ull << MSR_VR) |
6032 (1ull << MSR_VSX) |
6033 (1ull << MSR_EE) |
6034 (1ull << MSR_PR) |
6035 (1ull << MSR_FP) |
6036 (1ull << MSR_ME) |
6037 (1ull << MSR_FE0) |
6038 (1ull << MSR_SE) |
6039 (1ull << MSR_DE) |
6040 (1ull << MSR_FE1) |
6041 (1ull << MSR_IR) |
6042 (1ull << MSR_DR) |
6043 (1ull << MSR_PMM) |
6044 (1ull << MSR_RI) |
6045 (1ull << MSR_LE);
e232eccc
DG		 6046 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD |
6047 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6048 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 |
6049 LPCR_MER | LPCR_TC |
6050 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE;
6051 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
ba9fd9f1 6052 pcc->mmu_model = POWERPC_MMU_2_06;
b632a148 6053#if defined(CONFIG_SOFTMMU)
b07c59f7 6054 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
a8dafa52 6055 pcc->lrg_decr_bits = 32;
b650d6a2
AK		 6056#endif
6057 pcc->excp_model = POWERPC_EXCP_POWER7;
6058 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6059 pcc->bfd_mach = bfd_mach_ppc64;
6060 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6061 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6062 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6063 POWERPC_FLAG_VSX;
6064 pcc->l1_dcache_size = 0x8000;
6065 pcc->l1_icache_size = 0x8000;
6066}
6067
60511041
TM		 6068static void init_proc_POWER8(CPUPPCState *env)
6069{
4f4f28ff
SJS		 6070 /* Common Registers */
6071 init_proc_book3s_common(env);
a08eea67
BL		 6072 register_sdr1_sprs(env);
6073 register_book3s_207_dbg_sprs(env);
4f4f28ff 6074
8f2e9d40
DHB		 6075 /* Common TCG PMU */
6076 init_tcg_pmu_power8(env);
6077
4f4f28ff 6078 /* POWER8 Specific Registers */
a08eea67
BL		 6079 register_book3s_ids_sprs(env);
6080 register_rmor_sprs(env);
6081 register_amr_sprs(env);
6082 register_iamr_sprs(env);
6083 register_book3s_purr_sprs(env);
6084 register_power5p_common_sprs(env);
6085 register_power5p_lpar_sprs(env);
6086 register_power5p_ear_sprs(env);
6087 register_power5p_tb_sprs(env);
6088 register_power6_common_sprs(env);
6089 register_power6_dbg_sprs(env);
6090 register_power8_tce_address_control_sprs(env);
6091 register_power8_ids_sprs(env);
6092 register_power8_ebb_sprs(env);
6093 register_power8_fscr_sprs(env);
6094 register_power8_pmu_sup_sprs(env);
6095 register_power8_pmu_user_sprs(env);
6096 register_power8_tm_sprs(env);
6097 register_power8_pspb_sprs(env);
6098 register_power8_dpdes_sprs(env);
6099 register_vtb_sprs(env);
6100 register_power8_ic_sprs(env);
6101 register_power8_book4_sprs(env);
6102 register_power8_rpr_sprs(env);
4f4f28ff
SJS		 6103
6104 /* env variables */
4f4f28ff
SJS		 6105 env->dcache_line_size = 128;
6106 env->icache_line_size = 128;
6107
6108 /* Allocate hardware IRQ controller */
6109 init_excp_POWER8(env);
db70b311 6110 ppcPOWER7_irq_init(env_archcpu(env));
60511041
TM		 6111}
6112
21d3a78e 6113static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
03ae4133 6114{
21d3a78e
NP		 6115 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6116 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6117
6118 if (!best) {
6119 if (base == CPU_POWERPC_POWER8_BASE) {
6120 return true;
6121 }
6122 if (base == CPU_POWERPC_POWER8E_BASE) {
6123 return true;
6124 }
6125 if (base == CPU_POWERPC_POWER8NVL_BASE) {
6126 return true;
6127 }
03ae4133 6128 }
21d3a78e
NP		 6129 if (base != pcc_base) {
6130 return false;
03ae4133 6131 }
21d3a78e
NP		 6132
6133 return true;
03ae4133
AK		 6134}
6135
7778a575
BH		 6136static bool cpu_has_work_POWER8(CPUState *cs)
6137{
6138 PowerPCCPU *cpu = POWERPC_CPU(cs);
6139 CPUPPCState *env = &cpu->env;
6140
6141 if (cs->halted) {
6142 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6143 return false;
6144 }
6145 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6146 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) {
6147 return true;
6148 }
6149 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6150 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) {
6151 return true;
6152 }
6153 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) &&
6154 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6155 return true;
6156 }
6157 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) &&
6158 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) {
6159 return true;
6160 }
6161 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6162 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) {
6163 return true;
6164 }
6165 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6166 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) {
6167 return true;
6168 }
6169 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6170 return true;
6171 }
6172 return false;
6173 } else {
0939b8f8
VC		 6174 return FIELD_EX64(env->msr, MSR, EE) &&
6175 (cs->interrupt_request & CPU_INTERRUPT_HARD);
7778a575
BH		 6176 }
6177}
6178
b60c6007 6179POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
8d43ea1c
PS		 6180{
6181 DeviceClass *dc = DEVICE_CLASS(oc);
6182 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7778a575 6183 CPUClass *cc = CPU_CLASS(oc);
8d43ea1c 6184
793826cd 6185 dc->fw_name = "PowerPC,POWER8";
b60c6007 6186 dc->desc = "POWER8";
03ae4133 6187 pcc->pvr_match = ppc_pvr_match_power8;
8cd2ce7a
TH		 6188 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6189 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
60511041 6190 pcc->init_proc = init_proc_POWER8;
8d43ea1c 6191 pcc->check_pow = check_pow_nocheck;
7778a575 6192 cc->has_work = cpu_has_work_POWER8;
536492eb 6193 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
8d43ea1c
PS		 6194 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6195 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
ce8ca30b 6196 PPC_FLOAT_FRSQRTES |
8d43ea1c 6197 PPC_FLOAT_STFIWX |
c7386080 6198 PPC_FLOAT_EXT |
8d43ea1c
PS		 6199 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6200 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6201 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
4e080611 6202 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
8d43ea1c 6203 PPC_SEGMENT_64B | PPC_SLBI |
b7815375
BH		 6204 PPC_POPCNTB | PPC_POPCNTWD |
6205 PPC_CILDST;
86ba37ed 6206 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
1fa6c533 6207 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
29a0e4e9 6208 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
38a85337 6209 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
df99d30d 6210 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
3e28c5e3 6211 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
4dc5f8ab
MF		 6212 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
6213 PPC2_BCDA_ISA206;
9df5a466 6214 pcc->msr_mask = (1ull << MSR_SF) |
23513f81 6215 (1ull << MSR_HV) |
cdcdda27 6216 (1ull << MSR_TM) |
9df5a466
TM		 6217 (1ull << MSR_VR) |
6218 (1ull << MSR_VSX) |
6219 (1ull << MSR_EE) |
6220 (1ull << MSR_PR) |
6221 (1ull << MSR_FP) |
6222 (1ull << MSR_ME) |
6223 (1ull << MSR_FE0) |
6224 (1ull << MSR_SE) |
6225 (1ull << MSR_DE) |
6226 (1ull << MSR_FE1) |
6227 (1ull << MSR_IR) |
6228 (1ull << MSR_DR) |
6229 (1ull << MSR_PMM) |
6230 (1ull << MSR_RI) |
21b786f6
SG		 6231 (1ull << MSR_TS0) |
6232 (1ull << MSR_TS1) |
9df5a466 6233 (1ull << MSR_LE);
e232eccc
DG		 6234 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV |
6235 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE |
6236 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 |
6237 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
6238 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE;
6239 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
6240 LPCR_P8_PECE3 | LPCR_P8_PECE4;
aa4bb587 6241 pcc->mmu_model = POWERPC_MMU_2_07;
8d43ea1c 6242#if defined(CONFIG_SOFTMMU)
b07c59f7 6243 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
a8dafa52 6244 pcc->lrg_decr_bits = 32;
289af4ac 6245 pcc->n_host_threads = 8;
706d6467
AK		 6246#endif
6247 pcc->excp_model = POWERPC_EXCP_POWER8;
6248 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
6249 pcc->bfd_mach = bfd_mach_ppc64;
6250 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6251 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6252 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
6253 POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
6254 pcc->l1_dcache_size = 0x8000;
6255 pcc->l1_icache_size = 0x8000;
706d6467 6256}
4f4f28ff 6257
ccd531b9
SJS		 6258#ifdef CONFIG_SOFTMMU
6259/*
6260 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6261 * Encoded as array of int_32s in the form:
6262 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6263 * x -> AP encoding
6264 * y -> radix mode supported page size (encoded as a shift)
6265 */
6266static struct ppc_radix_page_info POWER9_radix_page_info = {
6267 .count = 4,
6268 .entries = {
6269 0x0000000c, /* 4K - enc: 0x0 */
6270 0xa0000010, /* 64K - enc: 0x5 */
6271 0x20000015, /* 2M - enc: 0x1 */
6272 0x4000001e /* 1G - enc: 0x2 */
6273 }
6274};
6275#endif /* CONFIG_SOFTMMU */
6276
706d6467
AK		 6277static void init_proc_POWER9(CPUPPCState *env)
6278{
4f4f28ff
SJS		 6279 /* Common Registers */
6280 init_proc_book3s_common(env);
a08eea67 6281 register_book3s_207_dbg_sprs(env);
4f4f28ff 6282
8f2e9d40
DHB		 6283 /* Common TCG PMU */
6284 init_tcg_pmu_power8(env);
6285
4f4f28ff 6286 /* POWER8 Specific Registers */
a08eea67
BL		 6287 register_book3s_ids_sprs(env);
6288 register_amr_sprs(env);
6289 register_iamr_sprs(env);
6290 register_book3s_purr_sprs(env);
6291 register_power5p_common_sprs(env);
6292 register_power5p_lpar_sprs(env);
6293 register_power5p_ear_sprs(env);
6294 register_power5p_tb_sprs(env);
6295 register_power6_common_sprs(env);
6296 register_power6_dbg_sprs(env);
6297 register_power8_tce_address_control_sprs(env);
6298 register_power8_ids_sprs(env);
6299 register_power8_ebb_sprs(env);
6300 register_power8_fscr_sprs(env);
6301 register_power8_pmu_sup_sprs(env);
6302 register_power8_pmu_user_sprs(env);
6303 register_power8_tm_sprs(env);
6304 register_power8_pspb_sprs(env);
6305 register_power8_dpdes_sprs(env);
6306 register_vtb_sprs(env);
6307 register_power8_ic_sprs(env);
6308 register_power8_book4_sprs(env);
6309 register_power8_rpr_sprs(env);
6310 register_power9_mmu_sprs(env);
4f4f28ff 6311
650f3287
DG		 6312 /* POWER9 Specific registers */
6313 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
6314 spr_read_generic, spr_write_generic,
6315 KVM_REG_PPC_TIDR, 0);
6316
b8af5b2d
DG		 6317 /* FIXME: Filter fields properly based on privilege level */
6318 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6319 spr_read_generic, spr_write_generic,
6320 KVM_REG_PPC_PSSCR, 0);
6321
4f4f28ff 6322 /* env variables */
4f4f28ff
SJS		 6323 env->dcache_line_size = 128;
6324 env->icache_line_size = 128;
6325
6326 /* Allocate hardware IRQ controller */
d8ce5fd6 6327 init_excp_POWER9(env);
db70b311 6328 ppcPOWER9_irq_init(env_archcpu(env));
706d6467
AK		 6329}
6330
21d3a78e 6331static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
706d6467 6332{
21d3a78e
NP		 6333 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6334 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6335
6336 if (!best) {
6337 if (base == CPU_POWERPC_POWER9_BASE) {
6338 return true;
6339 }
6340 }
6341
6342 if (base != pcc_base) {
6343 return false;
6344 }
6345
6346 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6347 /* Major DD version matches to power9_v1.0 and power9_v2.0 */
706d6467
AK		 6348 return true;
6349 }
21d3a78e 6350
706d6467
AK		 6351 return false;
6352}
6353
6f46dcb3
SJS		 6354static bool cpu_has_work_POWER9(CPUState *cs)
6355{
6356 PowerPCCPU *cpu = POWERPC_CPU(cs);
6357 CPUPPCState *env = &cpu->env;
6358
6359 if (cs->halted) {
21c0d66a
BH		 6360 uint64_t psscr = env->spr[SPR_PSSCR];
6361
6f46dcb3
SJS		 6362 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6363 return false;
6364 }
21c0d66a
BH		 6365
6366 /* If EC is clear, just return true on any pending interrupt */
6367 if (!(psscr & PSSCR_EC)) {
6368 return true;
6369 }
6f46dcb3
SJS		 6370 /* External Exception */
6371 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6372 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6eebe6dc 6373 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
9de754d3
VC		 6374 if (!heic || !FIELD_EX64_HV(env->msr) ||
6375 FIELD_EX64(env->msr, MSR, PR)) {
6eebe6dc
BH		 6376 return true;
6377 }
6f46dcb3
SJS		 6378 }
6379 /* Decrementer Exception */
6380 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6381 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6382 return true;
6383 }
6384 /* Machine Check or Hypervisor Maintenance Exception */
6385 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6386 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6387 return true;
6388 }
6389 /* Privileged Doorbell Exception */
6390 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6391 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6392 return true;
6393 }
6394 /* Hypervisor Doorbell Exception */
6395 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6396 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6397 return true;
6398 }
d8ce5fd6
BH		 6399 /* Hypervisor virtualization exception */
6400 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6401 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6402 return true;
6403 }
6f46dcb3
SJS		 6404 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6405 return true;
6406 }
6407 return false;
6408 } else {
0939b8f8
VC		 6409 return FIELD_EX64(env->msr, MSR, EE) &&
6410 (cs->interrupt_request & CPU_INTERRUPT_HARD);
6f46dcb3
SJS		 6411 }
6412}
6413
706d6467
AK		 6414POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
6415{
6416 DeviceClass *dc = DEVICE_CLASS(oc);
6417 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6f46dcb3 6418 CPUClass *cc = CPU_CLASS(oc);
706d6467
AK		 6419
6420 dc->fw_name = "PowerPC,POWER9";
6421 dc->desc = "POWER9";
706d6467
AK		 6422 pcc->pvr_match = ppc_pvr_match_power9;
6423 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
216c944e
SJS		 6424 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
6425 PCR_COMPAT_2_05;
706d6467
AK		 6426 pcc->init_proc = init_proc_POWER9;
6427 pcc->check_pow = check_pow_nocheck;
6f46dcb3 6428 cc->has_work = cpu_has_work_POWER9;
706d6467
AK		 6429 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6430 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6431 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6432 PPC_FLOAT_FRSQRTES |
6433 PPC_FLOAT_STFIWX |
6434 PPC_FLOAT_EXT |
6435 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6436 PPC_MEM_SYNC | PPC_MEM_EIEIO |
016b6e1d 6437 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
da874d90 6438 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
706d6467
AK		 6439 PPC_SEGMENT_64B | PPC_SLBI |
6440 PPC_POPCNTB | PPC_POPCNTWD |
6441 PPC_CILDST;
6442 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6443 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6444 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6445 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6446 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6447 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
4dc5f8ab
MF		 6448 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC |
6449 PPC2_BCDA_ISA206;
706d6467 6450 pcc->msr_mask = (1ull << MSR_SF) |
23513f81 6451 (1ull << MSR_HV) |
706d6467
AK		 6452 (1ull << MSR_TM) |
6453 (1ull << MSR_VR) |
6454 (1ull << MSR_VSX) |
6455 (1ull << MSR_EE) |
6456 (1ull << MSR_PR) |
6457 (1ull << MSR_FP) |
6458 (1ull << MSR_ME) |
6459 (1ull << MSR_FE0) |
6460 (1ull << MSR_SE) |
6461 (1ull << MSR_DE) |
6462 (1ull << MSR_FE1) |
6463 (1ull << MSR_IR) |
6464 (1ull << MSR_DR) |
6465 (1ull << MSR_PMM) |
6466 (1ull << MSR_RI) |
6467 (1ull << MSR_LE);
e232eccc
DG		 6468 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6469 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6470 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6471 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6472 LPCR_DEE | LPCR_OEE))
6473 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6474 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
6475 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
86cf1e9f 6476 pcc->mmu_model = POWERPC_MMU_3_00;
706d6467 6477#if defined(CONFIG_SOFTMMU)
706d6467 6478 /* segment page size remain the same */
b07c59f7 6479 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
ccd531b9 6480 pcc->radix_page_info = &POWER9_radix_page_info;
a8dafa52 6481 pcc->lrg_decr_bits = 56;
289af4ac 6482 pcc->n_host_threads = 4;
8d43ea1c 6483#endif
a790e82b 6484 pcc->excp_model = POWERPC_EXCP_POWER9;
67afe775 6485 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
8d43ea1c
PS		 6486 pcc->bfd_mach = bfd_mach_ppc64;
6487 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6488 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
74f23997 6489 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
3c89b8d6 6490 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
8d43ea1c
PS		 6491 pcc->l1_dcache_size = 0x8000;
6492 pcc->l1_icache_size = 0x8000;
6493}
a750fc0b 6494
7d37b274
CLG		 6495#ifdef CONFIG_SOFTMMU
6496/*
6497 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
6498 * Encoded as array of int_32s in the form:
6499 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
6500 * x -> AP encoding
6501 * y -> radix mode supported page size (encoded as a shift)
6502 */
6503static struct ppc_radix_page_info POWER10_radix_page_info = {
6504 .count = 4,
6505 .entries = {
6506 0x0000000c, /* 4K - enc: 0x0 */
6507 0xa0000010, /* 64K - enc: 0x5 */
6508 0x20000015, /* 2M - enc: 0x1 */
6509 0x4000001e /* 1G - enc: 0x2 */
6510 }
6511};
6512#endif /* CONFIG_SOFTMMU */
6513
6514static void init_proc_POWER10(CPUPPCState *env)
6515{
6516 /* Common Registers */
6517 init_proc_book3s_common(env);
a08eea67 6518 register_book3s_207_dbg_sprs(env);
7d37b274 6519
8f2e9d40
DHB		 6520 /* Common TCG PMU */
6521 init_tcg_pmu_power8(env);
6522
7d37b274 6523 /* POWER8 Specific Registers */
a08eea67
BL		 6524 register_book3s_ids_sprs(env);
6525 register_amr_sprs(env);
6526 register_iamr_sprs(env);
6527 register_book3s_purr_sprs(env);
6528 register_power5p_common_sprs(env);
6529 register_power5p_lpar_sprs(env);
6530 register_power5p_ear_sprs(env);
4e610064 6531 register_power5p_tb_sprs(env);
a08eea67
BL		 6532 register_power6_common_sprs(env);
6533 register_power6_dbg_sprs(env);
6534 register_power8_tce_address_control_sprs(env);
6535 register_power8_ids_sprs(env);
6536 register_power8_ebb_sprs(env);
6537 register_power8_fscr_sprs(env);
6538 register_power8_pmu_sup_sprs(env);
6539 register_power8_pmu_user_sprs(env);
6540 register_power8_tm_sprs(env);
6541 register_power8_pspb_sprs(env);
4e610064 6542 register_power8_dpdes_sprs(env);
a08eea67
BL		 6543 register_vtb_sprs(env);
6544 register_power8_ic_sprs(env);
6545 register_power8_book4_sprs(env);
6546 register_power8_rpr_sprs(env);
6547 register_power9_mmu_sprs(env);
903f84eb 6548 register_power10_hash_sprs(env);
7d37b274 6549
7d37b274
CLG		 6550 /* FIXME: Filter fields properly based on privilege level */
6551 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
6552 spr_read_generic, spr_write_generic,
6553 KVM_REG_PPC_PSSCR, 0);
6554
6555 /* env variables */
6556 env->dcache_line_size = 128;
6557 env->icache_line_size = 128;
6558
6559 /* Allocate hardware IRQ controller */
6560 init_excp_POWER10(env);
6561 ppcPOWER9_irq_init(env_archcpu(env));
6562}
6563
21d3a78e 6564static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
7d37b274 6565{
21d3a78e
NP		 6566 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK;
6567 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK;
6568
6569 if (!best) {
6570 if (base == CPU_POWERPC_POWER10_BASE) {
6571 return true;
6572 }
6573 }
6574
6575 if (base != pcc_base) {
6576 return false;
6577 }
6578
6579 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) {
6580 /* Major DD version matches to power10_v1.0 and power10_v2.0 */
7d37b274
CLG		 6581 return true;
6582 }
21d3a78e 6583
7d37b274
CLG		 6584 return false;
6585}
6586
6587static bool cpu_has_work_POWER10(CPUState *cs)
6588{
6589 PowerPCCPU *cpu = POWERPC_CPU(cs);
6590 CPUPPCState *env = &cpu->env;
6591
6592 if (cs->halted) {
6593 uint64_t psscr = env->spr[SPR_PSSCR];
6594
6595 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
6596 return false;
6597 }
6598
6599 /* If EC is clear, just return true on any pending interrupt */
6600 if (!(psscr & PSSCR_EC)) {
6601 return true;
6602 }
6603 /* External Exception */
6604 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
6605 (env->spr[SPR_LPCR] & LPCR_EEE)) {
6606 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
9de754d3
VC		 6607 if (!heic || !FIELD_EX64_HV(env->msr) ||
6608 FIELD_EX64(env->msr, MSR, PR)) {
7d37b274
CLG		 6609 return true;
6610 }
6611 }
6612 /* Decrementer Exception */
6613 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
6614 (env->spr[SPR_LPCR] & LPCR_DEE)) {
6615 return true;
6616 }
6617 /* Machine Check or Hypervisor Maintenance Exception */
6618 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
6619 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
6620 return true;
6621 }
6622 /* Privileged Doorbell Exception */
6623 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
6624 (env->spr[SPR_LPCR] & LPCR_PDEE)) {
6625 return true;
6626 }
6627 /* Hypervisor Doorbell Exception */
6628 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
6629 (env->spr[SPR_LPCR] & LPCR_HDEE)) {
6630 return true;
6631 }
6632 /* Hypervisor virtualization exception */
6633 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
6634 (env->spr[SPR_LPCR] & LPCR_HVEE)) {
6635 return true;
6636 }
6637 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
6638 return true;
6639 }
6640 return false;
6641 } else {
0939b8f8
VC		 6642 return FIELD_EX64(env->msr, MSR, EE) &&
6643 (cs->interrupt_request & CPU_INTERRUPT_HARD);
7d37b274
CLG		 6644 }
6645}
6646
6647POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
6648{
6649 DeviceClass *dc = DEVICE_CLASS(oc);
6650 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6651 CPUClass *cc = CPU_CLASS(oc);
6652
6653 dc->fw_name = "PowerPC,POWER10";
6654 dc->desc = "POWER10";
7d37b274
CLG		 6655 pcc->pvr_match = ppc_pvr_match_power10;
6656 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
6657 PCR_COMPAT_3_00;
6658 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
6659 PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
6660 pcc->init_proc = init_proc_POWER10;
6661 pcc->check_pow = check_pow_nocheck;
6662 cc->has_work = cpu_has_work_POWER10;
6663 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
6664 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6665 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6666 PPC_FLOAT_FRSQRTES |
6667 PPC_FLOAT_STFIWX |
6668 PPC_FLOAT_EXT |
6669 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6670 PPC_MEM_SYNC | PPC_MEM_EIEIO |
016b6e1d 6671 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7d37b274
CLG		 6672 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
6673 PPC_SEGMENT_64B | PPC_SLBI |
6674 PPC_POPCNTB | PPC_POPCNTWD |
6675 PPC_CILDST;
6676 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
6677 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
6678 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
6679 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
6680 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
6681 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
03abfd90 6682 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
4dc5f8ab 6683 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
7d37b274 6684 pcc->msr_mask = (1ull << MSR_SF) |
23513f81 6685 (1ull << MSR_HV) |
7d37b274
CLG		 6686 (1ull << MSR_TM) |
6687 (1ull << MSR_VR) |
6688 (1ull << MSR_VSX) |
6689 (1ull << MSR_EE) |
6690 (1ull << MSR_PR) |
6691 (1ull << MSR_FP) |
6692 (1ull << MSR_ME) |
6693 (1ull << MSR_FE0) |
6694 (1ull << MSR_SE) |
6695 (1ull << MSR_DE) |
6696 (1ull << MSR_FE1) |
6697 (1ull << MSR_IR) |
6698 (1ull << MSR_DR) |
6699 (1ull << MSR_PMM) |
6700 (1ull << MSR_RI) |
6701 (1ull << MSR_LE);
e232eccc
DG		 6702 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
6703 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
6704 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD |
6705 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
6706 LPCR_DEE | LPCR_OEE))
6707 | LPCR_MER | LPCR_GTSE | LPCR_TC |
6708 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE;
363fd548
CLG		 6709 /* DD2 adds an extra HAIL bit */
6710 pcc->lpcr_mask |= LPCR_HAIL;
6711
e232eccc 6712 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
7d37b274
CLG		 6713 pcc->mmu_model = POWERPC_MMU_3_00;
6714#if defined(CONFIG_SOFTMMU)
7d37b274
CLG		 6715 /* segment page size remain the same */
6716 pcc->hash64_opts = &ppc_hash64_opts_POWER7;
6717 pcc->radix_page_info = &POWER10_radix_page_info;
6718 pcc->lrg_decr_bits = 56;
6719#endif
526cdce7 6720 pcc->excp_model = POWERPC_EXCP_POWER10;
7d37b274
CLG		 6721 pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
6722 pcc->bfd_mach = bfd_mach_ppc64;
6723 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6724 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6725 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
98a6a365 6726 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV;
7d37b274
CLG		 6727 pcc->l1_dcache_size = 0x8000;
6728 pcc->l1_icache_size = 0x8000;
7d37b274
CLG		 6729}
6730
26a7f129 6731#if !defined(CONFIG_USER_ONLY)
da20aed1 6732void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
26a7f129
BH		 6733{
6734 CPUPPCState *env = &cpu->env;
6735
b7b0b1f1
DG		 6736 cpu->vhyp = vhyp;
6737
4550f6a5
DG		 6738 /*
6739 * With a virtual hypervisor mode we never allow the CPU to go
6740 * hypervisor mode itself
26a7f129 6741 */
4550f6a5 6742 env->msr_mask &= ~MSR_HVB;
26a7f129
BH		 6743}
6744
6745#endif /* !defined(CONFIG_USER_ONLY) */
6746
c364946d 6747#endif /* defined(TARGET_PPC64) */
fd5ed418 6748
a750fc0b 6749/*****************************************************************************/
60b14d95 6750/* Generic CPU instantiation routine */
cfe34f44 6751static void init_ppc_proc(PowerPCCPU *cpu)
a750fc0b 6752{
cfe34f44
AF		 6753 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6754 CPUPPCState *env = &cpu->env;
a750fc0b 6755#if !defined(CONFIG_USER_ONLY)
e1833e1f
JM		 6756 int i;
6757
e1833e1f 6758 /* Set all exception vectors to an invalid address */
1d28b5f6 6759 for (i = 0; i < POWERPC_EXCP_NB; i++) {
e1833e1f 6760 env->excp_vectors[i] = (target_ulong)(-1ULL);
1d28b5f6 6761 }
e1833e1f
JM		 6762 env->ivor_mask = 0x00000000;
6763 env->ivpr_mask = 0x00000000;
a750fc0b
JM		 6764 /* Default MMU definitions */
6765 env->nb_BATs = 0;
6766 env->nb_tlb = 0;
6767 env->nb_ways = 0;
1c53accc 6768 env->tlb_type = TLB_NONE;
f2e63a42 6769#endif
a750fc0b 6770 /* Register SPR common to all PowerPC implementations */
e78280a2
FR		 6771 register_generic_sprs(cpu);
6772
a750fc0b 6773 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
cfe34f44 6774 (*pcc->init_proc)(env);
2cf3eb6d 6775
707c7c2e
FR		 6776#if !defined(CONFIG_USER_ONLY)
6777 ppc_gdb_gen_spr_xml(cpu);
6778#endif
6779
25ba3a68
JM		 6780 /* MSR bits & flags consistency checks */
6781 if (env->msr_mask & (1 << 25)) {
6782 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6783 case POWERPC_FLAG_SPE:
6784 case POWERPC_FLAG_VRE:
6785 break;
6786 default:
6787 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6788 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
6789 exit(1);
6790 }
6791 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
6792 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6793 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
6794 exit(1);
6795 }
6796 if (env->msr_mask & (1 << 17)) {
6797 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6798 case POWERPC_FLAG_TGPR:
6799 case POWERPC_FLAG_CE:
6800 break;
6801 default:
6802 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6803 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
6804 exit(1);
6805 }
6806 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
6807 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6808 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
6809 exit(1);
6810 }
6811 if (env->msr_mask & (1 << 10)) {
6812 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6813 POWERPC_FLAG_UBLE)) {
6814 case POWERPC_FLAG_SE:
6815 case POWERPC_FLAG_DWE:
6816 case POWERPC_FLAG_UBLE:
6817 break;
6818 default:
6819 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6820 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
6821 "POWERPC_FLAG_UBLE\n");
6822 exit(1);
6823 }
6824 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
6825 POWERPC_FLAG_UBLE)) {
6826 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6827 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
6828 "POWERPC_FLAG_UBLE\n");
6829 exit(1);
6830 }
6831 if (env->msr_mask & (1 << 9)) {
6832 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6833 case POWERPC_FLAG_BE:
6834 case POWERPC_FLAG_DE:
6835 break;
6836 default:
6837 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6838 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
6839 exit(1);
6840 }
6841 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
6842 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6843 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
6844 exit(1);
6845 }
6846 if (env->msr_mask & (1 << 2)) {
6847 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6848 case POWERPC_FLAG_PX:
6849 case POWERPC_FLAG_PMM:
6850 break;
6851 default:
6852 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6853 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
6854 exit(1);
6855 }
6856 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
6857 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
6858 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
6859 exit(1);
6860 }
005b69fd 6861 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) {
4018bae9
JM		 6862 fprintf(stderr, "PowerPC flags inconsistency\n"
6863 "Should define the time-base and decrementer clock source\n");
6864 exit(1);
6865 }
a750fc0b 6866 /* Allocate TLBs buffer when needed */
f2e63a42 6867#if !defined(CONFIG_USER_ONLY)
a750fc0b
JM		 6868 if (env->nb_tlb != 0) {
6869 int nb_tlb = env->nb_tlb;
1d28b5f6 6870 if (env->id_tlbs != 0) {
a750fc0b 6871 nb_tlb *= 2;
1d28b5f6 6872 }
1c53accc
AG		 6873 switch (env->tlb_type) {
6874 case TLB_6XX:
cc226c06 6875 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb);
1c53accc
AG		 6876 break;
6877 case TLB_EMB:
cc226c06 6878 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb);
1c53accc
AG		 6879 break;
6880 case TLB_MAS:
cc226c06 6881 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb);
1c53accc
AG		 6882 break;
6883 }
a750fc0b
JM		 6884 /* Pre-compute some useful values */
6885 env->tlb_per_way = env->nb_tlb / env->nb_ways;
6886 }
a750fc0b 6887#endif
2f462816 6888 if (env->check_pow == NULL) {
b62e39b4 6889 warn_report("no power management check handler registered."
8297be80 6890 " Attempt QEMU to crash very soon !");
2f462816 6891 }
a750fc0b
JM		 6892}
6893
a750fc0b 6894
e850da55 6895static void ppc_cpu_realize(DeviceState *dev, Error **errp)
a750fc0b 6896{
22169d41 6897 CPUState *cs = CPU(dev);
4776ce60 6898 PowerPCCPU *cpu = POWERPC_CPU(dev);
2985b86b 6899 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
2985b86b 6900 Error *local_err = NULL;
fe828a4d 6901
ce5b1bbf 6902 cpu_exec_realizefn(cs, &local_err);
6dd0f834
BR		 6903 if (local_err != NULL) {
6904 error_propagate(errp, local_err);
6905 return;
6906 }
7cca3e46
SB		 6907 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) {
6908 cpu->vcpu_id = cs->cpu_index;
41264b38 6909 }
4656e1f0 6910
0ce470cd 6911 if (tcg_enabled()) {
55e5c285 6912 if (ppc_fixup_cpu(cpu) != 0) {
2985b86b 6913 error_setg(errp, "Unable to emulate selected CPU with TCG");
fd356563 6914 goto unrealize;
12b1143b
DG		 6915 }
6916 }
6917
2985b86b
AF		 6918 create_ppc_opcodes(cpu, &local_err);
6919 if (local_err != NULL) {
6920 error_propagate(errp, local_err);
fd356563 6921 goto unrealize;
2985b86b 6922 }
cfe34f44 6923 init_ppc_proc(cpu);
24951522 6924
35a5d74e 6925 ppc_gdb_init(cs, pcc);
14a10fc3
AF		 6926 qemu_init_vcpu(cs);
6927
4776ce60
AF		 6928 pcc->parent_realize(dev, errp);
6929
fd356563
BR		 6930 return;
6931
6932unrealize:
6933 cpu_exec_unrealizefn(cs);
a750fc0b 6934}
3fc6c082 6935
b69c3c21 6936static void ppc_cpu_unrealize(DeviceState *dev)
b048960f
AF		 6937{
6938 PowerPCCPU *cpu = POWERPC_CPU(dev);
7bbc124e 6939 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
b048960f 6940
b69c3c21 6941 pcc->parent_unrealize(dev);
6dd0f834 6942
f1023d21
GK		 6943 cpu_remove_sync(CPU(cpu));
6944
7468e2c8 6945 destroy_ppc_opcodes(cpu);
b048960f
AF		 6946}
6947
2985b86b 6948static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
f0ad8c34 6949{
2985b86b
AF		 6950 ObjectClass *oc = (ObjectClass *)a;
6951 uint32_t pvr = *(uint32_t *)b;
6952 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
6953
6954 /* -cpu host does a PVR lookup during construction */
6955 if (unlikely(strcmp(object_class_get_name(oc),
6956 TYPE_HOST_POWERPC_CPU) == 0)) {
6957 return -1;
f0ad8c34 6958 }
f0ad8c34 6959
cfe34f44 6960 return pcc->pvr == pvr ? 0 : -1;
f0ad8c34
AG		 6961}
6962
2985b86b 6963PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
3fc6c082 6964{
2985b86b
AF		 6965 GSList *list, *item;
6966 PowerPCCPUClass *pcc = NULL;
be40edcd 6967
2985b86b
AF		 6968 list = object_class_get_list(TYPE_POWERPC_CPU, false);
6969 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
6970 if (item != NULL) {
6971 pcc = POWERPC_CPU_CLASS(item->data);
3fc6c082 6972 }
2985b86b
AF		 6973 g_slist_free(list);
6974
6975 return pcc;
6976}
6977
3bc9ccc0
AK		 6978static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
6979{
6980 ObjectClass *oc = (ObjectClass *)a;
6981 uint32_t pvr = *(uint32_t *)b;
6982 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
3bc9ccc0
AK		 6983
6984 /* -cpu host does a PVR lookup during construction */
6985 if (unlikely(strcmp(object_class_get_name(oc),
6986 TYPE_HOST_POWERPC_CPU) == 0)) {
6987 return -1;
6988 }
6989
21d3a78e 6990 if (pcc->pvr_match(pcc, pvr, true)) {
03ae4133
AK		 6991 return 0;
6992 }
3bc9ccc0 6993
03ae4133 6994 return -1;
3bc9ccc0
AK		 6995}
6996
6997PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
6998{
6999 GSList *list, *item;
7000 PowerPCCPUClass *pcc = NULL;
7001
7002 list = object_class_get_list(TYPE_POWERPC_CPU, true);
7003 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
7004 if (item != NULL) {
7005 pcc = POWERPC_CPU_CLASS(item->data);
7006 }
7007 g_slist_free(list);
7008
7009 return pcc;
7010}
7011
2e9c10eb 7012static const char *ppc_cpu_lookup_alias(const char *alias)
b918f885
IM		 7013{
7014 int ai;
7015
7016 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) {
7017 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) {
7018 return ppc_cpu_aliases[ai].model;
7019 }
7020 }
7021
7022 return NULL;
7023}
7024
2985b86b 7025static ObjectClass *ppc_cpu_class_by_name(const char *name)
ee4e83ed 7026{
03c9141d
IM		 7027 char *cpu_model, *typename;
7028 ObjectClass *oc;
b55266b5 7029 const char *p;
b376db77
IM		 7030 unsigned long pvr;
7031
1d28b5f6
DG		 7032 /*
7033 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl:
7034 * 0x prefix if present)
b376db77
IM		 7035 */
7036 if (!qemu_strtoul(name, &p, 16, &pvr)) {
7037 int len = p - name;
7038 len = (len == 10) && (name[1] == 'x') ? len - 2 : len;
7039 if ((len == 8) && (*p == '\0')) {
7040 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr));
f0ad8c34 7041 }
2985b86b 7042 }
f0ad8c34 7043
c7e89de1
MOA		 7044 /*
7045 * All ppc CPUs represent hardware that exists in the real world, i.e.: we
7046 * do not have a "max" CPU with all possible emulated features enabled.
7047 * Return the default CPU type for the machine because that has greater
7048 * chance of being useful as the "max" CPU.
7049 */
7050#if !defined(CONFIG_USER_ONLY)
7051 if (strcmp(name, "max") == 0) {
7052 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
7053 if (mc) {
7054 return object_class_by_name(mc->default_cpu_type);
7055 }
7056 }
7057#endif
7058
03c9141d
IM		 7059 cpu_model = g_ascii_strdown(name, -1);
7060 p = ppc_cpu_lookup_alias(cpu_model);
7061 if (p) {
7062 g_free(cpu_model);
7063 cpu_model = g_strdup(p);
3fc6c082 7064 }
ee4e83ed 7065
03c9141d
IM		 7066 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model);
7067 oc = object_class_by_name(typename);
7068 g_free(typename);
7069 g_free(cpu_model);
fdf8a960 7070
a69dc537 7071 return oc;
3fc6c082
FB		 7072}
7073
e9edd931
TH		 7074PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc)
7075{
7076 ObjectClass *oc = OBJECT_CLASS(pcc);
7077
7078 while (oc && !object_class_is_abstract(oc)) {
7079 oc = object_class_get_parent(oc);
7080 }
7081 assert(oc);
7082
7083 return POWERPC_CPU_CLASS(oc);
7084}
7085
2985b86b
AF		 7086/* Sort by PVR, ordering special case "host" last. */
7087static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
7088{
7089 ObjectClass *oc_a = (ObjectClass *)a;
7090 ObjectClass *oc_b = (ObjectClass *)b;
7091 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
7092 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
7093 const char *name_a = object_class_get_name(oc_a);
7094 const char *name_b = object_class_get_name(oc_b);
7095
7096 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
7097 return 1;
7098 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
7099 return -1;
7100 } else {
7101 /* Avoid an integer overflow during subtraction */
cfe34f44 7102 if (pcc_a->pvr < pcc_b->pvr) {
2985b86b 7103 return -1;
cfe34f44 7104 } else if (pcc_a->pvr > pcc_b->pvr) {
2985b86b
AF		 7105 return 1;
7106 } else {
7107 return 0;
7108 }
7109 }
7110}
7111
7112static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
7113{
7114 ObjectClass *oc = data;
2985b86b 7115 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
e9edd931 7116 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc));
de400129
AF		 7117 const char *typename = object_class_get_name(oc);
7118 char *name;
55d3d1a4 7119 int i;
2985b86b 7120
5ba4576b
AF		 7121 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
7122 return;
7123 }
4d7fb187 7124
de400129 7125 name = g_strndup(typename,
c9137065 7126 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
0442428a 7127 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr);
e9a96075 7128 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9761ad75 7129 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
2527cb91 7130 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model);
55d3d1a4
AF		 7131
7132 if (alias_oc != oc) {
7133 continue;
7134 }
e9edd931
TH		 7135 /*
7136 * If running with KVM, we might update the family alias later, so
7137 * avoid printing the wrong alias here and use "preferred" instead
7138 */
7139 if (strcmp(alias->alias, family->desc) == 0) {
0442428a
MA		 7140 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n",
7141 alias->alias, family->desc);
e9edd931 7142 } else {
0442428a
MA		 7143 qemu_printf("PowerPC %-16s (alias for %s)\n",
7144 alias->alias, name);
e9edd931 7145 }
55d3d1a4 7146 }
de400129 7147 g_free(name);
2985b86b
AF		 7148}
7149
0442428a 7150void ppc_cpu_list(void)
2985b86b 7151{
2985b86b
AF		 7152 GSList *list;
7153
7154 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7155 list = g_slist_sort(list, ppc_cpu_list_compare);
0442428a 7156 g_slist_foreach(list, ppc_cpu_list_entry, NULL);
2985b86b 7157 g_slist_free(list);
fd5ed418 7158
5ba4576b 7159#ifdef CONFIG_KVM
0442428a 7160 qemu_printf("\n");
61848717 7161 qemu_printf("PowerPC %s\n", "host");
5ba4576b 7162#endif
2985b86b
AF		 7163}
7164
7165static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
7166{
7167 ObjectClass *oc = data;
7168 CpuDefinitionInfoList **first = user_data;
de400129 7169 const char *typename;
2985b86b
AF		 7170 CpuDefinitionInfo *info;
7171
de400129 7172 typename = object_class_get_name(oc);
2985b86b 7173 info = g_malloc0(sizeof(*info));
de400129 7174 info->name = g_strndup(typename,
c9137065 7175 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX));
2985b86b 7176
54aa3de7 7177 QAPI_LIST_PREPEND(*first, info);
3fc6c082 7178}
1d0cb67d 7179
25a9d6ca 7180CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
70b7660a
AL		 7181{
7182 CpuDefinitionInfoList *cpu_list = NULL;
2985b86b 7183 GSList *list;
35e21d3f 7184 int i;
70b7660a 7185
2985b86b
AF		 7186 list = object_class_get_list(TYPE_POWERPC_CPU, false);
7187 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
7188 g_slist_free(list);
70b7660a 7189
e9a96075 7190 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9761ad75 7191 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
35e21d3f 7192 ObjectClass *oc;
35e21d3f
AF		 7193 CpuDefinitionInfo *info;
7194
2527cb91 7195 oc = ppc_cpu_class_by_name(alias->model);
35e21d3f
AF		 7196 if (oc == NULL) {
7197 continue;
7198 }
7199
7200 info = g_malloc0(sizeof(*info));
7201 info->name = g_strdup(alias->alias);
8ed877b7 7202 info->q_typename = g_strdup(object_class_get_name(oc));
35e21d3f 7203
54aa3de7 7204 QAPI_LIST_PREPEND(cpu_list, info);
35e21d3f
AF		 7205 }
7206
2985b86b
AF		 7207 return cpu_list;
7208}
70b7660a 7209
f45748f1
AF		 7210static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
7211{
7212 PowerPCCPU *cpu = POWERPC_CPU(cs);
7213
7214 cpu->env.nip = value;
7215}
7216
e4fdf9df
RH		 7217static vaddr ppc_cpu_get_pc(CPUState *cs)
7218{
7219 PowerPCCPU *cpu = POWERPC_CPU(cs);
7220
7221 return cpu->env.nip;
7222}
7223
8c2e1b00
AF		 7224static bool ppc_cpu_has_work(CPUState *cs)
7225{
7226 PowerPCCPU *cpu = POWERPC_CPU(cs);
7227 CPUPPCState *env = &cpu->env;
7228
0939b8f8
VC		 7229 return FIELD_EX64(env->msr, MSR, EE) &&
7230 (cs->interrupt_request & CPU_INTERRUPT_HARD);
8c2e1b00
AF		 7231}
7232
781c67ca 7233static void ppc_cpu_reset(DeviceState *dev)
1d0cb67d 7234{
781c67ca 7235 CPUState *s = CPU(dev);
1d0cb67d
AF		 7236 PowerPCCPU *cpu = POWERPC_CPU(s);
7237 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7238 CPUPPCState *env = &cpu->env;
a1389542 7239 target_ulong msr;
d197fdbc 7240 int i;
a1389542 7241
781c67ca 7242 pcc->parent_reset(dev);
1d0cb67d 7243
a1389542 7244 msr = (target_ulong)0;
932ccbdd 7245 msr |= (target_ulong)MSR_HVB;
a1389542
AF		 7246 msr |= (target_ulong)1 << MSR_EP;
7247#if defined(DO_SINGLE_STEP) && 0
7248 /* Single step trace mode */
7249 msr |= (target_ulong)1 << MSR_SE;
7250 msr |= (target_ulong)1 << MSR_BE;
7251#endif
7252#if defined(CONFIG_USER_ONLY)
7253 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
e82c42b7
RH		 7254 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */
7255 msr |= (target_ulong)1 << MSR_FE1;
a1389542 7256 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
5b274ed7 7257 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */
a1389542
AF		 7258 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
7259 msr |= (target_ulong)1 << MSR_PR;
cdcdda27
AK		 7260#if defined(TARGET_PPC64)
7261 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */
7262#endif
ee3eb3a7 7263#if !TARGET_BIG_ENDIAN
e22c357b 7264 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
a74029f6
RH		 7265 if (!((env->msr_mask >> MSR_LE) & 1)) {
7266 fprintf(stderr, "Selected CPU does not support little-endian.\n");
7267 exit(1);
7268 }
e22c357b 7269#endif
a1389542 7270#endif
2cf3eb6d 7271
a1389542 7272#if defined(TARGET_PPC64)
d57d72a8 7273 if (mmu_is_64bit(env->mmu_model)) {
8b9f2118 7274 msr |= (1ULL << MSR_SF);
a1389542
AF		 7275 }
7276#endif
2cf3eb6d
FC		 7277
7278 hreg_store_msr(env, msr, 1);
7279
7280#if !defined(CONFIG_USER_ONLY)
7281 env->nip = env->hreset_vector | env->excp_prefix;
33edcde7
DHB		 7282
7283 if (tcg_enabled()) {
7284 if (env->mmu_model != POWERPC_MMU_REAL) {
7285 ppc_tlb_invalidate_all(env);
7286 }
7287 pmu_update_summaries(env);
2cf3eb6d 7288 }
609b1c86
FB		 7289
7290 /* clean any pending stop state */
7291 env->resume_as_sreset = 0;
2cf3eb6d 7292#endif
a1389542
AF		 7293 hreg_compute_hflags(env);
7294 env->reserve_addr = (target_ulong)-1ULL;
7295 /* Be sure no exception or interrupt is pending */
7296 env->pending_interrupts = 0;
27103424 7297 s->exception_index = POWERPC_EXCP_NONE;
a1389542 7298 env->error_code = 0;
40177438 7299 ppc_irq_reset(cpu);
2b15811c 7300
cbc65a8f
RH		 7301 /* tininess for underflow is detected before rounding */
7302 set_float_detect_tininess(float_tininess_before_rounding,
7303 &env->fp_status);
7304
d197fdbc
AK		 7305 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
7306 ppc_spr_t *spr = &env->spr_cb[i];
7307
7308 if (!spr->name) {
7309 continue;
7310 }
7311 env->spr[i] = spr->default_value;
7312 }
1d0cb67d
AF		 7313}
7314
7826c2b2 7315#ifndef CONFIG_USER_ONLY
48c1a3e3 7316
7826c2b2
GK		 7317static bool ppc_cpu_is_big_endian(CPUState *cs)
7318{
7319 PowerPCCPU *cpu = POWERPC_CPU(cs);
7320 CPUPPCState *env = &cpu->env;
7321
7322 cpu_synchronize_state(cs);
7323
1922322c 7324 return !FIELD_EX64(env->msr, MSR, LE);
7826c2b2 7325}
03ef074c 7326
48c1a3e3 7327#ifdef CONFIG_TCG
03ef074c
NP		 7328static void ppc_cpu_exec_enter(CPUState *cs)
7329{
7330 PowerPCCPU *cpu = POWERPC_CPU(cs);
7331
7332 if (cpu->vhyp) {
7333 PPCVirtualHypervisorClass *vhc =
7334 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7335 vhc->cpu_exec_enter(cpu->vhyp, cpu);
7336 }
7337}
7338
7339static void ppc_cpu_exec_exit(CPUState *cs)
7340{
7341 PowerPCCPU *cpu = POWERPC_CPU(cs);
7342
7343 if (cpu->vhyp) {
7344 PPCVirtualHypervisorClass *vhc =
7345 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
7346 vhc->cpu_exec_exit(cpu->vhyp, cpu);
7347 }
7348}
48c1a3e3
EH		 7349#endif /* CONFIG_TCG */
7350
7351#endif /* !CONFIG_USER_ONLY */
7826c2b2 7352
e850da55 7353static void ppc_cpu_instance_init(Object *obj)
6cca7ad6
AF		 7354{
7355 PowerPCCPU *cpu = POWERPC_CPU(obj);
2985b86b 7356 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
6cca7ad6
AF		 7357 CPUPPCState *env = &cpu->env;
7358
7506ed90 7359 cpu_set_cpustate_pointers(cpu);
7cca3e46 7360 cpu->vcpu_id = UNASSIGNED_CPU_INDEX;
2985b86b 7361
cfe34f44
AF		 7362 env->msr_mask = pcc->msr_mask;
7363 env->mmu_model = pcc->mmu_model;
7364 env->excp_model = pcc->excp_model;
7365 env->bus_model = pcc->bus_model;
7366 env->insns_flags = pcc->insns_flags;
7367 env->insns_flags2 = pcc->insns_flags2;
7368 env->flags = pcc->flags;
7369 env->bfd_mach = pcc->bfd_mach;
7370 env->check_pow = pcc->check_pow;
2985b86b 7371
1d28b5f6
DG		 7372 /*
7373 * Mark HV mode as supported if the CPU has an MSR_HV bit in the
7374 * msr_mask. The mask can later be cleared by PAPR mode but the hv
7375 * mode support will remain, thus enforcing that we cannot use
7376 * priv. instructions in guest in PAPR mode. For 970 we currently
7377 * simply don't set HV in msr_mask thus simulating an "Apple mode"
7378 * 970. If we ever want to support 970 HV mode, we'll have to add
7379 * a processor attribute of some sort.
932ccbdd
BH		 7380 */
7381#if !defined(CONFIG_USER_ONLY)
7382 env->has_hv_mode = !!(env->msr_mask & MSR_HVB);
7383#endif
7384
a059471d
DG		 7385 ppc_hash64_init(cpu);
7386}
7387
7388static void ppc_cpu_instance_finalize(Object *obj)
7389{
7390 PowerPCCPU *cpu = POWERPC_CPU(obj);
7391
7392 ppc_hash64_finalize(cpu);
6cca7ad6
AF		 7393}
7394
21d3a78e 7395static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best)
03ae4133
AK		 7396{
7397 return pcc->pvr == pvr;
7398}
7399
0eea8cdd
RH		 7400static void ppc_disas_set_info(CPUState *cs, disassemble_info *info)
7401{
7402 PowerPCCPU *cpu = POWERPC_CPU(cs);
7403 CPUPPCState *env = &cpu->env;
7404
7405 if ((env->hflags >> MSR_LE) & 1) {
7406 info->endian = BFD_ENDIAN_LITTLE;
7407 }
7408 info->mach = env->bfd_mach;
7409 if (!env->bfd_mach) {
7410#ifdef TARGET_PPC64
7411 info->mach = bfd_mach_ppc64;
7412#else
7413 info->mach = bfd_mach_ppc;
7414#endif
7415 }
ac226899
RH		 7416
7417 info->cap_arch = CS_ARCH_PPC;
7418#ifdef TARGET_PPC64
7419 info->cap_mode = CS_MODE_64;
7420#endif
0eea8cdd
RH		 7421}
7422
146c11f1
DG		 7423static Property ppc_cpu_properties[] = {
7424 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
d5fc133e
DG		 7425 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
7426 false),
d8c0c7af 7427 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration,
67d7d66f 7428 false),
146c11f1
DG		 7429 DEFINE_PROP_END_OF_LIST(),
7430};
7431
8b80bd28
PMD		 7432#ifndef CONFIG_USER_ONLY
7433#include "hw/core/sysemu-cpu-ops.h"
7434
7435static const struct SysemuCPUOps ppc_sysemu_ops = {
08928c6d 7436 .get_phys_page_debug = ppc_cpu_get_phys_page_debug,
715e3c1a
PMD		 7437 .write_elf32_note = ppc32_cpu_write_elf32_note,
7438 .write_elf64_note = ppc64_cpu_write_elf64_note,
da383e02 7439 .virtio_is_big_endian = ppc_cpu_is_big_endian,
feece4d0 7440 .legacy_vmsd = &vmstate_ppc_cpu,
8b80bd28
PMD		 7441};
7442#endif
7443
78271684
CF		 7444#ifdef CONFIG_TCG
7445#include "hw/core/tcg-cpu-ops.h"
7446
11906557 7447static const struct TCGCPUOps ppc_tcg_ops = {
78271684 7448 .initialize = ppc_translate_init,
78271684 7449
1db8af5c
RH		 7450#ifdef CONFIG_USER_ONLY
7451 .record_sigsegv = ppc_cpu_record_sigsegv,
7452#else
7453 .tlb_fill = ppc_cpu_tlb_fill,
f725245c 7454 .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
78271684
CF		 7455 .do_interrupt = ppc_cpu_do_interrupt,
7456 .cpu_exec_enter = ppc_cpu_exec_enter,
7457 .cpu_exec_exit = ppc_cpu_exec_exit,
7458 .do_unaligned_access = ppc_cpu_do_unaligned_access,
7459#endif /* !CONFIG_USER_ONLY */
7460};
7461#endif /* CONFIG_TCG */
7462
1d0cb67d
AF		 7463static void ppc_cpu_class_init(ObjectClass *oc, void *data)
7464{
7465 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7466 CPUClass *cc = CPU_CLASS(oc);
4776ce60
AF		 7467 DeviceClass *dc = DEVICE_CLASS(oc);
7468
e850da55 7469 device_class_set_parent_realize(dc, ppc_cpu_realize,
bf853881 7470 &pcc->parent_realize);
e850da55 7471 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
bf853881 7472 &pcc->parent_unrealize);
03ae4133 7473 pcc->pvr_match = ppc_pvr_match_default;
4f67d30b 7474 device_class_set_props(dc, ppc_cpu_properties);
1d0cb67d 7475
781c67ca 7476 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
2b8c2754
AF		 7477
7478 cc->class_by_name = ppc_cpu_class_by_name;
8c2e1b00 7479 cc->has_work = ppc_cpu_has_work;
878096ee 7480 cc->dump_state = ppc_cpu_dump_state;
f45748f1 7481 cc->set_pc = ppc_cpu_set_pc;
e4fdf9df 7482 cc->get_pc = ppc_cpu_get_pc;
5b50e790
AF		 7483 cc->gdb_read_register = ppc_cpu_gdb_read_register;
7484 cc->gdb_write_register = ppc_cpu_gdb_write_register;
351bc97e 7485#ifndef CONFIG_USER_ONLY
8b80bd28 7486 cc->sysemu_ops = &ppc_sysemu_ops;
00b941e5 7487#endif
a0e372f0
AF		 7488
7489 cc->gdb_num_core_regs = 71;
707c7c2e
FR		 7490#ifndef CONFIG_USER_ONLY
7491 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml;
7492#endif
b3cad3ab
AG		 7493#ifdef USE_APPLE_GDB
7494 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple;
7495 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple;
7496 cc->gdb_num_core_regs = 71 + 32;
7497#endif
7498
b3820e6c 7499 cc->gdb_arch_name = ppc_gdb_arch_name;
5b24c641
AF		 7500#if defined(TARGET_PPC64)
7501 cc->gdb_core_xml_file = "power64-core.xml";
7502#else
7503 cc->gdb_core_xml_file = "power-core.xml";
7826c2b2 7504#endif
0eea8cdd 7505 cc->disas_set_info = ppc_disas_set_info;
1d28b5f6 7506
3bbf37f2 7507 dc->fw_name = "PowerPC,UNKNOWN";
78271684
CF		 7508
7509#ifdef CONFIG_TCG
7510 cc->tcg_ops = &ppc_tcg_ops;
7511#endif /* CONFIG_TCG */
1d0cb67d
AF		 7512}
7513
7514static const TypeInfo ppc_cpu_type_info = {
7515 .name = TYPE_POWERPC_CPU,
7516 .parent = TYPE_CPU,
7517 .instance_size = sizeof(PowerPCCPU),
1b49d144 7518 .instance_align = __alignof__(PowerPCCPU),
e850da55 7519 .instance_init = ppc_cpu_instance_init,
a059471d 7520 .instance_finalize = ppc_cpu_instance_finalize,
2985b86b 7521 .abstract = true,
1d0cb67d
AF		 7522 .class_size = sizeof(PowerPCCPUClass),
7523 .class_init = ppc_cpu_class_init,
7524};
7525
e89aac1a 7526#ifndef CONFIG_USER_ONLY
1d1be34d
DG		 7527static const TypeInfo ppc_vhyp_type_info = {
7528 .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
7529 .parent = TYPE_INTERFACE,
7530 .class_size = sizeof(PPCVirtualHypervisorClass),
7531};
e89aac1a 7532#endif
1d1be34d 7533
1d0cb67d
AF		 7534static void ppc_cpu_register_types(void)
7535{
7536 type_register_static(&ppc_cpu_type_info);
e89aac1a 7537#ifndef CONFIG_USER_ONLY
1d1be34d 7538 type_register_static(&ppc_vhyp_type_info);
e89aac1a 7539#endif
1d0cb67d
AF		 7540}
7541
47334e17
BL		 7542void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
7543{
7544#define RGPL 4
7545#define RFPL 4
7546
7547 PowerPCCPU *cpu = POWERPC_CPU(cs);
7548 CPUPPCState *env = &cpu->env;
7549 int i;
7550
7551 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
7552 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
7553 env->nip, env->lr, env->ctr, cpu_read_xer(env),
7554 cs->cpu_index);
7555 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
7556 "%08x iidx %d didx %d\n",
7557 env->msr, env->spr[SPR_HID0], env->hflags,
7558 cpu_mmu_index(env, true), cpu_mmu_index(env, false));
47334e17 7559#if !defined(CONFIG_USER_ONLY)
3778aa97
MF		 7560 if (env->tb_env) {
7561 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
7562 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
7563 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
7564 }
7565#else
7566 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
7567 cpu_ppc_load_tbl(env));
47334e17
BL		 7568#endif
7569 for (i = 0; i < 32; i++) {
7570 if ((i & (RGPL - 1)) == 0) {
7571 qemu_fprintf(f, "GPR%02d", i);
7572 }
7573 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
7574 if ((i & (RGPL - 1)) == (RGPL - 1)) {
7575 qemu_fprintf(f, "\n");
7576 }
7577 }
7578 qemu_fprintf(f, "CR ");
7579 for (i = 0; i < 8; i++)
7580 qemu_fprintf(f, "%01x", env->crf[i]);
7581 qemu_fprintf(f, " [");
7582 for (i = 0; i < 8; i++) {
7583 char a = '-';
7584 if (env->crf[i] & 0x08) {
7585 a = 'L';
7586 } else if (env->crf[i] & 0x04) {
7587 a = 'G';
7588 } else if (env->crf[i] & 0x02) {
7589 a = 'E';
7590 }
7591 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
7592 }
7593 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
7594 env->reserve_addr);
7595
7596 if (flags & CPU_DUMP_FPU) {
7597 for (i = 0; i < 32; i++) {
7598 if ((i & (RFPL - 1)) == 0) {
7599 qemu_fprintf(f, "FPR%02d", i);
7600 }
7601 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
7602 if ((i & (RFPL - 1)) == (RFPL - 1)) {
7603 qemu_fprintf(f, "\n");
7604 }
7605 }
7606 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
7607 }
7608
7609#if !defined(CONFIG_USER_ONLY)
7610 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
7611 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
7612 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
7613 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
7614
7615 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
7616 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
7617 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
7618 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
7619
7620 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
7621 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
7622 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
7623 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
7624
fbe08667 7625 switch (env->excp_model) {
47334e17 7626#if defined(TARGET_PPC64)
fbe08667
CLG		 7627 case POWERPC_EXCP_POWER7:
7628 case POWERPC_EXCP_POWER8:
7629 case POWERPC_EXCP_POWER9:
7630 case POWERPC_EXCP_POWER10:
47334e17
BL		 7631 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
7632 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
fbe08667 7633 break;
47334e17 7634#endif
fbe08667 7635 case POWERPC_EXCP_BOOKE:
47334e17
BL		 7636 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
7637 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
7638 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
7639 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
7640
7641 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7642 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7643 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
7644 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
7645
7646 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
7647 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
7648 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
7649 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
7650
7651 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
7652 " EPR " TARGET_FMT_lx "\n",
7653 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
7654 env->spr[SPR_BOOKE_EPR]);
7655
7656 /* FSL-specific */
7657 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
7658 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
7659 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
7660 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
7661
7662 /*
7663 * IVORs are left out as they are large and do not change often --
7664 * they can be read with "p $ivor0", "p $ivor1", etc.
7665 */
fbe08667
CLG		 7666 break;
7667 case POWERPC_EXCP_40x:
7668 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
7669 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
7670 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
7671 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]);
7672
7673 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx
7674 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7675 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2],
7676 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]);
7677 break;
7678 default:
7679 break;
47334e17
BL		 7680 }
7681
7682#if defined(TARGET_PPC64)
7683 if (env->flags & POWERPC_FLAG_CFAR) {
7684 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
7685 }
7686#endif
7687
7688 if (env->spr_cb[SPR_LPCR].name) {
7689 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
7690 }
7691
7692 switch (env->mmu_model) {
7693 case POWERPC_MMU_32B:
47334e17 7694 case POWERPC_MMU_SOFT_6xx:
47334e17
BL		 7695#if defined(TARGET_PPC64)
7696 case POWERPC_MMU_64B:
7697 case POWERPC_MMU_2_03:
7698 case POWERPC_MMU_2_06:
7699 case POWERPC_MMU_2_07:
7700 case POWERPC_MMU_3_00:
7701#endif
7702 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
7703 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
7704 }
7705 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
7706 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
7707 }
7708 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
7709 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
7710 break;
7711 case POWERPC_MMU_BOOKE206:
7712 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
7713 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
7714 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
7715 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
7716
7717 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
7718 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
7719 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
7720 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
7721
7722 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
7723 " TLB1CFG " TARGET_FMT_lx "\n",
7724 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
7725 env->spr[SPR_BOOKE_TLB1CFG]);
7726 break;
7727 default:
7728 break;
7729 }
7730#endif
7731
7732#undef RGPL
7733#undef RFPL
7734}
1d0cb67d 7735type_init(ppc_cpu_register_types)
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