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ad71ed68 BS |
1 | /* |
2 | * PowerPC exception emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
f1c29ebc | 20 | #include "qemu/main-loop.h" |
ad71ed68 | 21 | #include "cpu.h" |
2ef6175a | 22 | #include "exec/helper-proto.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
f08b6170 | 24 | #include "exec/cpu_ldst.h" |
0f3110fa | 25 | #include "internal.h" |
ad71ed68 BS |
26 | #include "helper_regs.h" |
27 | ||
47733729 DG |
28 | /* #define DEBUG_OP */ |
29 | /* #define DEBUG_SOFTWARE_TLB */ | |
30 | /* #define DEBUG_EXCEPTIONS */ | |
ad71ed68 | 31 | |
c79c73f6 BS |
32 | #ifdef DEBUG_EXCEPTIONS |
33 | # define LOG_EXCP(...) qemu_log(__VA_ARGS__) | |
34 | #else | |
35 | # define LOG_EXCP(...) do { } while (0) | |
36 | #endif | |
37 | ||
c79c73f6 BS |
38 | /*****************************************************************************/ |
39 | /* Exception processing */ | |
40 | #if defined(CONFIG_USER_ONLY) | |
97a8ea5a | 41 | void ppc_cpu_do_interrupt(CPUState *cs) |
c79c73f6 | 42 | { |
97a8ea5a AF |
43 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
44 | CPUPPCState *env = &cpu->env; | |
45 | ||
27103424 | 46 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 BS |
47 | env->error_code = 0; |
48 | } | |
49 | ||
458dd766 | 50 | static void ppc_hw_interrupt(CPUPPCState *env) |
c79c73f6 | 51 | { |
db70b311 | 52 | CPUState *cs = env_cpu(env); |
27103424 AF |
53 | |
54 | cs->exception_index = POWERPC_EXCP_NONE; | |
c79c73f6 BS |
55 | env->error_code = 0; |
56 | } | |
57 | #else /* defined(CONFIG_USER_ONLY) */ | |
58 | static inline void dump_syscall(CPUPPCState *env) | |
59 | { | |
60 | qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 | |
61 | " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 | |
62 | " nip=" TARGET_FMT_lx "\n", | |
63 | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), | |
64 | ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), | |
65 | ppc_dump_gpr(env, 6), env->nip); | |
66 | } | |
67 | ||
dead760b BH |
68 | static int powerpc_reset_wakeup(CPUState *cs, CPUPPCState *env, int excp, |
69 | target_ulong *msr) | |
70 | { | |
71 | /* We no longer are in a PM state */ | |
1e7fd61d | 72 | env->resume_as_sreset = false; |
dead760b BH |
73 | |
74 | /* Pretend to be returning from doze always as we don't lose state */ | |
75 | *msr |= (0x1ull << (63 - 47)); | |
76 | ||
77 | /* Machine checks are sent normally */ | |
78 | if (excp == POWERPC_EXCP_MCHECK) { | |
79 | return excp; | |
80 | } | |
81 | switch (excp) { | |
82 | case POWERPC_EXCP_RESET: | |
83 | *msr |= 0x4ull << (63 - 45); | |
84 | break; | |
85 | case POWERPC_EXCP_EXTERNAL: | |
86 | *msr |= 0x8ull << (63 - 45); | |
87 | break; | |
88 | case POWERPC_EXCP_DECR: | |
89 | *msr |= 0x6ull << (63 - 45); | |
90 | break; | |
91 | case POWERPC_EXCP_SDOOR: | |
92 | *msr |= 0x5ull << (63 - 45); | |
93 | break; | |
94 | case POWERPC_EXCP_SDOOR_HV: | |
95 | *msr |= 0x3ull << (63 - 45); | |
96 | break; | |
97 | case POWERPC_EXCP_HV_MAINT: | |
98 | *msr |= 0xaull << (63 - 45); | |
99 | break; | |
d8ce5fd6 BH |
100 | case POWERPC_EXCP_HVIRT: |
101 | *msr |= 0x9ull << (63 - 45); | |
102 | break; | |
dead760b BH |
103 | default: |
104 | cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", | |
105 | excp); | |
106 | } | |
107 | return POWERPC_EXCP_RESET; | |
108 | } | |
109 | ||
2586a4d7 FR |
110 | static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail) |
111 | { | |
112 | uint64_t offset = 0; | |
113 | ||
114 | switch (ail) { | |
bc5fdfc0 FR |
115 | case AIL_NONE: |
116 | break; | |
2586a4d7 FR |
117 | case AIL_0001_8000: |
118 | offset = 0x18000; | |
119 | break; | |
120 | case AIL_C000_0000_0000_4000: | |
121 | offset = 0xc000000000004000ull; | |
122 | break; | |
123 | default: | |
124 | cpu_abort(cs, "Invalid AIL combination %d\n", ail); | |
125 | break; | |
126 | } | |
127 | ||
128 | return offset; | |
129 | } | |
dead760b | 130 | |
ad77c6ca NP |
131 | static inline void powerpc_set_excp_state(PowerPCCPU *cpu, |
132 | target_ulong vector, target_ulong msr) | |
133 | { | |
134 | CPUState *cs = CPU(cpu); | |
135 | CPUPPCState *env = &cpu->env; | |
136 | ||
137 | /* | |
138 | * We don't use hreg_store_msr here as already have treated any | |
139 | * special case that could occur. Just store MSR and update hflags | |
140 | * | |
141 | * Note: We *MUST* not use hreg_store_msr() as-is anyway because it | |
142 | * will prevent setting of the HV bit which some exceptions might need | |
143 | * to do. | |
144 | */ | |
145 | env->msr = msr & env->msr_mask; | |
146 | hreg_compute_hflags(env); | |
147 | env->nip = vector; | |
148 | /* Reset exception state */ | |
149 | cs->exception_index = POWERPC_EXCP_NONE; | |
150 | env->error_code = 0; | |
151 | ||
152 | /* Reset the reservation */ | |
153 | env->reserve_addr = -1; | |
154 | ||
155 | /* | |
156 | * Any interrupt is context synchronizing, check if TCG TLB needs | |
157 | * a delayed flush on ppc64 | |
158 | */ | |
159 | check_tlb_flush(env, false); | |
160 | } | |
161 | ||
47733729 DG |
162 | /* |
163 | * Note that this function should be greatly optimized when called | |
164 | * with a constant excp, from ppc_hw_interrupt | |
c79c73f6 | 165 | */ |
5c26a5b3 | 166 | static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) |
c79c73f6 | 167 | { |
27103424 | 168 | CPUState *cs = CPU(cpu); |
5c26a5b3 | 169 | CPUPPCState *env = &cpu->env; |
c79c73f6 | 170 | target_ulong msr, new_msr, vector; |
6d49d6d4 BH |
171 | int srr0, srr1, asrr0, asrr1, lev, ail; |
172 | bool lpes0; | |
c79c73f6 BS |
173 | |
174 | qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx | |
175 | " => %08x (%02x)\n", env->nip, excp, env->error_code); | |
176 | ||
177 | /* new srr1 value excluding must-be-zero bits */ | |
a1bb7384 SW |
178 | if (excp_model == POWERPC_EXCP_BOOKE) { |
179 | msr = env->msr; | |
180 | } else { | |
181 | msr = env->msr & ~0x783f0000ULL; | |
182 | } | |
c79c73f6 | 183 | |
47733729 DG |
184 | /* |
185 | * new interrupt handler msr preserves existing HV and ME unless | |
6d49d6d4 BH |
186 | * explicitly overriden |
187 | */ | |
188 | new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); | |
c79c73f6 BS |
189 | |
190 | /* target registers */ | |
191 | srr0 = SPR_SRR0; | |
192 | srr1 = SPR_SRR1; | |
193 | asrr0 = -1; | |
194 | asrr1 = -1; | |
195 | ||
21c0d66a BH |
196 | /* |
197 | * check for special resume at 0x100 from doze/nap/sleep/winkle on | |
198 | * P7/P8/P9 | |
199 | */ | |
1e7fd61d | 200 | if (env->resume_as_sreset) { |
dead760b | 201 | excp = powerpc_reset_wakeup(cs, env, excp, &msr); |
7778a575 BH |
202 | } |
203 | ||
47733729 DG |
204 | /* |
205 | * Exception targetting modifiers | |
6d49d6d4 | 206 | * |
a790e82b | 207 | * LPES0 is supported on POWER7/8/9 |
6d49d6d4 BH |
208 | * LPES1 is not supported (old iSeries mode) |
209 | * | |
210 | * On anything else, we behave as if LPES0 is 1 | |
211 | * (externals don't alter MSR:HV) | |
5c94b2a5 CLG |
212 | * |
213 | * AIL is initialized here but can be cleared by | |
214 | * selected exceptions | |
215 | */ | |
216 | #if defined(TARGET_PPC64) | |
217 | if (excp_model == POWERPC_EXCP_POWER7 || | |
a790e82b BH |
218 | excp_model == POWERPC_EXCP_POWER8 || |
219 | excp_model == POWERPC_EXCP_POWER9) { | |
6d49d6d4 | 220 | lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); |
a790e82b | 221 | if (excp_model != POWERPC_EXCP_POWER7) { |
5c94b2a5 CLG |
222 | ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; |
223 | } else { | |
224 | ail = 0; | |
225 | } | |
226 | } else | |
227 | #endif /* defined(TARGET_PPC64) */ | |
228 | { | |
6d49d6d4 | 229 | lpes0 = true; |
5c94b2a5 CLG |
230 | ail = 0; |
231 | } | |
232 | ||
47733729 DG |
233 | /* |
234 | * Hypervisor emulation assistance interrupt only exists on server | |
9b2fadda BH |
235 | * arch 2.05 server or later. We also don't want to generate it if |
236 | * we don't have HVB in msr_mask (PAPR mode). | |
237 | */ | |
238 | if (excp == POWERPC_EXCP_HV_EMU | |
239 | #if defined(TARGET_PPC64) | |
240 | && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB)) | |
241 | #endif /* defined(TARGET_PPC64) */ | |
242 | ||
243 | ) { | |
244 | excp = POWERPC_EXCP_PROGRAM; | |
245 | } | |
246 | ||
c79c73f6 BS |
247 | switch (excp) { |
248 | case POWERPC_EXCP_NONE: | |
249 | /* Should never happen */ | |
250 | return; | |
251 | case POWERPC_EXCP_CRITICAL: /* Critical input */ | |
252 | switch (excp_model) { | |
253 | case POWERPC_EXCP_40x: | |
254 | srr0 = SPR_40x_SRR2; | |
255 | srr1 = SPR_40x_SRR3; | |
256 | break; | |
257 | case POWERPC_EXCP_BOOKE: | |
258 | srr0 = SPR_BOOKE_CSRR0; | |
259 | srr1 = SPR_BOOKE_CSRR1; | |
260 | break; | |
261 | case POWERPC_EXCP_G2: | |
262 | break; | |
263 | default: | |
264 | goto excp_invalid; | |
265 | } | |
bd6fefe7 | 266 | break; |
c79c73f6 BS |
267 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
268 | if (msr_me == 0) { | |
47733729 DG |
269 | /* |
270 | * Machine check exception is not enabled. Enter | |
271 | * checkstop state. | |
c79c73f6 | 272 | */ |
013a2942 PB |
273 | fprintf(stderr, "Machine check while not allowed. " |
274 | "Entering checkstop state\n"); | |
275 | if (qemu_log_separate()) { | |
c79c73f6 BS |
276 | qemu_log("Machine check while not allowed. " |
277 | "Entering checkstop state\n"); | |
c79c73f6 | 278 | } |
259186a7 | 279 | cs->halted = 1; |
044897ef | 280 | cpu_interrupt_exittb(cs); |
c79c73f6 | 281 | } |
10c21b5c | 282 | if (env->msr_mask & MSR_HVB) { |
47733729 DG |
283 | /* |
284 | * ISA specifies HV, but can be delivered to guest with HV | |
285 | * clear (e.g., see FWNMI in PAPR). | |
10c21b5c NP |
286 | */ |
287 | new_msr |= (target_ulong)MSR_HVB; | |
288 | } | |
5c94b2a5 | 289 | ail = 0; |
c79c73f6 BS |
290 | |
291 | /* machine check exceptions don't have ME set */ | |
292 | new_msr &= ~((target_ulong)1 << MSR_ME); | |
293 | ||
294 | /* XXX: should also have something loaded in DAR / DSISR */ | |
295 | switch (excp_model) { | |
296 | case POWERPC_EXCP_40x: | |
297 | srr0 = SPR_40x_SRR2; | |
298 | srr1 = SPR_40x_SRR3; | |
299 | break; | |
300 | case POWERPC_EXCP_BOOKE: | |
a1bb7384 | 301 | /* FIXME: choose one or the other based on CPU type */ |
c79c73f6 BS |
302 | srr0 = SPR_BOOKE_MCSRR0; |
303 | srr1 = SPR_BOOKE_MCSRR1; | |
304 | asrr0 = SPR_BOOKE_CSRR0; | |
305 | asrr1 = SPR_BOOKE_CSRR1; | |
306 | break; | |
307 | default: | |
308 | break; | |
309 | } | |
bd6fefe7 | 310 | break; |
c79c73f6 BS |
311 | case POWERPC_EXCP_DSI: /* Data storage exception */ |
312 | LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx | |
313 | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); | |
bd6fefe7 | 314 | break; |
c79c73f6 BS |
315 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
316 | LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx | |
317 | "\n", msr, env->nip); | |
c79c73f6 | 318 | msr |= env->error_code; |
bd6fefe7 | 319 | break; |
c79c73f6 | 320 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
fdfba1a2 EI |
321 | cs = CPU(cpu); |
322 | ||
6d49d6d4 | 323 | if (!lpes0) { |
c79c73f6 | 324 | new_msr |= (target_ulong)MSR_HVB; |
6d49d6d4 BH |
325 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); |
326 | srr0 = SPR_HSRR0; | |
327 | srr1 = SPR_HSRR1; | |
c79c73f6 | 328 | } |
68c2dd70 AG |
329 | if (env->mpic_proxy) { |
330 | /* IACK the IRQ on delivery */ | |
fdfba1a2 | 331 | env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); |
68c2dd70 | 332 | } |
bd6fefe7 | 333 | break; |
c79c73f6 | 334 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
c79c73f6 | 335 | /* Get rS/rD and rA from faulting opcode */ |
47733729 DG |
336 | /* |
337 | * Note: the opcode fields will not be set properly for a | |
338 | * direct store load/store, but nobody cares as nobody | |
339 | * actually uses direct store segments. | |
3433b732 BH |
340 | */ |
341 | env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; | |
bd6fefe7 | 342 | break; |
c79c73f6 BS |
343 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
344 | switch (env->error_code & ~0xF) { | |
345 | case POWERPC_EXCP_FP: | |
346 | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { | |
347 | LOG_EXCP("Ignore floating point exception\n"); | |
27103424 | 348 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 BS |
349 | env->error_code = 0; |
350 | return; | |
351 | } | |
1b7d17ca | 352 | |
47733729 DG |
353 | /* |
354 | * FP exceptions always have NIP pointing to the faulting | |
1b7d17ca BH |
355 | * instruction, so always use store_next and claim we are |
356 | * precise in the MSR. | |
357 | */ | |
c79c73f6 | 358 | msr |= 0x00100000; |
0ee604ab | 359 | env->spr[SPR_BOOKE_ESR] = ESR_FP; |
bd6fefe7 | 360 | break; |
c79c73f6 BS |
361 | case POWERPC_EXCP_INVAL: |
362 | LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); | |
c79c73f6 BS |
363 | msr |= 0x00080000; |
364 | env->spr[SPR_BOOKE_ESR] = ESR_PIL; | |
365 | break; | |
366 | case POWERPC_EXCP_PRIV: | |
c79c73f6 BS |
367 | msr |= 0x00040000; |
368 | env->spr[SPR_BOOKE_ESR] = ESR_PPR; | |
369 | break; | |
370 | case POWERPC_EXCP_TRAP: | |
c79c73f6 BS |
371 | msr |= 0x00020000; |
372 | env->spr[SPR_BOOKE_ESR] = ESR_PTR; | |
373 | break; | |
374 | default: | |
375 | /* Should never occur */ | |
a47dddd7 | 376 | cpu_abort(cs, "Invalid program exception %d. Aborting\n", |
c79c73f6 BS |
377 | env->error_code); |
378 | break; | |
379 | } | |
bd6fefe7 | 380 | break; |
c79c73f6 BS |
381 | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
382 | dump_syscall(env); | |
383 | lev = env->error_code; | |
6d49d6d4 | 384 | |
47733729 DG |
385 | /* |
386 | * We need to correct the NIP which in this case is supposed | |
bd6fefe7 BH |
387 | * to point to the next instruction |
388 | */ | |
389 | env->nip += 4; | |
390 | ||
6d49d6d4 | 391 | /* "PAPR mode" built-in hypercall emulation */ |
1d1be34d DG |
392 | if ((lev == 1) && cpu->vhyp) { |
393 | PPCVirtualHypervisorClass *vhc = | |
394 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
395 | vhc->hypercall(cpu->vhyp, cpu); | |
c79c73f6 BS |
396 | return; |
397 | } | |
6d49d6d4 | 398 | if (lev == 1) { |
c79c73f6 BS |
399 | new_msr |= (target_ulong)MSR_HVB; |
400 | } | |
bd6fefe7 BH |
401 | break; |
402 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ | |
c79c73f6 | 403 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
c79c73f6 | 404 | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
bd6fefe7 | 405 | break; |
c79c73f6 BS |
406 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
407 | /* FIT on 4xx */ | |
408 | LOG_EXCP("FIT exception\n"); | |
bd6fefe7 | 409 | break; |
c79c73f6 BS |
410 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
411 | LOG_EXCP("WDT exception\n"); | |
412 | switch (excp_model) { | |
413 | case POWERPC_EXCP_BOOKE: | |
414 | srr0 = SPR_BOOKE_CSRR0; | |
415 | srr1 = SPR_BOOKE_CSRR1; | |
416 | break; | |
417 | default: | |
418 | break; | |
419 | } | |
bd6fefe7 | 420 | break; |
c79c73f6 | 421 | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
c79c73f6 | 422 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
bd6fefe7 | 423 | break; |
c79c73f6 | 424 | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
0e3bf489 | 425 | if (env->flags & POWERPC_FLAG_DE) { |
a1bb7384 | 426 | /* FIXME: choose one or the other based on CPU type */ |
c79c73f6 BS |
427 | srr0 = SPR_BOOKE_DSRR0; |
428 | srr1 = SPR_BOOKE_DSRR1; | |
429 | asrr0 = SPR_BOOKE_CSRR0; | |
430 | asrr1 = SPR_BOOKE_CSRR1; | |
0e3bf489 RK |
431 | /* DBSR already modified by caller */ |
432 | } else { | |
433 | cpu_abort(cs, "Debug exception triggered on unsupported model\n"); | |
c79c73f6 | 434 | } |
bd6fefe7 | 435 | break; |
c79c73f6 BS |
436 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
437 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
bd6fefe7 | 438 | break; |
c79c73f6 BS |
439 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
440 | /* XXX: TODO */ | |
a47dddd7 | 441 | cpu_abort(cs, "Embedded floating point data exception " |
c79c73f6 BS |
442 | "is not implemented yet !\n"); |
443 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
bd6fefe7 | 444 | break; |
c79c73f6 BS |
445 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
446 | /* XXX: TODO */ | |
a47dddd7 | 447 | cpu_abort(cs, "Embedded floating point round exception " |
c79c73f6 BS |
448 | "is not implemented yet !\n"); |
449 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
bd6fefe7 | 450 | break; |
c79c73f6 BS |
451 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
452 | /* XXX: TODO */ | |
a47dddd7 | 453 | cpu_abort(cs, |
c79c73f6 | 454 | "Performance counter exception is not implemented yet !\n"); |
bd6fefe7 | 455 | break; |
c79c73f6 | 456 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
bd6fefe7 | 457 | break; |
c79c73f6 BS |
458 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
459 | srr0 = SPR_BOOKE_CSRR0; | |
460 | srr1 = SPR_BOOKE_CSRR1; | |
bd6fefe7 | 461 | break; |
c79c73f6 | 462 | case POWERPC_EXCP_RESET: /* System reset exception */ |
f85bcec3 | 463 | /* A power-saving exception sets ME, otherwise it is unchanged */ |
c79c73f6 BS |
464 | if (msr_pow) { |
465 | /* indicate that we resumed from power save mode */ | |
466 | msr |= 0x10000; | |
f85bcec3 | 467 | new_msr |= ((target_ulong)1 << MSR_ME); |
c79c73f6 | 468 | } |
10c21b5c | 469 | if (env->msr_mask & MSR_HVB) { |
47733729 DG |
470 | /* |
471 | * ISA specifies HV, but can be delivered to guest with HV | |
472 | * clear (e.g., see FWNMI in PAPR, NMI injection in QEMU). | |
10c21b5c NP |
473 | */ |
474 | new_msr |= (target_ulong)MSR_HVB; | |
475 | } else { | |
476 | if (msr_pow) { | |
477 | cpu_abort(cs, "Trying to deliver power-saving system reset " | |
478 | "exception %d with no HV support\n", excp); | |
479 | } | |
480 | } | |
5c94b2a5 | 481 | ail = 0; |
bd6fefe7 | 482 | break; |
c79c73f6 | 483 | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
c79c73f6 | 484 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
c79c73f6 | 485 | case POWERPC_EXCP_TRACE: /* Trace exception */ |
bd6fefe7 BH |
486 | break; |
487 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ | |
c79c73f6 | 488 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
c79c73f6 | 489 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
c79c73f6 | 490 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
c79c73f6 | 491 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
7af1e7b0 | 492 | case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */ |
bd6fefe7 | 493 | case POWERPC_EXCP_HV_EMU: |
d8ce5fd6 | 494 | case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */ |
c79c73f6 BS |
495 | srr0 = SPR_HSRR0; |
496 | srr1 = SPR_HSRR1; | |
497 | new_msr |= (target_ulong)MSR_HVB; | |
498 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
bd6fefe7 | 499 | break; |
c79c73f6 | 500 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
1f29871c | 501 | case POWERPC_EXCP_VSXU: /* VSX unavailable exception */ |
7019cb3d | 502 | case POWERPC_EXCP_FU: /* Facility unavailable exception */ |
5310799a BS |
503 | #ifdef TARGET_PPC64 |
504 | env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); | |
493028d8 CLG |
505 | #endif |
506 | break; | |
507 | case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */ | |
508 | #ifdef TARGET_PPC64 | |
509 | env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS); | |
510 | srr0 = SPR_HSRR0; | |
511 | srr1 = SPR_HSRR1; | |
512 | new_msr |= (target_ulong)MSR_HVB; | |
513 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
5310799a | 514 | #endif |
bd6fefe7 | 515 | break; |
c79c73f6 BS |
516 | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
517 | LOG_EXCP("PIT exception\n"); | |
bd6fefe7 | 518 | break; |
c79c73f6 BS |
519 | case POWERPC_EXCP_IO: /* IO error exception */ |
520 | /* XXX: TODO */ | |
a47dddd7 | 521 | cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); |
bd6fefe7 | 522 | break; |
c79c73f6 BS |
523 | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
524 | /* XXX: TODO */ | |
a47dddd7 | 525 | cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); |
bd6fefe7 | 526 | break; |
c79c73f6 BS |
527 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
528 | /* XXX: TODO */ | |
a47dddd7 | 529 | cpu_abort(cs, "602 emulation trap exception " |
c79c73f6 | 530 | "is not implemented yet !\n"); |
bd6fefe7 | 531 | break; |
c79c73f6 | 532 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
c79c73f6 BS |
533 | switch (excp_model) { |
534 | case POWERPC_EXCP_602: | |
535 | case POWERPC_EXCP_603: | |
536 | case POWERPC_EXCP_603E: | |
537 | case POWERPC_EXCP_G2: | |
538 | goto tlb_miss_tgpr; | |
539 | case POWERPC_EXCP_7x5: | |
540 | goto tlb_miss; | |
541 | case POWERPC_EXCP_74xx: | |
542 | goto tlb_miss_74xx; | |
543 | default: | |
a47dddd7 | 544 | cpu_abort(cs, "Invalid instruction TLB miss exception\n"); |
c79c73f6 BS |
545 | break; |
546 | } | |
547 | break; | |
548 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
c79c73f6 BS |
549 | switch (excp_model) { |
550 | case POWERPC_EXCP_602: | |
551 | case POWERPC_EXCP_603: | |
552 | case POWERPC_EXCP_603E: | |
553 | case POWERPC_EXCP_G2: | |
554 | goto tlb_miss_tgpr; | |
555 | case POWERPC_EXCP_7x5: | |
556 | goto tlb_miss; | |
557 | case POWERPC_EXCP_74xx: | |
558 | goto tlb_miss_74xx; | |
559 | default: | |
a47dddd7 | 560 | cpu_abort(cs, "Invalid data load TLB miss exception\n"); |
c79c73f6 BS |
561 | break; |
562 | } | |
563 | break; | |
564 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
c79c73f6 BS |
565 | switch (excp_model) { |
566 | case POWERPC_EXCP_602: | |
567 | case POWERPC_EXCP_603: | |
568 | case POWERPC_EXCP_603E: | |
569 | case POWERPC_EXCP_G2: | |
570 | tlb_miss_tgpr: | |
571 | /* Swap temporary saved registers with GPRs */ | |
572 | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { | |
573 | new_msr |= (target_ulong)1 << MSR_TGPR; | |
574 | hreg_swap_gpr_tgpr(env); | |
575 | } | |
576 | goto tlb_miss; | |
577 | case POWERPC_EXCP_7x5: | |
578 | tlb_miss: | |
579 | #if defined(DEBUG_SOFTWARE_TLB) | |
580 | if (qemu_log_enabled()) { | |
581 | const char *es; | |
582 | target_ulong *miss, *cmp; | |
583 | int en; | |
584 | ||
585 | if (excp == POWERPC_EXCP_IFTLB) { | |
586 | es = "I"; | |
587 | en = 'I'; | |
588 | miss = &env->spr[SPR_IMISS]; | |
589 | cmp = &env->spr[SPR_ICMP]; | |
590 | } else { | |
591 | if (excp == POWERPC_EXCP_DLTLB) { | |
592 | es = "DL"; | |
593 | } else { | |
594 | es = "DS"; | |
595 | } | |
596 | en = 'D'; | |
597 | miss = &env->spr[SPR_DMISS]; | |
598 | cmp = &env->spr[SPR_DCMP]; | |
599 | } | |
600 | qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " | |
601 | TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " | |
602 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
603 | env->spr[SPR_HASH1], env->spr[SPR_HASH2], | |
604 | env->error_code); | |
605 | } | |
606 | #endif | |
607 | msr |= env->crf[0] << 28; | |
608 | msr |= env->error_code; /* key, D/I, S/L bits */ | |
609 | /* Set way using a LRU mechanism */ | |
610 | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; | |
611 | break; | |
612 | case POWERPC_EXCP_74xx: | |
613 | tlb_miss_74xx: | |
614 | #if defined(DEBUG_SOFTWARE_TLB) | |
615 | if (qemu_log_enabled()) { | |
616 | const char *es; | |
617 | target_ulong *miss, *cmp; | |
618 | int en; | |
619 | ||
620 | if (excp == POWERPC_EXCP_IFTLB) { | |
621 | es = "I"; | |
622 | en = 'I'; | |
623 | miss = &env->spr[SPR_TLBMISS]; | |
624 | cmp = &env->spr[SPR_PTEHI]; | |
625 | } else { | |
626 | if (excp == POWERPC_EXCP_DLTLB) { | |
627 | es = "DL"; | |
628 | } else { | |
629 | es = "DS"; | |
630 | } | |
631 | en = 'D'; | |
632 | miss = &env->spr[SPR_TLBMISS]; | |
633 | cmp = &env->spr[SPR_PTEHI]; | |
634 | } | |
635 | qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " | |
636 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
637 | env->error_code); | |
638 | } | |
639 | #endif | |
640 | msr |= env->error_code; /* key bit */ | |
641 | break; | |
642 | default: | |
a47dddd7 | 643 | cpu_abort(cs, "Invalid data store TLB miss exception\n"); |
c79c73f6 BS |
644 | break; |
645 | } | |
bd6fefe7 | 646 | break; |
c79c73f6 BS |
647 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
648 | /* XXX: TODO */ | |
a47dddd7 | 649 | cpu_abort(cs, "Floating point assist exception " |
c79c73f6 | 650 | "is not implemented yet !\n"); |
bd6fefe7 | 651 | break; |
c79c73f6 BS |
652 | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
653 | /* XXX: TODO */ | |
a47dddd7 | 654 | cpu_abort(cs, "DABR exception is not implemented yet !\n"); |
bd6fefe7 | 655 | break; |
c79c73f6 BS |
656 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
657 | /* XXX: TODO */ | |
a47dddd7 | 658 | cpu_abort(cs, "IABR exception is not implemented yet !\n"); |
bd6fefe7 | 659 | break; |
c79c73f6 BS |
660 | case POWERPC_EXCP_SMI: /* System management interrupt */ |
661 | /* XXX: TODO */ | |
a47dddd7 | 662 | cpu_abort(cs, "SMI exception is not implemented yet !\n"); |
bd6fefe7 | 663 | break; |
c79c73f6 BS |
664 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
665 | /* XXX: TODO */ | |
a47dddd7 | 666 | cpu_abort(cs, "Thermal management exception " |
c79c73f6 | 667 | "is not implemented yet !\n"); |
bd6fefe7 | 668 | break; |
c79c73f6 | 669 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
c79c73f6 | 670 | /* XXX: TODO */ |
a47dddd7 | 671 | cpu_abort(cs, |
c79c73f6 | 672 | "Performance counter exception is not implemented yet !\n"); |
bd6fefe7 | 673 | break; |
c79c73f6 BS |
674 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
675 | /* XXX: TODO */ | |
a47dddd7 | 676 | cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); |
bd6fefe7 | 677 | break; |
c79c73f6 BS |
678 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
679 | /* XXX: TODO */ | |
a47dddd7 | 680 | cpu_abort(cs, |
c79c73f6 | 681 | "970 soft-patch exception is not implemented yet !\n"); |
bd6fefe7 | 682 | break; |
c79c73f6 BS |
683 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
684 | /* XXX: TODO */ | |
a47dddd7 | 685 | cpu_abort(cs, |
c79c73f6 | 686 | "970 maintenance exception is not implemented yet !\n"); |
bd6fefe7 | 687 | break; |
c79c73f6 BS |
688 | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
689 | /* XXX: TODO */ | |
a47dddd7 | 690 | cpu_abort(cs, "Maskable external exception " |
c79c73f6 | 691 | "is not implemented yet !\n"); |
bd6fefe7 | 692 | break; |
c79c73f6 BS |
693 | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ |
694 | /* XXX: TODO */ | |
a47dddd7 | 695 | cpu_abort(cs, "Non maskable external exception " |
c79c73f6 | 696 | "is not implemented yet !\n"); |
bd6fefe7 | 697 | break; |
c79c73f6 BS |
698 | default: |
699 | excp_invalid: | |
a47dddd7 | 700 | cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); |
c79c73f6 | 701 | break; |
c79c73f6 | 702 | } |
bd6fefe7 BH |
703 | |
704 | /* Save PC */ | |
705 | env->spr[srr0] = env->nip; | |
706 | ||
c79c73f6 BS |
707 | /* Save MSR */ |
708 | env->spr[srr1] = msr; | |
6d49d6d4 BH |
709 | |
710 | /* Sanity check */ | |
10c21b5c NP |
711 | if (!(env->msr_mask & MSR_HVB)) { |
712 | if (new_msr & MSR_HVB) { | |
713 | cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " | |
714 | "no HV support\n", excp); | |
715 | } | |
716 | if (srr0 == SPR_HSRR0) { | |
717 | cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " | |
718 | "no HV support\n", excp); | |
719 | } | |
6d49d6d4 BH |
720 | } |
721 | ||
c79c73f6 BS |
722 | /* If any alternate SRR register are defined, duplicate saved values */ |
723 | if (asrr0 != -1) { | |
724 | env->spr[asrr0] = env->spr[srr0]; | |
725 | } | |
726 | if (asrr1 != -1) { | |
727 | env->spr[asrr1] = env->spr[srr1]; | |
728 | } | |
d5ac4f54 | 729 | |
47733729 DG |
730 | /* |
731 | * Sort out endianness of interrupt, this differs depending on the | |
6d49d6d4 BH |
732 | * CPU, the HV mode, etc... |
733 | */ | |
1e0c7e55 | 734 | #ifdef TARGET_PPC64 |
6d49d6d4 BH |
735 | if (excp_model == POWERPC_EXCP_POWER7) { |
736 | if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) { | |
737 | new_msr |= (target_ulong)1 << MSR_LE; | |
738 | } | |
739 | } else if (excp_model == POWERPC_EXCP_POWER8) { | |
740 | if (new_msr & MSR_HVB) { | |
a790e82b BH |
741 | if (env->spr[SPR_HID0] & HID0_HILE) { |
742 | new_msr |= (target_ulong)1 << MSR_LE; | |
743 | } | |
744 | } else if (env->spr[SPR_LPCR] & LPCR_ILE) { | |
745 | new_msr |= (target_ulong)1 << MSR_LE; | |
746 | } | |
747 | } else if (excp_model == POWERPC_EXCP_POWER9) { | |
748 | if (new_msr & MSR_HVB) { | |
749 | if (env->spr[SPR_HID0] & HID0_POWER9_HILE) { | |
6d49d6d4 BH |
750 | new_msr |= (target_ulong)1 << MSR_LE; |
751 | } | |
752 | } else if (env->spr[SPR_LPCR] & LPCR_ILE) { | |
1e0c7e55 AB |
753 | new_msr |= (target_ulong)1 << MSR_LE; |
754 | } | |
755 | } else if (msr_ile) { | |
756 | new_msr |= (target_ulong)1 << MSR_LE; | |
757 | } | |
758 | #else | |
c79c73f6 BS |
759 | if (msr_ile) { |
760 | new_msr |= (target_ulong)1 << MSR_LE; | |
761 | } | |
1e0c7e55 | 762 | #endif |
c79c73f6 BS |
763 | |
764 | /* Jump to handler */ | |
765 | vector = env->excp_vectors[excp]; | |
766 | if (vector == (target_ulong)-1ULL) { | |
a47dddd7 | 767 | cpu_abort(cs, "Raised an exception without defined vector %d\n", |
c79c73f6 BS |
768 | excp); |
769 | } | |
770 | vector |= env->excp_prefix; | |
5c94b2a5 | 771 | |
47733729 DG |
772 | /* |
773 | * AIL only works if there is no HV transition and we are running | |
774 | * with translations enabled | |
5c94b2a5 | 775 | */ |
6d49d6d4 BH |
776 | if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) || |
777 | ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) { | |
5c94b2a5 CLG |
778 | ail = 0; |
779 | } | |
780 | /* Handle AIL */ | |
781 | if (ail) { | |
782 | new_msr |= (1 << MSR_IR) | (1 << MSR_DR); | |
2586a4d7 | 783 | vector |= ppc_excp_vector_offset(cs, ail); |
5c94b2a5 CLG |
784 | } |
785 | ||
c79c73f6 BS |
786 | #if defined(TARGET_PPC64) |
787 | if (excp_model == POWERPC_EXCP_BOOKE) { | |
e42a61f1 AG |
788 | if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { |
789 | /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ | |
c79c73f6 | 790 | new_msr |= (target_ulong)1 << MSR_CM; |
e42a61f1 AG |
791 | } else { |
792 | vector = (uint32_t)vector; | |
c79c73f6 BS |
793 | } |
794 | } else { | |
795 | if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { | |
796 | vector = (uint32_t)vector; | |
797 | } else { | |
798 | new_msr |= (target_ulong)1 << MSR_SF; | |
799 | } | |
800 | } | |
801 | #endif | |
cd0c6f47 | 802 | |
ad77c6ca | 803 | powerpc_set_excp_state(cpu, vector, new_msr); |
c79c73f6 BS |
804 | } |
805 | ||
97a8ea5a | 806 | void ppc_cpu_do_interrupt(CPUState *cs) |
c79c73f6 | 807 | { |
97a8ea5a AF |
808 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
809 | CPUPPCState *env = &cpu->env; | |
5c26a5b3 | 810 | |
27103424 | 811 | powerpc_excp(cpu, env->excp_model, cs->exception_index); |
c79c73f6 BS |
812 | } |
813 | ||
458dd766 | 814 | static void ppc_hw_interrupt(CPUPPCState *env) |
c79c73f6 | 815 | { |
db70b311 | 816 | PowerPCCPU *cpu = env_archcpu(env); |
3621e2c9 | 817 | bool async_deliver; |
259186a7 | 818 | |
c79c73f6 BS |
819 | /* External reset */ |
820 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { | |
821 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); | |
5c26a5b3 | 822 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); |
c79c73f6 BS |
823 | return; |
824 | } | |
825 | /* Machine check exception */ | |
826 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { | |
827 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); | |
5c26a5b3 | 828 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); |
c79c73f6 BS |
829 | return; |
830 | } | |
831 | #if 0 /* TODO */ | |
832 | /* External debug exception */ | |
833 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { | |
834 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); | |
5c26a5b3 | 835 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG); |
c79c73f6 BS |
836 | return; |
837 | } | |
838 | #endif | |
3621e2c9 BH |
839 | |
840 | /* | |
841 | * For interrupts that gate on MSR:EE, we need to do something a | |
842 | * bit more subtle, as we need to let them through even when EE is | |
843 | * clear when coming out of some power management states (in order | |
844 | * for them to become a 0x100). | |
845 | */ | |
1e7fd61d | 846 | async_deliver = (msr_ee != 0) || env->resume_as_sreset; |
3621e2c9 | 847 | |
4b236b62 BH |
848 | /* Hypervisor decrementer exception */ |
849 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { | |
850 | /* LPCR will be clear when not supported so this will work */ | |
851 | bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); | |
3621e2c9 | 852 | if ((async_deliver || msr_hv == 0) && hdice) { |
4b236b62 BH |
853 | /* HDEC clears on delivery */ |
854 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); | |
5c26a5b3 | 855 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR); |
c79c73f6 BS |
856 | return; |
857 | } | |
858 | } | |
d8ce5fd6 BH |
859 | |
860 | /* Hypervisor virtualization interrupt */ | |
861 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) { | |
862 | /* LPCR will be clear when not supported so this will work */ | |
863 | bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE); | |
864 | if ((async_deliver || msr_hv == 0) && hvice) { | |
865 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HVIRT); | |
866 | return; | |
867 | } | |
868 | } | |
869 | ||
870 | /* External interrupt can ignore MSR:EE under some circumstances */ | |
d1dbe37c BH |
871 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { |
872 | bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); | |
6eebe6dc BH |
873 | bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); |
874 | /* HEIC blocks delivery to the hypervisor */ | |
875 | if ((async_deliver && !(heic && msr_hv && !msr_pr)) || | |
876 | (env->has_hv_mode && msr_hv == 0 && !lpes0)) { | |
d1dbe37c BH |
877 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL); |
878 | return; | |
879 | } | |
880 | } | |
c79c73f6 BS |
881 | if (msr_ce != 0) { |
882 | /* External critical interrupt */ | |
883 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { | |
5c26a5b3 | 884 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL); |
c79c73f6 BS |
885 | return; |
886 | } | |
887 | } | |
3621e2c9 | 888 | if (async_deliver != 0) { |
c79c73f6 BS |
889 | /* Watchdog timer on embedded PowerPC */ |
890 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { | |
891 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); | |
5c26a5b3 | 892 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT); |
c79c73f6 BS |
893 | return; |
894 | } | |
895 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { | |
896 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); | |
5c26a5b3 | 897 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI); |
c79c73f6 BS |
898 | return; |
899 | } | |
900 | /* Fixed interval timer on embedded PowerPC */ | |
901 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { | |
902 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); | |
5c26a5b3 | 903 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT); |
c79c73f6 BS |
904 | return; |
905 | } | |
906 | /* Programmable interval timer on embedded PowerPC */ | |
907 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { | |
908 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); | |
5c26a5b3 | 909 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT); |
c79c73f6 BS |
910 | return; |
911 | } | |
912 | /* Decrementer exception */ | |
913 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { | |
e81a982a AG |
914 | if (ppc_decr_clear_on_delivery(env)) { |
915 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); | |
916 | } | |
5c26a5b3 | 917 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR); |
c79c73f6 BS |
918 | return; |
919 | } | |
c79c73f6 BS |
920 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
921 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); | |
5ba7ba1d CLG |
922 | if (is_book3s_arch2x(env)) { |
923 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR); | |
924 | } else { | |
925 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); | |
926 | } | |
c79c73f6 BS |
927 | return; |
928 | } | |
7af1e7b0 CLG |
929 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDOORBELL)) { |
930 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL); | |
931 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_SDOOR_HV); | |
932 | return; | |
933 | } | |
c79c73f6 BS |
934 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { |
935 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); | |
5c26a5b3 | 936 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM); |
c79c73f6 BS |
937 | return; |
938 | } | |
939 | /* Thermal interrupt */ | |
940 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { | |
941 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); | |
5c26a5b3 | 942 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); |
c79c73f6 BS |
943 | return; |
944 | } | |
945 | } | |
f8154fd2 BH |
946 | |
947 | if (env->resume_as_sreset) { | |
948 | /* | |
949 | * This is a bug ! It means that has_work took us out of halt without | |
950 | * anything to deliver while in a PM state that requires getting | |
951 | * out via a 0x100 | |
952 | * | |
953 | * This means we will incorrectly execute past the power management | |
954 | * instruction instead of triggering a reset. | |
955 | * | |
956 | * It generally means a discrepancy between the wakup conditions in the | |
957 | * processor has_work implementation and the logic in this function. | |
958 | */ | |
db70b311 | 959 | cpu_abort(env_cpu(env), |
f8154fd2 BH |
960 | "Wakeup from PM state but interrupt Undelivered"); |
961 | } | |
c79c73f6 | 962 | } |
34316482 | 963 | |
9aa25280 | 964 | void ppc_cpu_do_system_reset(CPUState *cs, target_ulong vector) |
34316482 AK |
965 | { |
966 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
967 | CPUPPCState *env = &cpu->env; | |
968 | ||
969 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); | |
9aa25280 NP |
970 | if (vector != -1) { |
971 | env->nip = vector; | |
972 | } | |
34316482 | 973 | } |
ad77c6ca NP |
974 | |
975 | void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector) | |
976 | { | |
977 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
978 | CPUPPCState *env = &cpu->env; | |
979 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
980 | target_ulong msr = 0; | |
981 | ||
982 | /* | |
983 | * Set MSR and NIP for the handler, SRR0/1, DAR and DSISR have already | |
984 | * been set by KVM. | |
985 | */ | |
986 | msr = (1ULL << MSR_ME); | |
987 | msr |= env->msr & (1ULL << MSR_SF); | |
988 | if (!(*pcc->interrupts_big_endian)(cpu)) { | |
989 | msr |= (1ULL << MSR_LE); | |
990 | } | |
991 | ||
992 | powerpc_set_excp_state(cpu, vector, msr); | |
993 | } | |
c79c73f6 BS |
994 | #endif /* !CONFIG_USER_ONLY */ |
995 | ||
458dd766 RH |
996 | bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
997 | { | |
998 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
999 | CPUPPCState *env = &cpu->env; | |
1000 | ||
1001 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
1002 | ppc_hw_interrupt(env); | |
1003 | if (env->pending_interrupts == 0) { | |
1004 | cs->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
1005 | } | |
1006 | return true; | |
1007 | } | |
1008 | return false; | |
1009 | } | |
1010 | ||
c79c73f6 BS |
1011 | #if defined(DEBUG_OP) |
1012 | static void cpu_dump_rfi(target_ulong RA, target_ulong msr) | |
1013 | { | |
1014 | qemu_log("Return from exception at " TARGET_FMT_lx " with flags " | |
1015 | TARGET_FMT_lx "\n", RA, msr); | |
1016 | } | |
1017 | #endif | |
1018 | ||
ad71ed68 BS |
1019 | /*****************************************************************************/ |
1020 | /* Exceptions processing helpers */ | |
1021 | ||
db789c6c BH |
1022 | void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, |
1023 | uint32_t error_code, uintptr_t raddr) | |
ad71ed68 | 1024 | { |
db70b311 | 1025 | CPUState *cs = env_cpu(env); |
27103424 | 1026 | |
27103424 | 1027 | cs->exception_index = exception; |
ad71ed68 | 1028 | env->error_code = error_code; |
db789c6c BH |
1029 | cpu_loop_exit_restore(cs, raddr); |
1030 | } | |
1031 | ||
1032 | void raise_exception_err(CPUPPCState *env, uint32_t exception, | |
1033 | uint32_t error_code) | |
1034 | { | |
1035 | raise_exception_err_ra(env, exception, error_code, 0); | |
1036 | } | |
1037 | ||
1038 | void raise_exception(CPUPPCState *env, uint32_t exception) | |
1039 | { | |
1040 | raise_exception_err_ra(env, exception, 0, 0); | |
1041 | } | |
1042 | ||
1043 | void raise_exception_ra(CPUPPCState *env, uint32_t exception, | |
1044 | uintptr_t raddr) | |
1045 | { | |
1046 | raise_exception_err_ra(env, exception, 0, raddr); | |
1047 | } | |
1048 | ||
1049 | void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, | |
1050 | uint32_t error_code) | |
1051 | { | |
1052 | raise_exception_err_ra(env, exception, error_code, 0); | |
ad71ed68 BS |
1053 | } |
1054 | ||
e5f17ac6 | 1055 | void helper_raise_exception(CPUPPCState *env, uint32_t exception) |
ad71ed68 | 1056 | { |
db789c6c | 1057 | raise_exception_err_ra(env, exception, 0, 0); |
ad71ed68 BS |
1058 | } |
1059 | ||
1060 | #if !defined(CONFIG_USER_ONLY) | |
e5f17ac6 | 1061 | void helper_store_msr(CPUPPCState *env, target_ulong val) |
ad71ed68 | 1062 | { |
db789c6c | 1063 | uint32_t excp = hreg_store_msr(env, val, 0); |
259186a7 | 1064 | |
db789c6c | 1065 | if (excp != 0) { |
db70b311 | 1066 | CPUState *cs = env_cpu(env); |
044897ef | 1067 | cpu_interrupt_exittb(cs); |
db789c6c | 1068 | raise_exception(env, excp); |
ad71ed68 BS |
1069 | } |
1070 | } | |
1071 | ||
7778a575 BH |
1072 | #if defined(TARGET_PPC64) |
1073 | void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) | |
1074 | { | |
1075 | CPUState *cs; | |
1076 | ||
db70b311 | 1077 | cs = env_cpu(env); |
7778a575 | 1078 | cs->halted = 1; |
7778a575 | 1079 | |
47733729 DG |
1080 | /* |
1081 | * The architecture specifies that HDEC interrupts are discarded | |
1082 | * in PM states | |
4b236b62 BH |
1083 | */ |
1084 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); | |
1085 | ||
3621e2c9 | 1086 | /* Condition for waking up at 0x100 */ |
1e7fd61d | 1087 | env->resume_as_sreset = (insn != PPC_PM_STOP) || |
21c0d66a | 1088 | (env->spr[SPR_PSSCR] & PSSCR_EC); |
7778a575 BH |
1089 | } |
1090 | #endif /* defined(TARGET_PPC64) */ | |
1091 | ||
a2e71b28 | 1092 | static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) |
ad71ed68 | 1093 | { |
db70b311 | 1094 | CPUState *cs = env_cpu(env); |
259186a7 | 1095 | |
a2e71b28 BH |
1096 | /* MSR:POW cannot be set by any form of rfi */ |
1097 | msr &= ~(1ULL << MSR_POW); | |
1098 | ||
ad71ed68 | 1099 | #if defined(TARGET_PPC64) |
a2e71b28 BH |
1100 | /* Switching to 32-bit ? Crop the nip */ |
1101 | if (!msr_is_64bit(env, msr)) { | |
ad71ed68 | 1102 | nip = (uint32_t)nip; |
ad71ed68 BS |
1103 | } |
1104 | #else | |
1105 | nip = (uint32_t)nip; | |
ad71ed68 BS |
1106 | #endif |
1107 | /* XXX: beware: this is false if VLE is supported */ | |
1108 | env->nip = nip & ~((target_ulong)0x00000003); | |
1109 | hreg_store_msr(env, msr, 1); | |
1110 | #if defined(DEBUG_OP) | |
1111 | cpu_dump_rfi(env->nip, env->msr); | |
1112 | #endif | |
47733729 DG |
1113 | /* |
1114 | * No need to raise an exception here, as rfi is always the last | |
1115 | * insn of a TB | |
ad71ed68 | 1116 | */ |
044897ef | 1117 | cpu_interrupt_exittb(cs); |
a8b73734 ND |
1118 | /* Reset the reservation */ |
1119 | env->reserve_addr = -1; | |
1120 | ||
cd0c6f47 | 1121 | /* Context synchronizing: check if TCG TLB needs flush */ |
e3cffe6f | 1122 | check_tlb_flush(env, false); |
ad71ed68 BS |
1123 | } |
1124 | ||
e5f17ac6 | 1125 | void helper_rfi(CPUPPCState *env) |
ad71ed68 | 1126 | { |
a2e71b28 | 1127 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); |
ad71ed68 BS |
1128 | } |
1129 | ||
a2e71b28 | 1130 | #define MSR_BOOK3S_MASK |
ad71ed68 | 1131 | #if defined(TARGET_PPC64) |
e5f17ac6 | 1132 | void helper_rfid(CPUPPCState *env) |
ad71ed68 | 1133 | { |
47733729 DG |
1134 | /* |
1135 | * The architeture defines a number of rules for which bits can | |
1136 | * change but in practice, we handle this in hreg_store_msr() | |
a2e71b28 BH |
1137 | * which will be called by do_rfi(), so there is no need to filter |
1138 | * here | |
1139 | */ | |
1140 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); | |
ad71ed68 BS |
1141 | } |
1142 | ||
e5f17ac6 | 1143 | void helper_hrfid(CPUPPCState *env) |
ad71ed68 | 1144 | { |
a2e71b28 | 1145 | do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); |
ad71ed68 BS |
1146 | } |
1147 | #endif | |
1148 | ||
1149 | /*****************************************************************************/ | |
1150 | /* Embedded PowerPC specific helpers */ | |
e5f17ac6 | 1151 | void helper_40x_rfci(CPUPPCState *env) |
ad71ed68 | 1152 | { |
a2e71b28 | 1153 | do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); |
ad71ed68 BS |
1154 | } |
1155 | ||
e5f17ac6 | 1156 | void helper_rfci(CPUPPCState *env) |
ad71ed68 | 1157 | { |
a2e71b28 | 1158 | do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); |
ad71ed68 BS |
1159 | } |
1160 | ||
e5f17ac6 | 1161 | void helper_rfdi(CPUPPCState *env) |
ad71ed68 | 1162 | { |
a1bb7384 | 1163 | /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ |
a2e71b28 | 1164 | do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); |
ad71ed68 BS |
1165 | } |
1166 | ||
e5f17ac6 | 1167 | void helper_rfmci(CPUPPCState *env) |
ad71ed68 | 1168 | { |
a1bb7384 | 1169 | /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ |
a2e71b28 | 1170 | do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
ad71ed68 BS |
1171 | } |
1172 | #endif | |
1173 | ||
e5f17ac6 BS |
1174 | void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
1175 | uint32_t flags) | |
ad71ed68 BS |
1176 | { |
1177 | if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || | |
1178 | ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || | |
1179 | ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || | |
1180 | ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || | |
1181 | ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { | |
72073dcc BH |
1182 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
1183 | POWERPC_EXCP_TRAP, GETPC()); | |
ad71ed68 BS |
1184 | } |
1185 | } | |
1186 | ||
1187 | #if defined(TARGET_PPC64) | |
e5f17ac6 BS |
1188 | void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
1189 | uint32_t flags) | |
ad71ed68 BS |
1190 | { |
1191 | if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || | |
1192 | ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || | |
1193 | ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || | |
1194 | ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || | |
1195 | ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { | |
72073dcc BH |
1196 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
1197 | POWERPC_EXCP_TRAP, GETPC()); | |
ad71ed68 BS |
1198 | } |
1199 | } | |
1200 | #endif | |
1201 | ||
1202 | #if !defined(CONFIG_USER_ONLY) | |
1203 | /*****************************************************************************/ | |
1204 | /* PowerPC 601 specific instructions (POWER bridge) */ | |
1205 | ||
e5f17ac6 | 1206 | void helper_rfsvc(CPUPPCState *env) |
ad71ed68 | 1207 | { |
a2e71b28 | 1208 | do_rfi(env, env->lr, env->ctr & 0x0000FFFF); |
ad71ed68 BS |
1209 | } |
1210 | ||
1211 | /* Embedded.Processor Control */ | |
1212 | static int dbell2irq(target_ulong rb) | |
1213 | { | |
1214 | int msg = rb & DBELL_TYPE_MASK; | |
1215 | int irq = -1; | |
1216 | ||
1217 | switch (msg) { | |
1218 | case DBELL_TYPE_DBELL: | |
1219 | irq = PPC_INTERRUPT_DOORBELL; | |
1220 | break; | |
1221 | case DBELL_TYPE_DBELL_CRIT: | |
1222 | irq = PPC_INTERRUPT_CDOORBELL; | |
1223 | break; | |
1224 | case DBELL_TYPE_G_DBELL: | |
1225 | case DBELL_TYPE_G_DBELL_CRIT: | |
1226 | case DBELL_TYPE_G_DBELL_MC: | |
1227 | /* XXX implement */ | |
1228 | default: | |
1229 | break; | |
1230 | } | |
1231 | ||
1232 | return irq; | |
1233 | } | |
1234 | ||
e5f17ac6 | 1235 | void helper_msgclr(CPUPPCState *env, target_ulong rb) |
ad71ed68 BS |
1236 | { |
1237 | int irq = dbell2irq(rb); | |
1238 | ||
1239 | if (irq < 0) { | |
1240 | return; | |
1241 | } | |
1242 | ||
1243 | env->pending_interrupts &= ~(1 << irq); | |
1244 | } | |
1245 | ||
1246 | void helper_msgsnd(target_ulong rb) | |
1247 | { | |
1248 | int irq = dbell2irq(rb); | |
1249 | int pir = rb & DBELL_PIRTAG_MASK; | |
182735ef | 1250 | CPUState *cs; |
ad71ed68 BS |
1251 | |
1252 | if (irq < 0) { | |
1253 | return; | |
1254 | } | |
1255 | ||
f1c29ebc | 1256 | qemu_mutex_lock_iothread(); |
bdc44640 | 1257 | CPU_FOREACH(cs) { |
182735ef AF |
1258 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1259 | CPUPPCState *cenv = &cpu->env; | |
1260 | ||
ad71ed68 BS |
1261 | if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { |
1262 | cenv->pending_interrupts |= 1 << irq; | |
182735ef | 1263 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
ad71ed68 BS |
1264 | } |
1265 | } | |
f1c29ebc | 1266 | qemu_mutex_unlock_iothread(); |
ad71ed68 | 1267 | } |
7af1e7b0 CLG |
1268 | |
1269 | /* Server Processor Control */ | |
7af1e7b0 | 1270 | |
5ba7ba1d CLG |
1271 | static bool dbell_type_server(target_ulong rb) |
1272 | { | |
47733729 DG |
1273 | /* |
1274 | * A Directed Hypervisor Doorbell message is sent only if the | |
7af1e7b0 | 1275 | * message type is 5. All other types are reserved and the |
47733729 DG |
1276 | * instruction is a no-op |
1277 | */ | |
5ba7ba1d | 1278 | return (rb & DBELL_TYPE_MASK) == DBELL_TYPE_DBELL_SERVER; |
7af1e7b0 CLG |
1279 | } |
1280 | ||
1281 | void helper_book3s_msgclr(CPUPPCState *env, target_ulong rb) | |
1282 | { | |
5ba7ba1d | 1283 | if (!dbell_type_server(rb)) { |
7af1e7b0 CLG |
1284 | return; |
1285 | } | |
1286 | ||
5ba7ba1d | 1287 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDOORBELL); |
7af1e7b0 CLG |
1288 | } |
1289 | ||
5ba7ba1d | 1290 | static void book3s_msgsnd_common(int pir, int irq) |
7af1e7b0 | 1291 | { |
7af1e7b0 CLG |
1292 | CPUState *cs; |
1293 | ||
7af1e7b0 CLG |
1294 | qemu_mutex_lock_iothread(); |
1295 | CPU_FOREACH(cs) { | |
1296 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
1297 | CPUPPCState *cenv = &cpu->env; | |
1298 | ||
1299 | /* TODO: broadcast message to all threads of the same processor */ | |
1300 | if (cenv->spr_cb[SPR_PIR].default_value == pir) { | |
1301 | cenv->pending_interrupts |= 1 << irq; | |
1302 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); | |
1303 | } | |
1304 | } | |
1305 | qemu_mutex_unlock_iothread(); | |
1306 | } | |
5ba7ba1d CLG |
1307 | |
1308 | void helper_book3s_msgsnd(target_ulong rb) | |
1309 | { | |
1310 | int pir = rb & DBELL_PROCIDTAG_MASK; | |
1311 | ||
1312 | if (!dbell_type_server(rb)) { | |
1313 | return; | |
1314 | } | |
1315 | ||
1316 | book3s_msgsnd_common(pir, PPC_INTERRUPT_HDOORBELL); | |
1317 | } | |
1318 | ||
1319 | #if defined(TARGET_PPC64) | |
1320 | void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) | |
1321 | { | |
493028d8 CLG |
1322 | helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP); |
1323 | ||
5ba7ba1d CLG |
1324 | if (!dbell_type_server(rb)) { |
1325 | return; | |
1326 | } | |
1327 | ||
1328 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); | |
1329 | } | |
1330 | ||
1331 | /* | |
1332 | * sends a message to other threads that are on the same | |
1333 | * multi-threaded processor | |
1334 | */ | |
1335 | void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) | |
1336 | { | |
1337 | int pir = env->spr_cb[SPR_PIR].default_value; | |
1338 | ||
493028d8 CLG |
1339 | helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP); |
1340 | ||
5ba7ba1d CLG |
1341 | if (!dbell_type_server(rb)) { |
1342 | return; | |
1343 | } | |
1344 | ||
1345 | /* TODO: TCG supports only one thread */ | |
1346 | ||
1347 | book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); | |
1348 | } | |
1349 | #endif | |
ad71ed68 | 1350 | #endif |
0f3110fa RH |
1351 | |
1352 | void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, | |
1353 | MMUAccessType access_type, | |
1354 | int mmu_idx, uintptr_t retaddr) | |
1355 | { | |
1356 | CPUPPCState *env = cs->env_ptr; | |
1357 | uint32_t insn; | |
1358 | ||
1359 | /* Restore state and reload the insn we executed, for filling in DSISR. */ | |
1360 | cpu_restore_state(cs, retaddr, true); | |
1361 | insn = cpu_ldl_code(env, env->nip); | |
1362 | ||
1363 | cs->exception_index = POWERPC_EXCP_ALIGN; | |
1364 | env->error_code = insn & 0x03FF0000; | |
1365 | cpu_loop_exit(cs); | |
1366 | } |