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ad71ed68 BS |
1 | /* |
2 | * PowerPC exception emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
ad71ed68 | 20 | #include "cpu.h" |
2ef6175a | 21 | #include "exec/helper-proto.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
f08b6170 | 23 | #include "exec/cpu_ldst.h" |
ad71ed68 BS |
24 | |
25 | #include "helper_regs.h" | |
26 | ||
27 | //#define DEBUG_OP | |
48880da6 | 28 | //#define DEBUG_SOFTWARE_TLB |
ad71ed68 BS |
29 | //#define DEBUG_EXCEPTIONS |
30 | ||
c79c73f6 BS |
31 | #ifdef DEBUG_EXCEPTIONS |
32 | # define LOG_EXCP(...) qemu_log(__VA_ARGS__) | |
33 | #else | |
34 | # define LOG_EXCP(...) do { } while (0) | |
35 | #endif | |
36 | ||
37 | /*****************************************************************************/ | |
38 | /* PowerPC Hypercall emulation */ | |
39 | ||
1b14670a | 40 | void (*cpu_ppc_hypercall)(PowerPCCPU *); |
c79c73f6 BS |
41 | |
42 | /*****************************************************************************/ | |
43 | /* Exception processing */ | |
44 | #if defined(CONFIG_USER_ONLY) | |
97a8ea5a | 45 | void ppc_cpu_do_interrupt(CPUState *cs) |
c79c73f6 | 46 | { |
97a8ea5a AF |
47 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
48 | CPUPPCState *env = &cpu->env; | |
49 | ||
27103424 | 50 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 BS |
51 | env->error_code = 0; |
52 | } | |
53 | ||
458dd766 | 54 | static void ppc_hw_interrupt(CPUPPCState *env) |
c79c73f6 | 55 | { |
27103424 AF |
56 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
57 | ||
58 | cs->exception_index = POWERPC_EXCP_NONE; | |
c79c73f6 BS |
59 | env->error_code = 0; |
60 | } | |
61 | #else /* defined(CONFIG_USER_ONLY) */ | |
62 | static inline void dump_syscall(CPUPPCState *env) | |
63 | { | |
64 | qemu_log_mask(CPU_LOG_INT, "syscall r0=%016" PRIx64 " r3=%016" PRIx64 | |
65 | " r4=%016" PRIx64 " r5=%016" PRIx64 " r6=%016" PRIx64 | |
66 | " nip=" TARGET_FMT_lx "\n", | |
67 | ppc_dump_gpr(env, 0), ppc_dump_gpr(env, 3), | |
68 | ppc_dump_gpr(env, 4), ppc_dump_gpr(env, 5), | |
69 | ppc_dump_gpr(env, 6), env->nip); | |
70 | } | |
71 | ||
72 | /* Note that this function should be greatly optimized | |
73 | * when called with a constant excp, from ppc_hw_interrupt | |
74 | */ | |
5c26a5b3 | 75 | static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) |
c79c73f6 | 76 | { |
27103424 | 77 | CPUState *cs = CPU(cpu); |
5c26a5b3 | 78 | CPUPPCState *env = &cpu->env; |
c79c73f6 | 79 | target_ulong msr, new_msr, vector; |
6d49d6d4 BH |
80 | int srr0, srr1, asrr0, asrr1, lev, ail; |
81 | bool lpes0; | |
c79c73f6 BS |
82 | |
83 | qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx | |
84 | " => %08x (%02x)\n", env->nip, excp, env->error_code); | |
85 | ||
86 | /* new srr1 value excluding must-be-zero bits */ | |
a1bb7384 SW |
87 | if (excp_model == POWERPC_EXCP_BOOKE) { |
88 | msr = env->msr; | |
89 | } else { | |
90 | msr = env->msr & ~0x783f0000ULL; | |
91 | } | |
c79c73f6 | 92 | |
6d49d6d4 BH |
93 | /* new interrupt handler msr preserves existing HV and ME unless |
94 | * explicitly overriden | |
95 | */ | |
96 | new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB); | |
c79c73f6 BS |
97 | |
98 | /* target registers */ | |
99 | srr0 = SPR_SRR0; | |
100 | srr1 = SPR_SRR1; | |
101 | asrr0 = -1; | |
102 | asrr1 = -1; | |
103 | ||
7778a575 BH |
104 | /* check for special resume at 0x100 from doze/nap/sleep/winkle on P7/P8 */ |
105 | if (env->in_pm_state) { | |
106 | env->in_pm_state = false; | |
107 | ||
108 | /* Pretend to be returning from doze always as we don't lose state */ | |
109 | msr |= (0x1ull << (63 - 47)); | |
110 | ||
111 | /* Non-machine check are routed to 0x100 with a wakeup cause | |
112 | * encoded in SRR1 | |
113 | */ | |
114 | if (excp != POWERPC_EXCP_MCHECK) { | |
115 | switch (excp) { | |
116 | case POWERPC_EXCP_RESET: | |
117 | msr |= 0x4ull << (63 - 45); | |
118 | break; | |
119 | case POWERPC_EXCP_EXTERNAL: | |
120 | msr |= 0x8ull << (63 - 45); | |
121 | break; | |
122 | case POWERPC_EXCP_DECR: | |
123 | msr |= 0x6ull << (63 - 45); | |
124 | break; | |
125 | case POWERPC_EXCP_SDOOR: | |
126 | msr |= 0x5ull << (63 - 45); | |
127 | break; | |
128 | case POWERPC_EXCP_SDOOR_HV: | |
129 | msr |= 0x3ull << (63 - 45); | |
130 | break; | |
131 | case POWERPC_EXCP_HV_MAINT: | |
132 | msr |= 0xaull << (63 - 45); | |
133 | break; | |
134 | default: | |
135 | cpu_abort(cs, "Unsupported exception %d in Power Save mode\n", | |
136 | excp); | |
137 | } | |
138 | excp = POWERPC_EXCP_RESET; | |
139 | } | |
140 | } | |
141 | ||
5c94b2a5 | 142 | /* Exception targetting modifiers |
6d49d6d4 BH |
143 | * |
144 | * LPES0 is supported on POWER7/8 | |
145 | * LPES1 is not supported (old iSeries mode) | |
146 | * | |
147 | * On anything else, we behave as if LPES0 is 1 | |
148 | * (externals don't alter MSR:HV) | |
5c94b2a5 CLG |
149 | * |
150 | * AIL is initialized here but can be cleared by | |
151 | * selected exceptions | |
152 | */ | |
153 | #if defined(TARGET_PPC64) | |
154 | if (excp_model == POWERPC_EXCP_POWER7 || | |
155 | excp_model == POWERPC_EXCP_POWER8) { | |
6d49d6d4 | 156 | lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); |
5c94b2a5 CLG |
157 | if (excp_model == POWERPC_EXCP_POWER8) { |
158 | ail = (env->spr[SPR_LPCR] & LPCR_AIL) >> LPCR_AIL_SHIFT; | |
159 | } else { | |
160 | ail = 0; | |
161 | } | |
162 | } else | |
163 | #endif /* defined(TARGET_PPC64) */ | |
164 | { | |
6d49d6d4 | 165 | lpes0 = true; |
5c94b2a5 CLG |
166 | ail = 0; |
167 | } | |
168 | ||
9b2fadda BH |
169 | /* Hypervisor emulation assistance interrupt only exists on server |
170 | * arch 2.05 server or later. We also don't want to generate it if | |
171 | * we don't have HVB in msr_mask (PAPR mode). | |
172 | */ | |
173 | if (excp == POWERPC_EXCP_HV_EMU | |
174 | #if defined(TARGET_PPC64) | |
175 | && !((env->mmu_model & POWERPC_MMU_64) && (env->msr_mask & MSR_HVB)) | |
176 | #endif /* defined(TARGET_PPC64) */ | |
177 | ||
178 | ) { | |
179 | excp = POWERPC_EXCP_PROGRAM; | |
180 | } | |
181 | ||
c79c73f6 BS |
182 | switch (excp) { |
183 | case POWERPC_EXCP_NONE: | |
184 | /* Should never happen */ | |
185 | return; | |
186 | case POWERPC_EXCP_CRITICAL: /* Critical input */ | |
187 | switch (excp_model) { | |
188 | case POWERPC_EXCP_40x: | |
189 | srr0 = SPR_40x_SRR2; | |
190 | srr1 = SPR_40x_SRR3; | |
191 | break; | |
192 | case POWERPC_EXCP_BOOKE: | |
193 | srr0 = SPR_BOOKE_CSRR0; | |
194 | srr1 = SPR_BOOKE_CSRR1; | |
195 | break; | |
196 | case POWERPC_EXCP_G2: | |
197 | break; | |
198 | default: | |
199 | goto excp_invalid; | |
200 | } | |
bd6fefe7 | 201 | break; |
c79c73f6 BS |
202 | case POWERPC_EXCP_MCHECK: /* Machine check exception */ |
203 | if (msr_me == 0) { | |
204 | /* Machine check exception is not enabled. | |
205 | * Enter checkstop state. | |
206 | */ | |
013a2942 PB |
207 | fprintf(stderr, "Machine check while not allowed. " |
208 | "Entering checkstop state\n"); | |
209 | if (qemu_log_separate()) { | |
c79c73f6 BS |
210 | qemu_log("Machine check while not allowed. " |
211 | "Entering checkstop state\n"); | |
c79c73f6 | 212 | } |
259186a7 AF |
213 | cs->halted = 1; |
214 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; | |
c79c73f6 | 215 | } |
10c21b5c NP |
216 | if (env->msr_mask & MSR_HVB) { |
217 | /* ISA specifies HV, but can be delivered to guest with HV clear | |
218 | * (e.g., see FWNMI in PAPR). | |
219 | */ | |
220 | new_msr |= (target_ulong)MSR_HVB; | |
221 | } | |
5c94b2a5 | 222 | ail = 0; |
c79c73f6 BS |
223 | |
224 | /* machine check exceptions don't have ME set */ | |
225 | new_msr &= ~((target_ulong)1 << MSR_ME); | |
226 | ||
227 | /* XXX: should also have something loaded in DAR / DSISR */ | |
228 | switch (excp_model) { | |
229 | case POWERPC_EXCP_40x: | |
230 | srr0 = SPR_40x_SRR2; | |
231 | srr1 = SPR_40x_SRR3; | |
232 | break; | |
233 | case POWERPC_EXCP_BOOKE: | |
a1bb7384 | 234 | /* FIXME: choose one or the other based on CPU type */ |
c79c73f6 BS |
235 | srr0 = SPR_BOOKE_MCSRR0; |
236 | srr1 = SPR_BOOKE_MCSRR1; | |
237 | asrr0 = SPR_BOOKE_CSRR0; | |
238 | asrr1 = SPR_BOOKE_CSRR1; | |
239 | break; | |
240 | default: | |
241 | break; | |
242 | } | |
bd6fefe7 | 243 | break; |
c79c73f6 BS |
244 | case POWERPC_EXCP_DSI: /* Data storage exception */ |
245 | LOG_EXCP("DSI exception: DSISR=" TARGET_FMT_lx" DAR=" TARGET_FMT_lx | |
246 | "\n", env->spr[SPR_DSISR], env->spr[SPR_DAR]); | |
bd6fefe7 | 247 | break; |
c79c73f6 BS |
248 | case POWERPC_EXCP_ISI: /* Instruction storage exception */ |
249 | LOG_EXCP("ISI exception: msr=" TARGET_FMT_lx ", nip=" TARGET_FMT_lx | |
250 | "\n", msr, env->nip); | |
c79c73f6 | 251 | msr |= env->error_code; |
bd6fefe7 | 252 | break; |
c79c73f6 | 253 | case POWERPC_EXCP_EXTERNAL: /* External input */ |
fdfba1a2 EI |
254 | cs = CPU(cpu); |
255 | ||
6d49d6d4 | 256 | if (!lpes0) { |
c79c73f6 | 257 | new_msr |= (target_ulong)MSR_HVB; |
6d49d6d4 BH |
258 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); |
259 | srr0 = SPR_HSRR0; | |
260 | srr1 = SPR_HSRR1; | |
c79c73f6 | 261 | } |
68c2dd70 AG |
262 | if (env->mpic_proxy) { |
263 | /* IACK the IRQ on delivery */ | |
fdfba1a2 | 264 | env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack); |
68c2dd70 | 265 | } |
bd6fefe7 | 266 | break; |
c79c73f6 | 267 | case POWERPC_EXCP_ALIGN: /* Alignment exception */ |
c79c73f6 | 268 | /* Get rS/rD and rA from faulting opcode */ |
3433b732 BH |
269 | /* Note: the opcode fields will not be set properly for a direct |
270 | * store load/store, but nobody cares as nobody actually uses | |
271 | * direct store segments. | |
272 | */ | |
273 | env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; | |
bd6fefe7 | 274 | break; |
c79c73f6 BS |
275 | case POWERPC_EXCP_PROGRAM: /* Program exception */ |
276 | switch (env->error_code & ~0xF) { | |
277 | case POWERPC_EXCP_FP: | |
278 | if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) { | |
279 | LOG_EXCP("Ignore floating point exception\n"); | |
27103424 | 280 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 BS |
281 | env->error_code = 0; |
282 | return; | |
283 | } | |
1b7d17ca BH |
284 | |
285 | /* FP exceptions always have NIP pointing to the faulting | |
286 | * instruction, so always use store_next and claim we are | |
287 | * precise in the MSR. | |
288 | */ | |
c79c73f6 | 289 | msr |= 0x00100000; |
bd6fefe7 | 290 | break; |
c79c73f6 BS |
291 | case POWERPC_EXCP_INVAL: |
292 | LOG_EXCP("Invalid instruction at " TARGET_FMT_lx "\n", env->nip); | |
c79c73f6 BS |
293 | msr |= 0x00080000; |
294 | env->spr[SPR_BOOKE_ESR] = ESR_PIL; | |
295 | break; | |
296 | case POWERPC_EXCP_PRIV: | |
c79c73f6 BS |
297 | msr |= 0x00040000; |
298 | env->spr[SPR_BOOKE_ESR] = ESR_PPR; | |
299 | break; | |
300 | case POWERPC_EXCP_TRAP: | |
c79c73f6 BS |
301 | msr |= 0x00020000; |
302 | env->spr[SPR_BOOKE_ESR] = ESR_PTR; | |
303 | break; | |
304 | default: | |
305 | /* Should never occur */ | |
a47dddd7 | 306 | cpu_abort(cs, "Invalid program exception %d. Aborting\n", |
c79c73f6 BS |
307 | env->error_code); |
308 | break; | |
309 | } | |
bd6fefe7 | 310 | break; |
c79c73f6 BS |
311 | case POWERPC_EXCP_SYSCALL: /* System call exception */ |
312 | dump_syscall(env); | |
313 | lev = env->error_code; | |
6d49d6d4 | 314 | |
bd6fefe7 BH |
315 | /* We need to correct the NIP which in this case is supposed |
316 | * to point to the next instruction | |
317 | */ | |
318 | env->nip += 4; | |
319 | ||
6d49d6d4 | 320 | /* "PAPR mode" built-in hypercall emulation */ |
c79c73f6 | 321 | if ((lev == 1) && cpu_ppc_hypercall) { |
1b14670a | 322 | cpu_ppc_hypercall(cpu); |
c79c73f6 BS |
323 | return; |
324 | } | |
6d49d6d4 | 325 | if (lev == 1) { |
c79c73f6 BS |
326 | new_msr |= (target_ulong)MSR_HVB; |
327 | } | |
bd6fefe7 BH |
328 | break; |
329 | case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */ | |
c79c73f6 | 330 | case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */ |
c79c73f6 | 331 | case POWERPC_EXCP_DECR: /* Decrementer exception */ |
bd6fefe7 | 332 | break; |
c79c73f6 BS |
333 | case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */ |
334 | /* FIT on 4xx */ | |
335 | LOG_EXCP("FIT exception\n"); | |
bd6fefe7 | 336 | break; |
c79c73f6 BS |
337 | case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */ |
338 | LOG_EXCP("WDT exception\n"); | |
339 | switch (excp_model) { | |
340 | case POWERPC_EXCP_BOOKE: | |
341 | srr0 = SPR_BOOKE_CSRR0; | |
342 | srr1 = SPR_BOOKE_CSRR1; | |
343 | break; | |
344 | default: | |
345 | break; | |
346 | } | |
bd6fefe7 | 347 | break; |
c79c73f6 | 348 | case POWERPC_EXCP_DTLB: /* Data TLB error */ |
c79c73f6 | 349 | case POWERPC_EXCP_ITLB: /* Instruction TLB error */ |
bd6fefe7 | 350 | break; |
c79c73f6 BS |
351 | case POWERPC_EXCP_DEBUG: /* Debug interrupt */ |
352 | switch (excp_model) { | |
353 | case POWERPC_EXCP_BOOKE: | |
a1bb7384 | 354 | /* FIXME: choose one or the other based on CPU type */ |
c79c73f6 BS |
355 | srr0 = SPR_BOOKE_DSRR0; |
356 | srr1 = SPR_BOOKE_DSRR1; | |
357 | asrr0 = SPR_BOOKE_CSRR0; | |
358 | asrr1 = SPR_BOOKE_CSRR1; | |
359 | break; | |
360 | default: | |
361 | break; | |
362 | } | |
363 | /* XXX: TODO */ | |
a47dddd7 | 364 | cpu_abort(cs, "Debug exception is not implemented yet !\n"); |
bd6fefe7 | 365 | break; |
c79c73f6 BS |
366 | case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */ |
367 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
bd6fefe7 | 368 | break; |
c79c73f6 BS |
369 | case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */ |
370 | /* XXX: TODO */ | |
a47dddd7 | 371 | cpu_abort(cs, "Embedded floating point data exception " |
c79c73f6 BS |
372 | "is not implemented yet !\n"); |
373 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
bd6fefe7 | 374 | break; |
c79c73f6 BS |
375 | case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */ |
376 | /* XXX: TODO */ | |
a47dddd7 | 377 | cpu_abort(cs, "Embedded floating point round exception " |
c79c73f6 BS |
378 | "is not implemented yet !\n"); |
379 | env->spr[SPR_BOOKE_ESR] = ESR_SPV; | |
bd6fefe7 | 380 | break; |
c79c73f6 BS |
381 | case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */ |
382 | /* XXX: TODO */ | |
a47dddd7 | 383 | cpu_abort(cs, |
c79c73f6 | 384 | "Performance counter exception is not implemented yet !\n"); |
bd6fefe7 | 385 | break; |
c79c73f6 | 386 | case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */ |
bd6fefe7 | 387 | break; |
c79c73f6 BS |
388 | case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */ |
389 | srr0 = SPR_BOOKE_CSRR0; | |
390 | srr1 = SPR_BOOKE_CSRR1; | |
bd6fefe7 | 391 | break; |
c79c73f6 | 392 | case POWERPC_EXCP_RESET: /* System reset exception */ |
f85bcec3 | 393 | /* A power-saving exception sets ME, otherwise it is unchanged */ |
c79c73f6 BS |
394 | if (msr_pow) { |
395 | /* indicate that we resumed from power save mode */ | |
396 | msr |= 0x10000; | |
f85bcec3 | 397 | new_msr |= ((target_ulong)1 << MSR_ME); |
c79c73f6 | 398 | } |
10c21b5c NP |
399 | if (env->msr_mask & MSR_HVB) { |
400 | /* ISA specifies HV, but can be delivered to guest with HV clear | |
401 | * (e.g., see FWNMI in PAPR, NMI injection in QEMU). | |
402 | */ | |
403 | new_msr |= (target_ulong)MSR_HVB; | |
404 | } else { | |
405 | if (msr_pow) { | |
406 | cpu_abort(cs, "Trying to deliver power-saving system reset " | |
407 | "exception %d with no HV support\n", excp); | |
408 | } | |
409 | } | |
5c94b2a5 | 410 | ail = 0; |
bd6fefe7 | 411 | break; |
c79c73f6 | 412 | case POWERPC_EXCP_DSEG: /* Data segment exception */ |
c79c73f6 | 413 | case POWERPC_EXCP_ISEG: /* Instruction segment exception */ |
c79c73f6 | 414 | case POWERPC_EXCP_TRACE: /* Trace exception */ |
bd6fefe7 BH |
415 | break; |
416 | case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */ | |
c79c73f6 | 417 | case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */ |
c79c73f6 | 418 | case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */ |
c79c73f6 | 419 | case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */ |
c79c73f6 | 420 | case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */ |
bd6fefe7 | 421 | case POWERPC_EXCP_HV_EMU: |
c79c73f6 BS |
422 | srr0 = SPR_HSRR0; |
423 | srr1 = SPR_HSRR1; | |
424 | new_msr |= (target_ulong)MSR_HVB; | |
425 | new_msr |= env->msr & ((target_ulong)1 << MSR_RI); | |
bd6fefe7 | 426 | break; |
c79c73f6 | 427 | case POWERPC_EXCP_VPU: /* Vector unavailable exception */ |
1f29871c | 428 | case POWERPC_EXCP_VSXU: /* VSX unavailable exception */ |
7019cb3d | 429 | case POWERPC_EXCP_FU: /* Facility unavailable exception */ |
5310799a BS |
430 | #ifdef TARGET_PPC64 |
431 | env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); | |
432 | #endif | |
bd6fefe7 | 433 | break; |
c79c73f6 BS |
434 | case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ |
435 | LOG_EXCP("PIT exception\n"); | |
bd6fefe7 | 436 | break; |
c79c73f6 BS |
437 | case POWERPC_EXCP_IO: /* IO error exception */ |
438 | /* XXX: TODO */ | |
a47dddd7 | 439 | cpu_abort(cs, "601 IO error exception is not implemented yet !\n"); |
bd6fefe7 | 440 | break; |
c79c73f6 BS |
441 | case POWERPC_EXCP_RUNM: /* Run mode exception */ |
442 | /* XXX: TODO */ | |
a47dddd7 | 443 | cpu_abort(cs, "601 run mode exception is not implemented yet !\n"); |
bd6fefe7 | 444 | break; |
c79c73f6 BS |
445 | case POWERPC_EXCP_EMUL: /* Emulation trap exception */ |
446 | /* XXX: TODO */ | |
a47dddd7 | 447 | cpu_abort(cs, "602 emulation trap exception " |
c79c73f6 | 448 | "is not implemented yet !\n"); |
bd6fefe7 | 449 | break; |
c79c73f6 | 450 | case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */ |
c79c73f6 BS |
451 | switch (excp_model) { |
452 | case POWERPC_EXCP_602: | |
453 | case POWERPC_EXCP_603: | |
454 | case POWERPC_EXCP_603E: | |
455 | case POWERPC_EXCP_G2: | |
456 | goto tlb_miss_tgpr; | |
457 | case POWERPC_EXCP_7x5: | |
458 | goto tlb_miss; | |
459 | case POWERPC_EXCP_74xx: | |
460 | goto tlb_miss_74xx; | |
461 | default: | |
a47dddd7 | 462 | cpu_abort(cs, "Invalid instruction TLB miss exception\n"); |
c79c73f6 BS |
463 | break; |
464 | } | |
465 | break; | |
466 | case POWERPC_EXCP_DLTLB: /* Data load TLB miss */ | |
c79c73f6 BS |
467 | switch (excp_model) { |
468 | case POWERPC_EXCP_602: | |
469 | case POWERPC_EXCP_603: | |
470 | case POWERPC_EXCP_603E: | |
471 | case POWERPC_EXCP_G2: | |
472 | goto tlb_miss_tgpr; | |
473 | case POWERPC_EXCP_7x5: | |
474 | goto tlb_miss; | |
475 | case POWERPC_EXCP_74xx: | |
476 | goto tlb_miss_74xx; | |
477 | default: | |
a47dddd7 | 478 | cpu_abort(cs, "Invalid data load TLB miss exception\n"); |
c79c73f6 BS |
479 | break; |
480 | } | |
481 | break; | |
482 | case POWERPC_EXCP_DSTLB: /* Data store TLB miss */ | |
c79c73f6 BS |
483 | switch (excp_model) { |
484 | case POWERPC_EXCP_602: | |
485 | case POWERPC_EXCP_603: | |
486 | case POWERPC_EXCP_603E: | |
487 | case POWERPC_EXCP_G2: | |
488 | tlb_miss_tgpr: | |
489 | /* Swap temporary saved registers with GPRs */ | |
490 | if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) { | |
491 | new_msr |= (target_ulong)1 << MSR_TGPR; | |
492 | hreg_swap_gpr_tgpr(env); | |
493 | } | |
494 | goto tlb_miss; | |
495 | case POWERPC_EXCP_7x5: | |
496 | tlb_miss: | |
497 | #if defined(DEBUG_SOFTWARE_TLB) | |
498 | if (qemu_log_enabled()) { | |
499 | const char *es; | |
500 | target_ulong *miss, *cmp; | |
501 | int en; | |
502 | ||
503 | if (excp == POWERPC_EXCP_IFTLB) { | |
504 | es = "I"; | |
505 | en = 'I'; | |
506 | miss = &env->spr[SPR_IMISS]; | |
507 | cmp = &env->spr[SPR_ICMP]; | |
508 | } else { | |
509 | if (excp == POWERPC_EXCP_DLTLB) { | |
510 | es = "DL"; | |
511 | } else { | |
512 | es = "DS"; | |
513 | } | |
514 | en = 'D'; | |
515 | miss = &env->spr[SPR_DMISS]; | |
516 | cmp = &env->spr[SPR_DCMP]; | |
517 | } | |
518 | qemu_log("6xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " | |
519 | TARGET_FMT_lx " H1 " TARGET_FMT_lx " H2 " | |
520 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
521 | env->spr[SPR_HASH1], env->spr[SPR_HASH2], | |
522 | env->error_code); | |
523 | } | |
524 | #endif | |
525 | msr |= env->crf[0] << 28; | |
526 | msr |= env->error_code; /* key, D/I, S/L bits */ | |
527 | /* Set way using a LRU mechanism */ | |
528 | msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17; | |
529 | break; | |
530 | case POWERPC_EXCP_74xx: | |
531 | tlb_miss_74xx: | |
532 | #if defined(DEBUG_SOFTWARE_TLB) | |
533 | if (qemu_log_enabled()) { | |
534 | const char *es; | |
535 | target_ulong *miss, *cmp; | |
536 | int en; | |
537 | ||
538 | if (excp == POWERPC_EXCP_IFTLB) { | |
539 | es = "I"; | |
540 | en = 'I'; | |
541 | miss = &env->spr[SPR_TLBMISS]; | |
542 | cmp = &env->spr[SPR_PTEHI]; | |
543 | } else { | |
544 | if (excp == POWERPC_EXCP_DLTLB) { | |
545 | es = "DL"; | |
546 | } else { | |
547 | es = "DS"; | |
548 | } | |
549 | en = 'D'; | |
550 | miss = &env->spr[SPR_TLBMISS]; | |
551 | cmp = &env->spr[SPR_PTEHI]; | |
552 | } | |
553 | qemu_log("74xx %sTLB miss: %cM " TARGET_FMT_lx " %cC " | |
554 | TARGET_FMT_lx " %08x\n", es, en, *miss, en, *cmp, | |
555 | env->error_code); | |
556 | } | |
557 | #endif | |
558 | msr |= env->error_code; /* key bit */ | |
559 | break; | |
560 | default: | |
a47dddd7 | 561 | cpu_abort(cs, "Invalid data store TLB miss exception\n"); |
c79c73f6 BS |
562 | break; |
563 | } | |
bd6fefe7 | 564 | break; |
c79c73f6 BS |
565 | case POWERPC_EXCP_FPA: /* Floating-point assist exception */ |
566 | /* XXX: TODO */ | |
a47dddd7 | 567 | cpu_abort(cs, "Floating point assist exception " |
c79c73f6 | 568 | "is not implemented yet !\n"); |
bd6fefe7 | 569 | break; |
c79c73f6 BS |
570 | case POWERPC_EXCP_DABR: /* Data address breakpoint */ |
571 | /* XXX: TODO */ | |
a47dddd7 | 572 | cpu_abort(cs, "DABR exception is not implemented yet !\n"); |
bd6fefe7 | 573 | break; |
c79c73f6 BS |
574 | case POWERPC_EXCP_IABR: /* Instruction address breakpoint */ |
575 | /* XXX: TODO */ | |
a47dddd7 | 576 | cpu_abort(cs, "IABR exception is not implemented yet !\n"); |
bd6fefe7 | 577 | break; |
c79c73f6 BS |
578 | case POWERPC_EXCP_SMI: /* System management interrupt */ |
579 | /* XXX: TODO */ | |
a47dddd7 | 580 | cpu_abort(cs, "SMI exception is not implemented yet !\n"); |
bd6fefe7 | 581 | break; |
c79c73f6 BS |
582 | case POWERPC_EXCP_THERM: /* Thermal interrupt */ |
583 | /* XXX: TODO */ | |
a47dddd7 | 584 | cpu_abort(cs, "Thermal management exception " |
c79c73f6 | 585 | "is not implemented yet !\n"); |
bd6fefe7 | 586 | break; |
c79c73f6 | 587 | case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */ |
c79c73f6 | 588 | /* XXX: TODO */ |
a47dddd7 | 589 | cpu_abort(cs, |
c79c73f6 | 590 | "Performance counter exception is not implemented yet !\n"); |
bd6fefe7 | 591 | break; |
c79c73f6 BS |
592 | case POWERPC_EXCP_VPUA: /* Vector assist exception */ |
593 | /* XXX: TODO */ | |
a47dddd7 | 594 | cpu_abort(cs, "VPU assist exception is not implemented yet !\n"); |
bd6fefe7 | 595 | break; |
c79c73f6 BS |
596 | case POWERPC_EXCP_SOFTP: /* Soft patch exception */ |
597 | /* XXX: TODO */ | |
a47dddd7 | 598 | cpu_abort(cs, |
c79c73f6 | 599 | "970 soft-patch exception is not implemented yet !\n"); |
bd6fefe7 | 600 | break; |
c79c73f6 BS |
601 | case POWERPC_EXCP_MAINT: /* Maintenance exception */ |
602 | /* XXX: TODO */ | |
a47dddd7 | 603 | cpu_abort(cs, |
c79c73f6 | 604 | "970 maintenance exception is not implemented yet !\n"); |
bd6fefe7 | 605 | break; |
c79c73f6 BS |
606 | case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */ |
607 | /* XXX: TODO */ | |
a47dddd7 | 608 | cpu_abort(cs, "Maskable external exception " |
c79c73f6 | 609 | "is not implemented yet !\n"); |
bd6fefe7 | 610 | break; |
c79c73f6 BS |
611 | case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */ |
612 | /* XXX: TODO */ | |
a47dddd7 | 613 | cpu_abort(cs, "Non maskable external exception " |
c79c73f6 | 614 | "is not implemented yet !\n"); |
bd6fefe7 | 615 | break; |
c79c73f6 BS |
616 | default: |
617 | excp_invalid: | |
a47dddd7 | 618 | cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp); |
c79c73f6 | 619 | break; |
c79c73f6 | 620 | } |
bd6fefe7 BH |
621 | |
622 | /* Save PC */ | |
623 | env->spr[srr0] = env->nip; | |
624 | ||
c79c73f6 BS |
625 | /* Save MSR */ |
626 | env->spr[srr1] = msr; | |
6d49d6d4 BH |
627 | |
628 | /* Sanity check */ | |
10c21b5c NP |
629 | if (!(env->msr_mask & MSR_HVB)) { |
630 | if (new_msr & MSR_HVB) { | |
631 | cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with " | |
632 | "no HV support\n", excp); | |
633 | } | |
634 | if (srr0 == SPR_HSRR0) { | |
635 | cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with " | |
636 | "no HV support\n", excp); | |
637 | } | |
6d49d6d4 BH |
638 | } |
639 | ||
c79c73f6 BS |
640 | /* If any alternate SRR register are defined, duplicate saved values */ |
641 | if (asrr0 != -1) { | |
642 | env->spr[asrr0] = env->spr[srr0]; | |
643 | } | |
644 | if (asrr1 != -1) { | |
645 | env->spr[asrr1] = env->spr[srr1]; | |
646 | } | |
d5ac4f54 | 647 | |
6d49d6d4 BH |
648 | /* Sort out endianness of interrupt, this differs depending on the |
649 | * CPU, the HV mode, etc... | |
650 | */ | |
1e0c7e55 | 651 | #ifdef TARGET_PPC64 |
6d49d6d4 BH |
652 | if (excp_model == POWERPC_EXCP_POWER7) { |
653 | if (!(new_msr & MSR_HVB) && (env->spr[SPR_LPCR] & LPCR_ILE)) { | |
654 | new_msr |= (target_ulong)1 << MSR_LE; | |
655 | } | |
656 | } else if (excp_model == POWERPC_EXCP_POWER8) { | |
657 | if (new_msr & MSR_HVB) { | |
658 | if (env->spr[SPR_HID0] & HID0_HILE) { | |
659 | new_msr |= (target_ulong)1 << MSR_LE; | |
660 | } | |
661 | } else if (env->spr[SPR_LPCR] & LPCR_ILE) { | |
1e0c7e55 AB |
662 | new_msr |= (target_ulong)1 << MSR_LE; |
663 | } | |
664 | } else if (msr_ile) { | |
665 | new_msr |= (target_ulong)1 << MSR_LE; | |
666 | } | |
667 | #else | |
c79c73f6 BS |
668 | if (msr_ile) { |
669 | new_msr |= (target_ulong)1 << MSR_LE; | |
670 | } | |
1e0c7e55 | 671 | #endif |
c79c73f6 BS |
672 | |
673 | /* Jump to handler */ | |
674 | vector = env->excp_vectors[excp]; | |
675 | if (vector == (target_ulong)-1ULL) { | |
a47dddd7 | 676 | cpu_abort(cs, "Raised an exception without defined vector %d\n", |
c79c73f6 BS |
677 | excp); |
678 | } | |
679 | vector |= env->excp_prefix; | |
5c94b2a5 CLG |
680 | |
681 | /* AIL only works if there is no HV transition and we are running with | |
682 | * translations enabled | |
683 | */ | |
6d49d6d4 BH |
684 | if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) || |
685 | ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) { | |
5c94b2a5 CLG |
686 | ail = 0; |
687 | } | |
688 | /* Handle AIL */ | |
689 | if (ail) { | |
690 | new_msr |= (1 << MSR_IR) | (1 << MSR_DR); | |
691 | switch(ail) { | |
692 | case AIL_0001_8000: | |
693 | vector |= 0x18000; | |
694 | break; | |
695 | case AIL_C000_0000_0000_4000: | |
696 | vector |= 0xc000000000004000ull; | |
697 | break; | |
698 | default: | |
699 | cpu_abort(cs, "Invalid AIL combination %d\n", ail); | |
700 | break; | |
701 | } | |
702 | } | |
703 | ||
c79c73f6 BS |
704 | #if defined(TARGET_PPC64) |
705 | if (excp_model == POWERPC_EXCP_BOOKE) { | |
e42a61f1 AG |
706 | if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) { |
707 | /* Cat.64-bit: EPCR.ICM is copied to MSR.CM */ | |
c79c73f6 | 708 | new_msr |= (target_ulong)1 << MSR_CM; |
e42a61f1 AG |
709 | } else { |
710 | vector = (uint32_t)vector; | |
c79c73f6 BS |
711 | } |
712 | } else { | |
713 | if (!msr_isf && !(env->mmu_model & POWERPC_MMU_64)) { | |
714 | vector = (uint32_t)vector; | |
715 | } else { | |
716 | new_msr |= (target_ulong)1 << MSR_SF; | |
717 | } | |
718 | } | |
719 | #endif | |
1c953ba5 BH |
720 | /* We don't use hreg_store_msr here as already have treated |
721 | * any special case that could occur. Just store MSR and update hflags | |
722 | * | |
723 | * Note: We *MUST* not use hreg_store_msr() as-is anyway because it | |
724 | * will prevent setting of the HV bit which some exceptions might need | |
725 | * to do. | |
c79c73f6 BS |
726 | */ |
727 | env->msr = new_msr & env->msr_mask; | |
728 | hreg_compute_hflags(env); | |
729 | env->nip = vector; | |
730 | /* Reset exception state */ | |
27103424 | 731 | cs->exception_index = POWERPC_EXCP_NONE; |
c79c73f6 | 732 | env->error_code = 0; |
cd0c6f47 BH |
733 | |
734 | /* Any interrupt is context synchronizing, check if TCG TLB | |
735 | * needs a delayed flush on ppc64 | |
736 | */ | |
e3cffe6f | 737 | check_tlb_flush(env, false); |
c79c73f6 BS |
738 | } |
739 | ||
97a8ea5a | 740 | void ppc_cpu_do_interrupt(CPUState *cs) |
c79c73f6 | 741 | { |
97a8ea5a AF |
742 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
743 | CPUPPCState *env = &cpu->env; | |
5c26a5b3 | 744 | |
27103424 | 745 | powerpc_excp(cpu, env->excp_model, cs->exception_index); |
c79c73f6 BS |
746 | } |
747 | ||
458dd766 | 748 | static void ppc_hw_interrupt(CPUPPCState *env) |
c79c73f6 | 749 | { |
5c26a5b3 | 750 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
c79c73f6 | 751 | #if 0 |
259186a7 AF |
752 | CPUState *cs = CPU(cpu); |
753 | ||
c79c73f6 | 754 | qemu_log_mask(CPU_LOG_INT, "%s: %p pending %08x req %08x me %d ee %d\n", |
259186a7 AF |
755 | __func__, env, env->pending_interrupts, |
756 | cs->interrupt_request, (int)msr_me, (int)msr_ee); | |
c79c73f6 BS |
757 | #endif |
758 | /* External reset */ | |
759 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { | |
760 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); | |
5c26a5b3 | 761 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); |
c79c73f6 BS |
762 | return; |
763 | } | |
764 | /* Machine check exception */ | |
765 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { | |
766 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); | |
5c26a5b3 | 767 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); |
c79c73f6 BS |
768 | return; |
769 | } | |
770 | #if 0 /* TODO */ | |
771 | /* External debug exception */ | |
772 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { | |
773 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); | |
5c26a5b3 | 774 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG); |
c79c73f6 BS |
775 | return; |
776 | } | |
777 | #endif | |
4b236b62 BH |
778 | /* Hypervisor decrementer exception */ |
779 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { | |
780 | /* LPCR will be clear when not supported so this will work */ | |
781 | bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE); | |
782 | if ((msr_ee != 0 || msr_hv == 0) && hdice) { | |
783 | /* HDEC clears on delivery */ | |
784 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); | |
5c26a5b3 | 785 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR); |
c79c73f6 BS |
786 | return; |
787 | } | |
788 | } | |
d1dbe37c BH |
789 | /* Extermal interrupt can ignore MSR:EE under some circumstances */ |
790 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_EXT)) { | |
791 | bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0); | |
792 | if (msr_ee != 0 || (env->has_hv_mode && msr_hv == 0 && !lpes0)) { | |
793 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL); | |
794 | return; | |
795 | } | |
796 | } | |
c79c73f6 BS |
797 | if (msr_ce != 0) { |
798 | /* External critical interrupt */ | |
799 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) { | |
800 | /* Taking a critical external interrupt does not clear the external | |
801 | * critical interrupt status | |
802 | */ | |
803 | #if 0 | |
804 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT); | |
805 | #endif | |
5c26a5b3 | 806 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL); |
c79c73f6 BS |
807 | return; |
808 | } | |
809 | } | |
810 | if (msr_ee != 0) { | |
811 | /* Watchdog timer on embedded PowerPC */ | |
812 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { | |
813 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); | |
5c26a5b3 | 814 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT); |
c79c73f6 BS |
815 | return; |
816 | } | |
817 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { | |
818 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); | |
5c26a5b3 | 819 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI); |
c79c73f6 BS |
820 | return; |
821 | } | |
822 | /* Fixed interval timer on embedded PowerPC */ | |
823 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { | |
824 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); | |
5c26a5b3 | 825 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT); |
c79c73f6 BS |
826 | return; |
827 | } | |
828 | /* Programmable interval timer on embedded PowerPC */ | |
829 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { | |
830 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); | |
5c26a5b3 | 831 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT); |
c79c73f6 BS |
832 | return; |
833 | } | |
834 | /* Decrementer exception */ | |
835 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { | |
e81a982a AG |
836 | if (ppc_decr_clear_on_delivery(env)) { |
837 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); | |
838 | } | |
5c26a5b3 | 839 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR); |
c79c73f6 BS |
840 | return; |
841 | } | |
c79c73f6 BS |
842 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { |
843 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); | |
5c26a5b3 | 844 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); |
c79c73f6 BS |
845 | return; |
846 | } | |
847 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { | |
848 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); | |
5c26a5b3 | 849 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM); |
c79c73f6 BS |
850 | return; |
851 | } | |
852 | /* Thermal interrupt */ | |
853 | if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { | |
854 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); | |
5c26a5b3 | 855 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); |
c79c73f6 BS |
856 | return; |
857 | } | |
858 | } | |
859 | } | |
34316482 AK |
860 | |
861 | void ppc_cpu_do_system_reset(CPUState *cs) | |
862 | { | |
863 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
864 | CPUPPCState *env = &cpu->env; | |
865 | ||
866 | powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); | |
867 | } | |
c79c73f6 BS |
868 | #endif /* !CONFIG_USER_ONLY */ |
869 | ||
458dd766 RH |
870 | bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) |
871 | { | |
872 | PowerPCCPU *cpu = POWERPC_CPU(cs); | |
873 | CPUPPCState *env = &cpu->env; | |
874 | ||
875 | if (interrupt_request & CPU_INTERRUPT_HARD) { | |
876 | ppc_hw_interrupt(env); | |
877 | if (env->pending_interrupts == 0) { | |
878 | cs->interrupt_request &= ~CPU_INTERRUPT_HARD; | |
879 | } | |
880 | return true; | |
881 | } | |
882 | return false; | |
883 | } | |
884 | ||
c79c73f6 BS |
885 | #if defined(DEBUG_OP) |
886 | static void cpu_dump_rfi(target_ulong RA, target_ulong msr) | |
887 | { | |
888 | qemu_log("Return from exception at " TARGET_FMT_lx " with flags " | |
889 | TARGET_FMT_lx "\n", RA, msr); | |
890 | } | |
891 | #endif | |
892 | ||
ad71ed68 BS |
893 | /*****************************************************************************/ |
894 | /* Exceptions processing helpers */ | |
895 | ||
db789c6c BH |
896 | void raise_exception_err_ra(CPUPPCState *env, uint32_t exception, |
897 | uint32_t error_code, uintptr_t raddr) | |
ad71ed68 | 898 | { |
27103424 AF |
899 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
900 | ||
27103424 | 901 | cs->exception_index = exception; |
ad71ed68 | 902 | env->error_code = error_code; |
db789c6c BH |
903 | cpu_loop_exit_restore(cs, raddr); |
904 | } | |
905 | ||
906 | void raise_exception_err(CPUPPCState *env, uint32_t exception, | |
907 | uint32_t error_code) | |
908 | { | |
909 | raise_exception_err_ra(env, exception, error_code, 0); | |
910 | } | |
911 | ||
912 | void raise_exception(CPUPPCState *env, uint32_t exception) | |
913 | { | |
914 | raise_exception_err_ra(env, exception, 0, 0); | |
915 | } | |
916 | ||
917 | void raise_exception_ra(CPUPPCState *env, uint32_t exception, | |
918 | uintptr_t raddr) | |
919 | { | |
920 | raise_exception_err_ra(env, exception, 0, raddr); | |
921 | } | |
922 | ||
923 | void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, | |
924 | uint32_t error_code) | |
925 | { | |
926 | raise_exception_err_ra(env, exception, error_code, 0); | |
ad71ed68 BS |
927 | } |
928 | ||
e5f17ac6 | 929 | void helper_raise_exception(CPUPPCState *env, uint32_t exception) |
ad71ed68 | 930 | { |
db789c6c | 931 | raise_exception_err_ra(env, exception, 0, 0); |
ad71ed68 BS |
932 | } |
933 | ||
934 | #if !defined(CONFIG_USER_ONLY) | |
e5f17ac6 | 935 | void helper_store_msr(CPUPPCState *env, target_ulong val) |
ad71ed68 | 936 | { |
db789c6c | 937 | uint32_t excp = hreg_store_msr(env, val, 0); |
259186a7 | 938 | |
db789c6c BH |
939 | if (excp != 0) { |
940 | CPUState *cs = CPU(ppc_env_get_cpu(env)); | |
259186a7 | 941 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
db789c6c | 942 | raise_exception(env, excp); |
ad71ed68 BS |
943 | } |
944 | } | |
945 | ||
7778a575 BH |
946 | #if defined(TARGET_PPC64) |
947 | void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn) | |
948 | { | |
949 | CPUState *cs; | |
950 | ||
951 | cs = CPU(ppc_env_get_cpu(env)); | |
952 | cs->halted = 1; | |
953 | env->in_pm_state = true; | |
954 | ||
4b236b62 BH |
955 | /* The architecture specifies that HDEC interrupts are |
956 | * discarded in PM states | |
957 | */ | |
958 | env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); | |
959 | ||
7778a575 BH |
960 | /* Technically, nap doesn't set EE, but if we don't set it |
961 | * then ppc_hw_interrupt() won't deliver. We could add some | |
962 | * other tests there based on LPCR but it's simpler to just | |
963 | * whack EE in. It will be cleared by the 0x100 at wakeup | |
964 | * anyway. It will still be observable by the guest in SRR1 | |
965 | * but this doesn't seem to be a problem. | |
966 | */ | |
967 | env->msr |= (1ull << MSR_EE); | |
db789c6c | 968 | raise_exception(env, EXCP_HLT); |
7778a575 BH |
969 | } |
970 | #endif /* defined(TARGET_PPC64) */ | |
971 | ||
a2e71b28 | 972 | static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) |
ad71ed68 | 973 | { |
259186a7 AF |
974 | CPUState *cs = CPU(ppc_env_get_cpu(env)); |
975 | ||
a2e71b28 BH |
976 | /* MSR:POW cannot be set by any form of rfi */ |
977 | msr &= ~(1ULL << MSR_POW); | |
978 | ||
ad71ed68 | 979 | #if defined(TARGET_PPC64) |
a2e71b28 BH |
980 | /* Switching to 32-bit ? Crop the nip */ |
981 | if (!msr_is_64bit(env, msr)) { | |
ad71ed68 | 982 | nip = (uint32_t)nip; |
ad71ed68 BS |
983 | } |
984 | #else | |
985 | nip = (uint32_t)nip; | |
ad71ed68 BS |
986 | #endif |
987 | /* XXX: beware: this is false if VLE is supported */ | |
988 | env->nip = nip & ~((target_ulong)0x00000003); | |
989 | hreg_store_msr(env, msr, 1); | |
990 | #if defined(DEBUG_OP) | |
991 | cpu_dump_rfi(env->nip, env->msr); | |
992 | #endif | |
993 | /* No need to raise an exception here, | |
994 | * as rfi is always the last insn of a TB | |
995 | */ | |
259186a7 | 996 | cs->interrupt_request |= CPU_INTERRUPT_EXITTB; |
cd0c6f47 BH |
997 | |
998 | /* Context synchronizing: check if TCG TLB needs flush */ | |
e3cffe6f | 999 | check_tlb_flush(env, false); |
ad71ed68 BS |
1000 | } |
1001 | ||
e5f17ac6 | 1002 | void helper_rfi(CPUPPCState *env) |
ad71ed68 | 1003 | { |
a2e71b28 | 1004 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); |
ad71ed68 BS |
1005 | } |
1006 | ||
a2e71b28 | 1007 | #define MSR_BOOK3S_MASK |
ad71ed68 | 1008 | #if defined(TARGET_PPC64) |
e5f17ac6 | 1009 | void helper_rfid(CPUPPCState *env) |
ad71ed68 | 1010 | { |
a2e71b28 BH |
1011 | /* The architeture defines a number of rules for which bits |
1012 | * can change but in practice, we handle this in hreg_store_msr() | |
1013 | * which will be called by do_rfi(), so there is no need to filter | |
1014 | * here | |
1015 | */ | |
1016 | do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1]); | |
ad71ed68 BS |
1017 | } |
1018 | ||
e5f17ac6 | 1019 | void helper_hrfid(CPUPPCState *env) |
ad71ed68 | 1020 | { |
a2e71b28 | 1021 | do_rfi(env, env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); |
ad71ed68 BS |
1022 | } |
1023 | #endif | |
1024 | ||
1025 | /*****************************************************************************/ | |
1026 | /* Embedded PowerPC specific helpers */ | |
e5f17ac6 | 1027 | void helper_40x_rfci(CPUPPCState *env) |
ad71ed68 | 1028 | { |
a2e71b28 | 1029 | do_rfi(env, env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3]); |
ad71ed68 BS |
1030 | } |
1031 | ||
e5f17ac6 | 1032 | void helper_rfci(CPUPPCState *env) |
ad71ed68 | 1033 | { |
a2e71b28 | 1034 | do_rfi(env, env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1]); |
ad71ed68 BS |
1035 | } |
1036 | ||
e5f17ac6 | 1037 | void helper_rfdi(CPUPPCState *env) |
ad71ed68 | 1038 | { |
a1bb7384 | 1039 | /* FIXME: choose CSRR1 or DSRR1 based on cpu type */ |
a2e71b28 | 1040 | do_rfi(env, env->spr[SPR_BOOKE_DSRR0], env->spr[SPR_BOOKE_DSRR1]); |
ad71ed68 BS |
1041 | } |
1042 | ||
e5f17ac6 | 1043 | void helper_rfmci(CPUPPCState *env) |
ad71ed68 | 1044 | { |
a1bb7384 | 1045 | /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ |
a2e71b28 | 1046 | do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
ad71ed68 BS |
1047 | } |
1048 | #endif | |
1049 | ||
e5f17ac6 BS |
1050 | void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
1051 | uint32_t flags) | |
ad71ed68 BS |
1052 | { |
1053 | if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) || | |
1054 | ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) || | |
1055 | ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) || | |
1056 | ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) || | |
1057 | ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) { | |
72073dcc BH |
1058 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
1059 | POWERPC_EXCP_TRAP, GETPC()); | |
ad71ed68 BS |
1060 | } |
1061 | } | |
1062 | ||
1063 | #if defined(TARGET_PPC64) | |
e5f17ac6 BS |
1064 | void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2, |
1065 | uint32_t flags) | |
ad71ed68 BS |
1066 | { |
1067 | if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) || | |
1068 | ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) || | |
1069 | ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) || | |
1070 | ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) || | |
1071 | ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) { | |
72073dcc BH |
1072 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
1073 | POWERPC_EXCP_TRAP, GETPC()); | |
ad71ed68 BS |
1074 | } |
1075 | } | |
1076 | #endif | |
1077 | ||
1078 | #if !defined(CONFIG_USER_ONLY) | |
1079 | /*****************************************************************************/ | |
1080 | /* PowerPC 601 specific instructions (POWER bridge) */ | |
1081 | ||
e5f17ac6 | 1082 | void helper_rfsvc(CPUPPCState *env) |
ad71ed68 | 1083 | { |
a2e71b28 | 1084 | do_rfi(env, env->lr, env->ctr & 0x0000FFFF); |
ad71ed68 BS |
1085 | } |
1086 | ||
1087 | /* Embedded.Processor Control */ | |
1088 | static int dbell2irq(target_ulong rb) | |
1089 | { | |
1090 | int msg = rb & DBELL_TYPE_MASK; | |
1091 | int irq = -1; | |
1092 | ||
1093 | switch (msg) { | |
1094 | case DBELL_TYPE_DBELL: | |
1095 | irq = PPC_INTERRUPT_DOORBELL; | |
1096 | break; | |
1097 | case DBELL_TYPE_DBELL_CRIT: | |
1098 | irq = PPC_INTERRUPT_CDOORBELL; | |
1099 | break; | |
1100 | case DBELL_TYPE_G_DBELL: | |
1101 | case DBELL_TYPE_G_DBELL_CRIT: | |
1102 | case DBELL_TYPE_G_DBELL_MC: | |
1103 | /* XXX implement */ | |
1104 | default: | |
1105 | break; | |
1106 | } | |
1107 | ||
1108 | return irq; | |
1109 | } | |
1110 | ||
e5f17ac6 | 1111 | void helper_msgclr(CPUPPCState *env, target_ulong rb) |
ad71ed68 BS |
1112 | { |
1113 | int irq = dbell2irq(rb); | |
1114 | ||
1115 | if (irq < 0) { | |
1116 | return; | |
1117 | } | |
1118 | ||
1119 | env->pending_interrupts &= ~(1 << irq); | |
1120 | } | |
1121 | ||
1122 | void helper_msgsnd(target_ulong rb) | |
1123 | { | |
1124 | int irq = dbell2irq(rb); | |
1125 | int pir = rb & DBELL_PIRTAG_MASK; | |
182735ef | 1126 | CPUState *cs; |
ad71ed68 BS |
1127 | |
1128 | if (irq < 0) { | |
1129 | return; | |
1130 | } | |
1131 | ||
bdc44640 | 1132 | CPU_FOREACH(cs) { |
182735ef AF |
1133 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
1134 | CPUPPCState *cenv = &cpu->env; | |
1135 | ||
ad71ed68 BS |
1136 | if ((rb & DBELL_BRDCAST) || (cenv->spr[SPR_BOOKE_PIR] == pir)) { |
1137 | cenv->pending_interrupts |= 1 << irq; | |
182735ef | 1138 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
ad71ed68 BS |
1139 | } |
1140 | } | |
1141 | } | |
1142 | #endif |