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target/ppc: Update float_invalid_op_mul for new flags
[mirror_qemu.git] / target / ppc / fpu_helper.c
CommitLineData
bd23cd45
BS		 1/*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
6bd039cd 9 * version 2.1 of the License, or (at your option) any later version.
bd23cd45
BS		 10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
0d75590d 19#include "qemu/osdep.h"
bd23cd45 20#include "cpu.h"
2ef6175a 21#include "exec/helper-proto.h"
a93ecff9 22#include "exec/exec-all.h"
985e3023 23#include "internal.h"
24f91e81 24#include "fpu/softfloat.h"
bd23cd45 25
e5487803
BR		 26static inline float128 float128_snan_to_qnan(float128 x)
27{
28 float128 r;
29
30 r.high = x.high | 0x0000800000000000;
31 r.low = x.low;
32 return r;
33}
34
b748863a
TM		 35#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36#define float32_snan_to_qnan(x) ((x) | 0x00400000)
f566c047 37#define float16_snan_to_qnan(x) ((x) | 0x0200)
b748863a 38
e82c42b7
RH		 39static inline bool fp_exceptions_enabled(CPUPPCState *env)
40{
41#ifdef CONFIG_USER_ONLY
42 return true;
43#else
44 return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
45#endif
46}
47
bd23cd45
BS		 48/*****************************************************************************/
49/* Floating point operations helpers */
86c0cab1
RH		 50
51/*
52 * This is the non-arithmatic conversion that happens e.g. on loads.
53 * In the Power ISA pseudocode, this is called DOUBLE.
54 */
55uint64_t helper_todouble(uint32_t arg)
bd23cd45 56{
86c0cab1
RH		 57 uint32_t abs_arg = arg & 0x7fffffff;
58 uint64_t ret;
bd23cd45 59
86c0cab1 60 if (likely(abs_arg >= 0x00800000)) {
a7b7b983
PC		 61 if (unlikely(extract32(arg, 23, 8) == 0xff)) {
62 /* Inf or NAN. */
63 ret = (uint64_t)extract32(arg, 31, 1) << 63;
64 ret |= (uint64_t)0x7ff << 52;
65 ret |= (uint64_t)extract32(arg, 0, 23) << 29;
66 } else {
67 /* Normalized operand. */
68 ret = (uint64_t)extract32(arg, 30, 2) << 62;
69 ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
70 ret |= (uint64_t)extract32(arg, 0, 30) << 29;
71 }
86c0cab1
RH		 72 } else {
73 /* Zero or Denormalized operand. */
74 ret = (uint64_t)extract32(arg, 31, 1) << 63;
75 if (unlikely(abs_arg != 0)) {
c0e6616b
PC		 76 /*
77 * Denormalized operand.
78 * Shift fraction so that the msb is in the implicit bit position.
79 * Thus, shift is in the range [1:23].
80 */
81 int shift = clz32(abs_arg) - 8;
82 /*
83 * The first 3 terms compute the float64 exponent. We then bias
84 * this result by -1 so that we can swallow the implicit bit below.
85 */
86 int exp = -126 - shift + 1023 - 1;
87
86c0cab1 88 ret |= (uint64_t)exp << 52;
c0e6616b 89 ret += (uint64_t)abs_arg << (52 - 23 + shift);
86c0cab1
RH		 90 }
91 }
92 return ret;
bd23cd45
BS		 93}
94
86c0cab1
RH		 95/*
96 * This is the non-arithmatic conversion that happens e.g. on stores.
97 * In the Power ISA pseudocode, this is called SINGLE.
98 */
99uint32_t helper_tosingle(uint64_t arg)
bd23cd45 100{
86c0cab1
RH		 101 int exp = extract64(arg, 52, 11);
102 uint32_t ret;
bd23cd45 103
86c0cab1
RH		 104 if (likely(exp > 896)) {
105 /* No denormalization required (includes Inf, NaN). */
106 ret = extract64(arg, 62, 2) << 30;
107 ret |= extract64(arg, 29, 30);
108 } else {
fa9ebf8c
DG		 109 /*
110 * Zero or Denormal result. If the exponent is in bounds for
111 * a single-precision denormal result, extract the proper
112 * bits. If the input is not zero, and the exponent is out of
113 * bounds, then the result is undefined; this underflows to
114 * zero.
86c0cab1
RH		 115 */
116 ret = extract64(arg, 63, 1) << 31;
117 if (unlikely(exp >= 874)) {
118 /* Denormal result. */
119 ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
120 }
121 }
122 return ret;
bd23cd45
BS		 123}
124
da29cb7b
TM		 125static inline int ppc_float32_get_unbiased_exp(float32 f)
126{
127 return ((f >> 23) & 0xFF) - 127;
128}
129
130static inline int ppc_float64_get_unbiased_exp(float64 f)
131{
132 return ((f >> 52) & 0x7FF) - 1023;
133}
134
0394d7a6
RH		 135/* Classify a floating-point number. */
136enum {
137 is_normal = 1,
138 is_zero = 2,
139 is_denormal = 4,
140 is_inf = 8,
141 is_qnan = 16,
142 is_snan = 32,
143 is_neg = 64,
144};
145
146#define COMPUTE_CLASS(tp) \
147static int tp##_classify(tp arg) \
ffc67420 148{ \
0394d7a6 149 int ret = tp##_is_neg(arg) * is_neg; \
ffc67420 150 if (unlikely(tp##_is_any_nan(arg))) { \
0394d7a6
RH		 151 float_status dummy = { }; /* snan_bit_is_one = 0 */ \
152 ret |= (tp##_is_signaling_nan(arg, &dummy) \
153 ? is_snan : is_qnan); \
ffc67420 154 } else if (unlikely(tp##_is_infinity(arg))) { \
0394d7a6
RH		 155 ret |= is_inf; \
156 } else if (tp##_is_zero(arg)) { \
157 ret |= is_zero; \
158 } else if (tp##_is_zero_or_denormal(arg)) { \
159 ret |= is_denormal; \
ffc67420 160 } else { \
0394d7a6 161 ret |= is_normal; \
ffc67420 162 } \
0394d7a6
RH		 163 return ret; \
164}
165
166COMPUTE_CLASS(float16)
167COMPUTE_CLASS(float32)
168COMPUTE_CLASS(float64)
169COMPUTE_CLASS(float128)
170
171static void set_fprf_from_class(CPUPPCState *env, int class)
172{
173 static const uint8_t fprf[6][2] = {
174 { 0x04, 0x08 }, /* normalized */
175 { 0x02, 0x12 }, /* zero */
176 { 0x14, 0x18 }, /* denormalized */
177 { 0x05, 0x09 }, /* infinity */
178 { 0x11, 0x11 }, /* qnan */
179 { 0x00, 0x00 }, /* snan -- flags are undefined */
180 };
181 bool isneg = class & is_neg;
182
5c94dd38 183 env->fpscr &= ~FP_FPRF;
0394d7a6
RH		 184 env->fpscr |= fprf[ctz32(class)][isneg] << FPSCR_FPRF;
185}
186
187#define COMPUTE_FPRF(tp) \
188void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
189{ \
190 set_fprf_from_class(env, tp##_classify(arg)); \
ffc67420
BR		 191}
192
f566c047 193COMPUTE_FPRF(float16)
9aeae8e1 194COMPUTE_FPRF(float32)
ffc67420 195COMPUTE_FPRF(float64)
07bdd247 196COMPUTE_FPRF(float128)
bd23cd45
BS		 197
198/* Floating-point invalid operations exception */
13c9115f 199static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
bd23cd45 200{
13c9115f 201 /* Update the floating-point invalid operation summary */
5c94dd38 202 env->fpscr |= FP_VX;
13c9115f
RH		 203 /* Update the floating-point exception summary */
204 env->fpscr |= FP_FX;
205 if (fpscr_ve != 0) {
206 /* Update the floating-point enabled exception summary */
5c94dd38 207 env->fpscr |= FP_FEX;
13c9115f
RH		 208 if (fp_exceptions_enabled(env)) {
209 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
210 POWERPC_EXCP_FP | op, retaddr);
211 }
212 }
213}
bd23cd45 214
13c9115f
RH		 215static void finish_invalid_op_arith(CPUPPCState *env, int op,
216 bool set_fpcc, uintptr_t retaddr)
217{
5c94dd38 218 env->fpscr &= ~(FP_FR | FP_FI);
13c9115f 219 if (fpscr_ve == 0) {
59800ec8 220 if (set_fpcc) {
5c94dd38
PC		 221 env->fpscr &= ~FP_FPCC;
222 env->fpscr |= (FP_C | FP_FU);
59800ec8 223 }
13c9115f
RH		 224 }
225 finish_invalid_op_excp(env, op, retaddr);
226}
227
228/* Signalling NaN */
229static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr)
230{
5c94dd38 231 env->fpscr |= FP_VXSNAN;
13c9115f
RH		 232 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr);
233}
234
235/* Magnitude subtraction of infinities */
236static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc,
237 uintptr_t retaddr)
238{
5c94dd38 239 env->fpscr |= FP_VXISI;
13c9115f
RH		 240 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr);
241}
242
243/* Division of infinity by infinity */
244static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc,
245 uintptr_t retaddr)
246{
5c94dd38 247 env->fpscr |= FP_VXIDI;
13c9115f
RH		 248 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr);
249}
250
251/* Division of zero by zero */
252static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc,
253 uintptr_t retaddr)
254{
5c94dd38 255 env->fpscr |= FP_VXZDZ;
13c9115f
RH		 256 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr);
257}
258
259/* Multiplication of zero by infinity */
260static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc,
261 uintptr_t retaddr)
262{
5c94dd38 263 env->fpscr |= FP_VXIMZ;
13c9115f
RH		 264 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr);
265}
266
267/* Square root of a negative number */
268static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc,
269 uintptr_t retaddr)
270{
5c94dd38 271 env->fpscr |= FP_VXSQRT;
13c9115f
RH		 272 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr);
273}
274
275/* Ordered comparison of NaN */
276static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
277 uintptr_t retaddr)
278{
5c94dd38 279 env->fpscr |= FP_VXVC;
13c9115f 280 if (set_fpcc) {
5c94dd38
PC		 281 env->fpscr &= ~FP_FPCC;
282 env->fpscr |= (FP_C | FP_FU);
bd23cd45
BS		 283 }
284 /* Update the floating-point invalid operation summary */
5c94dd38 285 env->fpscr |= FP_VX;
bd23cd45 286 /* Update the floating-point exception summary */
76247892 287 env->fpscr |= FP_FX;
13c9115f
RH		 288 /* We must update the target FPR before raising the exception */
289 if (fpscr_ve != 0) {
db70b311 290 CPUState *cs = env_cpu(env);
13c9115f
RH		 291
292 cs->exception_index = POWERPC_EXCP_PROGRAM;
293 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
bd23cd45 294 /* Update the floating-point enabled exception summary */
5c94dd38 295 env->fpscr |= FP_FEX;
92eeb004 296 /* Exception is deferred */
13c9115f
RH		 297 }
298}
299
300/* Invalid conversion */
301static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
302 uintptr_t retaddr)
303{
5c94dd38
PC		 304 env->fpscr |= FP_VXCVI;
305 env->fpscr &= ~(FP_FR | FP_FI);
13c9115f
RH		 306 if (fpscr_ve == 0) {
307 if (set_fpcc) {
5c94dd38
PC		 308 env->fpscr &= ~FP_FPCC;
309 env->fpscr |= (FP_C | FP_FU);
bd23cd45
BS		 310 }
311 }
13c9115f 312 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr);
bd23cd45
BS		 313}
314
44f35bd1 315static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
bd23cd45 316{
5c94dd38
PC		 317 env->fpscr |= FP_ZX;
318 env->fpscr &= ~(FP_FR | FP_FI);
bd23cd45 319 /* Update the floating-point exception summary */
76247892 320 env->fpscr |= FP_FX;
bd23cd45
BS		 321 if (fpscr_ze != 0) {
322 /* Update the floating-point enabled exception summary */
5c94dd38 323 env->fpscr |= FP_FEX;
e82c42b7 324 if (fp_exceptions_enabled(env)) {
44f35bd1
BH		 325 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
326 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
327 raddr);
bd23cd45
BS		 328 }
329 }
330}
331
8e703949 332static inline void float_overflow_excp(CPUPPCState *env)
bd23cd45 333{
db70b311 334 CPUState *cs = env_cpu(env);
27103424 335
5c94dd38 336 env->fpscr |= FP_OX;
bd23cd45 337 /* Update the floating-point exception summary */
76247892 338 env->fpscr |= FP_FX;
bd23cd45
BS		 339 if (fpscr_oe != 0) {
340 /* XXX: should adjust the result */
341 /* Update the floating-point enabled exception summary */
5c94dd38 342 env->fpscr |= FP_FEX;
bd23cd45 343 /* We must update the target FPR before raising the exception */
27103424 344 cs->exception_index = POWERPC_EXCP_PROGRAM;
bd23cd45
BS		 345 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
346 } else {
5c94dd38
PC		 347 env->fpscr |= FP_XX;
348 env->fpscr |= FP_FI;
bd23cd45
BS		 349 }
350}
351
8e703949 352static inline void float_underflow_excp(CPUPPCState *env)
bd23cd45 353{
db70b311 354 CPUState *cs = env_cpu(env);
27103424 355
5c94dd38 356 env->fpscr |= FP_UX;
bd23cd45 357 /* Update the floating-point exception summary */
76247892 358 env->fpscr |= FP_FX;
bd23cd45
BS		 359 if (fpscr_ue != 0) {
360 /* XXX: should adjust the result */
361 /* Update the floating-point enabled exception summary */
5c94dd38 362 env->fpscr |= FP_FEX;
bd23cd45 363 /* We must update the target FPR before raising the exception */
27103424 364 cs->exception_index = POWERPC_EXCP_PROGRAM;
bd23cd45
BS		 365 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
366 }
367}
368
8e703949 369static inline void float_inexact_excp(CPUPPCState *env)
bd23cd45 370{
db70b311 371 CPUState *cs = env_cpu(env);
27103424 372
5c94dd38
PC		 373 env->fpscr |= FP_FI;
374 env->fpscr |= FP_XX;
bd23cd45 375 /* Update the floating-point exception summary */
76247892 376 env->fpscr |= FP_FX;
bd23cd45
BS		 377 if (fpscr_xe != 0) {
378 /* Update the floating-point enabled exception summary */
5c94dd38 379 env->fpscr |= FP_FEX;
bd23cd45 380 /* We must update the target FPR before raising the exception */
27103424 381 cs->exception_index = POWERPC_EXCP_PROGRAM;
bd23cd45
BS		 382 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
383 }
384}
385
8e703949 386void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
bd23cd45 387{
fe43ba97
BL		 388 uint32_t mask = 1u << bit;
389 if (env->fpscr & mask) {
390 ppc_store_fpscr(env, env->fpscr & ~(target_ulong)mask);
bd23cd45
BS		 391 }
392}
393
8e703949 394void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
bd23cd45 395{
fe43ba97
BL		 396 uint32_t mask = 1u << bit;
397 if (!(env->fpscr & mask)) {
398 ppc_store_fpscr(env, env->fpscr | mask);
bd23cd45
BS		 399 }
400}
401
fe43ba97 402void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles)
bd23cd45 403{
fe43ba97 404 target_ulong mask = 0;
bd23cd45
BS		 405 int i;
406
fe43ba97 407 /* TODO: push this extension back to translation time */
7d08d856 408 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
fe43ba97
BL		 409 if (nibbles & (1 << i)) {
410 mask |= (target_ulong) 0xf << (4 * i);
bd23cd45
BS		 411 }
412 }
fe43ba97
BL		 413 val = (val & mask) | (env->fpscr & ~mask);
414 ppc_store_fpscr(env, val);
d6478bc7
FC		 415}
416
c3a824b0
LMC		 417void helper_fpscr_check_status(CPUPPCState *env)
418{
419 CPUState *cs = env_cpu(env);
420 target_ulong fpscr = env->fpscr;
421 int error = 0;
422
423 if ((fpscr & FP_OX) && (fpscr & FP_OE)) {
424 error = POWERPC_EXCP_FP_OX;
425 } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) {
426 error = POWERPC_EXCP_FP_UX;
427 } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) {
428 error = POWERPC_EXCP_FP_XX;
429 } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) {
430 error = POWERPC_EXCP_FP_ZX;
431 } else if (fpscr & FP_VE) {
432 if (fpscr & FP_VXSOFT) {
433 error = POWERPC_EXCP_FP_VXSOFT;
434 } else if (fpscr & FP_VXSNAN) {
435 error = POWERPC_EXCP_FP_VXSNAN;
436 } else if (fpscr & FP_VXISI) {
437 error = POWERPC_EXCP_FP_VXISI;
438 } else if (fpscr & FP_VXIDI) {
439 error = POWERPC_EXCP_FP_VXIDI;
440 } else if (fpscr & FP_VXZDZ) {
441 error = POWERPC_EXCP_FP_VXZDZ;
442 } else if (fpscr & FP_VXIMZ) {
443 error = POWERPC_EXCP_FP_VXIMZ;
444 } else if (fpscr & FP_VXVC) {
445 error = POWERPC_EXCP_FP_VXVC;
446 } else if (fpscr & FP_VXSQRT) {
447 error = POWERPC_EXCP_FP_VXSQRT;
448 } else if (fpscr & FP_VXCVI) {
449 error = POWERPC_EXCP_FP_VXCVI;
450 } else {
451 return;
452 }
453 } else {
454 return;
455 }
456 cs->exception_index = POWERPC_EXCP_PROGRAM;
457 env->error_code = error | POWERPC_EXCP_FP;
458 /* Deferred floating-point exception after target FPSCR update */
459 if (fp_exceptions_enabled(env)) {
460 raise_exception_err_ra(env, cs->exception_index,
461 env->error_code, GETPC());
462 }
463}
464
44f35bd1 465static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
bd23cd45 466{
db70b311 467 CPUState *cs = env_cpu(env);
db72c9f2
TG		 468 int status = get_float_exception_flags(&env->fp_status);
469
ae13018d 470 if (status & float_flag_overflow) {
db72c9f2
TG		 471 float_overflow_excp(env);
472 } else if (status & float_flag_underflow) {
473 float_underflow_excp(env);
9e430ca3 474 }
16ce2fff
RH		 475 if (status & float_flag_inexact) {
476 float_inexact_excp(env);
477 } else {
5c94dd38 478 env->fpscr &= ~FP_FI; /* clear the FPSCR[FI] bit */
db72c9f2
TG		 479 }
480
27103424 481 if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
bd23cd45 482 (env->error_code & POWERPC_EXCP_FP)) {
92eeb004 483 /* Deferred floating-point exception after target FPR update */
e82c42b7 484 if (fp_exceptions_enabled(env)) {
44f35bd1
BH		 485 raise_exception_err_ra(env, cs->exception_index,
486 env->error_code, raddr);
bd23cd45 487 }
bd23cd45
BS		 488 }
489}
490
44f35bd1
BH		 491void helper_float_check_status(CPUPPCState *env)
492{
493 do_float_check_status(env, GETPC());
494}
495
8e703949 496void helper_reset_fpstatus(CPUPPCState *env)
bd23cd45
BS		 497{
498 set_float_exception_flags(0, &env->fp_status);
499}
500
941298ec
RH		 501static void float_invalid_op_addsub(CPUPPCState *env, int flags,
502 bool set_fpcc, uintptr_t retaddr)
57483867 503{
941298ec 504 if (flags & float_flag_invalid_isi) {
57483867 505 float_invalid_op_vxisi(env, set_fpcc, retaddr);
941298ec 506 } else if (flags & float_flag_invalid_snan) {
57483867
RH		 507 float_invalid_op_vxsnan(env, retaddr);
508 }
509}
510
bd23cd45 511/* fadd - fadd. */
ac43cec3 512float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
bd23cd45 513{
ac43cec3 514 float64 ret = float64_add(arg1, arg2, &env->fp_status);
941298ec 515 int flags = get_float_exception_flags(&env->fp_status);
bd23cd45 516
941298ec
RH		 517 if (unlikely(flags & float_flag_invalid)) {
518 float_invalid_op_addsub(env, flags, 1, GETPC());
bd23cd45
BS		 519 }
520
ac43cec3 521 return ret;
bd23cd45
BS		 522}
523
524/* fsub - fsub. */
ac43cec3 525float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
bd23cd45 526{
ac43cec3 527 float64 ret = float64_sub(arg1, arg2, &env->fp_status);
941298ec 528 int flags = get_float_exception_flags(&env->fp_status);
bd23cd45 529
941298ec
RH		 530 if (unlikely(flags & float_flag_invalid)) {
531 float_invalid_op_addsub(env, flags, 1, GETPC());
bd23cd45
BS		 532 }
533
ac43cec3 534 return ret;
bd23cd45
BS		 535}
536
4edf5569
RH		 537static void float_invalid_op_mul(CPUPPCState *env, int flags,
538 bool set_fprc, uintptr_t retaddr)
4f0da706 539{
4edf5569 540 if (flags & float_flag_invalid_imz) {
4f0da706 541 float_invalid_op_vximz(env, set_fprc, retaddr);
4edf5569 542 } else if (flags & float_flag_invalid_snan) {
4f0da706
RH		 543 float_invalid_op_vxsnan(env, retaddr);
544 }
545}
546
bd23cd45 547/* fmul - fmul. */
79f91633 548float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
bd23cd45 549{
79f91633 550 float64 ret = float64_mul(arg1, arg2, &env->fp_status);
4edf5569 551 int flags = get_float_exception_flags(&env->fp_status);
bd23cd45 552
4edf5569
RH		 553 if (unlikely(flags & float_flag_invalid)) {
554 float_invalid_op_mul(env, flags, 1, GETPC());
bd23cd45
BS		 555 }
556
79f91633 557 return ret;
bd23cd45
BS		 558}
559
fec59ef3
RH		 560static void float_invalid_op_div(CPUPPCState *env, bool set_fprc,
561 uintptr_t retaddr, int classes)
562{
563 classes &= ~is_neg;
564 if (classes == is_inf) {
565 /* Division of infinity by infinity */
566 float_invalid_op_vxidi(env, set_fprc, retaddr);
567 } else if (classes == is_zero) {
568 /* Division of zero by zero */
569 float_invalid_op_vxzdz(env, set_fprc, retaddr);
570 } else if (classes & is_snan) {
571 float_invalid_op_vxsnan(env, retaddr);
572 }
573}
574
bd23cd45 575/* fdiv - fdiv. */
ae13018d 576float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
bd23cd45 577{
ae13018d
RH		 578 float64 ret = float64_div(arg1, arg2, &env->fp_status);
579 int status = get_float_exception_flags(&env->fp_status);
bd23cd45 580
ae13018d
RH		 581 if (unlikely(status)) {
582 if (status & float_flag_invalid) {
fec59ef3
RH		 583 float_invalid_op_div(env, 1, GETPC(),
584 float64_classify(arg1) |
585 float64_classify(arg2));
ae13018d
RH		 586 }
587 if (status & float_flag_divbyzero) {
588 float_zero_divide_excp(env, GETPC());
bd23cd45 589 }
bd23cd45
BS		 590 }
591
ae13018d 592 return ret;
bd23cd45
BS		 593}
594
a3dec427
RH		 595static void float_invalid_cvt(CPUPPCState *env, bool set_fprc,
596 uintptr_t retaddr, int class1)
597{
598 float_invalid_op_vxcvi(env, set_fprc, retaddr);
599 if (class1 & is_snan) {
600 float_invalid_op_vxsnan(env, retaddr);
601 }
602}
bd23cd45 603
fab7fe42 604#define FPU_FCTI(op, cvt, nanval) \
a3dec427 605uint64_t helper_##op(CPUPPCState *env, float64 arg) \
fab7fe42 606{ \
a3dec427
RH		 607 uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
608 int status = get_float_exception_flags(&env->fp_status); \
fab7fe42 609 \
a3dec427
RH		 610 if (unlikely(status)) { \
611 if (status & float_flag_invalid) { \
612 float_invalid_cvt(env, 1, GETPC(), float64_classify(arg)); \
613 ret = nanval; \
fab7fe42 614 } \
6525aadc 615 do_float_check_status(env, GETPC()); \
fab7fe42 616 } \
a3dec427
RH		 617 return ret; \
618}
fab7fe42 619
7dff9abe
TM		 620FPU_FCTI(fctiw, int32, 0x80000000U)
621FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
622FPU_FCTI(fctiwu, uint32, 0x00000000U)
623FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
7dff9abe
TM		 624FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
625FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
626FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
627FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
bd23cd45 628
28288b48
TM		 629#define FPU_FCFI(op, cvtr, is_single) \
630uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
631{ \
632 CPU_DoubleU farg; \
633 \
634 if (is_single) { \
635 float32 tmp = cvtr(arg, &env->fp_status); \
636 farg.d = float32_to_float64(tmp, &env->fp_status); \
637 } else { \
638 farg.d = cvtr(arg, &env->fp_status); \
639 } \
6525aadc 640 do_float_check_status(env, GETPC()); \
28288b48 641 return farg.ll; \
bd23cd45
BS		 642}
643
28288b48
TM		 644FPU_FCFI(fcfid, int64_to_float64, 0)
645FPU_FCFI(fcfids, int64_to_float32, 1)
646FPU_FCFI(fcfidu, uint64_to_float64, 0)
647FPU_FCFI(fcfidus, uint64_to_float32, 1)
bd23cd45 648
8e703949
BS		 649static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
650 int rounding_mode)
bd23cd45
BS		 651{
652 CPU_DoubleU farg;
63d06e90 653 FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
bd23cd45
BS		 654
655 farg.ll = arg;
656
af39bc8c 657 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
bd23cd45 658 /* sNaN round */
13c9115f 659 float_invalid_op_vxsnan(env, GETPC());
7dff9abe 660 farg.ll = arg | 0x0008000000000000ULL;
bd23cd45 661 } else {
c7386080
TM		 662 int inexact = get_float_exception_flags(&env->fp_status) &
663 float_flag_inexact;
bd23cd45
BS		 664 set_float_rounding_mode(rounding_mode, &env->fp_status);
665 farg.ll = float64_round_to_int(farg.d, &env->fp_status);
63d06e90 666 set_float_rounding_mode(old_rounding_mode, &env->fp_status);
c7386080
TM		 667
668 /* fri* does not set FPSCR[XX] */
669 if (!inexact) {
670 env->fp_status.float_exception_flags &= ~float_flag_inexact;
671 }
bd23cd45 672 }
6525aadc 673 do_float_check_status(env, GETPC());
bd23cd45
BS		 674 return farg.ll;
675}
676
8e703949 677uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
bd23cd45 678{
c7386080 679 return do_fri(env, arg, float_round_ties_away);
bd23cd45
BS		 680}
681
8e703949 682uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
bd23cd45 683{
8e703949 684 return do_fri(env, arg, float_round_to_zero);
bd23cd45
BS		 685}
686
8e703949 687uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
bd23cd45 688{
8e703949 689 return do_fri(env, arg, float_round_up);
bd23cd45
BS		 690}
691
8e703949 692uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
bd23cd45 693{
8e703949 694 return do_fri(env, arg, float_round_down);
bd23cd45
BS		 695}
696
3e5b26cf
ND		 697#define FPU_MADDSUB_UPDATE(NAME, TP) \
698static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3, \
13c9115f 699 unsigned int madd_flags, uintptr_t retaddr) \
3e5b26cf
ND		 700{ \
701 if (TP##_is_signaling_nan(arg1, &env->fp_status) || \
702 TP##_is_signaling_nan(arg2, &env->fp_status) || \
703 TP##_is_signaling_nan(arg3, &env->fp_status)) { \
704 /* sNaN operation */ \
13c9115f 705 float_invalid_op_vxsnan(env, retaddr); \
3e5b26cf
ND		 706 } \
707 if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) || \
708 (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) { \
709 /* Multiplication of zero by infinity */ \
13c9115f 710 float_invalid_op_vximz(env, 1, retaddr); \
3e5b26cf
ND		 711 } \
712 if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) && \
713 TP##_is_infinity(arg3)) { \
714 uint8_t aSign, bSign, cSign; \
715 \
716 aSign = TP##_is_neg(arg1); \
717 bSign = TP##_is_neg(arg2); \
718 cSign = TP##_is_neg(arg3); \
719 if (madd_flags & float_muladd_negate_c) { \
720 cSign ^= 1; \
721 } \
722 if (aSign ^ bSign ^ cSign) { \
13c9115f 723 float_invalid_op_vxisi(env, 1, retaddr); \
3e5b26cf
ND		 724 } \
725 } \
bd23cd45 726}
182fe2cf 727FPU_MADDSUB_UPDATE(float32_maddsub_update_excp, float32)
3e5b26cf 728FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64)
bd23cd45 729
992d7e97
ND		 730#define FPU_FMADD(op, madd_flags) \
731uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
732 uint64_t arg2, uint64_t arg3) \
733{ \
734 uint32_t flags; \
735 float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags, \
736 &env->fp_status); \
737 flags = get_float_exception_flags(&env->fp_status); \
738 if (flags) { \
739 if (flags & float_flag_invalid) { \
740 float64_maddsub_update_excp(env, arg1, arg2, arg3, \
13c9115f 741 madd_flags, GETPC()); \
992d7e97 742 } \
6525aadc 743 do_float_check_status(env, GETPC()); \
992d7e97
ND		 744 } \
745 return ret; \
bd23cd45
BS		 746}
747
992d7e97
ND		 748#define MADD_FLGS 0
749#define MSUB_FLGS float_muladd_negate_c
750#define NMADD_FLGS float_muladd_negate_result
751#define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
bd23cd45 752
992d7e97
ND		 753FPU_FMADD(fmadd, MADD_FLGS)
754FPU_FMADD(fnmadd, NMADD_FLGS)
755FPU_FMADD(fmsub, MSUB_FLGS)
756FPU_FMADD(fnmsub, NMSUB_FLGS)
bd23cd45
BS		 757
758/* frsp - frsp. */
8e703949 759uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 760{
761 CPU_DoubleU farg;
762 float32 f32;
763
764 farg.ll = arg;
765
af39bc8c 766 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
13c9115f 767 float_invalid_op_vxsnan(env, GETPC());
bd23cd45
BS		 768 }
769 f32 = float64_to_float32(farg.d, &env->fp_status);
770 farg.d = float32_to_float64(f32, &env->fp_status);
771
772 return farg.ll;
773}
774
775/* fsqrt - fsqrt. */
49ab52ef 776float64 helper_fsqrt(CPUPPCState *env, float64 arg)
bd23cd45 777{
49ab52ef
RH		 778 float64 ret = float64_sqrt(arg, &env->fp_status);
779 int status = get_float_exception_flags(&env->fp_status);
bd23cd45 780
49ab52ef
RH		 781 if (unlikely(status & float_flag_invalid)) {
782 if (unlikely(float64_is_any_nan(arg))) {
783 if (unlikely(float64_is_signaling_nan(arg, &env->fp_status))) {
784 /* sNaN square root */
13c9115f 785 float_invalid_op_vxsnan(env, GETPC());
49ab52ef
RH		 786 }
787 } else {
788 /* Square root of a negative nonzero number */
13c9115f 789 float_invalid_op_vxsqrt(env, 1, GETPC());
bd23cd45 790 }
bd23cd45 791 }
49ab52ef
RH		 792
793 return ret;
bd23cd45
BS		 794}
795
796/* fre - fre. */
38434717 797float64 helper_fre(CPUPPCState *env, float64 arg)
bd23cd45 798{
38434717
RH		 799 /* "Estimate" the reciprocal with actual division. */
800 float64 ret = float64_div(float64_one, arg, &env->fp_status);
801 int status = get_float_exception_flags(&env->fp_status);
bd23cd45 802
38434717
RH		 803 if (unlikely(status)) {
804 if (status & float_flag_invalid) {
805 if (float64_is_signaling_nan(arg, &env->fp_status)) {
806 /* sNaN reciprocal */
13c9115f 807 float_invalid_op_vxsnan(env, GETPC());
38434717
RH		 808 }
809 }
810 if (status & float_flag_divbyzero) {
811 float_zero_divide_excp(env, GETPC());
812 /* For FPSCR.ZE == 0, the result is 1/2. */
813 ret = float64_set_sign(float64_half, float64_is_neg(arg));
814 }
bd23cd45 815 }
38434717
RH		 816
817 return ret;
bd23cd45
BS		 818}
819
820/* fres - fres. */
8e703949 821uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
bd23cd45
BS		 822{
823 CPU_DoubleU farg;
824 float32 f32;
825
826 farg.ll = arg;
827
af39bc8c 828 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
bd23cd45 829 /* sNaN reciprocal */
13c9115f 830 float_invalid_op_vxsnan(env, GETPC());
bd23cd45
BS		 831 }
832 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
833 f32 = float64_to_float32(farg.d, &env->fp_status);
834 farg.d = float32_to_float64(f32, &env->fp_status);
835
836 return farg.ll;
837}
838
839/* frsqrte - frsqrte. */
38434717 840float64 helper_frsqrte(CPUPPCState *env, float64 arg)
bd23cd45 841{
38434717
RH		 842 /* "Estimate" the reciprocal with actual division. */
843 float64 rets = float64_sqrt(arg, &env->fp_status);
844 float64 retd = float64_div(float64_one, rets, &env->fp_status);
845 int status = get_float_exception_flags(&env->fp_status);
bd23cd45 846
38434717
RH		 847 if (unlikely(status)) {
848 if (status & float_flag_invalid) {
849 if (float64_is_signaling_nan(arg, &env->fp_status)) {
850 /* sNaN reciprocal */
13c9115f 851 float_invalid_op_vxsnan(env, GETPC());
38434717
RH		 852 } else {
853 /* Square root of a negative nonzero number */
13c9115f 854 float_invalid_op_vxsqrt(env, 1, GETPC());
38434717
RH		 855 }
856 }
857 if (status & float_flag_divbyzero) {
858 /* Reciprocal of (square root of) zero. */
859 float_zero_divide_excp(env, GETPC());
bd23cd45 860 }
bd23cd45 861 }
b748863a 862
38434717 863 return retd;
bd23cd45
BS		 864}
865
866/* fsel - fsel. */
8e703949
BS		 867uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
868 uint64_t arg3)
bd23cd45
BS		 869{
870 CPU_DoubleU farg1;
871
872 farg1.ll = arg1;
873
874 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
875 !float64_is_any_nan(farg1.d)) {
876 return arg2;
877 } else {
878 return arg3;
879 }
880}
881
da29cb7b
TM		 882uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
883{
884 int fe_flag = 0;
885 int fg_flag = 0;
886
887 if (unlikely(float64_is_infinity(fra) ||
888 float64_is_infinity(frb) ||
889 float64_is_zero(frb))) {
890 fe_flag = 1;
891 fg_flag = 1;
892 } else {
893 int e_a = ppc_float64_get_unbiased_exp(fra);
894 int e_b = ppc_float64_get_unbiased_exp(frb);
895
896 if (unlikely(float64_is_any_nan(fra) ||
897 float64_is_any_nan(frb))) {
898 fe_flag = 1;
899 } else if ((e_b <= -1022) || (e_b >= 1021)) {
900 fe_flag = 1;
901 } else if (!float64_is_zero(fra) &&
902 (((e_a - e_b) >= 1023) ||
903 ((e_a - e_b) <= -1021) ||
904 (e_a <= -970))) {
905 fe_flag = 1;
906 }
907
908 if (unlikely(float64_is_zero_or_denormal(frb))) {
909 /* XB is not zero because of the above check and */
910 /* so must be denormalized. */
911 fg_flag = 1;
912 }
913 }
914
915 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
916}
6d41d146
TM		 917
918uint32_t helper_ftsqrt(uint64_t frb)
919{
920 int fe_flag = 0;
921 int fg_flag = 0;
922
923 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
924 fe_flag = 1;
925 fg_flag = 1;
926 } else {
927 int e_b = ppc_float64_get_unbiased_exp(frb);
928
929 if (unlikely(float64_is_any_nan(frb))) {
930 fe_flag = 1;
931 } else if (unlikely(float64_is_zero(frb))) {
932 fe_flag = 1;
933 } else if (unlikely(float64_is_neg(frb))) {
934 fe_flag = 1;
fa9ebf8c 935 } else if (!float64_is_zero(frb) && (e_b <= (-1022 + 52))) {
6d41d146
TM		 936 fe_flag = 1;
937 }
938
939 if (unlikely(float64_is_zero_or_denormal(frb))) {
940 /* XB is not zero because of the above check and */
941 /* therefore must be denormalized. */
942 fg_flag = 1;
943 }
944 }
945
946 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
947}
da29cb7b 948
8e703949
BS		 949void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
950 uint32_t crfD)
bd23cd45
BS		 951{
952 CPU_DoubleU farg1, farg2;
953 uint32_t ret = 0;
954
955 farg1.ll = arg1;
956 farg2.ll = arg2;
957
958 if (unlikely(float64_is_any_nan(farg1.d) ||
959 float64_is_any_nan(farg2.d))) {
960 ret = 0x01UL;
961 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
962 ret = 0x08UL;
963 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
964 ret = 0x04UL;
965 } else {
966 ret = 0x02UL;
967 }
968
5c94dd38
PC		 969 env->fpscr &= ~FP_FPCC;
970 env->fpscr |= ret << FPSCR_FPCC;
bd23cd45
BS		 971 env->crf[crfD] = ret;
972 if (unlikely(ret == 0x01UL
af39bc8c
AM		 973 && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
974 float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
bd23cd45 975 /* sNaN comparison */
13c9115f 976 float_invalid_op_vxsnan(env, GETPC());
bd23cd45
BS		 977 }
978}
979
8e703949
BS		 980void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
981 uint32_t crfD)
bd23cd45
BS		 982{
983 CPU_DoubleU farg1, farg2;
984 uint32_t ret = 0;
985
986 farg1.ll = arg1;
987 farg2.ll = arg2;
988
989 if (unlikely(float64_is_any_nan(farg1.d) ||
990 float64_is_any_nan(farg2.d))) {
991 ret = 0x01UL;
992 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
993 ret = 0x08UL;
994 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
995 ret = 0x04UL;
996 } else {
997 ret = 0x02UL;
998 }
999
5c94dd38
PC		 1000 env->fpscr &= ~FP_FPCC;
1001 env->fpscr |= ret << FPSCR_FPCC;
1002 env->crf[crfD] = (uint32_t) ret;
bd23cd45 1003 if (unlikely(ret == 0x01UL)) {
13c9115f 1004 float_invalid_op_vxvc(env, 1, GETPC());
af39bc8c
AM		 1005 if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
1006 float64_is_signaling_nan(farg2.d, &env->fp_status)) {
bd23cd45 1007 /* sNaN comparison */
13c9115f 1008 float_invalid_op_vxsnan(env, GETPC());
bd23cd45
BS		 1009 }
1010 }
1011}
1012
1013/* Single-precision floating-point conversions */
8e703949 1014static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1015{
1016 CPU_FloatU u;
1017
1018 u.f = int32_to_float32(val, &env->vec_status);
1019
1020 return u.l;
1021}
1022
8e703949 1023static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1024{
1025 CPU_FloatU u;
1026
1027 u.f = uint32_to_float32(val, &env->vec_status);
1028
1029 return u.l;
1030}
1031
8e703949 1032static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1033{
1034 CPU_FloatU u;
1035
1036 u.l = val;
1037 /* NaN are not treated the same way IEEE 754 does */
af39bc8c 1038 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
bd23cd45
BS		 1039 return 0;
1040 }
1041
1042 return float32_to_int32(u.f, &env->vec_status);
1043}
1044
8e703949 1045static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1046{
1047 CPU_FloatU u;
1048
1049 u.l = val;
1050 /* NaN are not treated the same way IEEE 754 does */
af39bc8c 1051 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
bd23cd45
BS		 1052 return 0;
1053 }
1054
1055 return float32_to_uint32(u.f, &env->vec_status);
1056}
1057
8e703949 1058static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1059{
1060 CPU_FloatU u;
1061
1062 u.l = val;
1063 /* NaN are not treated the same way IEEE 754 does */
af39bc8c 1064 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
bd23cd45
BS		 1065 return 0;
1066 }
1067
1068 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1069}
1070
8e703949 1071static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1072{
1073 CPU_FloatU u;
1074
1075 u.l = val;
1076 /* NaN are not treated the same way IEEE 754 does */
af39bc8c 1077 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
bd23cd45
BS		 1078 return 0;
1079 }
1080
1081 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1082}
1083
8e703949 1084static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1085{
1086 CPU_FloatU u;
1087 float32 tmp;
1088
1089 u.f = int32_to_float32(val, &env->vec_status);
1090 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1091 u.f = float32_div(u.f, tmp, &env->vec_status);
1092
1093 return u.l;
1094}
1095
8e703949 1096static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1097{
1098 CPU_FloatU u;
1099 float32 tmp;
1100
1101 u.f = uint32_to_float32(val, &env->vec_status);
1102 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1103 u.f = float32_div(u.f, tmp, &env->vec_status);
1104
1105 return u.l;
1106}
1107
8e703949 1108static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1109{
1110 CPU_FloatU u;
1111 float32 tmp;
1112
1113 u.l = val;
1114 /* NaN are not treated the same way IEEE 754 does */
af39bc8c 1115 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
bd23cd45
BS		 1116 return 0;
1117 }
1118 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1119 u.f = float32_mul(u.f, tmp, &env->vec_status);
1120
1121 return float32_to_int32(u.f, &env->vec_status);
1122}
1123
8e703949 1124static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1125{
1126 CPU_FloatU u;
1127 float32 tmp;
1128
1129 u.l = val;
1130 /* NaN are not treated the same way IEEE 754 does */
af39bc8c 1131 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
bd23cd45
BS		 1132 return 0;
1133 }
1134 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1135 u.f = float32_mul(u.f, tmp, &env->vec_status);
1136
1137 return float32_to_uint32(u.f, &env->vec_status);
1138}
1139
8e703949
BS		 1140#define HELPER_SPE_SINGLE_CONV(name) \
1141 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1142 { \
1143 return e##name(env, val); \
bd23cd45
BS		 1144 }
1145/* efscfsi */
1146HELPER_SPE_SINGLE_CONV(fscfsi);
1147/* efscfui */
1148HELPER_SPE_SINGLE_CONV(fscfui);
1149/* efscfuf */
1150HELPER_SPE_SINGLE_CONV(fscfuf);
1151/* efscfsf */
1152HELPER_SPE_SINGLE_CONV(fscfsf);
1153/* efsctsi */
1154HELPER_SPE_SINGLE_CONV(fsctsi);
1155/* efsctui */
1156HELPER_SPE_SINGLE_CONV(fsctui);
1157/* efsctsiz */
1158HELPER_SPE_SINGLE_CONV(fsctsiz);
1159/* efsctuiz */
1160HELPER_SPE_SINGLE_CONV(fsctuiz);
1161/* efsctsf */
1162HELPER_SPE_SINGLE_CONV(fsctsf);
1163/* efsctuf */
1164HELPER_SPE_SINGLE_CONV(fsctuf);
1165
8e703949
BS		 1166#define HELPER_SPE_VECTOR_CONV(name) \
1167 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1168 { \
1169 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1170 (uint64_t)e##name(env, val); \
bd23cd45
BS		 1171 }
1172/* evfscfsi */
1173HELPER_SPE_VECTOR_CONV(fscfsi);
1174/* evfscfui */
1175HELPER_SPE_VECTOR_CONV(fscfui);
1176/* evfscfuf */
1177HELPER_SPE_VECTOR_CONV(fscfuf);
1178/* evfscfsf */
1179HELPER_SPE_VECTOR_CONV(fscfsf);
1180/* evfsctsi */
1181HELPER_SPE_VECTOR_CONV(fsctsi);
1182/* evfsctui */
1183HELPER_SPE_VECTOR_CONV(fsctui);
1184/* evfsctsiz */
1185HELPER_SPE_VECTOR_CONV(fsctsiz);
1186/* evfsctuiz */
1187HELPER_SPE_VECTOR_CONV(fsctuiz);
1188/* evfsctsf */
1189HELPER_SPE_VECTOR_CONV(fsctsf);
1190/* evfsctuf */
1191HELPER_SPE_VECTOR_CONV(fsctuf);
1192
1193/* Single-precision floating-point arithmetic */
8e703949 1194static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1195{
1196 CPU_FloatU u1, u2;
1197
1198 u1.l = op1;
1199 u2.l = op2;
1200 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1201 return u1.l;
1202}
1203
8e703949 1204static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1205{
1206 CPU_FloatU u1, u2;
1207
1208 u1.l = op1;
1209 u2.l = op2;
1210 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1211 return u1.l;
1212}
1213
8e703949 1214static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1215{
1216 CPU_FloatU u1, u2;
1217
1218 u1.l = op1;
1219 u2.l = op2;
1220 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1221 return u1.l;
1222}
1223
8e703949 1224static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1225{
1226 CPU_FloatU u1, u2;
1227
1228 u1.l = op1;
1229 u2.l = op2;
1230 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1231 return u1.l;
1232}
1233
8e703949
BS		 1234#define HELPER_SPE_SINGLE_ARITH(name) \
1235 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1236 { \
1237 return e##name(env, op1, op2); \
bd23cd45
BS		 1238 }
1239/* efsadd */
1240HELPER_SPE_SINGLE_ARITH(fsadd);
1241/* efssub */
1242HELPER_SPE_SINGLE_ARITH(fssub);
1243/* efsmul */
1244HELPER_SPE_SINGLE_ARITH(fsmul);
1245/* efsdiv */
1246HELPER_SPE_SINGLE_ARITH(fsdiv);
1247
1248#define HELPER_SPE_VECTOR_ARITH(name) \
8e703949 1249 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
bd23cd45 1250 { \
8e703949
BS		 1251 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1252 (uint64_t)e##name(env, op1, op2); \
bd23cd45
BS		 1253 }
1254/* evfsadd */
1255HELPER_SPE_VECTOR_ARITH(fsadd);
1256/* evfssub */
1257HELPER_SPE_VECTOR_ARITH(fssub);
1258/* evfsmul */
1259HELPER_SPE_VECTOR_ARITH(fsmul);
1260/* evfsdiv */
1261HELPER_SPE_VECTOR_ARITH(fsdiv);
1262
1263/* Single-precision floating-point comparisons */
8e703949 1264static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1265{
1266 CPU_FloatU u1, u2;
1267
1268 u1.l = op1;
1269 u2.l = op2;
1270 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1271}
1272
8e703949 1273static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1274{
1275 CPU_FloatU u1, u2;
1276
1277 u1.l = op1;
1278 u2.l = op2;
1279 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1280}
1281
8e703949 1282static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1283{
1284 CPU_FloatU u1, u2;
1285
1286 u1.l = op1;
1287 u2.l = op2;
1288 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1289}
1290
8e703949 1291static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1292{
1293 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1294 return efscmplt(env, op1, op2);
bd23cd45
BS		 1295}
1296
8e703949 1297static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1298{
1299 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1300 return efscmpgt(env, op1, op2);
bd23cd45
BS		 1301}
1302
8e703949 1303static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
bd23cd45
BS		 1304{
1305 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
8e703949 1306 return efscmpeq(env, op1, op2);
bd23cd45
BS		 1307}
1308
8e703949
BS		 1309#define HELPER_SINGLE_SPE_CMP(name) \
1310 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1311 { \
a575d9ab 1312 return e##name(env, op1, op2); \
bd23cd45
BS		 1313 }
1314/* efststlt */
1315HELPER_SINGLE_SPE_CMP(fststlt);
1316/* efststgt */
1317HELPER_SINGLE_SPE_CMP(fststgt);
1318/* efststeq */
1319HELPER_SINGLE_SPE_CMP(fststeq);
1320/* efscmplt */
1321HELPER_SINGLE_SPE_CMP(fscmplt);
1322/* efscmpgt */
1323HELPER_SINGLE_SPE_CMP(fscmpgt);
1324/* efscmpeq */
1325HELPER_SINGLE_SPE_CMP(fscmpeq);
1326
1327static inline uint32_t evcmp_merge(int t0, int t1)
1328{
1329 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1330}
1331
1332#define HELPER_VECTOR_SPE_CMP(name) \
8e703949 1333 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
bd23cd45 1334 { \
8e703949
BS		 1335 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1336 e##name(env, op1, op2)); \
bd23cd45
BS		 1337 }
1338/* evfststlt */
1339HELPER_VECTOR_SPE_CMP(fststlt);
1340/* evfststgt */
1341HELPER_VECTOR_SPE_CMP(fststgt);
1342/* evfststeq */
1343HELPER_VECTOR_SPE_CMP(fststeq);
1344/* evfscmplt */
1345HELPER_VECTOR_SPE_CMP(fscmplt);
1346/* evfscmpgt */
1347HELPER_VECTOR_SPE_CMP(fscmpgt);
1348/* evfscmpeq */
1349HELPER_VECTOR_SPE_CMP(fscmpeq);
1350
1351/* Double-precision floating-point conversion */
8e703949 1352uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1353{
1354 CPU_DoubleU u;
1355
1356 u.d = int32_to_float64(val, &env->vec_status);
1357
1358 return u.ll;
1359}
1360
8e703949 1361uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1362{
1363 CPU_DoubleU u;
1364
1365 u.d = int64_to_float64(val, &env->vec_status);
1366
1367 return u.ll;
1368}
1369
8e703949 1370uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1371{
1372 CPU_DoubleU u;
1373
1374 u.d = uint32_to_float64(val, &env->vec_status);
1375
1376 return u.ll;
1377}
1378
8e703949 1379uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1380{
1381 CPU_DoubleU u;
1382
1383 u.d = uint64_to_float64(val, &env->vec_status);
1384
1385 return u.ll;
1386}
1387
8e703949 1388uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1389{
1390 CPU_DoubleU u;
1391
1392 u.ll = val;
1393 /* NaN are not treated the same way IEEE 754 does */
1394 if (unlikely(float64_is_any_nan(u.d))) {
1395 return 0;
1396 }
1397
1398 return float64_to_int32(u.d, &env->vec_status);
1399}
1400
8e703949 1401uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1402{
1403 CPU_DoubleU u;
1404
1405 u.ll = val;
1406 /* NaN are not treated the same way IEEE 754 does */
1407 if (unlikely(float64_is_any_nan(u.d))) {
1408 return 0;
1409 }
1410
1411 return float64_to_uint32(u.d, &env->vec_status);
1412}
1413
8e703949 1414uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1415{
1416 CPU_DoubleU u;
1417
1418 u.ll = val;
1419 /* NaN are not treated the same way IEEE 754 does */
1420 if (unlikely(float64_is_any_nan(u.d))) {
1421 return 0;
1422 }
1423
1424 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1425}
1426
8e703949 1427uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1428{
1429 CPU_DoubleU u;
1430
1431 u.ll = val;
1432 /* NaN are not treated the same way IEEE 754 does */
1433 if (unlikely(float64_is_any_nan(u.d))) {
1434 return 0;
1435 }
1436
1437 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1438}
1439
8e703949 1440uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1441{
1442 CPU_DoubleU u;
1443
1444 u.ll = val;
1445 /* NaN are not treated the same way IEEE 754 does */
1446 if (unlikely(float64_is_any_nan(u.d))) {
1447 return 0;
1448 }
1449
1450 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1451}
1452
8e703949 1453uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1454{
1455 CPU_DoubleU u;
1456
1457 u.ll = val;
1458 /* NaN are not treated the same way IEEE 754 does */
1459 if (unlikely(float64_is_any_nan(u.d))) {
1460 return 0;
1461 }
1462
1463 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1464}
1465
8e703949 1466uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1467{
1468 CPU_DoubleU u;
1469 float64 tmp;
1470
1471 u.d = int32_to_float64(val, &env->vec_status);
1472 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1473 u.d = float64_div(u.d, tmp, &env->vec_status);
1474
1475 return u.ll;
1476}
1477
8e703949 1478uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1479{
1480 CPU_DoubleU u;
1481 float64 tmp;
1482
1483 u.d = uint32_to_float64(val, &env->vec_status);
1484 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1485 u.d = float64_div(u.d, tmp, &env->vec_status);
1486
1487 return u.ll;
1488}
1489
8e703949 1490uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1491{
1492 CPU_DoubleU u;
1493 float64 tmp;
1494
1495 u.ll = val;
1496 /* NaN are not treated the same way IEEE 754 does */
1497 if (unlikely(float64_is_any_nan(u.d))) {
1498 return 0;
1499 }
1500 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1501 u.d = float64_mul(u.d, tmp, &env->vec_status);
1502
1503 return float64_to_int32(u.d, &env->vec_status);
1504}
1505
8e703949 1506uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1507{
1508 CPU_DoubleU u;
1509 float64 tmp;
1510
1511 u.ll = val;
1512 /* NaN are not treated the same way IEEE 754 does */
1513 if (unlikely(float64_is_any_nan(u.d))) {
1514 return 0;
1515 }
1516 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1517 u.d = float64_mul(u.d, tmp, &env->vec_status);
1518
1519 return float64_to_uint32(u.d, &env->vec_status);
1520}
1521
8e703949 1522uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
bd23cd45
BS		 1523{
1524 CPU_DoubleU u1;
1525 CPU_FloatU u2;
1526
1527 u1.ll = val;
1528 u2.f = float64_to_float32(u1.d, &env->vec_status);
1529
1530 return u2.l;
1531}
1532
8e703949 1533uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
bd23cd45
BS		 1534{
1535 CPU_DoubleU u2;
1536 CPU_FloatU u1;
1537
1538 u1.l = val;
1539 u2.d = float32_to_float64(u1.f, &env->vec_status);
1540
1541 return u2.ll;
1542}
1543
1544/* Double precision fixed-point arithmetic */
8e703949 1545uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1546{
1547 CPU_DoubleU u1, u2;
1548
1549 u1.ll = op1;
1550 u2.ll = op2;
1551 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1552 return u1.ll;
1553}
1554
8e703949 1555uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1556{
1557 CPU_DoubleU u1, u2;
1558
1559 u1.ll = op1;
1560 u2.ll = op2;
1561 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1562 return u1.ll;
1563}
1564
8e703949 1565uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1566{
1567 CPU_DoubleU u1, u2;
1568
1569 u1.ll = op1;
1570 u2.ll = op2;
1571 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1572 return u1.ll;
1573}
1574
8e703949 1575uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1576{
1577 CPU_DoubleU u1, u2;
1578
1579 u1.ll = op1;
1580 u2.ll = op2;
1581 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1582 return u1.ll;
1583}
1584
1585/* Double precision floating point helpers */
8e703949 1586uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1587{
1588 CPU_DoubleU u1, u2;
1589
1590 u1.ll = op1;
1591 u2.ll = op2;
1592 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1593}
1594
8e703949 1595uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1596{
1597 CPU_DoubleU u1, u2;
1598
1599 u1.ll = op1;
1600 u2.ll = op2;
1601 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1602}
1603
8e703949 1604uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1605{
1606 CPU_DoubleU u1, u2;
1607
1608 u1.ll = op1;
1609 u2.ll = op2;
1610 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1611}
1612
8e703949 1613uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1614{
1615 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1616 return helper_efdtstlt(env, op1, op2);
bd23cd45
BS		 1617}
1618
8e703949 1619uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1620{
1621 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1622 return helper_efdtstgt(env, op1, op2);
bd23cd45
BS		 1623}
1624
8e703949 1625uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
bd23cd45
BS		 1626{
1627 /* XXX: TODO: test special values (NaN, infinites, ...) */
8e703949 1628 return helper_efdtsteq(env, op1, op2);
bd23cd45 1629}
3c3cbbdc 1630
3c3cbbdc 1631#define float64_to_float64(x, env) x
ee6e02c0
TM		 1632
1633
fa9ebf8c 1634/*
136fbf65 1635 * VSX_ADD_SUB - VSX floating point add/subtract
ee6e02c0
TM		 1636 * name - instruction mnemonic
1637 * op - operation (add or sub)
1638 * nels - number of elements (1, 2 or 4)
1639 * tp - type (float32 or float64)
bcb7652e 1640 * fld - vsr_t field (VsrD(*) or VsrW(*))
ee6e02c0
TM		 1641 * sfprf - set FPRF
1642 */
3fd0aadf 1643#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
99125c74
MCA		 1644void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
1645 ppc_vsr_t *xa, ppc_vsr_t *xb) \
ee6e02c0 1646{ \
cf3b0334 1647 ppc_vsr_t t = *xt; \
ee6e02c0
TM		 1648 int i; \
1649 \
ee6e02c0
TM		 1650 helper_reset_fpstatus(env); \
1651 \
1652 for (i = 0; i < nels; i++) { \
1653 float_status tstat = env->fp_status; \
1654 set_float_exception_flags(0, &tstat); \
cf3b0334 1655 t.fld = tp##_##op(xa->fld, xb->fld, &tstat); \
ee6e02c0
TM		 1656 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1657 \
1658 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
941298ec
RH		 1659 float_invalid_op_addsub(env, tstat.float_exception_flags, \
1660 sfprf, GETPC()); \
ee6e02c0
TM		 1661 } \
1662 \
3fd0aadf 1663 if (r2sp) { \
cf3b0334 1664 t.fld = helper_frsp(env, t.fld); \
3fd0aadf
TM		 1665 } \
1666 \
ee6e02c0 1667 if (sfprf) { \
cf3b0334 1668 helper_compute_fprf_float64(env, t.fld); \
ee6e02c0
TM		 1669 } \
1670 } \
cf3b0334 1671 *xt = t; \
6525aadc 1672 do_float_check_status(env, GETPC()); \
ee6e02c0
TM		 1673}
1674
bcb7652e
TM		 1675VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1676VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1677VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1678VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1679VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1680VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1681VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1682VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
5e591d88 1683
23d0766b
MCA		 1684void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
1685 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
07bdd247 1686{
cf3b0334 1687 ppc_vsr_t t = *xt;
07bdd247
BR		 1688 float_status tstat;
1689
07bdd247
BR		 1690 helper_reset_fpstatus(env);
1691
a8d411ab 1692 tstat = env->fp_status;
07bdd247 1693 if (unlikely(Rc(opcode) != 0)) {
a8d411ab 1694 tstat.float_rounding_mode = float_round_to_odd;
07bdd247
BR		 1695 }
1696
07bdd247 1697 set_float_exception_flags(0, &tstat);
cf3b0334 1698 t.f128 = float128_add(xa->f128, xb->f128, &tstat);
07bdd247
BR		 1699 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1700
1701 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
941298ec 1702 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
07bdd247
BR		 1703 }
1704
cf3b0334 1705 helper_compute_fprf_float128(env, t.f128);
07bdd247 1706
cf3b0334 1707 *xt = t;
6525aadc 1708 do_float_check_status(env, GETPC());
07bdd247
BR		 1709}
1710
fa9ebf8c
DG		 1711/*
1712 * VSX_MUL - VSX floating point multiply
5e591d88
TM		 1713 * op - instruction mnemonic
1714 * nels - number of elements (1, 2 or 4)
1715 * tp - type (float32 or float64)
bcb7652e 1716 * fld - vsr_t field (VsrD(*) or VsrW(*))
5e591d88
TM		 1717 * sfprf - set FPRF
1718 */
ab9408a2 1719#define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
99125c74
MCA		 1720void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1721 ppc_vsr_t *xa, ppc_vsr_t *xb) \
5e591d88 1722{ \
cf3b0334 1723 ppc_vsr_t t = *xt; \
5e591d88
TM		 1724 int i; \
1725 \
5e591d88
TM		 1726 helper_reset_fpstatus(env); \
1727 \
1728 for (i = 0; i < nels; i++) { \
1729 float_status tstat = env->fp_status; \
1730 set_float_exception_flags(0, &tstat); \
cf3b0334 1731 t.fld = tp##_mul(xa->fld, xb->fld, &tstat); \
5e591d88
TM		 1732 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1733 \
1734 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
4edf5569
RH		 1735 float_invalid_op_mul(env, tstat.float_exception_flags, \
1736 sfprf, GETPC()); \
5e591d88
TM		 1737 } \
1738 \
ab9408a2 1739 if (r2sp) { \
cf3b0334 1740 t.fld = helper_frsp(env, t.fld); \
ab9408a2
TM		 1741 } \
1742 \
5e591d88 1743 if (sfprf) { \
cf3b0334 1744 helper_compute_fprf_float64(env, t.fld); \
5e591d88
TM		 1745 } \
1746 } \
1747 \
cf3b0334 1748 *xt = t; \
6525aadc 1749 do_float_check_status(env, GETPC()); \
5e591d88
TM		 1750}
1751
bcb7652e
TM		 1752VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1753VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1754VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1755VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
4b98eeef 1756
23d0766b
MCA		 1757void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
1758 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
a811ec04 1759{
cf3b0334 1760 ppc_vsr_t t = *xt;
a8d411ab 1761 float_status tstat;
a811ec04 1762
a8d411ab
BR		 1763 helper_reset_fpstatus(env);
1764 tstat = env->fp_status;
a811ec04 1765 if (unlikely(Rc(opcode) != 0)) {
a8d411ab 1766 tstat.float_rounding_mode = float_round_to_odd;
a811ec04
BR		 1767 }
1768
a811ec04 1769 set_float_exception_flags(0, &tstat);
cf3b0334 1770 t.f128 = float128_mul(xa->f128, xb->f128, &tstat);
a811ec04
BR		 1771 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1772
1773 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
4edf5569 1774 float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC());
a811ec04 1775 }
cf3b0334 1776 helper_compute_fprf_float128(env, t.f128);
a811ec04 1777
cf3b0334 1778 *xt = t;
6525aadc 1779 do_float_check_status(env, GETPC());
a811ec04
BR		 1780}
1781
fa9ebf8c
DG		 1782/*
1783 * VSX_DIV - VSX floating point divide
4b98eeef
TM		 1784 * op - instruction mnemonic
1785 * nels - number of elements (1, 2 or 4)
1786 * tp - type (float32 or float64)
bcb7652e 1787 * fld - vsr_t field (VsrD(*) or VsrW(*))
4b98eeef
TM		 1788 * sfprf - set FPRF
1789 */
b24d0b47 1790#define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
99125c74
MCA		 1791void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1792 ppc_vsr_t *xa, ppc_vsr_t *xb) \
4b98eeef 1793{ \
cf3b0334 1794 ppc_vsr_t t = *xt; \
4b98eeef
TM		 1795 int i; \
1796 \
4b98eeef
TM		 1797 helper_reset_fpstatus(env); \
1798 \
1799 for (i = 0; i < nels; i++) { \
1800 float_status tstat = env->fp_status; \
1801 set_float_exception_flags(0, &tstat); \
cf3b0334 1802 t.fld = tp##_div(xa->fld, xb->fld, &tstat); \
4b98eeef
TM		 1803 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1804 \
1805 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
fec59ef3 1806 float_invalid_op_div(env, sfprf, GETPC(), \
cf3b0334
MCA		 1807 tp##_classify(xa->fld) | \
1808 tp##_classify(xb->fld)); \
ae13018d
RH		 1809 } \
1810 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1811 float_zero_divide_excp(env, GETPC()); \
4b98eeef
TM		 1812 } \
1813 \
b24d0b47 1814 if (r2sp) { \
cf3b0334 1815 t.fld = helper_frsp(env, t.fld); \
b24d0b47
TM		 1816 } \
1817 \
4b98eeef 1818 if (sfprf) { \
cf3b0334 1819 helper_compute_fprf_float64(env, t.fld); \
4b98eeef
TM		 1820 } \
1821 } \
1822 \
cf3b0334 1823 *xt = t; \
6525aadc 1824 do_float_check_status(env, GETPC()); \
4b98eeef
TM		 1825}
1826
bcb7652e
TM		 1827VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1828VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1829VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1830VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
2009227f 1831
23d0766b
MCA		 1832void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
1833 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
314c1163 1834{
cf3b0334 1835 ppc_vsr_t t = *xt;
a8d411ab 1836 float_status tstat;
314c1163 1837
a8d411ab
BR		 1838 helper_reset_fpstatus(env);
1839 tstat = env->fp_status;
314c1163 1840 if (unlikely(Rc(opcode) != 0)) {
a8d411ab 1841 tstat.float_rounding_mode = float_round_to_odd;
314c1163
BR		 1842 }
1843
314c1163 1844 set_float_exception_flags(0, &tstat);
cf3b0334 1845 t.f128 = float128_div(xa->f128, xb->f128, &tstat);
314c1163
BR		 1846 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1847
1848 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
fec59ef3 1849 float_invalid_op_div(env, 1, GETPC(),
cf3b0334
MCA		 1850 float128_classify(xa->f128) |
1851 float128_classify(xb->f128));
314c1163 1852 }
ae13018d
RH		 1853 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
1854 float_zero_divide_excp(env, GETPC());
1855 }
314c1163 1856
cf3b0334
MCA		 1857 helper_compute_fprf_float128(env, t.f128);
1858 *xt = t;
6525aadc 1859 do_float_check_status(env, GETPC());
314c1163
BR		 1860}
1861
fa9ebf8c
DG		 1862/*
1863 * VSX_RE - VSX floating point reciprocal estimate
2009227f
TM		 1864 * op - instruction mnemonic
1865 * nels - number of elements (1, 2 or 4)
1866 * tp - type (float32 or float64)
bcb7652e 1867 * fld - vsr_t field (VsrD(*) or VsrW(*))
2009227f
TM		 1868 * sfprf - set FPRF
1869 */
2c0c52ae 1870#define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
75cf84cb 1871void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2009227f 1872{ \
cf3b0334 1873 ppc_vsr_t t = *xt; \
2009227f
TM		 1874 int i; \
1875 \
2009227f
TM		 1876 helper_reset_fpstatus(env); \
1877 \
1878 for (i = 0; i < nels; i++) { \
cf3b0334 1879 if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
13c9115f 1880 float_invalid_op_vxsnan(env, GETPC()); \
2009227f 1881 } \
cf3b0334 1882 t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
2c0c52ae
TM		 1883 \
1884 if (r2sp) { \
cf3b0334 1885 t.fld = helper_frsp(env, t.fld); \
2c0c52ae
TM		 1886 } \
1887 \
2009227f 1888 if (sfprf) { \
cf3b0334 1889 helper_compute_fprf_float64(env, t.fld); \
2009227f
TM		 1890 } \
1891 } \
1892 \
cf3b0334 1893 *xt = t; \
6525aadc 1894 do_float_check_status(env, GETPC()); \
2009227f
TM		 1895}
1896
bcb7652e
TM		 1897VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
1898VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
1899VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
1900VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
d32404fe 1901
fa9ebf8c
DG		 1902/*
1903 * VSX_SQRT - VSX floating point square root
d32404fe
TM		 1904 * op - instruction mnemonic
1905 * nels - number of elements (1, 2 or 4)
1906 * tp - type (float32 or float64)
bcb7652e 1907 * fld - vsr_t field (VsrD(*) or VsrW(*))
d32404fe
TM		 1908 * sfprf - set FPRF
1909 */
cea4e574 1910#define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
75cf84cb 1911void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
d32404fe 1912{ \
cf3b0334 1913 ppc_vsr_t t = *xt; \
d32404fe
TM		 1914 int i; \
1915 \
d32404fe
TM		 1916 helper_reset_fpstatus(env); \
1917 \
1918 for (i = 0; i < nels; i++) { \
1919 float_status tstat = env->fp_status; \
1920 set_float_exception_flags(0, &tstat); \
cf3b0334 1921 t.fld = tp##_sqrt(xb->fld, &tstat); \
d32404fe
TM		 1922 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1923 \
1924 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
cf3b0334 1925 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
13c9115f 1926 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
cf3b0334 1927 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
13c9115f 1928 float_invalid_op_vxsnan(env, GETPC()); \
d32404fe
TM		 1929 } \
1930 } \
1931 \
cea4e574 1932 if (r2sp) { \
cf3b0334 1933 t.fld = helper_frsp(env, t.fld); \
cea4e574
TM		 1934 } \
1935 \
d32404fe 1936 if (sfprf) { \
cf3b0334 1937 helper_compute_fprf_float64(env, t.fld); \
d32404fe
TM		 1938 } \
1939 } \
1940 \
cf3b0334 1941 *xt = t; \
6525aadc 1942 do_float_check_status(env, GETPC()); \
d32404fe
TM		 1943}
1944
bcb7652e
TM		 1945VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
1946VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
1947VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
1948VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
d3f9df8f 1949
fa9ebf8c
DG		 1950/*
1951 *VSX_RSQRTE - VSX floating point reciprocal square root estimate
d3f9df8f
TM		 1952 * op - instruction mnemonic
1953 * nels - number of elements (1, 2 or 4)
1954 * tp - type (float32 or float64)
bcb7652e 1955 * fld - vsr_t field (VsrD(*) or VsrW(*))
d3f9df8f
TM		 1956 * sfprf - set FPRF
1957 */
968e76bc 1958#define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
75cf84cb 1959void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
d3f9df8f 1960{ \
cf3b0334 1961 ppc_vsr_t t = *xt; \
d3f9df8f
TM		 1962 int i; \
1963 \
d3f9df8f
TM		 1964 helper_reset_fpstatus(env); \
1965 \
1966 for (i = 0; i < nels; i++) { \
1967 float_status tstat = env->fp_status; \
1968 set_float_exception_flags(0, &tstat); \
cf3b0334
MCA		 1969 t.fld = tp##_sqrt(xb->fld, &tstat); \
1970 t.fld = tp##_div(tp##_one, t.fld, &tstat); \
d3f9df8f
TM		 1971 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1972 \
1973 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
cf3b0334 1974 if (tp##_is_neg(xb->fld) && !tp##_is_zero(xb->fld)) { \
13c9115f 1975 float_invalid_op_vxsqrt(env, sfprf, GETPC()); \
cf3b0334 1976 } else if (tp##_is_signaling_nan(xb->fld, &tstat)) { \
13c9115f 1977 float_invalid_op_vxsnan(env, GETPC()); \
d3f9df8f
TM		 1978 } \
1979 } \
1980 \
968e76bc 1981 if (r2sp) { \
cf3b0334 1982 t.fld = helper_frsp(env, t.fld); \
968e76bc
TM		 1983 } \
1984 \
d3f9df8f 1985 if (sfprf) { \
cf3b0334 1986 helper_compute_fprf_float64(env, t.fld); \
d3f9df8f
TM		 1987 } \
1988 } \
1989 \
cf3b0334 1990 *xt = t; \
6525aadc 1991 do_float_check_status(env, GETPC()); \
d3f9df8f
TM		 1992}
1993
bcb7652e
TM		 1994VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
1995VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
1996VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
1997VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
bc80838f 1998
fa9ebf8c
DG		 1999/*
2000 * VSX_TDIV - VSX floating point test for divide
bc80838f
TM		 2001 * op - instruction mnemonic
2002 * nels - number of elements (1, 2 or 4)
2003 * tp - type (float32 or float64)
bcb7652e 2004 * fld - vsr_t field (VsrD(*) or VsrW(*))
bc80838f
TM		 2005 * emin - minimum unbiased exponent
2006 * emax - maximum unbiased exponent
2007 * nbits - number of fraction bits
2008 */
2009#define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
033e1fcd
MCA		 2010void helper_##op(CPUPPCState *env, uint32_t opcode, \
2011 ppc_vsr_t *xa, ppc_vsr_t *xb) \
bc80838f 2012{ \
bc80838f
TM		 2013 int i; \
2014 int fe_flag = 0; \
2015 int fg_flag = 0; \
2016 \
bc80838f 2017 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 2018 if (unlikely(tp##_is_infinity(xa->fld) || \
2019 tp##_is_infinity(xb->fld) || \
2020 tp##_is_zero(xb->fld))) { \
bc80838f
TM		 2021 fe_flag = 1; \
2022 fg_flag = 1; \
2023 } else { \
cf3b0334
MCA		 2024 int e_a = ppc_##tp##_get_unbiased_exp(xa->fld); \
2025 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
bc80838f 2026 \
cf3b0334
MCA		 2027 if (unlikely(tp##_is_any_nan(xa->fld) || \
2028 tp##_is_any_nan(xb->fld))) { \
bc80838f 2029 fe_flag = 1; \
fa9ebf8c 2030 } else if ((e_b <= emin) || (e_b >= (emax - 2))) { \
bc80838f 2031 fe_flag = 1; \
cf3b0334 2032 } else if (!tp##_is_zero(xa->fld) && \
bc80838f 2033 (((e_a - e_b) >= emax) || \
fa9ebf8c
DG		 2034 ((e_a - e_b) <= (emin + 1)) || \
2035 (e_a <= (emin + nbits)))) { \
bc80838f
TM		 2036 fe_flag = 1; \
2037 } \
2038 \
cf3b0334 2039 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
fa9ebf8c
DG		 2040 /* \
2041 * XB is not zero because of the above check and so \
2042 * must be denormalized. \
2043 */ \
bc80838f
TM		 2044 fg_flag = 1; \
2045 } \
2046 } \
2047 } \
2048 \
2049 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2050}
2051
bcb7652e
TM		 2052VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2053VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2054VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
5cb151ac 2055
fa9ebf8c
DG		 2056/*
2057 * VSX_TSQRT - VSX floating point test for square root
5cb151ac
TM		 2058 * op - instruction mnemonic
2059 * nels - number of elements (1, 2 or 4)
2060 * tp - type (float32 or float64)
bcb7652e 2061 * fld - vsr_t field (VsrD(*) or VsrW(*))
5cb151ac
TM		 2062 * emin - minimum unbiased exponent
2063 * emax - maximum unbiased exponent
2064 * nbits - number of fraction bits
2065 */
2066#define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
8d830485 2067void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \
5cb151ac 2068{ \
5cb151ac
TM		 2069 int i; \
2070 int fe_flag = 0; \
2071 int fg_flag = 0; \
2072 \
5cb151ac 2073 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 2074 if (unlikely(tp##_is_infinity(xb->fld) || \
2075 tp##_is_zero(xb->fld))) { \
5cb151ac
TM		 2076 fe_flag = 1; \
2077 fg_flag = 1; \
2078 } else { \
cf3b0334 2079 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
5cb151ac 2080 \
cf3b0334 2081 if (unlikely(tp##_is_any_nan(xb->fld))) { \
5cb151ac 2082 fe_flag = 1; \
cf3b0334 2083 } else if (unlikely(tp##_is_zero(xb->fld))) { \
5cb151ac 2084 fe_flag = 1; \
cf3b0334 2085 } else if (unlikely(tp##_is_neg(xb->fld))) { \
5cb151ac 2086 fe_flag = 1; \
cf3b0334 2087 } else if (!tp##_is_zero(xb->fld) && \
fa9ebf8c 2088 (e_b <= (emin + nbits))) { \
5cb151ac
TM		 2089 fe_flag = 1; \
2090 } \
2091 \
cf3b0334 2092 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
fa9ebf8c
DG		 2093 /* \
2094 * XB is not zero because of the above check and \
2095 * therefore must be denormalized. \
2096 */ \
5cb151ac
TM		 2097 fg_flag = 1; \
2098 } \
2099 } \
2100 } \
2101 \
2102 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2103}
2104
bcb7652e
TM		 2105VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2106VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2107VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
595c6eef 2108
fa9ebf8c
DG		 2109/*
2110 * VSX_MADD - VSX floating point muliply/add variations
595c6eef
TM		 2111 * op - instruction mnemonic
2112 * nels - number of elements (1, 2 or 4)
2113 * tp - type (float32 or float64)
bcb7652e 2114 * fld - vsr_t field (VsrD(*) or VsrW(*))
595c6eef
TM		 2115 * maddflgs - flags for the float*muladd routine that control the
2116 * various forms (madd, msub, nmadd, nmsub)
595c6eef
TM		 2117 * sfprf - set FPRF
2118 */
c9f4e4d8 2119#define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) \
99125c74 2120void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
c9f4e4d8 2121 ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) \
595c6eef 2122{ \
c9f4e4d8 2123 ppc_vsr_t t = *xt; \
595c6eef
TM		 2124 int i; \
2125 \
595c6eef
TM		 2126 helper_reset_fpstatus(env); \
2127 \
2128 for (i = 0; i < nels; i++) { \
2129 float_status tstat = env->fp_status; \
2130 set_float_exception_flags(0, &tstat); \
f53f81e0 2131 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
fa9ebf8c
DG		 2132 /* \
2133 * Avoid double rounding errors by rounding the intermediate \
2134 * result to odd. \
2135 */ \
f53f81e0 2136 set_float_rounding_mode(float_round_to_zero, &tstat); \
cf3b0334
MCA		 2137 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2138 maddflgs, &tstat); \
2139 t.fld |= (get_float_exception_flags(&tstat) & \
2140 float_flag_inexact) != 0; \
f53f81e0 2141 } else { \
cf3b0334
MCA		 2142 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2143 maddflgs, &tstat); \
f53f81e0 2144 } \
595c6eef
TM		 2145 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2146 \
2147 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
cf3b0334 2148 tp##_maddsub_update_excp(env, xa->fld, b->fld, \
13c9115f 2149 c->fld, maddflgs, GETPC()); \
595c6eef 2150 } \
f53f81e0
TM		 2151 \
2152 if (r2sp) { \
cf3b0334 2153 t.fld = helper_frsp(env, t.fld); \
f53f81e0
TM		 2154 } \
2155 \
595c6eef 2156 if (sfprf) { \
cf3b0334 2157 helper_compute_fprf_float64(env, t.fld); \
595c6eef
TM		 2158 } \
2159 } \
cf3b0334 2160 *xt = t; \
6525aadc 2161 do_float_check_status(env, GETPC()); \
595c6eef
TM		 2162}
2163
c9f4e4d8
MCA		 2164VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
2165VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
2166VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
2167VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
2168VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
2169VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
2170VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
2171VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
2172
2173VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0)
2174VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0)
2175VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0)
2176VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0)
2177
2178VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0)
2179VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
2180VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
2181VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
4f17e9c7 2182
fa9ebf8c
DG		 2183/*
2184 * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
6d1ff9a7
SD		 2185 * op - instruction mnemonic
2186 * cmp - comparison operation
2187 * exp - expected result of comparison
2188 * svxvc - set VXVC bit
2189 */
2190#define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
99125c74
MCA		 2191void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2192 ppc_vsr_t *xa, ppc_vsr_t *xb) \
6d1ff9a7 2193{ \
cf3b0334 2194 ppc_vsr_t t = *xt; \
6d1ff9a7
SD		 2195 bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
2196 \
cf3b0334
MCA		 2197 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2198 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
6d1ff9a7
SD		 2199 vxsnan_flag = true; \
2200 if (fpscr_ve == 0 && svxvc) { \
2201 vxvc_flag = true; \
2202 } \
2203 } else if (svxvc) { \
cf3b0334
MCA		 2204 vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2205 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); \
6d1ff9a7
SD		 2206 } \
2207 if (vxsnan_flag) { \
13c9115f 2208 float_invalid_op_vxsnan(env, GETPC()); \
6d1ff9a7
SD		 2209 } \
2210 if (vxvc_flag) { \
13c9115f 2211 float_invalid_op_vxvc(env, 0, GETPC()); \
6d1ff9a7
SD		 2212 } \
2213 vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
2214 \
2215 if (!vex_flag) { \
cf3b0334
MCA		 2216 if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), \
2217 &env->fp_status) == exp) { \
2218 t.VsrD(0) = -1; \
2219 t.VsrD(1) = 0; \
6d1ff9a7 2220 } else { \
cf3b0334
MCA		 2221 t.VsrD(0) = 0; \
2222 t.VsrD(1) = 0; \
6d1ff9a7
SD		 2223 } \
2224 } \
cf3b0334 2225 *xt = t; \
6525aadc 2226 do_float_check_status(env, GETPC()); \
6d1ff9a7
SD		 2227}
2228
2229VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
2230VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
2231VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
2232VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
2233
033e1fcd
MCA		 2234void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
2235 ppc_vsr_t *xa, ppc_vsr_t *xb)
3a20d11d 2236{
3a20d11d
BR		 2237 int64_t exp_a, exp_b;
2238 uint32_t cc;
2239
cf3b0334
MCA		 2240 exp_a = extract64(xa->VsrD(0), 52, 11);
2241 exp_b = extract64(xb->VsrD(0), 52, 11);
3a20d11d 2242
cf3b0334
MCA		 2243 if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||
2244 float64_is_any_nan(xb->VsrD(0)))) {
3a20d11d
BR		 2245 cc = CRF_SO;
2246 } else {
2247 if (exp_a < exp_b) {
2248 cc = CRF_LT;
2249 } else if (exp_a > exp_b) {
2250 cc = CRF_GT;
2251 } else {
2252 cc = CRF_EQ;
2253 }
2254 }
2255
5c94dd38
PC		 2256 env->fpscr &= ~FP_FPCC;
2257 env->fpscr |= cc << FPSCR_FPCC;
3a20d11d
BR		 2258 env->crf[BF(opcode)] = cc;
2259
6525aadc 2260 do_float_check_status(env, GETPC());
3a20d11d
BR		 2261}
2262
6ae4a57a
MCA		 2263void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode,
2264 ppc_vsr_t *xa, ppc_vsr_t *xb)
3a20d11d 2265{
3a20d11d
BR		 2266 int64_t exp_a, exp_b;
2267 uint32_t cc;
2268
cf3b0334
MCA		 2269 exp_a = extract64(xa->VsrD(0), 48, 15);
2270 exp_b = extract64(xb->VsrD(0), 48, 15);
3a20d11d 2271
cf3b0334
MCA		 2272 if (unlikely(float128_is_any_nan(xa->f128) ||
2273 float128_is_any_nan(xb->f128))) {
3a20d11d
BR		 2274 cc = CRF_SO;
2275 } else {
2276 if (exp_a < exp_b) {
2277 cc = CRF_LT;
2278 } else if (exp_a > exp_b) {
2279 cc = CRF_GT;
2280 } else {
2281 cc = CRF_EQ;
2282 }
2283 }
2284
5c94dd38
PC		 2285 env->fpscr &= ~FP_FPCC;
2286 env->fpscr |= cc << FPSCR_FPCC;
3a20d11d
BR		 2287 env->crf[BF(opcode)] = cc;
2288
6525aadc 2289 do_float_check_status(env, GETPC());
3a20d11d
BR		 2290}
2291
132954a8
GM		 2292static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
2293 int crf_idx, bool ordered)
2294{
2295 uint32_t cc;
2296 bool vxsnan_flag = false, vxvc_flag = false;
2297
2298 helper_reset_fpstatus(env);
2299
132954a8
GM		 2300 switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {
2301 case float_relation_less:
2302 cc = CRF_LT;
2303 break;
2304 case float_relation_equal:
2305 cc = CRF_EQ;
2306 break;
2307 case float_relation_greater:
2308 cc = CRF_GT;
2309 break;
2310 case float_relation_unordered:
2311 cc = CRF_SO;
bc92c260
GM		 2312
2313 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
2314 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
2315 vxsnan_flag = true;
2316 if (fpscr_ve == 0 && ordered) {
2317 vxvc_flag = true;
2318 }
2319 } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
2320 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) {
2321 if (ordered) {
2322 vxvc_flag = true;
2323 }
2324 }
2325
132954a8
GM		 2326 break;
2327 default:
2328 g_assert_not_reached();
2329 }
2330
2331 env->fpscr &= ~FP_FPCC;
2332 env->fpscr |= cc << FPSCR_FPCC;
2333 env->crf[crf_idx] = cc;
2334
91699dbf
GM		 2335 if (vxsnan_flag) {
2336 float_invalid_op_vxsnan(env, GETPC());
2337 }
2338 if (vxvc_flag) {
2339 float_invalid_op_vxvc(env, 0, GETPC());
2340 }
2341
132954a8 2342 do_float_check_status(env, GETPC());
be0a4faf
BR		 2343}
2344
132954a8
GM		 2345void helper_xscmpodp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2346 ppc_vsr_t *xb)
2347{
2348 do_scalar_cmp(env, xa, xb, BF(opcode), true);
2349}
2350
2351void helper_xscmpudp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2352 ppc_vsr_t *xb)
2353{
2354 do_scalar_cmp(env, xa, xb, BF(opcode), false);
2355}
2356
2357static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
2358 ppc_vsr_t *xb, int crf_idx, bool ordered)
2359{
2360 uint32_t cc;
2361 bool vxsnan_flag = false, vxvc_flag = false;
2362
2363 helper_reset_fpstatus(env);
2364
132954a8
GM		 2365 switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) {
2366 case float_relation_less:
2367 cc = CRF_LT;
2368 break;
2369 case float_relation_equal:
2370 cc = CRF_EQ;
2371 break;
2372 case float_relation_greater:
2373 cc = CRF_GT;
2374 break;
2375 case float_relation_unordered:
2376 cc = CRF_SO;
bc92c260
GM		 2377
2378 if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
2379 float128_is_signaling_nan(xb->f128, &env->fp_status)) {
2380 vxsnan_flag = true;
2381 if (fpscr_ve == 0 && ordered) {
2382 vxvc_flag = true;
2383 }
2384 } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
2385 float128_is_quiet_nan(xb->f128, &env->fp_status)) {
2386 if (ordered) {
2387 vxvc_flag = true;
2388 }
2389 }
2390
132954a8
GM		 2391 break;
2392 default:
2393 g_assert_not_reached();
2394 }
2395
2396 env->fpscr &= ~FP_FPCC;
2397 env->fpscr |= cc << FPSCR_FPCC;
2398 env->crf[crf_idx] = cc;
2399
91699dbf
GM		 2400 if (vxsnan_flag) {
2401 float_invalid_op_vxsnan(env, GETPC());
2402 }
2403 if (vxvc_flag) {
2404 float_invalid_op_vxvc(env, 0, GETPC());
2405 }
2406
132954a8
GM		 2407 do_float_check_status(env, GETPC());
2408}
2409
2410void helper_xscmpoqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2411 ppc_vsr_t *xb)
2412{
2413 do_scalar_cmpq(env, xa, xb, BF(opcode), true);
2414}
2415
2416void helper_xscmpuqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2417 ppc_vsr_t *xb)
2418{
2419 do_scalar_cmpq(env, xa, xb, BF(opcode), false);
2420}
be0a4faf 2421
fa9ebf8c
DG		 2422/*
2423 * VSX_MAX_MIN - VSX floating point maximum/minimum
959e9c9d
TM		 2424 * name - instruction mnemonic
2425 * op - operation (max or min)
2426 * nels - number of elements (1, 2 or 4)
2427 * tp - type (float32 or float64)
bcb7652e 2428 * fld - vsr_t field (VsrD(*) or VsrW(*))
959e9c9d
TM		 2429 */
2430#define VSX_MAX_MIN(name, op, nels, tp, fld) \
99125c74
MCA		 2431void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
2432 ppc_vsr_t *xa, ppc_vsr_t *xb) \
959e9c9d 2433{ \
cf3b0334 2434 ppc_vsr_t t = *xt; \
959e9c9d
TM		 2435 int i; \
2436 \
959e9c9d 2437 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 2438 t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status); \
2439 if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2440 tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
13c9115f 2441 float_invalid_op_vxsnan(env, GETPC()); \
959e9c9d
TM		 2442 } \
2443 } \
2444 \
cf3b0334 2445 *xt = t; \
6525aadc 2446 do_float_check_status(env, GETPC()); \
959e9c9d
TM		 2447}
2448
bcb7652e
TM		 2449VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2450VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2451VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2452VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2453VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2454VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
354a6dec 2455
2770deed 2456#define VSX_MAX_MINC(name, max) \
23d0766b
MCA		 2457void helper_##name(CPUPPCState *env, uint32_t opcode, \
2458 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2770deed 2459{ \
cf3b0334 2460 ppc_vsr_t t = *xt; \
2770deed
BR		 2461 bool vxsnan_flag = false, vex_flag = false; \
2462 \
cf3b0334
MCA		 2463 if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
2464 float64_is_any_nan(xb->VsrD(0)))) { \
2465 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2466 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2770deed
BR		 2467 vxsnan_flag = true; \
2468 } \
cf3b0334 2469 t.VsrD(0) = xb->VsrD(0); \
2770deed 2470 } else if ((max && \
cf3b0334 2471 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2770deed 2472 (!max && \
cf3b0334
MCA		 2473 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2474 t.VsrD(0) = xa->VsrD(0); \
2770deed 2475 } else { \
cf3b0334 2476 t.VsrD(0) = xb->VsrD(0); \
2770deed
BR		 2477 } \
2478 \
2479 vex_flag = fpscr_ve & vxsnan_flag; \
2480 if (vxsnan_flag) { \
13c9115f 2481 float_invalid_op_vxsnan(env, GETPC()); \
2770deed
BR		 2482 } \
2483 if (!vex_flag) { \
cf3b0334 2484 *xt = t; \
2770deed
BR		 2485 } \
2486} \
2487
2488VSX_MAX_MINC(xsmaxcdp, 1);
2489VSX_MAX_MINC(xsmincdp, 0);
2490
d4ccd87e 2491#define VSX_MAX_MINJ(name, max) \
23d0766b
MCA		 2492void helper_##name(CPUPPCState *env, uint32_t opcode, \
2493 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
d4ccd87e 2494{ \
cf3b0334 2495 ppc_vsr_t t = *xt; \
d4ccd87e
BR		 2496 bool vxsnan_flag = false, vex_flag = false; \
2497 \
cf3b0334
MCA		 2498 if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { \
2499 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { \
d4ccd87e
BR		 2500 vxsnan_flag = true; \
2501 } \
cf3b0334
MCA		 2502 t.VsrD(0) = xa->VsrD(0); \
2503 } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { \
2504 if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
d4ccd87e
BR		 2505 vxsnan_flag = true; \
2506 } \
cf3b0334
MCA		 2507 t.VsrD(0) = xb->VsrD(0); \
2508 } else if (float64_is_zero(xa->VsrD(0)) && \
2509 float64_is_zero(xb->VsrD(0))) { \
d4ccd87e 2510 if (max) { \
cf3b0334
MCA		 2511 if (!float64_is_neg(xa->VsrD(0)) || \
2512 !float64_is_neg(xb->VsrD(0))) { \
2513 t.VsrD(0) = 0ULL; \
d4ccd87e 2514 } else { \
cf3b0334 2515 t.VsrD(0) = 0x8000000000000000ULL; \
d4ccd87e
BR		 2516 } \
2517 } else { \
cf3b0334
MCA		 2518 if (float64_is_neg(xa->VsrD(0)) || \
2519 float64_is_neg(xb->VsrD(0))) { \
2520 t.VsrD(0) = 0x8000000000000000ULL; \
d4ccd87e 2521 } else { \
cf3b0334 2522 t.VsrD(0) = 0ULL; \
d4ccd87e
BR		 2523 } \
2524 } \
2525 } else if ((max && \
cf3b0334 2526 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
d4ccd87e 2527 (!max && \
cf3b0334
MCA		 2528 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2529 t.VsrD(0) = xa->VsrD(0); \
d4ccd87e 2530 } else { \
cf3b0334 2531 t.VsrD(0) = xb->VsrD(0); \
d4ccd87e
BR		 2532 } \
2533 \
2534 vex_flag = fpscr_ve & vxsnan_flag; \
2535 if (vxsnan_flag) { \
13c9115f 2536 float_invalid_op_vxsnan(env, GETPC()); \
d4ccd87e
BR		 2537 } \
2538 if (!vex_flag) { \
cf3b0334 2539 *xt = t; \
d4ccd87e
BR		 2540 } \
2541} \
2542
2543VSX_MAX_MINJ(xsmaxjdp, 1);
2544VSX_MAX_MINJ(xsminjdp, 0);
2545
fa9ebf8c
DG		 2546/*
2547 * VSX_CMP - VSX floating point compare
354a6dec
TM		 2548 * op - instruction mnemonic
2549 * nels - number of elements (1, 2 or 4)
2550 * tp - type (float32 or float64)
bcb7652e 2551 * fld - vsr_t field (VsrD(*) or VsrW(*))
354a6dec
TM		 2552 * cmp - comparison operation
2553 * svxvc - set VXVC bit
6db246f9 2554 * exp - expected result of comparison
354a6dec 2555 */
6db246f9 2556#define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
00084a25
MCA		 2557uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2558 ppc_vsr_t *xa, ppc_vsr_t *xb) \
354a6dec 2559{ \
cf3b0334 2560 ppc_vsr_t t = *xt; \
00084a25 2561 uint32_t crf6 = 0; \
354a6dec
TM		 2562 int i; \
2563 int all_true = 1; \
2564 int all_false = 1; \
2565 \
354a6dec 2566 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 2567 if (unlikely(tp##_is_any_nan(xa->fld) || \
2568 tp##_is_any_nan(xb->fld))) { \
2569 if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2570 tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \
13c9115f 2571 float_invalid_op_vxsnan(env, GETPC()); \
354a6dec
TM		 2572 } \
2573 if (svxvc) { \
13c9115f 2574 float_invalid_op_vxvc(env, 0, GETPC()); \
354a6dec 2575 } \
cf3b0334 2576 t.fld = 0; \
354a6dec
TM		 2577 all_true = 0; \
2578 } else { \
cf3b0334
MCA		 2579 if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) == exp) { \
2580 t.fld = -1; \
354a6dec
TM		 2581 all_false = 0; \
2582 } else { \
cf3b0334 2583 t.fld = 0; \
354a6dec
TM		 2584 all_true = 0; \
2585 } \
2586 } \
2587 } \
2588 \
cf3b0334 2589 *xt = t; \
00084a25
MCA		 2590 crf6 = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2591 return crf6; \
2592}
354a6dec 2593
6db246f9
SB		 2594VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1)
2595VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1)
2596VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1, 1)
2597VSX_CMP(xvcmpnedp, 2, float64, VsrD(i), eq, 0, 0)
2598VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0, 1)
2599VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1, 1)
2600VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1, 1)
2601VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
ed8ac568 2602
fa9ebf8c
DG		 2603/*
2604 * VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
ed8ac568
TM		 2605 * op - instruction mnemonic
2606 * nels - number of elements (1, 2 or 4)
2607 * stp - source type (float32 or float64)
2608 * ttp - target type (float32 or float64)
2609 * sfld - source vsr_t field
2610 * tfld - target vsr_t field (f32 or f64)
2611 * sfprf - set FPRF
2612 */
2613#define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
75cf84cb 2614void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
ed8ac568 2615{ \
cf3b0334 2616 ppc_vsr_t t = *xt; \
ed8ac568
TM		 2617 int i; \
2618 \
ed8ac568 2619 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 2620 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2621 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
af39bc8c 2622 &env->fp_status))) { \
13c9115f 2623 float_invalid_op_vxsnan(env, GETPC()); \
cf3b0334 2624 t.tfld = ttp##_snan_to_qnan(t.tfld); \
ed8ac568
TM		 2625 } \
2626 if (sfprf) { \
cf3b0334 2627 helper_compute_fprf_##ttp(env, t.tfld); \
ed8ac568
TM		 2628 } \
2629 } \
2630 \
cf3b0334 2631 *xt = t; \
6525aadc 2632 do_float_check_status(env, GETPC()); \
ed8ac568
TM		 2633}
2634
6bbad7a9
TM		 2635VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2636VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
fa9ebf8c
DG		 2637VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
2638VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
5177d2ca 2639
fa9ebf8c
DG		 2640/*
2641 * VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
e5487803
BR		 2642 * op - instruction mnemonic
2643 * nels - number of elements (1, 2 or 4)
2644 * stp - source type (float32 or float64)
2645 * ttp - target type (float32 or float64)
2646 * sfld - source vsr_t field
2647 * tfld - target vsr_t field (f32 or f64)
2648 * sfprf - set FPRF
2649 */
2650#define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
99229620
MCA		 2651void helper_##op(CPUPPCState *env, uint32_t opcode, \
2652 ppc_vsr_t *xt, ppc_vsr_t *xb) \
e5487803 2653{ \
cf3b0334 2654 ppc_vsr_t t = *xt; \
e5487803
BR		 2655 int i; \
2656 \
e5487803 2657 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 2658 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2659 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
e5487803 2660 &env->fp_status))) { \
13c9115f 2661 float_invalid_op_vxsnan(env, GETPC()); \
cf3b0334 2662 t.tfld = ttp##_snan_to_qnan(t.tfld); \
e5487803
BR		 2663 } \
2664 if (sfprf) { \
cf3b0334 2665 helper_compute_fprf_##ttp(env, t.tfld); \
e5487803
BR		 2666 } \
2667 } \
2668 \
cf3b0334 2669 *xt = t; \
6525aadc 2670 do_float_check_status(env, GETPC()); \
e5487803
BR		 2671}
2672
2673VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2674
fa9ebf8c
DG		 2675/*
2676 * VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
f566c047
BR		 2677 * involving one half precision value
2678 * op - instruction mnemonic
8b920d8a 2679 * nels - number of elements (1, 2 or 4)
f566c047
BR		 2680 * stp - source type
2681 * ttp - target type
2682 * sfld - source vsr_t field
2683 * tfld - target vsr_t field
8b920d8a 2684 * sfprf - set FPRF
f566c047 2685 */
8b920d8a 2686#define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
75cf84cb 2687void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
f566c047 2688{ \
cf3b0334 2689 ppc_vsr_t t = { }; \
8b920d8a 2690 int i; \
f566c047 2691 \
8b920d8a 2692 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 2693 t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
2694 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
8b920d8a 2695 &env->fp_status))) { \
13c9115f 2696 float_invalid_op_vxsnan(env, GETPC()); \
cf3b0334 2697 t.tfld = ttp##_snan_to_qnan(t.tfld); \
8b920d8a
ND		 2698 } \
2699 if (sfprf) { \
cf3b0334 2700 helper_compute_fprf_##ttp(env, t.tfld); \
8b920d8a 2701 } \
f566c047 2702 } \
f566c047 2703 \
cf3b0334 2704 *xt = t; \
6525aadc 2705 do_float_check_status(env, GETPC()); \
f566c047
BR		 2706}
2707
8b920d8a
ND		 2708VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
2709VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
2710VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
2711VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
f566c047 2712
2a084dad
BR		 2713/*
2714 * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2715 * added to this later.
2716 */
e0d6a362
MCA		 2717void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
2718 ppc_vsr_t *xt, ppc_vsr_t *xb)
2a084dad 2719{
cf3b0334 2720 ppc_vsr_t t = { };
a8d411ab 2721 float_status tstat;
2a084dad 2722
a8d411ab 2723 tstat = env->fp_status;
2a084dad 2724 if (unlikely(Rc(opcode) != 0)) {
a8d411ab 2725 tstat.float_rounding_mode = float_round_to_odd;
2a084dad
BR		 2726 }
2727
cf3b0334 2728 t.VsrD(0) = float128_to_float64(xb->f128, &tstat);
a8d411ab 2729 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
cf3b0334 2730 if (unlikely(float128_is_signaling_nan(xb->f128, &tstat))) {
13c9115f 2731 float_invalid_op_vxsnan(env, GETPC());
cf3b0334 2732 t.VsrD(0) = float64_snan_to_qnan(t.VsrD(0));
2a084dad 2733 }
cf3b0334 2734 helper_compute_fprf_float64(env, t.VsrD(0));
2a084dad 2735
cf3b0334 2736 *xt = t;
6525aadc 2737 do_float_check_status(env, GETPC());
2a084dad
BR		 2738}
2739
7ee19fb9
TM		 2740uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2741{
fa7d9cb9 2742 uint64_t result, sign, exp, frac;
e6f1bfb2 2743
7ee19fb9
TM		 2744 float_status tstat = env->fp_status;
2745 set_float_exception_flags(0, &tstat);
2746
fa7d9cb9
PC		 2747 sign = extract64(xb, 63, 1);
2748 exp = extract64(xb, 52, 11);
2749 frac = extract64(xb, 0, 52) | 0x10000000000000ULL;
2750
2751 if (unlikely(exp == 0 && extract64(frac, 0, 52) != 0)) {
2752 /* DP denormal operand. */
2753 /* Exponent override to DP min exp. */
2754 exp = 1;
2755 /* Implicit bit override to 0. */
2756 frac = deposit64(frac, 53, 1, 0);
2757 }
2758
2759 if (unlikely(exp < 897 && frac != 0)) {
2760 /* SP tiny operand. */
2761 if (897 - exp > 63) {
2762 frac = 0;
2763 } else {
2764 /* Denormalize until exp = SP min exp. */
2765 frac >>= (897 - exp);
2766 }
2767 /* Exponent override to SP min exp - 1. */
2768 exp = 896;
2769 }
2770
2771 result = sign << 31;
2772 result |= extract64(exp, 10, 1) << 30;
2773 result |= extract64(exp, 0, 7) << 23;
2774 result |= extract64(frac, 29, 23);
2775
e6f1bfb2
PC		 2776 /* hardware replicates result to both words of the doubleword result. */
2777 return (result << 32) | result;
7ee19fb9
TM		 2778}
2779
2780uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2781{
2782 float_status tstat = env->fp_status;
2783 set_float_exception_flags(0, &tstat);
2784
2785 return float32_to_float64(xb >> 32, &tstat);
2786}
2787
fa9ebf8c
DG		 2788/*
2789 * VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
5177d2ca
TM		 2790 * op - instruction mnemonic
2791 * nels - number of elements (1, 2 or 4)
2792 * stp - source type (float32 or float64)
2793 * ttp - target type (int32, uint32, int64 or uint64)
2794 * sfld - source vsr_t field
2795 * tfld - target vsr_t field
5177d2ca
TM		 2796 * rnan - resulting NaN
2797 */
d1dec5ef 2798#define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
75cf84cb 2799void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
5177d2ca 2800{ \
a3dec427 2801 int all_flags = env->fp_status.float_exception_flags, flags; \
cf3b0334 2802 ppc_vsr_t t = *xt; \
5177d2ca
TM		 2803 int i; \
2804 \
5177d2ca 2805 for (i = 0; i < nels; i++) { \
a3dec427 2806 env->fp_status.float_exception_flags = 0; \
cf3b0334 2807 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
a3dec427
RH		 2808 flags = env->fp_status.float_exception_flags; \
2809 if (unlikely(flags & float_flag_invalid)) { \
cf3b0334
MCA		 2810 float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
2811 t.tfld = rnan; \
5177d2ca 2812 } \
a3dec427 2813 all_flags |= flags; \
5177d2ca
TM		 2814 } \
2815 \
cf3b0334 2816 *xt = t; \
a3dec427 2817 env->fp_status.float_exception_flags = all_flags; \
6525aadc 2818 do_float_check_status(env, GETPC()); \
5177d2ca
TM		 2819}
2820
d1dec5ef 2821VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
7dff9abe 2822 0x8000000000000000ULL)
d1dec5ef
TM		 2823VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2824 0x80000000U)
2825VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2826VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2827VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
7dff9abe 2828 0x8000000000000000ULL)
fa9ebf8c 2829VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
7dff9abe 2830 0x80000000U)
d1dec5ef 2831VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
fa9ebf8c
DG		 2832VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
2833VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
d1dec5ef
TM		 2834 0x8000000000000000ULL)
2835VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
fa9ebf8c 2836VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
d1dec5ef 2837VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
5177d2ca 2838
fa9ebf8c
DG		 2839/*
2840 * VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
05590b92
BR		 2841 * op - instruction mnemonic
2842 * stp - source type (float32 or float64)
2843 * ttp - target type (int32, uint32, int64 or uint64)
2844 * sfld - source vsr_t field
2845 * tfld - target vsr_t field
2846 * rnan - resulting NaN
2847 */
2848#define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
99229620
MCA		 2849void helper_##op(CPUPPCState *env, uint32_t opcode, \
2850 ppc_vsr_t *xt, ppc_vsr_t *xb) \
05590b92 2851{ \
cf3b0334 2852 ppc_vsr_t t = { }; \
05590b92 2853 \
cf3b0334 2854 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
a3dec427 2855 if (env->fp_status.float_exception_flags & float_flag_invalid) { \
cf3b0334
MCA		 2856 float_invalid_cvt(env, 0, GETPC(), stp##_classify(xb->sfld)); \
2857 t.tfld = rnan; \
05590b92
BR		 2858 } \
2859 \
cf3b0334 2860 *xt = t; \
6525aadc 2861 do_float_check_status(env, GETPC()); \
05590b92
BR		 2862}
2863
2864VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
2865 0x8000000000000000ULL)
2866
2867VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
2868 0xffffffff80000000ULL)
e0aee726
BR		 2869VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
2870VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
05590b92 2871
fa9ebf8c
DG		 2872/*
2873 * VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
5177d2ca
TM		 2874 * op - instruction mnemonic
2875 * nels - number of elements (1, 2 or 4)
2876 * stp - source type (int32, uint32, int64 or uint64)
2877 * ttp - target type (float32 or float64)
2878 * sfld - source vsr_t field
2879 * tfld - target vsr_t field
2880 * jdef - definition of the j index (i or 2*i)
2881 * sfprf - set FPRF
2882 */
6cd7db3d 2883#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
75cf84cb 2884void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
5177d2ca 2885{ \
cf3b0334 2886 ppc_vsr_t t = *xt; \
5177d2ca
TM		 2887 int i; \
2888 \
5177d2ca 2889 for (i = 0; i < nels; i++) { \
cf3b0334 2890 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
74698350 2891 if (r2sp) { \
cf3b0334 2892 t.tfld = helper_frsp(env, t.tfld); \
74698350 2893 } \
5177d2ca 2894 if (sfprf) { \
cf3b0334 2895 helper_compute_fprf_float64(env, t.tfld); \
5177d2ca
TM		 2896 } \
2897 } \
2898 \
cf3b0334 2899 *xt = t; \
6525aadc 2900 do_float_check_status(env, GETPC()); \
5177d2ca
TM		 2901}
2902
6cd7db3d
TM		 2903VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2904VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2905VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2906VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2907VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2908VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
fa9ebf8c
DG		 2909VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
2910VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
2911VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
2912VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
6cd7db3d
TM		 2913VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2914VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
88e33d08 2915
fa9ebf8c
DG		 2916/*
2917 * VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
48ef23cb
BR		 2918 * op - instruction mnemonic
2919 * stp - source type (int32, uint32, int64 or uint64)
2920 * ttp - target type (float32 or float64)
2921 * sfld - source vsr_t field
2922 * tfld - target vsr_t field
2923 */
2924#define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
99229620
MCA		 2925void helper_##op(CPUPPCState *env, uint32_t opcode, \
2926 ppc_vsr_t *xt, ppc_vsr_t *xb) \
48ef23cb 2927{ \
cf3b0334 2928 ppc_vsr_t t = *xt; \
48ef23cb 2929 \
cf3b0334
MCA		 2930 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2931 helper_compute_fprf_##ttp(env, t.tfld); \
48ef23cb 2932 \
cf3b0334 2933 *xt = t; \
6525aadc 2934 do_float_check_status(env, GETPC()); \
48ef23cb
BR		 2935}
2936
2937VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
2938VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
2939
fa9ebf8c
DG		 2940/*
2941 * For "use current rounding mode", define a value that will not be
2942 * one of the existing rounding model enums.
88e33d08
TM		 2943 */
2944#define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2945 float_round_up + float_round_to_zero)
2946
fa9ebf8c
DG		 2947/*
2948 * VSX_ROUND - VSX floating point round
88e33d08
TM		 2949 * op - instruction mnemonic
2950 * nels - number of elements (1, 2 or 4)
2951 * tp - type (float32 or float64)
bcb7652e 2952 * fld - vsr_t field (VsrD(*) or VsrW(*))
88e33d08
TM		 2953 * rmode - rounding mode
2954 * sfprf - set FPRF
2955 */
2956#define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
75cf84cb 2957void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
88e33d08 2958{ \
cf3b0334 2959 ppc_vsr_t t = *xt; \
88e33d08 2960 int i; \
63d06e90 2961 FloatRoundMode curr_rounding_mode; \
88e33d08
TM		 2962 \
2963 if (rmode != FLOAT_ROUND_CURRENT) { \
63d06e90 2964 curr_rounding_mode = get_float_rounding_mode(&env->fp_status); \
88e33d08
TM		 2965 set_float_rounding_mode(rmode, &env->fp_status); \
2966 } \
2967 \
2968 for (i = 0; i < nels; i++) { \
cf3b0334 2969 if (unlikely(tp##_is_signaling_nan(xb->fld, \
af39bc8c 2970 &env->fp_status))) { \
13c9115f 2971 float_invalid_op_vxsnan(env, GETPC()); \
cf3b0334 2972 t.fld = tp##_snan_to_qnan(xb->fld); \
88e33d08 2973 } else { \
cf3b0334 2974 t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
88e33d08
TM		 2975 } \
2976 if (sfprf) { \
cf3b0334 2977 helper_compute_fprf_float64(env, t.fld); \
88e33d08
TM		 2978 } \
2979 } \
2980 \
fa9ebf8c
DG		 2981 /* \
2982 * If this is not a "use current rounding mode" instruction, \
88e33d08 2983 * then inhibit setting of the XX bit and restore rounding \
fa9ebf8c
DG		 2984 * mode from FPSCR \
2985 */ \
88e33d08 2986 if (rmode != FLOAT_ROUND_CURRENT) { \
63d06e90 2987 set_float_rounding_mode(curr_rounding_mode, &env->fp_status); \
88e33d08
TM		 2988 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
2989 } \
2990 \
cf3b0334 2991 *xt = t; \
6525aadc 2992 do_float_check_status(env, GETPC()); \
88e33d08
TM		 2993}
2994
158c87e5 2995VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
bcb7652e
TM		 2996VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
2997VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
2998VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
2999VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
88e33d08 3000
158c87e5 3001VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
bcb7652e
TM		 3002VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
3003VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
3004VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
3005VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
88e33d08 3006
158c87e5 3007VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
bcb7652e
TM		 3008VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
3009VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
3010VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
3011VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
3d1140bf
TM		 3012
3013uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
3014{
3015 helper_reset_fpstatus(env);
3016
3017 uint64_t xt = helper_frsp(env, xb);
3018
ffc67420 3019 helper_compute_fprf_float64(env, xt);
6525aadc 3020 do_float_check_status(env, GETPC());
3d1140bf
TM		 3021 return xt;
3022}
234068ab
BR		 3023
3024#define VSX_XXPERM(op, indexed) \
99125c74
MCA		 3025void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
3026 ppc_vsr_t *xa, ppc_vsr_t *pcv) \
234068ab 3027{ \
cf3b0334 3028 ppc_vsr_t t = *xt; \
234068ab
BR		 3029 int i, idx; \
3030 \
234068ab 3031 for (i = 0; i < 16; i++) { \
cf3b0334 3032 idx = pcv->VsrB(i) & 0x1F; \
234068ab
BR		 3033 if (indexed) { \
3034 idx = 31 - idx; \
3035 } \
cf3b0334
MCA		 3036 t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \
3037 : xt->VsrB(idx - 16); \
234068ab 3038 } \
cf3b0334 3039 *xt = t; \
234068ab
BR		 3040}
3041
3042VSX_XXPERM(xxperm, 0)
3043VSX_XXPERM(xxpermr, 1)
c5969d2e 3044
75cf84cb 3045void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
c5969d2e 3046{
cf3b0334 3047 ppc_vsr_t t = { };
c5969d2e
ND		 3048 uint32_t exp, i, fraction;
3049
c5969d2e 3050 for (i = 0; i < 4; i++) {
cf3b0334
MCA		 3051 exp = (xb->VsrW(i) >> 23) & 0xFF;
3052 fraction = xb->VsrW(i) & 0x7FFFFF;
c5969d2e 3053 if (exp != 0 && exp != 255) {
cf3b0334 3054 t.VsrW(i) = fraction | 0x00800000;
c5969d2e 3055 } else {
cf3b0334 3056 t.VsrW(i) = fraction;
c5969d2e
ND		 3057 }
3058 }
cf3b0334 3059 *xt = t;
c5969d2e 3060}
403a884a 3061
fa9ebf8c
DG		 3062/*
3063 * VSX_TEST_DC - VSX floating point test data class
403a884a
ND		 3064 * op - instruction mnemonic
3065 * nels - number of elements (1, 2 or 4)
3066 * xbn - VSR register number
3067 * tp - type (float32 or float64)
3068 * fld - vsr_t field (VsrD(*) or VsrW(*))
3069 * tfld - target vsr_t field (VsrD(*) or VsrW(*))
3070 * fld_max - target field max
78241762 3071 * scrf - set result in CR and FPCC
403a884a 3072 */
78241762 3073#define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
403a884a
ND		 3074void helper_##op(CPUPPCState *env, uint32_t opcode) \
3075{ \
cf3b0334
MCA		 3076 ppc_vsr_t *xt = &env->vsr[xT(opcode)]; \
3077 ppc_vsr_t *xb = &env->vsr[xbn]; \
3078 ppc_vsr_t t = { }; \
403a884a 3079 uint32_t i, sign, dcmx; \
78241762 3080 uint32_t cc, match = 0; \
403a884a 3081 \
78241762 3082 if (!scrf) { \
78241762
ND		 3083 dcmx = DCMX_XV(opcode); \
3084 } else { \
cf3b0334 3085 t = *xt; \
78241762
ND		 3086 dcmx = DCMX(opcode); \
3087 } \
403a884a
ND		 3088 \
3089 for (i = 0; i < nels; i++) { \
cf3b0334
MCA		 3090 sign = tp##_is_neg(xb->fld); \
3091 if (tp##_is_any_nan(xb->fld)) { \
403a884a 3092 match = extract32(dcmx, 6, 1); \
cf3b0334 3093 } else if (tp##_is_infinity(xb->fld)) { \
403a884a 3094 match = extract32(dcmx, 4 + !sign, 1); \
cf3b0334 3095 } else if (tp##_is_zero(xb->fld)) { \
403a884a 3096 match = extract32(dcmx, 2 + !sign, 1); \
cf3b0334 3097 } else if (tp##_is_zero_or_denormal(xb->fld)) { \
403a884a
ND		 3098 match = extract32(dcmx, 0 + !sign, 1); \
3099 } \
78241762
ND		 3100 \
3101 if (scrf) { \
3102 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
5c94dd38
PC		 3103 env->fpscr &= ~FP_FPCC; \
3104 env->fpscr |= cc << FPSCR_FPCC; \
78241762
ND		 3105 env->crf[BF(opcode)] = cc; \
3106 } else { \
cf3b0334 3107 t.tfld = match ? fld_max : 0; \
78241762 3108 } \
403a884a
ND		 3109 match = 0; \
3110 } \
78241762 3111 if (!scrf) { \
cf3b0334 3112 *xt = t; \
78241762 3113 } \
403a884a
ND		 3114}
3115
78241762
ND		 3116VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
3117VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
3118VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
3119VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
3120
8d830485 3121void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
78241762 3122{
78241762
ND		 3123 uint32_t dcmx, sign, exp;
3124 uint32_t cc, match = 0, not_sp = 0;
3125
78241762 3126 dcmx = DCMX(opcode);
cf3b0334 3127 exp = (xb->VsrD(0) >> 52) & 0x7FF;
78241762 3128
cf3b0334
MCA		 3129 sign = float64_is_neg(xb->VsrD(0));
3130 if (float64_is_any_nan(xb->VsrD(0))) {
78241762 3131 match = extract32(dcmx, 6, 1);
cf3b0334 3132 } else if (float64_is_infinity(xb->VsrD(0))) {
78241762 3133 match = extract32(dcmx, 4 + !sign, 1);
cf3b0334 3134 } else if (float64_is_zero(xb->VsrD(0))) {
78241762 3135 match = extract32(dcmx, 2 + !sign, 1);
cf3b0334 3136 } else if (float64_is_zero_or_denormal(xb->VsrD(0)) ||
78241762
ND		 3137 (exp > 0 && exp < 0x381)) {
3138 match = extract32(dcmx, 0 + !sign, 1);
3139 }
3140
cf3b0334 3141 not_sp = !float64_eq(xb->VsrD(0),
78241762 3142 float32_to_float64(
cf3b0334 3143 float64_to_float32(xb->VsrD(0), &env->fp_status),
78241762
ND		 3144 &env->fp_status), &env->fp_status);
3145
3146 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
5c94dd38
PC		 3147 env->fpscr &= ~FP_FPCC;
3148 env->fpscr |= cc << FPSCR_FPCC;
78241762
ND		 3149 env->crf[BF(opcode)] = cc;
3150}
be07ad58 3151
99229620
MCA		 3152void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
3153 ppc_vsr_t *xt, ppc_vsr_t *xb)
be07ad58 3154{
cf3b0334 3155 ppc_vsr_t t = { };
be07ad58
JRZ		 3156 uint8_t r = Rrm(opcode);
3157 uint8_t ex = Rc(opcode);
3158 uint8_t rmc = RMC(opcode);
3159 uint8_t rmode = 0;
3160 float_status tstat;
3161
be07ad58
JRZ		 3162 helper_reset_fpstatus(env);
3163
3164 if (r == 0 && rmc == 0) {
3165 rmode = float_round_ties_away;
3166 } else if (r == 0 && rmc == 0x3) {
3167 rmode = fpscr_rn;
3168 } else if (r == 1) {
3169 switch (rmc) {
3170 case 0:
3171 rmode = float_round_nearest_even;
3172 break;
3173 case 1:
3174 rmode = float_round_to_zero;
3175 break;
3176 case 2:
3177 rmode = float_round_up;
3178 break;
3179 case 3:
3180 rmode = float_round_down;
3181 break;
3182 default:
3183 abort();
3184 }
3185 }
3186
3187 tstat = env->fp_status;
3188 set_float_exception_flags(0, &tstat);
3189 set_float_rounding_mode(rmode, &tstat);
cf3b0334 3190 t.f128 = float128_round_to_int(xb->f128, &tstat);
be07ad58
JRZ		 3191 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3192
3193 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
cf3b0334 3194 if (float128_is_signaling_nan(xb->f128, &tstat)) {
13c9115f 3195 float_invalid_op_vxsnan(env, GETPC());
cf3b0334 3196 t.f128 = float128_snan_to_qnan(t.f128);
be07ad58
JRZ		 3197 }
3198 }
3199
3200 if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3201 env->fp_status.float_exception_flags &= ~float_flag_inexact;
3202 }
3203
cf3b0334 3204 helper_compute_fprf_float128(env, t.f128);
6525aadc 3205 do_float_check_status(env, GETPC());
cf3b0334 3206 *xt = t;
be07ad58 3207}
917950d7 3208
99229620
MCA		 3209void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
3210 ppc_vsr_t *xt, ppc_vsr_t *xb)
917950d7 3211{
cf3b0334 3212 ppc_vsr_t t = { };
917950d7
JRZ		 3213 uint8_t r = Rrm(opcode);
3214 uint8_t rmc = RMC(opcode);
3215 uint8_t rmode = 0;
3216 floatx80 round_res;
3217 float_status tstat;
3218
917950d7
JRZ		 3219 helper_reset_fpstatus(env);
3220
3221 if (r == 0 && rmc == 0) {
3222 rmode = float_round_ties_away;
3223 } else if (r == 0 && rmc == 0x3) {
3224 rmode = fpscr_rn;
3225 } else if (r == 1) {
3226 switch (rmc) {
3227 case 0:
3228 rmode = float_round_nearest_even;
3229 break;
3230 case 1:
3231 rmode = float_round_to_zero;
3232 break;
3233 case 2:
3234 rmode = float_round_up;
3235 break;
3236 case 3:
3237 rmode = float_round_down;
3238 break;
3239 default:
3240 abort();
3241 }
3242 }
3243
3244 tstat = env->fp_status;
3245 set_float_exception_flags(0, &tstat);
3246 set_float_rounding_mode(rmode, &tstat);
cf3b0334
MCA		 3247 round_res = float128_to_floatx80(xb->f128, &tstat);
3248 t.f128 = floatx80_to_float128(round_res, &tstat);
917950d7
JRZ		 3249 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3250
3251 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
cf3b0334 3252 if (float128_is_signaling_nan(xb->f128, &tstat)) {
13c9115f 3253 float_invalid_op_vxsnan(env, GETPC());
cf3b0334 3254 t.f128 = float128_snan_to_qnan(t.f128);
917950d7
JRZ		 3255 }
3256 }
3257
cf3b0334
MCA		 3258 helper_compute_fprf_float128(env, t.f128);
3259 *xt = t;
6525aadc 3260 do_float_check_status(env, GETPC());
917950d7 3261}
a4a68476 3262
99229620
MCA		 3263void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode,
3264 ppc_vsr_t *xt, ppc_vsr_t *xb)
a4a68476 3265{
cf3b0334 3266 ppc_vsr_t t = { };
a4a68476
JRZ		 3267 float_status tstat;
3268
a4a68476
JRZ		 3269 helper_reset_fpstatus(env);
3270
a8d411ab 3271 tstat = env->fp_status;
a4a68476 3272 if (unlikely(Rc(opcode) != 0)) {
a8d411ab 3273 tstat.float_rounding_mode = float_round_to_odd;
a4a68476
JRZ		 3274 }
3275
a4a68476 3276 set_float_exception_flags(0, &tstat);
cf3b0334 3277 t.f128 = float128_sqrt(xb->f128, &tstat);
a4a68476
JRZ		 3278 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3279
3280 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
cf3b0334 3281 if (float128_is_signaling_nan(xb->f128, &tstat)) {
13c9115f 3282 float_invalid_op_vxsnan(env, GETPC());
cf3b0334
MCA		 3283 t.f128 = float128_snan_to_qnan(xb->f128);
3284 } else if (float128_is_quiet_nan(xb->f128, &tstat)) {
3285 t.f128 = xb->f128;
3286 } else if (float128_is_neg(xb->f128) && !float128_is_zero(xb->f128)) {
13c9115f 3287 float_invalid_op_vxsqrt(env, 1, GETPC());
cf3b0334 3288 t.f128 = float128_default_nan(&env->fp_status);
a4a68476
JRZ		 3289 }
3290 }
3291
cf3b0334
MCA		 3292 helper_compute_fprf_float128(env, t.f128);
3293 *xt = t;
6525aadc 3294 do_float_check_status(env, GETPC());
a4a68476 3295}
f6b99afd 3296
23d0766b
MCA		 3297void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
3298 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
f6b99afd 3299{
cf3b0334 3300 ppc_vsr_t t = *xt;
f6b99afd
JRZ		 3301 float_status tstat;
3302
f6b99afd
JRZ		 3303 helper_reset_fpstatus(env);
3304
a8d411ab 3305 tstat = env->fp_status;
f6b99afd 3306 if (unlikely(Rc(opcode) != 0)) {
a8d411ab 3307 tstat.float_rounding_mode = float_round_to_odd;
f6b99afd
JRZ		 3308 }
3309
f6b99afd 3310 set_float_exception_flags(0, &tstat);
cf3b0334 3311 t.f128 = float128_sub(xa->f128, xb->f128, &tstat);
f6b99afd
JRZ		 3312 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3313
3314 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
941298ec 3315 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
f6b99afd
JRZ		 3316 }
3317
cf3b0334
MCA		 3318 helper_compute_fprf_float128(env, t.f128);
3319 *xt = t;
6525aadc 3320 do_float_check_status(env, GETPC());
f6b99afd 3321}
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