[mirror_qemu.git] / target / ppc / internal.h

/*
 *  PowerPC internal definitions for qemu.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#ifndef PPC_INTERNAL_H
#define PPC_INTERNAL_H

#define FUNC_MASK(name, ret_type, size, max_val)                  \
static inline ret_type name(uint##size##_t start,                 \
                              uint##size##_t end)                 \
{                                                                 \
    ret_type ret, max_bit = size - 1;                             \
                                                                  \
    if (likely(start == 0)) {                                     \
        ret = max_val << (max_bit - end);                         \
    } else if (likely(end == max_bit)) {                          \
        ret = max_val >> start;                                   \
    } else {                                                      \
        ret = (((uint##size##_t)(-1ULL)) >> (start)) ^            \
            (((uint##size##_t)(-1ULL) >> (end)) >> 1);            \
        if (unlikely(start > end)) {                              \
            return ~ret;                                          \
        }                                                         \
    }                                                             \
                                                                  \
    return ret;                                                   \
}

#if defined(TARGET_PPC64)
FUNC_MASK(MASK, target_ulong, 64, UINT64_MAX);
#else
FUNC_MASK(MASK, target_ulong, 32, UINT32_MAX);
#endif
FUNC_MASK(mask_u32, uint32_t, 32, UINT32_MAX);
FUNC_MASK(mask_u64, uint64_t, 64, UINT64_MAX);

/*****************************************************************************/
/***                           Instruction decoding                        ***/
#define EXTRACT_HELPER(name, shift, nb)                                       \
static inline uint32_t name(uint32_t opcode)                                  \
{                                                                             \
    return extract32(opcode, shift, nb);                                      \
}

#define EXTRACT_SHELPER(name, shift, nb)                                      \
static inline int32_t name(uint32_t opcode)                                   \
{                                                                             \
    return sextract32(opcode, shift, nb);                                     \
}

#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2)                  \
static inline uint32_t name(uint32_t opcode)                                  \
{                                                                             \
    return extract32(opcode, shift1, nb1) << nb2 |                            \
               extract32(opcode, shift2, nb2);                                \
}

#define EXTRACT_HELPER_SPLIT_3(name,                                          \
                              d0_bits, shift_op_d0, shift_d0,                 \
                              d1_bits, shift_op_d1, shift_d1,                 \
                              d2_bits, shift_op_d2, shift_d2)                 \
static inline int16_t name(uint32_t opcode)                                   \
{                                                                             \
    return                                                                    \
        (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
        (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
        (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2));  \
}


/* Opcode part 1 */
EXTRACT_HELPER(opc1, 26, 6);
/* Opcode part 2 */
EXTRACT_HELPER(opc2, 1, 5);
/* Opcode part 3 */
EXTRACT_HELPER(opc3, 6, 5);
/* Opcode part 4 */
EXTRACT_HELPER(opc4, 16, 5);
/* Update Cr0 flags */
EXTRACT_HELPER(Rc, 0, 1);
/* Update Cr6 flags (Altivec) */
EXTRACT_HELPER(Rc21, 10, 1);
/* Destination */
EXTRACT_HELPER(rD, 21, 5);
/* Source */
EXTRACT_HELPER(rS, 21, 5);
/* First operand */
EXTRACT_HELPER(rA, 16, 5);
/* Second operand */
EXTRACT_HELPER(rB, 11, 5);
/* Third operand */
EXTRACT_HELPER(rC, 6, 5);
/***                               Get CRn                                 ***/
EXTRACT_HELPER(crfD, 23, 3);
EXTRACT_HELPER(BF, 23, 3);
EXTRACT_HELPER(crfS, 18, 3);
EXTRACT_HELPER(crbD, 21, 5);
EXTRACT_HELPER(crbA, 16, 5);
EXTRACT_HELPER(crbB, 11, 5);
/* SPR / TBL */
EXTRACT_HELPER(_SPR, 11, 10);
static inline uint32_t SPR(uint32_t opcode)
{
    uint32_t sprn = _SPR(opcode);

    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
}
/***                              Get constants                            ***/
/* 16 bits signed immediate value */
EXTRACT_SHELPER(SIMM, 0, 16);
/* 16 bits unsigned immediate value */
EXTRACT_HELPER(UIMM, 0, 16);
/* 5 bits signed immediate value */
EXTRACT_SHELPER(SIMM5, 16, 5);
/* 5 bits signed immediate value */
EXTRACT_HELPER(UIMM5, 16, 5);
/* 4 bits unsigned immediate value */
EXTRACT_HELPER(UIMM4, 16, 4);
/* Bit count */
EXTRACT_HELPER(NB, 11, 5);
/* Shift count */
EXTRACT_HELPER(SH, 11, 5);
/* lwat/stwat/ldat/lwat */
EXTRACT_HELPER(FC, 11, 5);
/* Vector shift count */
EXTRACT_HELPER(VSH, 6, 4);
/* Mask start */
EXTRACT_HELPER(MB, 6, 5);
/* Mask end */
EXTRACT_HELPER(ME, 1, 5);
/* Trap operand */
EXTRACT_HELPER(TO, 21, 5);

EXTRACT_HELPER(CRM, 12, 8);

#ifndef CONFIG_USER_ONLY
EXTRACT_HELPER(SR, 16, 4);
#endif

/* mtfsf/mtfsfi */
EXTRACT_HELPER(FPBF, 23, 3);
EXTRACT_HELPER(FPIMM, 12, 4);
EXTRACT_HELPER(FPL, 25, 1);
EXTRACT_HELPER(FPFLM, 17, 8);
EXTRACT_HELPER(FPW, 16, 1);

/* mffscrni */
EXTRACT_HELPER(RM, 11, 2);

/* addpcis */
EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
#if defined(TARGET_PPC64)
/* darn */
EXTRACT_HELPER(L, 16, 2);
#endif

/***                            Jump target decoding                       ***/
/* Immediate address */
static inline target_ulong LI(uint32_t opcode)
{
    return (opcode >> 0) & 0x03FFFFFC;
}

static inline uint32_t BD(uint32_t opcode)
{
    return (opcode >> 0) & 0xFFFC;
}

EXTRACT_HELPER(BO, 21, 5);
EXTRACT_HELPER(BI, 16, 5);
/* Absolute/relative address */
EXTRACT_HELPER(AA, 1, 1);
/* Link */
EXTRACT_HELPER(LK, 0, 1);

/* DFP Z22-form */
EXTRACT_HELPER(DCM, 10, 6)

/* DFP Z23-form */
EXTRACT_HELPER(RMC, 9, 2)
EXTRACT_HELPER(Rrm, 16, 1)

EXTRACT_HELPER_SPLIT(DQxT, 3, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
EXTRACT_HELPER(DM, 8, 2);
EXTRACT_HELPER(UIM, 16, 2);
EXTRACT_HELPER(SHW, 8, 2);
EXTRACT_HELPER(SP, 19, 2);
EXTRACT_HELPER(IMM8, 11, 8);
EXTRACT_HELPER(DCMX, 16, 7);
EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);

void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);

/* translate.c */

int ppc_fixup_cpu(PowerPCCPU *cpu);
void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp);
void destroy_ppc_opcodes(PowerPCCPU *cpu);

/* gdbstub.c */
void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *ppc);
gchar *ppc_gdb_arch_name(CPUState *cs);

/**
 * prot_for_access_type:
 * @access_type: Access type
 *
 * Return the protection bit required for the given access type.
 */
static inline int prot_for_access_type(MMUAccessType access_type)
{
    switch (access_type) {
    case MMU_INST_FETCH:
        return PAGE_EXEC;
    case MMU_DATA_LOAD:
        return PAGE_READ;
    case MMU_DATA_STORE:
        return PAGE_WRITE;
    }
    g_assert_not_reached();
}

/* PowerPC MMU emulation */

typedef struct mmu_ctx_t mmu_ctx_t;
bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
                      hwaddr *raddrp, int *psizep, int *protp,
                      int mmu_idx, bool guest_visible);
int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
                                     target_ulong eaddr,
                                     MMUAccessType access_type, int type,
                                     int mmu_idx);
/* Software driven TLB helpers */
int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
                                    int way, int is_code);
/* Context used internally during MMU translations */
struct mmu_ctx_t {
    hwaddr raddr;      /* Real address              */
    hwaddr eaddr;      /* Effective address         */
    int prot;                      /* Protection bits           */
    hwaddr hash[2];    /* Pagetable hash values     */
    target_ulong ptem;             /* Virtual segment ID | API  */
    int key;                       /* Access key                */
    int nx;                        /* Non-execute area          */
};

/* Common routines used by software and hardware TLBs emulation */
static inline int pte_is_valid(target_ulong pte0)
{
    return pte0 & 0x80000000 ? 1 : 0;
}

static inline void pte_invalidate(target_ulong *pte0)
{
    *pte0 &= ~0x80000000;
}

#define PTE_PTEM_MASK 0x7FFFFFBF
#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)

#ifdef CONFIG_USER_ONLY
void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
                            MMUAccessType access_type,
                            bool maperr, uintptr_t ra);
#else
bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                      MMUAccessType access_type, int mmu_idx,
                      bool probe, uintptr_t retaddr);
void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
                                 MMUAccessType access_type, int mmu_idx,
                                 uintptr_t retaddr) QEMU_NORETURN;
#endif

#endif /* PPC_INTERNAL_H */
Commit	Line	Data
3e00884f	1	/*
136fbf65	2	* PowerPC internal definitions for qemu.
3e00884f GS	3	*
	4	* This library is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU Lesser General Public
	6	* License as published by the Free Software Foundation; either
6bd039cd	7	* version 2.1 of the License, or (at your option) any later version.
3e00884f GS	8	*
	9	* This library is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	12	* Lesser General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU Lesser General Public
	15	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef PPC_INTERNAL_H
	19	#define PPC_INTERNAL_H
	20
	21	#define FUNC_MASK(name, ret_type, size, max_val) \
	22	static inline ret_type name(uint##size##_t start, \
	23	uint##size##_t end) \
	24	{ \
	25	ret_type ret, max_bit = size - 1; \
	26	\
	27	if (likely(start == 0)) { \
	28	ret = max_val << (max_bit - end); \
	29	} else if (likely(end == max_bit)) { \
	30	ret = max_val >> start; \
	31	} else { \
	32	ret = (((uint##size##_t)(-1ULL)) >> (start)) ^ \
	33	(((uint##size##_t)(-1ULL) >> (end)) >> 1); \
	34	if (unlikely(start > end)) { \
	35	return ~ret; \
	36	} \
	37	} \
	38	\
	39	return ret; \
	40	}
	41
	42	#if defined(TARGET_PPC64)
	43	FUNC_MASK(MASK, target_ulong, 64, UINT64_MAX);
	44	#else
	45	FUNC_MASK(MASK, target_ulong, 32, UINT32_MAX);
	46	#endif
	47	FUNC_MASK(mask_u32, uint32_t, 32, UINT32_MAX);
	48	FUNC_MASK(mask_u64, uint64_t, 64, UINT64_MAX);
	49
985e3023 BR	50	/*****************************************************************************/
	51	/* Instruction decoding */
	52	#define EXTRACT_HELPER(name, shift, nb) \
	53	static inline uint32_t name(uint32_t opcode) \
	54	{ \
4c23c2a5	55	return extract32(opcode, shift, nb); \
985e3023 BR	56	}
	57
	58	#define EXTRACT_SHELPER(name, shift, nb) \
	59	static inline int32_t name(uint32_t opcode) \
	60	{ \
4c23c2a5	61	return sextract32(opcode, shift, nb); \
985e3023 BR	62	}
	63
	64	#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
	65	static inline uint32_t name(uint32_t opcode) \
	66	{ \
4c23c2a5 MCA	67	return extract32(opcode, shift1, nb1) << nb2 \| \
4c23c2a5 MCA	68	extract32(opcode, shift2, nb2); \
985e3023 BR	69	}
985e3023 BR	70
403a884a	71	#define EXTRACT_HELPER_SPLIT_3(name, \
985e3023 BR	72	d0_bits, shift_op_d0, shift_d0, \
	73	d1_bits, shift_op_d1, shift_d1, \
	74	d2_bits, shift_op_d2, shift_d2) \
	75	static inline int16_t name(uint32_t opcode) \
	76	{ \
	77	return \
	78	(((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) \| \
	79	(((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) \| \
	80	(((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
	81	}
	82
	83
	84	/* Opcode part 1 */
	85	EXTRACT_HELPER(opc1, 26, 6);
	86	/* Opcode part 2 */
	87	EXTRACT_HELPER(opc2, 1, 5);
	88	/* Opcode part 3 */
	89	EXTRACT_HELPER(opc3, 6, 5);
	90	/* Opcode part 4 */
	91	EXTRACT_HELPER(opc4, 16, 5);
	92	/* Update Cr0 flags */
	93	EXTRACT_HELPER(Rc, 0, 1);
	94	/* Update Cr6 flags (Altivec) */
	95	EXTRACT_HELPER(Rc21, 10, 1);
	96	/* Destination */
	97	EXTRACT_HELPER(rD, 21, 5);
	98	/* Source */
	99	EXTRACT_HELPER(rS, 21, 5);
	100	/* First operand */
	101	EXTRACT_HELPER(rA, 16, 5);
	102	/* Second operand */
	103	EXTRACT_HELPER(rB, 11, 5);
	104	/* Third operand */
	105	EXTRACT_HELPER(rC, 6, 5);
	106	/* Get CRn */
	107	EXTRACT_HELPER(crfD, 23, 3);
	108	EXTRACT_HELPER(BF, 23, 3);
	109	EXTRACT_HELPER(crfS, 18, 3);
	110	EXTRACT_HELPER(crbD, 21, 5);
	111	EXTRACT_HELPER(crbA, 16, 5);
	112	EXTRACT_HELPER(crbB, 11, 5);
	113	/* SPR / TBL */
	114	EXTRACT_HELPER(_SPR, 11, 10);
	115	static inline uint32_t SPR(uint32_t opcode)
	116	{
	117	uint32_t sprn = _SPR(opcode);
	118
	119	return ((sprn >> 5) & 0x1F) \| ((sprn & 0x1F) << 5);
	120	}
	121	/* Get constants */
	122	/* 16 bits signed immediate value */
	123	EXTRACT_SHELPER(SIMM, 0, 16);
	124	/* 16 bits unsigned immediate value */
	125	EXTRACT_HELPER(UIMM, 0, 16);
	126	/* 5 bits signed immediate value */
ffcd21ac	127	EXTRACT_SHELPER(SIMM5, 16, 5);
985e3023 BR	128	/* 5 bits signed immediate value */
	129	EXTRACT_HELPER(UIMM5, 16, 5);
	130	/* 4 bits unsigned immediate value */
	131	EXTRACT_HELPER(UIMM4, 16, 4);
	132	/* Bit count */
	133	EXTRACT_HELPER(NB, 11, 5);
	134	/* Shift count */
	135	EXTRACT_HELPER(SH, 11, 5);
a68a6146 B	136	/* lwat/stwat/ldat/lwat */
a68a6146 B	137	EXTRACT_HELPER(FC, 11, 5);
985e3023 BR	138	/* Vector shift count */
	139	EXTRACT_HELPER(VSH, 6, 4);
	140	/* Mask start */
	141	EXTRACT_HELPER(MB, 6, 5);
	142	/* Mask end */
	143	EXTRACT_HELPER(ME, 1, 5);
	144	/* Trap operand */
	145	EXTRACT_HELPER(TO, 21, 5);
	146
	147	EXTRACT_HELPER(CRM, 12, 8);
	148
	149	#ifndef CONFIG_USER_ONLY
	150	EXTRACT_HELPER(SR, 16, 4);
	151	#endif
	152
	153	/* mtfsf/mtfsfi */
	154	EXTRACT_HELPER(FPBF, 23, 3);
	155	EXTRACT_HELPER(FPIMM, 12, 4);
	156	EXTRACT_HELPER(FPL, 25, 1);
	157	EXTRACT_HELPER(FPFLM, 17, 8);
	158	EXTRACT_HELPER(FPW, 16, 1);
	159
a2735cf4 PC	160	/* mffscrni */
	161	EXTRACT_HELPER(RM, 11, 2);
	162
985e3023	163	/* addpcis */
403a884a	164	EXTRACT_HELPER_SPLIT_3(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
985e3023 BR	165	#if defined(TARGET_PPC64)
	166	/* darn */
	167	EXTRACT_HELPER(L, 16, 2);
	168	#endif
	169
	170	/* Jump target decoding */
	171	/* Immediate address */
	172	static inline target_ulong LI(uint32_t opcode)
	173	{
	174	return (opcode >> 0) & 0x03FFFFFC;
	175	}
	176
	177	static inline uint32_t BD(uint32_t opcode)
	178	{
	179	return (opcode >> 0) & 0xFFFC;
	180	}
	181
	182	EXTRACT_HELPER(BO, 21, 5);
	183	EXTRACT_HELPER(BI, 16, 5);
	184	/* Absolute/relative address */
	185	EXTRACT_HELPER(AA, 1, 1);
	186	/* Link */
	187	EXTRACT_HELPER(LK, 0, 1);
	188
	189	/* DFP Z22-form */
	190	EXTRACT_HELPER(DCM, 10, 6)
	191
	192	/* DFP Z23-form */
	193	EXTRACT_HELPER(RMC, 9, 2)
be07ad58	194	EXTRACT_HELPER(Rrm, 16, 1)
985e3023	195
d59ba583	196	EXTRACT_HELPER_SPLIT(DQxT, 3, 1, 21, 5);
985e3023 BR	197	EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
	198	EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
	199	EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
	200	EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
	201	EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
	202	EXTRACT_HELPER(DM, 8, 2);
	203	EXTRACT_HELPER(UIM, 16, 2);
	204	EXTRACT_HELPER(SHW, 8, 2);
	205	EXTRACT_HELPER(SP, 19, 2);
	206	EXTRACT_HELPER(IMM8, 11, 8);
78241762	207	EXTRACT_HELPER(DCMX, 16, 7);
403a884a	208	EXTRACT_HELPER_SPLIT_3(DCMX_XV, 5, 16, 0, 1, 2, 5, 1, 6, 6);
985e3023	209
f566c047	210	void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
9aeae8e1	211	void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
07bdd247	212	void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
0f3110fa	213
7468e2c8 BL	214	/* translate.c */
7468e2c8 BL	215
7468e2c8 BL	216	int ppc_fixup_cpu(PowerPCCPU *cpu);
	217	void create_ppc_opcodes(PowerPCCPU cpu, Error *errp);
	218	void destroy_ppc_opcodes(PowerPCCPU *cpu);
	219
35a5d74e BL	220	/* gdbstub.c */
	221	void ppc_gdb_init(CPUState cs, PowerPCCPUClass ppc);
	222	gchar ppc_gdb_arch_name(CPUState cs);
	223
182357db RH	224	/**
	225	* prot_for_access_type:
	226	* @access_type: Access type
	227	*
	228	* Return the protection bit required for the given access type.
	229	*/
	230	static inline int prot_for_access_type(MMUAccessType access_type)
	231	{
	232	switch (access_type) {
	233	case MMU_INST_FETCH:
	234	return PAGE_EXEC;
	235	case MMU_DATA_LOAD:
	236	return PAGE_READ;
	237	case MMU_DATA_STORE:
	238	return PAGE_WRITE;
	239	}
	240	g_assert_not_reached();
	241	}
	242
5118ebe8 LMC	243	/* PowerPC MMU emulation */
	244
	245	typedef struct mmu_ctx_t mmu_ctx_t;
	246	bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
	247	hwaddr raddrp, int psizep, int *protp,
	248	int mmu_idx, bool guest_visible);
	249	int get_physical_address_wtlb(CPUPPCState env, mmu_ctx_t ctx,
	250	target_ulong eaddr,
	251	MMUAccessType access_type, int type,
	252	int mmu_idx);
	253	/* Software driven TLB helpers */
	254	int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
	255	int way, int is_code);
	256	/* Context used internally during MMU translations */
	257	struct mmu_ctx_t {
	258	hwaddr raddr; /* Real address */
	259	hwaddr eaddr; /* Effective address */
	260	int prot; /* Protection bits */
	261	hwaddr hash[2]; /* Pagetable hash values */
	262	target_ulong ptem; /* Virtual segment ID \| API */
	263	int key; /* Access key */
	264	int nx; /* Non-execute area */
	265	};
	266
	267	/* Common routines used by software and hardware TLBs emulation */
	268	static inline int pte_is_valid(target_ulong pte0)
	269	{
	270	return pte0 & 0x80000000 ? 1 : 0;
	271	}
	272
	273	static inline void pte_invalidate(target_ulong *pte0)
	274	{
	275	*pte0 &= ~0x80000000;
	276	}
	277
	278	#define PTE_PTEM_MASK 0x7FFFFFBF
	279	#define PTE_CHECK_MASK (TARGET_PAGE_MASK \| 0x7B)
	280
1db8af5c RH	281	#ifdef CONFIG_USER_ONLY
	282	void ppc_cpu_record_sigsegv(CPUState *cs, vaddr addr,
	283	MMUAccessType access_type,
	284	bool maperr, uintptr_t ra);
	285	#else
	286	bool ppc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
	287	MMUAccessType access_type, int mmu_idx,
	288	bool probe, uintptr_t retaddr);
996473e4 RH	289	void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
	290	MMUAccessType access_type, int mmu_idx,
	291	uintptr_t retaddr) QEMU_NORETURN;
1db8af5c	292	#endif
5118ebe8	293
3e00884f	294	#endif /* PPC_INTERNAL_H */