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[mirror_qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
30f4b05b 24#include "qapi/error.h"
072ed5f2 25#include "qemu/error-report.h"
33c11879 26#include "cpu.h"
715d4b96 27#include "cpu-models.h"
1de7afc9 28#include "qemu/timer.h"
b3946626 29#include "sysemu/hw_accel.h"
d76d1650 30#include "kvm_ppc.h"
9c17d615
PB		 31#include "sysemu/cpus.h"
32#include "sysemu/device_tree.h"
d5aea6f3 33#include "mmu-hash64.h"
d76d1650 34
0d09e41a 35#include "hw/ppc/spapr.h"
7ebaf795 36#include "hw/ppc/spapr_cpu_core.h"
650d103d 37#include "hw/hw.h"
98a8b524 38#include "hw/ppc/ppc.h"
ca77ee28 39#include "migration/qemu-file-types.h"
31f2cb8f 40#include "sysemu/watchdog.h"
b36f100e 41#include "trace.h"
88365d17 42#include "exec/gdbstub.h"
4c663752 43#include "exec/memattrs.h"
9c607668 44#include "exec/ram_addr.h"
2d103aae 45#include "sysemu/hostmem.h"
f348b6d1 46#include "qemu/cutils.h"
db725815 47#include "qemu/main-loop.h"
9c607668 48#include "qemu/mmap-alloc.h"
f3d9f303 49#include "elf.h"
c64abd1f 50#include "sysemu/kvm_int.h"
f61b4bed 51
eadaada1
AG		 52#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
53
6e0552a3
FR		 54#define DEBUG_RETURN_GUEST 0
55#define DEBUG_RETURN_GDB 1
56
94a8d39a
JK		 57const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
58 KVM_CAP_LAST_INFO
59};
60
c995e942 61static int cap_interrupt_unset;
90dc8812 62static int cap_segstate;
90dc8812 63static int cap_booke_sregs;
e97c3636 64static int cap_ppc_smt;
fa98fbfc 65static int cap_ppc_smt_possible;
0f5cb298 66static int cap_spapr_tce;
d6ee2a7c 67static int cap_spapr_tce_64;
da95324e 68static int cap_spapr_multitce;
9bb62a07 69static int cap_spapr_vfio;
f1af19d7 70static int cap_hior;
d67d40ea 71static int cap_one_reg;
3b961124 72static int cap_epr;
31f2cb8f 73static int cap_ppc_watchdog;
9b00ea49 74static int cap_papr;
e68cb8b4 75static int cap_htab_fd;
87a91de6 76static int cap_fixup_hcalls;
bac3bf28 77static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 78static int cap_mmu_radix;
79static int cap_mmu_hash_v3;
38afd772 80static int cap_xive;
b55d295e 81static int cap_resize_hpt;
c363a37a 82static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 83static int cap_ppc_safe_cache;
84static int cap_ppc_safe_bounds_check;
85static int cap_ppc_safe_indirect_branch;
8ff43ee4 86static int cap_ppc_count_cache_flush_assist;
b9a477b7 87static int cap_ppc_nested_kvm_hv;
7d050527 88static int cap_large_decr;
ec010c00 89static int cap_fwnmi;
82123b75 90static int cap_rpt_invalidate;
ccc5a4c5 91static int cap_ail_mode_3;
fc87e185 92
3c902d44
BB		 93static uint32_t debug_inst_opcode;
94
c995e942
DG		 95/*
96 * Check whether we are running with KVM-PR (instead of KVM-HV). This
96c9cff0
TH		 97 * should only be used for fallback tests - generally we should use
98 * explicit capabilities for the features we want, rather than
c995e942
DG		 99 * assuming what is/isn't available depending on the KVM variant.
100 */
96c9cff0
TH		 101static bool kvmppc_is_pr(KVMState *ks)
102{
103 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 104 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 105}
106
165dc3ed 107static int kvm_ppc_register_host_cpu_type(void);
8acc2ae5 108static void kvmppc_get_cpu_characteristics(KVMState *s);
7d050527 109static int kvmppc_get_dec_bits(void);
5ba4576b 110
5e0d6590
AO		 111int kvm_arch_get_default_type(MachineState *ms)
112{
113 return 0;
114}
115
b16565b3 116int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 117{
fc87e185 118 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
90dc8812 119 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 120 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 121 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 122 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 123 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 124 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 125 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 126 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 127 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 128 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 129 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
c995e942
DG		 130 /*
131 * Note: we don't set cap_papr here, because this capability is
132 * only activated after this by kvmppc_set_papr()
133 */
6977afda 134 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 135 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 136 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 137 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 138 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
139 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
38afd772 140 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
b55d295e 141 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 142 kvmppc_get_cpu_characteristics(s);
b9a477b7 143 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
7d050527 144 cap_large_decr = kvmppc_get_dec_bits();
ec010c00 145 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
c363a37a
DHB		 146 /*
147 * Note: setting it to false because there is not such capability
148 * in KVM at this moment.
149 *
150 * TODO: call kvm_vm_check_extension() with the right capability
c995e942
DG		 151 * after the kernel starts implementing it.
152 */
c363a37a 153 cap_ppc_pvr_compat = false;
fc87e185 154
1e8f51e8
SB		 155 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
156 error_report("KVM: Host kernel doesn't have level irq capability");
157 exit(1);
fc87e185
AG		 158 }
159
82123b75 160 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
ccc5a4c5 161 cap_ail_mode_3 = kvm_vm_check_extension(s, KVM_CAP_PPC_AIL_MODE_3);
165dc3ed 162 kvm_ppc_register_host_cpu_type();
5ba4576b 163
d76d1650
AJ		 164 return 0;
165}
166
4376c40d 167int kvm_arch_irqchip_create(KVMState *s)
d525ffab
PB		 168{
169 return 0;
170}
171
1bc22652 172static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 173{
1bc22652
AF		 174 CPUPPCState *cenv = &cpu->env;
175 CPUState *cs = CPU(cpu);
861bbc80 176 struct kvm_sregs sregs;
5666ca4a
SW		 177 int ret;
178
179 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
c995e942
DG		 180 /*
181 * What we're really trying to say is "if we're on BookE, we
182 * use the native PVR for now". This is the only sane way to
183 * check it though, so we potentially confuse users that they
184 * can run BookE guests on BookS. Let's hope nobody dares
185 * enough :)
186 */
5666ca4a
SW		 187 return 0;
188 } else {
90dc8812 189 if (!cap_segstate) {
64e07be5
AG		 190 fprintf(stderr, "kvm error: missing PVR setting capability\n");
191 return -ENOSYS;
5666ca4a 192 }
5666ca4a
SW		 193 }
194
1bc22652 195 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 196 if (ret) {
197 return ret;
198 }
861bbc80
AG		 199
200 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 201 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 202}
203
93dd5e85 204/* Set up a shared TLB array with KVM */
1bc22652 205static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 206{
1bc22652
AF		 207 CPUPPCState *env = &cpu->env;
208 CPUState *cs = CPU(cpu);
93dd5e85
SW		 209 struct kvm_book3e_206_tlb_params params = {};
210 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 211 unsigned int entries = 0;
212 int ret, i;
213
214 if (!kvm_enabled() ||
a60f24b5 215 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 216 return 0;
217 }
218
219 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
220
221 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
222 params.tlb_sizes[i] = booke206_tlb_size(env, i);
223 params.tlb_ways[i] = booke206_tlb_ways(env, i);
224 entries += params.tlb_sizes[i];
225 }
226
227 assert(entries == env->nb_tlb);
228 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
229
230 env->tlb_dirty = true;
231
232 cfg.array = (uintptr_t)env->tlb.tlbm;
233 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
234 cfg.params = (uintptr_t)&params;
235 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
236
48add816 237 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 238 if (ret < 0) {
239 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
240 __func__, strerror(-ret));
241 return ret;
242 }
243
244 env->kvm_sw_tlb = true;
245 return 0;
246}
247
4656e1f0
BH		 248
249#if defined(TARGET_PPC64)
ab256960 250static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 251{
71d0f1ea 252 int ret;
a60f24b5 253
ab256960
GK		 254 assert(kvm_state != NULL);
255
256 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 257 error_setg(errp, "KVM doesn't expose the MMU features it supports");
258 error_append_hint(errp, "Consider switching to a newer KVM\n");
259 return;
4656e1f0 260 }
4656e1f0 261
ab256960 262 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 263 if (ret == 0) {
264 return;
4656e1f0
BH		 265 }
266
71d0f1ea
GK		 267 error_setg_errno(errp, -ret,
268 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 269}
270
aa6edf97 271static struct ppc_radix_page_info *kvmppc_get_radix_page_info(void)
c64abd1f 272{
4f7f5893 273 KVMState *s = KVM_STATE(current_accel());
c64abd1f 274 struct ppc_radix_page_info *radix_page_info;
55baf4b5 275 struct kvm_ppc_rmmu_info rmmu_info = { };
c64abd1f
SB		 276 int i;
277
278 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
279 return NULL;
280 }
281 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
282 return NULL;
283 }
284 radix_page_info = g_malloc0(sizeof(*radix_page_info));
285 radix_page_info->count = 0;
286 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
287 if (rmmu_info.ap_encodings[i]) {
288 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
289 radix_page_info->count++;
290 }
291 }
292 return radix_page_info;
293}
294
b4db5413
SJS		 295target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
296 bool radix, bool gtse,
297 uint64_t proc_tbl)
298{
299 CPUState *cs = CPU(cpu);
300 int ret;
301 uint64_t flags = 0;
302 struct kvm_ppc_mmuv3_cfg cfg = {
303 .process_table = proc_tbl,
304 };
305
306 if (radix) {
307 flags |= KVM_PPC_MMUV3_RADIX;
308 }
309 if (gtse) {
310 flags |= KVM_PPC_MMUV3_GTSE;
311 }
312 cfg.flags = flags;
313 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
314 switch (ret) {
315 case 0:
316 return H_SUCCESS;
317 case -EINVAL:
318 return H_PARAMETER;
319 case -ENODEV:
320 return H_NOT_AVAILABLE;
321 default:
322 return H_HARDWARE;
323 }
324}
325
24c6863c
DG		 326bool kvmppc_hpt_needs_host_contiguous_pages(void)
327{
24c6863c
DG		 328 static struct kvm_ppc_smmu_info smmu_info;
329
330 if (!kvm_enabled()) {
331 return false;
332 }
333
ab256960 334 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 335 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
336}
337
e5ca28ec 338void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 339{
e5ca28ec 340 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 341 int iq, ik, jq, jk;
71d0f1ea 342 Error *local_err = NULL;
4656e1f0 343
e5ca28ec
DG		 344 /* For now, we only have anything to check on hash64 MMUs */
345 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 346 return;
347 }
348
ab256960 349 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 350 if (local_err) {
351 error_propagate(errp, local_err);
352 return;
353 }
4656e1f0 354
e5ca28ec
DG		 355 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
356 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
357 error_setg(errp,
358 "KVM does not support 1TiB segments which guest expects");
359 return;
df587133 360 }
4656e1f0 361
e5ca28ec
DG		 362 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
363 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
364 smmu_info.slb_size, cpu->hash64_opts->slb_size);
365 return;
90da0d5a
BH		 366 }
367
08215d8f 368 /*
e5ca28ec
DG		 369 * Verify that every pagesize supported by the cpu model is
370 * supported by KVM with the same encodings
08215d8f 371 */
e5ca28ec 372 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 373 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 374 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 375
e5ca28ec
DG		 376 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
377 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 378 break;
379 }
380 }
e5ca28ec
DG		 381 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
382 error_setg(errp, "KVM doesn't support for base page shift %u",
383 qsps->page_shift);
384 return;
385 }
386
387 ksps = &smmu_info.sps[ik];
388 if (ksps->slb_enc != qsps->slb_enc) {
389 error_setg(errp,
390"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
391 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
392 return;
393 }
394
395 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
396 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
397 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
398 break;
399 }
400 }
401
402 if (jk >= ARRAY_SIZE(ksps->enc)) {
403 error_setg(errp, "KVM doesn't support page shift %u/%u",
404 qsps->enc[jq].page_shift, qsps->page_shift);
405 return;
406 }
407 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
408 error_setg(errp,
409"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
410 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
411 qsps->page_shift, qsps->enc[jq].pte_enc);
412 return;
413 }
4656e1f0
BH		 414 }
415 }
4656e1f0 416
e5ca28ec 417 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
c995e942
DG		 418 /*
419 * Mostly what guest pagesizes we can use are related to the
e5ca28ec
DG		 420 * host pages used to map guest RAM, which is handled in the
421 * platform code. Cache-Inhibited largepages (64k) however are
422 * used for I/O, so if they're mapped to the host at all it
423 * will be a normal mapping, not a special hugepage one used
c995e942
DG		 424 * for RAM.
425 */
8e3b0cbb 426 if (qemu_real_host_page_size() < 0x10000) {
e5ca28ec
DG		 427 error_setg(errp,
428 "KVM can't supply 64kiB CI pages, which guest expects");
429 }
430 }
4656e1f0 431}
4656e1f0
BH		 432#endif /* !defined (TARGET_PPC64) */
433
b164e48e
EH		 434unsigned long kvm_arch_vcpu_id(CPUState *cpu)
435{
2e886fb3 436 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 437}
438
c995e942
DG		 439/*
440 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
441 * only 1 watchpoint, so array size of 4 is sufficient for now.
88365d17
BB		 442 */
443#define MAX_HW_BKPTS 4
444
445static struct HWBreakpoint {
446 target_ulong addr;
447 int type;
448} hw_debug_points[MAX_HW_BKPTS];
449
450static CPUWatchpoint hw_watchpoint;
451
452/* Default there is no breakpoint and watchpoint supported */
453static int max_hw_breakpoint;
454static int max_hw_watchpoint;
455static int nb_hw_breakpoint;
456static int nb_hw_watchpoint;
457
458static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
459{
460 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
461 max_hw_breakpoint = 2;
462 max_hw_watchpoint = 2;
463 }
464
465 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
466 fprintf(stderr, "Error initializing h/w breakpoints\n");
467 return;
468 }
469}
470
20d695a9 471int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 472{
20d695a9
AF		 473 PowerPCCPU *cpu = POWERPC_CPU(cs);
474 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 475 int ret;
476
4656e1f0 477 /* Synchronize sregs with kvm */
1bc22652 478 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 479 if (ret) {
388e47c7
TH		 480 if (ret == -EINVAL) {
481 error_report("Register sync failed... If you're using kvm-hv.ko,"
482 " only \"-cpu host\" is possible");
483 }
5666ca4a
SW		 484 return ret;
485 }
861bbc80 486
93dd5e85
SW		 487 switch (cenv->mmu_model) {
488 case POWERPC_MMU_BOOKE206:
7f516c96 489 /* This target supports access to KVM's guest TLB */
1bc22652 490 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 491 break;
7f516c96
TH		 492 case POWERPC_MMU_2_07:
493 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
c995e942
DG		 494 /*
495 * KVM-HV has transactional memory on POWER8 also without
496 * the KVM_CAP_PPC_HTM extension, so enable it here
136fbf65 497 * instead as long as it's available to userspace on the
c995e942
DG		 498 * host.
499 */
f3d9f303
SB		 500 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
501 cap_htm = true;
502 }
7f516c96
TH		 503 }
504 break;
93dd5e85
SW		 505 default:
506 break;
507 }
508
3c902d44 509 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 510 kvmppc_hw_debug_points_init(cenv);
3c902d44 511
861bbc80 512 return ret;
d76d1650
AJ		 513}
514
b1115c99
LA		 515int kvm_arch_destroy_vcpu(CPUState *cs)
516{
517 return 0;
518}
519
1bc22652 520static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 521{
1bc22652
AF		 522 CPUPPCState *env = &cpu->env;
523 CPUState *cs = CPU(cpu);
93dd5e85
SW		 524 struct kvm_dirty_tlb dirty_tlb;
525 unsigned char *bitmap;
526 int ret;
527
528 if (!env->kvm_sw_tlb) {
529 return;
530 }
531
532 bitmap = g_malloc((env->nb_tlb + 7) / 8);
533 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
534
535 dirty_tlb.bitmap = (uintptr_t)bitmap;
536 dirty_tlb.num_dirty = env->nb_tlb;
537
1bc22652 538 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 539 if (ret) {
540 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
541 __func__, strerror(-ret));
542 }
543
544 g_free(bitmap);
545}
546
d67d40ea
DG		 547static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
548{
549 PowerPCCPU *cpu = POWERPC_CPU(cs);
550 CPUPPCState *env = &cpu->env;
942069e0 551 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */
d67d40ea
DG		 552 union {
553 uint32_t u32;
554 uint64_t u64;
942069e0 555 } val = { };
d67d40ea
DG		 556 struct kvm_one_reg reg = {
557 .id = id,
558 .addr = (uintptr_t) &val,
559 };
560 int ret;
561
562 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
563 if (ret != 0) {
b36f100e 564 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 565 } else {
566 switch (id & KVM_REG_SIZE_MASK) {
567 case KVM_REG_SIZE_U32:
568 env->spr[spr] = val.u32;
569 break;
570
571 case KVM_REG_SIZE_U64:
572 env->spr[spr] = val.u64;
573 break;
574
575 default:
576 /* Don't handle this size yet */
577 abort();
578 }
579 }
580}
581
582static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
583{
584 PowerPCCPU *cpu = POWERPC_CPU(cs);
585 CPUPPCState *env = &cpu->env;
586 union {
587 uint32_t u32;
588 uint64_t u64;
589 } val;
590 struct kvm_one_reg reg = {
591 .id = id,
592 .addr = (uintptr_t) &val,
593 };
594 int ret;
595
596 switch (id & KVM_REG_SIZE_MASK) {
597 case KVM_REG_SIZE_U32:
598 val.u32 = env->spr[spr];
599 break;
600
601 case KVM_REG_SIZE_U64:
602 val.u64 = env->spr[spr];
603 break;
604
605 default:
606 /* Don't handle this size yet */
607 abort();
608 }
609
610 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
611 if (ret != 0) {
b36f100e 612 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 613 }
614}
615
70b79849
DG		 616static int kvm_put_fp(CPUState *cs)
617{
618 PowerPCCPU *cpu = POWERPC_CPU(cs);
619 CPUPPCState *env = &cpu->env;
620 struct kvm_one_reg reg;
621 int i;
622 int ret;
623
624 if (env->insns_flags & PPC_FLOAT) {
625 uint64_t fpscr = env->fpscr;
626 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
627
628 reg.id = KVM_REG_PPC_FPSCR;
629 reg.addr = (uintptr_t)&fpscr;
630 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
631 if (ret < 0) {
8d83cbf1 632 trace_kvm_failed_fpscr_set(strerror(errno));
70b79849
DG		 633 return ret;
634 }
635
636 for (i = 0; i < 32; i++) {
637 uint64_t vsr[2];
ef96e3ae
MCA		 638 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
639 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849 640
e03b5686 641#if HOST_BIG_ENDIAN
ef96e3ae
MCA		 642 vsr[0] = float64_val(*fpr);
643 vsr[1] = *vsrl;
3a4b791b 644#else
ef96e3ae
MCA		 645 vsr[0] = *vsrl;
646 vsr[1] = float64_val(*fpr);
3a4b791b 647#endif
70b79849
DG		 648 reg.addr = (uintptr_t) &vsr;
649 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
650
651 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
652 if (ret < 0) {
8d83cbf1
GK		 653 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
654 strerror(errno));
70b79849
DG		 655 return ret;
656 }
657 }
658 }
659
660 if (env->insns_flags & PPC_ALTIVEC) {
661 reg.id = KVM_REG_PPC_VSCR;
662 reg.addr = (uintptr_t)&env->vscr;
663 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
664 if (ret < 0) {
8d83cbf1 665 trace_kvm_failed_vscr_set(strerror(errno));
70b79849
DG		 666 return ret;
667 }
668
669 for (i = 0; i < 32; i++) {
670 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 671 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 672 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
673 if (ret < 0) {
8d83cbf1 674 trace_kvm_failed_vr_set(i, strerror(errno));
70b79849
DG		 675 return ret;
676 }
677 }
678 }
679
680 return 0;
681}
682
683static int kvm_get_fp(CPUState *cs)
684{
685 PowerPCCPU *cpu = POWERPC_CPU(cs);
686 CPUPPCState *env = &cpu->env;
687 struct kvm_one_reg reg;
688 int i;
689 int ret;
690
691 if (env->insns_flags & PPC_FLOAT) {
692 uint64_t fpscr;
693 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
694
695 reg.id = KVM_REG_PPC_FPSCR;
696 reg.addr = (uintptr_t)&fpscr;
697 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
698 if (ret < 0) {
8d83cbf1 699 trace_kvm_failed_fpscr_get(strerror(errno));
70b79849
DG		 700 return ret;
701 } else {
702 env->fpscr = fpscr;
703 }
704
705 for (i = 0; i < 32; i++) {
706 uint64_t vsr[2];
ef96e3ae
MCA		 707 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
708 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849
DG		 709
710 reg.addr = (uintptr_t) &vsr;
711 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
712
713 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
714 if (ret < 0) {
8d83cbf1
GK		 715 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
716 strerror(errno));
70b79849
DG		 717 return ret;
718 } else {
e03b5686 719#if HOST_BIG_ENDIAN
ef96e3ae 720 *fpr = vsr[0];
70b79849 721 if (vsx) {
ef96e3ae 722 *vsrl = vsr[1];
70b79849 723 }
3a4b791b 724#else
ef96e3ae 725 *fpr = vsr[1];
3a4b791b 726 if (vsx) {
ef96e3ae 727 *vsrl = vsr[0];
3a4b791b
GK		 728 }
729#endif
70b79849
DG		 730 }
731 }
732 }
733
734 if (env->insns_flags & PPC_ALTIVEC) {
735 reg.id = KVM_REG_PPC_VSCR;
736 reg.addr = (uintptr_t)&env->vscr;
737 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
738 if (ret < 0) {
8d83cbf1 739 trace_kvm_failed_vscr_get(strerror(errno));
70b79849
DG		 740 return ret;
741 }
742
743 for (i = 0; i < 32; i++) {
744 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 745 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 746 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
747 if (ret < 0) {
8d83cbf1 748 trace_kvm_failed_vr_get(i, strerror(errno));
70b79849
DG		 749 return ret;
750 }
751 }
752 }
753
754 return 0;
755}
756
9b00ea49
DG		 757#if defined(TARGET_PPC64)
758static int kvm_get_vpa(CPUState *cs)
759{
760 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 761 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 762 struct kvm_one_reg reg;
763 int ret;
764
765 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 766 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 767 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
768 if (ret < 0) {
8d83cbf1 769 trace_kvm_failed_vpa_addr_get(strerror(errno));
9b00ea49
DG		 770 return ret;
771 }
772
7388efaf
DG		 773 assert((uintptr_t)&spapr_cpu->slb_shadow_size
774 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 775 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 776 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 777 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
778 if (ret < 0) {
8d83cbf1 779 trace_kvm_failed_slb_get(strerror(errno));
9b00ea49
DG		 780 return ret;
781 }
782
7388efaf
DG		 783 assert((uintptr_t)&spapr_cpu->dtl_size
784 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 785 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 786 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 787 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
788 if (ret < 0) {
8d83cbf1 789 trace_kvm_failed_dtl_get(strerror(errno));
9b00ea49
DG		 790 return ret;
791 }
792
793 return 0;
794}
795
796static int kvm_put_vpa(CPUState *cs)
797{
798 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 799 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 800 struct kvm_one_reg reg;
801 int ret;
802
c995e942
DG		 803 /*
804 * SLB shadow or DTL can't be registered unless a master VPA is
9b00ea49
DG		 805 * registered. That means when restoring state, if a VPA *is*
806 * registered, we need to set that up first. If not, we need to
c995e942
DG		 807 * deregister the others before deregistering the master VPA
808 */
7388efaf
DG		 809 assert(spapr_cpu->vpa_addr
810 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 811
7388efaf 812 if (spapr_cpu->vpa_addr) {
9b00ea49 813 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 814 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 815 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
816 if (ret < 0) {
8d83cbf1 817 trace_kvm_failed_vpa_addr_set(strerror(errno));
9b00ea49
DG		 818 return ret;
819 }
820 }
821
7388efaf
DG		 822 assert((uintptr_t)&spapr_cpu->slb_shadow_size
823 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 824 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 825 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 826 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
827 if (ret < 0) {
8d83cbf1 828 trace_kvm_failed_slb_set(strerror(errno));
9b00ea49
DG		 829 return ret;
830 }
831
7388efaf
DG		 832 assert((uintptr_t)&spapr_cpu->dtl_size
833 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 834 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 835 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 836 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
837 if (ret < 0) {
8d83cbf1 838 trace_kvm_failed_dtl_set(strerror(errno));
9b00ea49
DG		 839 return ret;
840 }
841
7388efaf 842 if (!spapr_cpu->vpa_addr) {
9b00ea49 843 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 844 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 845 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
846 if (ret < 0) {
8d83cbf1 847 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
9b00ea49
DG		 848 return ret;
849 }
850 }
851
852 return 0;
853}
854#endif /* TARGET_PPC64 */
855
e5c0d3ce 856int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 857{
858 CPUPPCState *env = &cpu->env;
b339427c 859 struct kvm_sregs sregs = { };
a7a00a72
DG		 860 int i;
861
862 sregs.pvr = env->spr[SPR_PVR];
863
1ec26c75
GK		 864 if (cpu->vhyp) {
865 PPCVirtualHypervisorClass *vhc =
866 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
867 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
868 } else {
869 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
870 }
a7a00a72
DG		 871
872 /* Sync SLB */
873#ifdef TARGET_PPC64
874 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
875 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
876 if (env->slb[i].esid & SLB_ESID_V) {
877 sregs.u.s.ppc64.slb[i].slbe |= i;
878 }
879 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
880 }
881#endif
882
883 /* Sync SRs */
884 for (i = 0; i < 16; i++) {
885 sregs.u.s.ppc32.sr[i] = env->sr[i];
886 }
887
888 /* Sync BATs */
889 for (i = 0; i < 8; i++) {
890 /* Beware. We have to swap upper and lower bits here */
891 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
892 | env->DBAT[1][i];
893 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
894 | env->IBAT[1][i];
895 }
896
897 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
898}
899
20d695a9 900int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 901{
20d695a9
AF		 902 PowerPCCPU *cpu = POWERPC_CPU(cs);
903 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 904 struct kvm_regs regs;
905 int ret;
906 int i;
907
1bc22652
AF		 908 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
909 if (ret < 0) {
d76d1650 910 return ret;
1bc22652 911 }
d76d1650
AJ		 912
913 regs.ctr = env->ctr;
914 regs.lr = env->lr;
da91a00f 915 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 916 regs.msr = env->msr;
917 regs.pc = env->nip;
918
919 regs.srr0 = env->spr[SPR_SRR0];
920 regs.srr1 = env->spr[SPR_SRR1];
921
922 regs.sprg0 = env->spr[SPR_SPRG0];
923 regs.sprg1 = env->spr[SPR_SPRG1];
924 regs.sprg2 = env->spr[SPR_SPRG2];
925 regs.sprg3 = env->spr[SPR_SPRG3];
926 regs.sprg4 = env->spr[SPR_SPRG4];
927 regs.sprg5 = env->spr[SPR_SPRG5];
928 regs.sprg6 = env->spr[SPR_SPRG6];
929 regs.sprg7 = env->spr[SPR_SPRG7];
930
90dc8812
SW		 931 regs.pid = env->spr[SPR_BOOKE_PID];
932
c995e942 933 for (i = 0; i < 32; i++) {
d76d1650 934 regs.gpr[i] = env->gpr[i];
c995e942 935 }
d76d1650 936
2060436a 937 regs.cr = ppc_get_cr(env);
4bddaf55 938
1bc22652 939 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
c995e942 940 if (ret < 0) {
d76d1650 941 return ret;
c995e942 942 }
d76d1650 943
70b79849
DG		 944 kvm_put_fp(cs);
945
93dd5e85 946 if (env->tlb_dirty) {
1bc22652 947 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 948 env->tlb_dirty = false;
949 }
950
f1af19d7 951 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 952 ret = kvmppc_put_books_sregs(cpu);
953 if (ret < 0) {
f1af19d7
DG		 954 return ret;
955 }
956 }
957
958 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 959 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
960 }
f1af19d7 961
d67d40ea 962 if (cap_one_reg) {
c995e942
DG		 963 /*
964 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 965 * the ONE_REG calls, but don't support the specific
966 * registers, there's a reasonable chance things will still
c995e942
DG		 967 * work, at least until we try to migrate.
968 */
d67d40ea
DG		 969 for (i = 0; i < 1024; i++) {
970 uint64_t id = env->spr_cb[i].one_reg_id;
971
972 if (id != 0) {
973 kvm_put_one_spr(cs, id, i);
974 }
f1af19d7 975 }
9b00ea49
DG		 976
977#ifdef TARGET_PPC64
ca241959 978 if (FIELD_EX64(env->msr, MSR, TS)) {
80b3f79b
AK		 979 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
981 }
982 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
984 }
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
994 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
995 }
996
9b00ea49
DG		 997 if (cap_papr) {
998 if (kvm_put_vpa(cs) < 0) {
8d83cbf1 999 trace_kvm_failed_put_vpa();
9b00ea49
DG		 1000 }
1001 }
98a8b524
AK		 1002
1003 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576
AK		 1004
1005 if (level > KVM_PUT_RUNTIME_STATE) {
1006 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1007 }
9b00ea49 1008#endif /* TARGET_PPC64 */
f1af19d7
DG		 1009 }
1010
d76d1650
AJ		 1011 return ret;
1012}
1013
c371c2e3
BB		 1014static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1015{
1016 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1017}
1018
a7a00a72
DG		 1019static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1020{
1021 CPUPPCState *env = &cpu->env;
1022 struct kvm_sregs sregs;
1023 int ret;
1024
1025 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1026 if (ret < 0) {
1027 return ret;
1028 }
1029
1030 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1031 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1032 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1033 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1034 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1035 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1036 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1037 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1038 env->spr[SPR_DECR] = sregs.u.e.dec;
1039 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1040 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1041 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1042 }
1043
1044 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1045 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1046 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1047 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1048 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1049 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1050 }
1051
1052 if (sregs.u.e.features & KVM_SREGS_E_64) {
1053 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1054 }
1055
1056 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1057 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1058 }
1059
1060 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1061 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1062 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1063 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1064 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1065 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1066 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1067 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1068 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1069 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1070 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1071 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1072 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1073 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1074 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1075 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1076 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1077 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1078 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1079 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1080 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1081 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1082 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1083 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1084 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1085 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1086 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1087 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1088 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1089 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1090 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1091 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1092 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1093
1094 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1095 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1096 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1097 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1098 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1099 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1100 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1101 }
1102
1103 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1104 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1105 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1106 }
1107
1108 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1109 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1110 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1111 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1112 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1113 }
1114 }
1115
1116 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1117 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1118 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1119 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1120 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1121 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1122 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1123 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1124 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1125 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1126 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1127 }
1128
1129 if (sregs.u.e.features & KVM_SREGS_EXP) {
1130 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1131 }
1132
1133 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1134 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1135 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1136 }
1137
1138 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1139 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1140 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1141 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1142
1143 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1144 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1145 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1146 }
1147 }
1148
1149 return 0;
1150}
1151
1152static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1153{
1154 CPUPPCState *env = &cpu->env;
1155 struct kvm_sregs sregs;
1156 int ret;
1157 int i;
1158
1159 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1160 if (ret < 0) {
1161 return ret;
1162 }
1163
e57ca75c 1164 if (!cpu->vhyp) {
a7a00a72
DG		 1165 ppc_store_sdr1(env, sregs.u.s.sdr1);
1166 }
1167
1168 /* Sync SLB */
1169#ifdef TARGET_PPC64
1170 /*
1171 * The packed SLB array we get from KVM_GET_SREGS only contains
1172 * information about valid entries. So we flush our internal copy
1173 * to get rid of stale ones, then put all valid SLB entries back
1174 * in.
1175 */
1176 memset(env->slb, 0, sizeof(env->slb));
1177 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1178 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1179 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1180 /*
1181 * Only restore valid entries
1182 */
1183 if (rb & SLB_ESID_V) {
1184 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1185 }
1186 }
1187#endif
1188
1189 /* Sync SRs */
1190 for (i = 0; i < 16; i++) {
1191 env->sr[i] = sregs.u.s.ppc32.sr[i];
1192 }
1193
1194 /* Sync BATs */
1195 for (i = 0; i < 8; i++) {
1196 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1197 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1198 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1199 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1200 }
1201
1202 return 0;
1203}
1204
20d695a9 1205int kvm_arch_get_registers(CPUState *cs)
d76d1650 1206{
20d695a9
AF		 1207 PowerPCCPU *cpu = POWERPC_CPU(cs);
1208 CPUPPCState *env = &cpu->env;
d76d1650 1209 struct kvm_regs regs;
138b38b6 1210 int i, ret;
d76d1650 1211
1bc22652 1212 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
c995e942 1213 if (ret < 0) {
d76d1650 1214 return ret;
c995e942 1215 }
d76d1650 1216
2060436a 1217 ppc_set_cr(env, regs.cr);
d76d1650
AJ		 1218 env->ctr = regs.ctr;
1219 env->lr = regs.lr;
da91a00f 1220 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1221 env->msr = regs.msr;
1222 env->nip = regs.pc;
1223
1224 env->spr[SPR_SRR0] = regs.srr0;
1225 env->spr[SPR_SRR1] = regs.srr1;
1226
1227 env->spr[SPR_SPRG0] = regs.sprg0;
1228 env->spr[SPR_SPRG1] = regs.sprg1;
1229 env->spr[SPR_SPRG2] = regs.sprg2;
1230 env->spr[SPR_SPRG3] = regs.sprg3;
1231 env->spr[SPR_SPRG4] = regs.sprg4;
1232 env->spr[SPR_SPRG5] = regs.sprg5;
1233 env->spr[SPR_SPRG6] = regs.sprg6;
1234 env->spr[SPR_SPRG7] = regs.sprg7;
1235
90dc8812
SW		 1236 env->spr[SPR_BOOKE_PID] = regs.pid;
1237
c995e942 1238 for (i = 0; i < 32; i++) {
d76d1650 1239 env->gpr[i] = regs.gpr[i];
c995e942 1240 }
d76d1650 1241
70b79849
DG		 1242 kvm_get_fp(cs);
1243
90dc8812 1244 if (cap_booke_sregs) {
a7a00a72 1245 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1246 if (ret < 0) {
1247 return ret;
1248 }
fafc0b6a 1249 }
90dc8812 1250
90dc8812 1251 if (cap_segstate) {
a7a00a72 1252 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1253 if (ret < 0) {
1254 return ret;
1255 }
fafc0b6a 1256 }
ba5e5090 1257
d67d40ea
DG		 1258 if (cap_hior) {
1259 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1260 }
1261
1262 if (cap_one_reg) {
c995e942
DG		 1263 /*
1264 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 1265 * the ONE_REG calls, but don't support the specific
1266 * registers, there's a reasonable chance things will still
c995e942
DG		 1267 * work, at least until we try to migrate.
1268 */
d67d40ea
DG		 1269 for (i = 0; i < 1024; i++) {
1270 uint64_t id = env->spr_cb[i].one_reg_id;
1271
1272 if (id != 0) {
1273 kvm_get_one_spr(cs, id, i);
1274 }
1275 }
9b00ea49
DG		 1276
1277#ifdef TARGET_PPC64
ca241959 1278 if (FIELD_EX64(env->msr, MSR, TS)) {
80b3f79b
AK		 1279 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1280 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1281 }
1282 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1284 }
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1295 }
1296
9b00ea49
DG		 1297 if (cap_papr) {
1298 if (kvm_get_vpa(cs) < 0) {
8d83cbf1 1299 trace_kvm_failed_get_vpa();
9b00ea49
DG		 1300 }
1301 }
98a8b524
AK		 1302
1303 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576 1304 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
9b00ea49 1305#endif
d67d40ea
DG		 1306 }
1307
d76d1650
AJ		 1308 return 0;
1309}
1310
1bc22652 1311int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1312{
1313 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1314
1315 if (irq != PPC_INTERRUPT_EXT) {
1316 return 0;
1317 }
1318
76d93e14 1319 if (!cap_interrupt_unset) {
fc87e185
AG		 1320 return 0;
1321 }
1322
1bc22652 1323 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1324
1325 return 0;
1326}
1327
20d695a9 1328void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1329{
1e8f51e8 1330 return;
d76d1650
AJ		 1331}
1332
4c663752 1333MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1334{
4c663752 1335 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1336}
1337
20d695a9 1338int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1339{
259186a7 1340 return cs->halted;
0af691d7
MT		 1341}
1342
259186a7 1343static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1344{
259186a7
AF		 1345 CPUState *cs = CPU(cpu);
1346 CPUPPCState *env = &cpu->env;
1347
0939b8f8
VC		 1348 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1349 FIELD_EX64(env->msr, MSR, EE)) {
259186a7 1350 cs->halted = 1;
27103424 1351 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1352 }
1353
bb4ea393 1354 return 0;
d76d1650
AJ		 1355}
1356
1357/* map dcr access to existing qemu dcr emulation */
c995e942
DG		 1358static int kvmppc_handle_dcr_read(CPUPPCState *env,
1359 uint32_t dcrn, uint32_t *data)
d76d1650 1360{
c995e942 1361 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
d76d1650 1362 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
c995e942 1363 }
d76d1650 1364
bb4ea393 1365 return 0;
d76d1650
AJ		 1366}
1367
c995e942
DG		 1368static int kvmppc_handle_dcr_write(CPUPPCState *env,
1369 uint32_t dcrn, uint32_t data)
d76d1650 1370{
c995e942 1371 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
d76d1650 1372 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
c995e942 1373 }
d76d1650 1374
bb4ea393 1375 return 0;
d76d1650
AJ		 1376}
1377
8a0548f9
BB		 1378int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1379{
1380 /* Mixed endian case is not handled */
1381 uint32_t sc = debug_inst_opcode;
1382
1383 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1384 sizeof(sc), 0) ||
1385 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1386 return -EINVAL;
1387 }
1388
1389 return 0;
1390}
1391
1392int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1393{
1394 uint32_t sc;
1395
1396 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1397 sc != debug_inst_opcode ||
1398 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1399 sizeof(sc), 1)) {
1400 return -EINVAL;
1401 }
1402
1403 return 0;
1404}
1405
88365d17
BB		 1406static int find_hw_breakpoint(target_ulong addr, int type)
1407{
1408 int n;
1409
1410 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1411 <= ARRAY_SIZE(hw_debug_points));
1412
1413 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1414 if (hw_debug_points[n].addr == addr &&
1415 hw_debug_points[n].type == type) {
1416 return n;
1417 }
1418 }
1419
1420 return -1;
1421}
1422
1423static int find_hw_watchpoint(target_ulong addr, int *flag)
1424{
1425 int n;
1426
1427 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1428 if (n >= 0) {
1429 *flag = BP_MEM_ACCESS;
1430 return n;
1431 }
1432
1433 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1434 if (n >= 0) {
1435 *flag = BP_MEM_WRITE;
1436 return n;
1437 }
1438
1439 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1440 if (n >= 0) {
1441 *flag = BP_MEM_READ;
1442 return n;
1443 }
1444
1445 return -1;
1446}
1447
b8a6eb18 1448int kvm_arch_insert_hw_breakpoint(vaddr addr, vaddr len, int type)
88365d17 1449{
b8a6eb18
AJ		 1450 const unsigned breakpoint_index = nb_hw_breakpoint + nb_hw_watchpoint;
1451 if (breakpoint_index >= ARRAY_SIZE(hw_debug_points)) {
88365d17
BB		 1452 return -ENOBUFS;
1453 }
1454
b8a6eb18
AJ		 1455 hw_debug_points[breakpoint_index].addr = addr;
1456 hw_debug_points[breakpoint_index].type = type;
88365d17
BB		 1457
1458 switch (type) {
1459 case GDB_BREAKPOINT_HW:
1460 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1461 return -ENOBUFS;
1462 }
1463
1464 if (find_hw_breakpoint(addr, type) >= 0) {
1465 return -EEXIST;
1466 }
1467
1468 nb_hw_breakpoint++;
1469 break;
1470
1471 case GDB_WATCHPOINT_WRITE:
1472 case GDB_WATCHPOINT_READ:
1473 case GDB_WATCHPOINT_ACCESS:
1474 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1475 return -ENOBUFS;
1476 }
1477
1478 if (find_hw_breakpoint(addr, type) >= 0) {
1479 return -EEXIST;
1480 }
1481
1482 nb_hw_watchpoint++;
1483 break;
1484
1485 default:
1486 return -ENOSYS;
1487 }
1488
1489 return 0;
1490}
1491
b8a6eb18 1492int kvm_arch_remove_hw_breakpoint(vaddr addr, vaddr len, int type)
88365d17
BB		 1493{
1494 int n;
1495
1496 n = find_hw_breakpoint(addr, type);
1497 if (n < 0) {
1498 return -ENOENT;
1499 }
1500
1501 switch (type) {
1502 case GDB_BREAKPOINT_HW:
1503 nb_hw_breakpoint--;
1504 break;
1505
1506 case GDB_WATCHPOINT_WRITE:
1507 case GDB_WATCHPOINT_READ:
1508 case GDB_WATCHPOINT_ACCESS:
1509 nb_hw_watchpoint--;
1510 break;
1511
1512 default:
1513 return -ENOSYS;
1514 }
1515 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1516
1517 return 0;
1518}
1519
1520void kvm_arch_remove_all_hw_breakpoints(void)
1521{
1522 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1523}
1524
8a0548f9
BB		 1525void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1526{
88365d17
BB		 1527 int n;
1528
8a0548f9
BB		 1529 /* Software Breakpoint updates */
1530 if (kvm_sw_breakpoints_active(cs)) {
1531 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1532 }
88365d17
BB		 1533
1534 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1535 <= ARRAY_SIZE(hw_debug_points));
1536 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1537
1538 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1539 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1540 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1541 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1542 switch (hw_debug_points[n].type) {
1543 case GDB_BREAKPOINT_HW:
1544 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1545 break;
1546 case GDB_WATCHPOINT_WRITE:
1547 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1548 break;
1549 case GDB_WATCHPOINT_READ:
1550 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1551 break;
1552 case GDB_WATCHPOINT_ACCESS:
1553 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1554 KVMPPC_DEBUG_WATCH_READ;
1555 break;
1556 default:
1557 cpu_abort(cs, "Unsupported breakpoint type\n");
1558 }
1559 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1560 }
1561 }
8a0548f9
BB		 1562}
1563
2cbd1581
FR		 1564static int kvm_handle_hw_breakpoint(CPUState *cs,
1565 struct kvm_debug_exit_arch *arch_info)
1566{
6e0552a3 1567 int handle = DEBUG_RETURN_GUEST;
2cbd1581
FR		 1568 int n;
1569 int flag = 0;
1570
1571 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1572 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1573 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1574 if (n >= 0) {
6e0552a3 1575 handle = DEBUG_RETURN_GDB;
2cbd1581
FR		 1576 }
1577 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1578 KVMPPC_DEBUG_WATCH_WRITE)) {
1579 n = find_hw_watchpoint(arch_info->address, &flag);
1580 if (n >= 0) {
6e0552a3 1581 handle = DEBUG_RETURN_GDB;
2cbd1581
FR		 1582 cs->watchpoint_hit = &hw_watchpoint;
1583 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1584 hw_watchpoint.flags = flag;
1585 }
1586 }
1587 }
1588 return handle;
1589}
1590
468e3a1a
FR		 1591static int kvm_handle_singlestep(void)
1592{
6e0552a3 1593 return DEBUG_RETURN_GDB;
468e3a1a
FR		 1594}
1595
1596static int kvm_handle_sw_breakpoint(void)
1597{
6e0552a3 1598 return DEBUG_RETURN_GDB;
468e3a1a
FR		 1599}
1600
8a0548f9
BB		 1601static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1602{
1603 CPUState *cs = CPU(cpu);
1604 CPUPPCState *env = &cpu->env;
1605 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
8a0548f9 1606
88365d17 1607 if (cs->singlestep_enabled) {
468e3a1a
FR		 1608 return kvm_handle_singlestep();
1609 }
8a0548f9 1610
468e3a1a
FR		 1611 if (arch_info->status) {
1612 return kvm_handle_hw_breakpoint(cs, arch_info);
8a0548f9
BB		 1613 }
1614
468e3a1a
FR		 1615 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1616 return kvm_handle_sw_breakpoint();
1617 }
1618
1619 /*
1620 * QEMU is not able to handle debug exception, so inject
1621 * program exception to guest;
1622 * Yes program exception NOT debug exception !!
1623 * When QEMU is using debug resources then debug exception must
1624 * be always set. To achieve this we set MSR_DE and also set
1625 * MSRP_DEP so guest cannot change MSR_DE.
1626 * When emulating debug resource for guest we want guest
1627 * to control MSR_DE (enable/disable debug interrupt on need).
1628 * Supporting both configurations are NOT possible.
1629 * So the result is that we cannot share debug resources
1630 * between QEMU and Guest on BOOKE architecture.
1631 * In the current design QEMU gets the priority over guest,
1632 * this means that if QEMU is using debug resources then guest
1633 * cannot use them;
1634 * For software breakpoint QEMU uses a privileged instruction;
1635 * So there cannot be any reason that we are here for guest
1636 * set debug exception, only possibility is guest executed a
1637 * privileged / illegal instruction and that's why we are
1638 * injecting a program interrupt.
1639 */
1640 cpu_synchronize_state(cs);
1641 /*
1642 * env->nip is PC, so increment this by 4 to use
1643 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1644 */
1645 env->nip += 4;
1646 cs->exception_index = POWERPC_EXCP_PROGRAM;
1647 env->error_code = POWERPC_EXCP_INVAL;
1648 ppc_cpu_do_interrupt(cs);
1649
6e0552a3 1650 return DEBUG_RETURN_GUEST;
8a0548f9
BB		 1651}
1652
20d695a9 1653int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1654{
20d695a9
AF		 1655 PowerPCCPU *cpu = POWERPC_CPU(cs);
1656 CPUPPCState *env = &cpu->env;
bb4ea393 1657 int ret;
d76d1650 1658
195801d7 1659 bql_lock();
4b8523ee 1660
d76d1650
AJ		 1661 switch (run->exit_reason) {
1662 case KVM_EXIT_DCR:
1663 if (run->dcr.is_write) {
8d83cbf1 1664 trace_kvm_handle_dcr_write();
d76d1650
AJ		 1665 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1666 } else {
228152c2 1667 trace_kvm_handle_dcr_read();
d76d1650
AJ		 1668 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1669 }
1670 break;
1671 case KVM_EXIT_HLT:
8d83cbf1 1672 trace_kvm_handle_halt();
259186a7 1673 ret = kvmppc_handle_halt(cpu);
d76d1650 1674 break;
c6304a4a 1675#if defined(TARGET_PPC64)
f61b4bed 1676 case KVM_EXIT_PAPR_HCALL:
f290a238 1677 trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
20d695a9 1678 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1679 run->papr_hcall.nr,
f61b4bed 1680 run->papr_hcall.args);
78e8fde2 1681 ret = 0;
f61b4bed
AG		 1682 break;
1683#endif
5b95b8b9 1684 case KVM_EXIT_EPR:
8d83cbf1 1685 trace_kvm_handle_epr();
933b19ea 1686 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1687 ret = 0;
1688 break;
31f2cb8f 1689 case KVM_EXIT_WATCHDOG:
8d83cbf1 1690 trace_kvm_handle_watchdog_expiry();
31f2cb8f
BB		 1691 watchdog_perform_action();
1692 ret = 0;
1693 break;
1694
8a0548f9 1695 case KVM_EXIT_DEBUG:
8d83cbf1 1696 trace_kvm_handle_debug_exception();
8a0548f9
BB		 1697 if (kvm_handle_debug(cpu, run)) {
1698 ret = EXCP_DEBUG;
1699 break;
1700 }
1701 /* re-enter, this exception was guest-internal */
1702 ret = 0;
1703 break;
1704
9ac703ac
AP		 1705#if defined(TARGET_PPC64)
1706 case KVM_EXIT_NMI:
1707 trace_kvm_handle_nmi_exception();
1708 ret = kvm_handle_nmi(cpu, run);
1709 break;
1710#endif
1711
73aaec4a
JK		 1712 default:
1713 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1714 ret = -1;
1715 break;
d76d1650
AJ		 1716 }
1717
195801d7 1718 bql_unlock();
d76d1650
AJ		 1719 return ret;
1720}
1721
31f2cb8f
BB		 1722int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1723{
1724 CPUState *cs = CPU(cpu);
1725 uint32_t bits = tsr_bits;
1726 struct kvm_one_reg reg = {
1727 .id = KVM_REG_PPC_OR_TSR,
1728 .addr = (uintptr_t) &bits,
1729 };
1730
c4550e6e
CLG		 1731 if (!kvm_enabled()) {
1732 return 0;
1733 }
1734
31f2cb8f
BB		 1735 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1736}
1737
1738int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1739{
1740
1741 CPUState *cs = CPU(cpu);
1742 uint32_t bits = tsr_bits;
1743 struct kvm_one_reg reg = {
1744 .id = KVM_REG_PPC_CLEAR_TSR,
1745 .addr = (uintptr_t) &bits,
1746 };
1747
c4550e6e
CLG		 1748 if (!kvm_enabled()) {
1749 return 0;
1750 }
1751
31f2cb8f
BB		 1752 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1753}
1754
1755int kvmppc_set_tcr(PowerPCCPU *cpu)
1756{
1757 CPUState *cs = CPU(cpu);
1758 CPUPPCState *env = &cpu->env;
1759 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1760
1761 struct kvm_one_reg reg = {
1762 .id = KVM_REG_PPC_TCR,
1763 .addr = (uintptr_t) &tcr,
1764 };
1765
c4550e6e
CLG		 1766 if (!kvm_enabled()) {
1767 return 0;
1768 }
1769
31f2cb8f
BB		 1770 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1771}
1772
1773int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1774{
1775 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1776 int ret;
1777
1778 if (!kvm_enabled()) {
1779 return -1;
1780 }
1781
1782 if (!cap_ppc_watchdog) {
1783 printf("warning: KVM does not support watchdog");
1784 return -1;
1785 }
1786
48add816 1787 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1788 if (ret < 0) {
1789 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1790 __func__, strerror(-ret));
1791 return ret;
1792 }
1793
1794 return ret;
1795}
1796
dc333cd6
AG		 1797static int read_cpuinfo(const char *field, char *value, int len)
1798{
1799 FILE *f;
1800 int ret = -1;
1801 int field_len = strlen(field);
1802 char line[512];
1803
1804 f = fopen("/proc/cpuinfo", "r");
1805 if (!f) {
1806 return -1;
1807 }
1808
1809 do {
ef951443 1810 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1811 break;
1812 }
1813 if (!strncmp(line, field, field_len)) {
ae215068 1814 pstrcpy(value, len, line);
dc333cd6
AG		 1815 ret = 0;
1816 break;
1817 }
c995e942 1818 } while (*line);
dc333cd6
AG		 1819
1820 fclose(f);
1821
1822 return ret;
1823}
1824
9cbcfb59 1825static uint32_t kvmppc_get_tbfreq_procfs(void)
dc333cd6
AG		 1826{
1827 char line[512];
1828 char *ns;
9cbcfb59
GK		 1829 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1830 uint32_t tbfreq_procfs;
dc333cd6
AG		 1831
1832 if (read_cpuinfo("timebase", line, sizeof(line))) {
9cbcfb59 1833 return tbfreq_fallback;
dc333cd6
AG		 1834 }
1835
c995e942
DG		 1836 ns = strchr(line, ':');
1837 if (!ns) {
9cbcfb59 1838 return tbfreq_fallback;
dc333cd6
AG		 1839 }
1840
9cbcfb59
GK		 1841 tbfreq_procfs = atoi(++ns);
1842
1843 /* 0 is certainly not acceptable by the guest, return fallback value */
1844 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1845}
1846
1847uint32_t kvmppc_get_tbfreq(void)
1848{
1849 static uint32_t cached_tbfreq;
1850
1851 if (!cached_tbfreq) {
1852 cached_tbfreq = kvmppc_get_tbfreq_procfs();
1853 }
dc333cd6 1854
9cbcfb59 1855 return cached_tbfreq;
dc333cd6 1856}
4513d923 1857
ef951443
ND		 1858bool kvmppc_get_host_serial(char **value)
1859{
1860 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1861 NULL);
1862}
1863
1864bool kvmppc_get_host_model(char **value)
1865{
1866 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1867}
1868
eadaada1
AG		 1869/* Try to find a device tree node for a CPU with clock-frequency property */
1870static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1871{
1872 struct dirent *dirp;
1873 DIR *dp;
1874
c995e942
DG		 1875 dp = opendir(PROC_DEVTREE_CPU);
1876 if (!dp) {
eadaada1
AG		 1877 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1878 return -1;
1879 }
1880
1881 buf[0] = '\0';
1882 while ((dirp = readdir(dp)) != NULL) {
1883 FILE *f;
1a42c692
MOA		 1884
1885 /* Don't accidentally read from the current and parent directories */
1886 if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) {
1887 continue;
1888 }
1889
eadaada1
AG		 1890 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1891 dirp->d_name);
1892 f = fopen(buf, "r");
1893 if (f) {
1894 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1895 fclose(f);
1896 break;
1897 }
1898 buf[0] = '\0';
1899 }
1900 closedir(dp);
1901 if (buf[0] == '\0') {
1902 printf("Unknown host!\n");
1903 return -1;
1904 }
1905
1906 return 0;
1907}
1908
7d94a30b 1909static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1910{
9bc884b7
DG		 1911 union {
1912 uint32_t v32;
1913 uint64_t v64;
1914 } u;
eadaada1
AG		 1915 FILE *f;
1916 int len;
1917
7d94a30b 1918 f = fopen(filename, "rb");
eadaada1
AG		 1919 if (!f) {
1920 return -1;
1921 }
1922
9bc884b7 1923 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1924 fclose(f);
1925 switch (len) {
9bc884b7
DG		 1926 case 4:
1927 /* property is a 32-bit quantity */
1928 return be32_to_cpu(u.v32);
1929 case 8:
1930 return be64_to_cpu(u.v64);
eadaada1
AG		 1931 }
1932
1933 return 0;
1934}
1935
c995e942
DG		 1936/*
1937 * Read a CPU node property from the host device tree that's a single
7d94a30b 1938 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
c995e942
DG		 1939 * (can't find or open the property, or doesn't understand the format)
1940 */
7d94a30b
SB		 1941static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1942{
1943 char buf[PATH_MAX], *tmp;
1944 uint64_t val;
1945
1946 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1947 return -1;
1948 }
1949
1950 tmp = g_strdup_printf("%s/%s", buf, propname);
1951 val = kvmppc_read_int_dt(tmp);
1952 g_free(tmp);
1953
1954 return val;
1955}
1956
9bc884b7
DG		 1957uint64_t kvmppc_get_clockfreq(void)
1958{
1959 return kvmppc_read_int_cpu_dt("clock-frequency");
1960}
1961
7d050527
SJS		 1962static int kvmppc_get_dec_bits(void)
1963{
1964 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1965
1966 if (nr_bits > 0) {
1967 return nr_bits;
1968 }
1969 return 0;
1970}
1971
1a61a9ae 1972static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
db70b311
RH		 1973{
1974 CPUState *cs = env_cpu(env);
1a61a9ae 1975
6fd33a75 1976 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1977 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1978 return 0;
1979 }
1980
1981 return 1;
1982}
1983
1984int kvmppc_get_hasidle(CPUPPCState *env)
1985{
1986 struct kvm_ppc_pvinfo pvinfo;
1987
1988 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1989 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1990 return 1;
1991 }
1992
1993 return 0;
1994}
1995
1328c2bf 1996int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09 1997{
c995e942 1998 uint32_t *hc = (uint32_t *)buf;
45024f09
AG		 1999 struct kvm_ppc_pvinfo pvinfo;
2000
1a61a9ae 2001 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 2002 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 2003 return 0;
2004 }
45024f09
AG		 2005
2006 /*
d13fc32e 2007 * Fallback to always fail hypercalls regardless of endianness:
45024f09 2008 *
d13fc32e 2009 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 2010 * li r3, -1
d13fc32e
AG		 2011 * b .+8 (becomes nop in wrong endian)
2012 * bswap32(li r3, -1)
45024f09
AG		 2013 */
2014
d13fc32e
AG		 2015 hc[0] = cpu_to_be32(0x08000048);
2016 hc[1] = cpu_to_be32(0x3860ffff);
2017 hc[2] = cpu_to_be32(0x48000008);
2018 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 2019
0ddbd053 2020 return 1;
45024f09
AG		 2021}
2022
026bfd89
DG		 2023static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2024{
2025 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2026}
2027
2028void kvmppc_enable_logical_ci_hcalls(void)
2029{
2030 /*
2031 * FIXME: it would be nice if we could detect the cases where
2032 * we're using a device which requires the in kernel
2033 * implementation of these hcalls, but the kernel lacks them and
2034 * produce a warning.
2035 */
2036 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2037 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2038}
2039
ef9971dd
AK		 2040void kvmppc_enable_set_mode_hcall(void)
2041{
2042 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2043}
2044
5145ad4f
NW		 2045void kvmppc_enable_clear_ref_mod_hcalls(void)
2046{
2047 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2048 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2049}
2050
68f9f708
SJS		 2051void kvmppc_enable_h_page_init(void)
2052{
2053 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2054}
2055
82123b75
BR		 2056void kvmppc_enable_h_rpt_invalidate(void)
2057{
2058 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2059}
2060
1bc22652 2061void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2062{
1bc22652 2063 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2064 int ret;
2065
da20aed1
DG		 2066 if (!kvm_enabled()) {
2067 return;
2068 }
2069
48add816 2070 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2071 if (ret) {
072ed5f2
TH		 2072 error_report("This vCPU type or KVM version does not support PAPR");
2073 exit(1);
94135e81 2074 }
9b00ea49 2075
c995e942
DG		 2076 /*
2077 * Update the capability flag so we sync the right information
2078 * with kvm
2079 */
9b00ea49 2080 cap_papr = 1;
f61b4bed
AG		 2081}
2082
d6e166c0 2083int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2084{
d6e166c0 2085 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2086}
2087
5b95b8b9
AG		 2088void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2089{
5b95b8b9 2090 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2091 int ret;
2092
48add816 2093 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2094 if (ret && mpic_proxy) {
072ed5f2
TH		 2095 error_report("This KVM version does not support EPR");
2096 exit(1);
5b95b8b9
AG		 2097 }
2098}
2099
ec010c00
NP		 2100bool kvmppc_get_fwnmi(void)
2101{
2102 return cap_fwnmi;
2103}
2104
aef92d87 2105int kvmppc_set_fwnmi(PowerPCCPU *cpu)
9d953ce4 2106{
9d953ce4
AP		 2107 CPUState *cs = CPU(cpu);
2108
2109 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2110}
2111
e97c3636
DG		 2112int kvmppc_smt_threads(void)
2113{
2114 return cap_ppc_smt ? cap_ppc_smt : 1;
2115}
2116
fa98fbfc
SB		 2117int kvmppc_set_smt_threads(int smt)
2118{
2119 int ret;
2120
2121 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2122 if (!ret) {
2123 cap_ppc_smt = smt;
2124 }
2125 return ret;
2126}
2127
0c115681 2128void kvmppc_error_append_smt_possible_hint(Error *const *errp)
fa98fbfc
SB		 2129{
2130 int i;
2131 GString *g;
2132 char *s;
2133
2134 assert(kvm_enabled());
2135 if (cap_ppc_smt_possible) {
2136 g = g_string_new("Available VSMT modes:");
2137 for (i = 63; i >= 0; i--) {
2138 if ((1UL << i) & cap_ppc_smt_possible) {
2139 g_string_append_printf(g, " %lu", (1UL << i));
2140 }
2141 }
2142 s = g_string_free(g, false);
1a639fdf 2143 error_append_hint(errp, "%s.\n", s);
fa98fbfc
SB		 2144 g_free(s);
2145 } else {
1a639fdf 2146 error_append_hint(errp,
fa98fbfc
SB		 2147 "This KVM seems to be too old to support VSMT.\n");
2148 }
2149}
2150
2151
7f763a5d 2152#ifdef TARGET_PPC64
6a84737c 2153uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
7f763a5d 2154{
f36951c1
DG		 2155 struct kvm_ppc_smmu_info info;
2156 long rampagesize, best_page_shift;
2157 int i;
2158
c995e942
DG		 2159 /*
2160 * Find the largest hardware supported page size that's less than
2161 * or equal to the (logical) backing page size of guest RAM
2162 */
ab256960 2163 kvm_get_smmu_info(&info, &error_fatal);
905b7ee4 2164 rampagesize = qemu_minrampagesize();
f36951c1
DG		 2165 best_page_shift = 0;
2166
2167 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2168 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2169
2170 if (!sps->page_shift) {
2171 continue;
2172 }
2173
2174 if ((sps->page_shift > best_page_shift)
2175 && ((1UL << sps->page_shift) <= rampagesize)) {
2176 best_page_shift = sps->page_shift;
2177 }
2178 }
2179
6a84737c 2180 return 1ULL << (best_page_shift + hash_shift - 7);
7f763a5d
DG		 2181}
2182#endif
2183
da95324e
AK		 2184bool kvmppc_spapr_use_multitce(void)
2185{
2186 return cap_spapr_multitce;
2187}
2188
3dc410ae
AK		 2189int kvmppc_spapr_enable_inkernel_multitce(void)
2190{
2191 int ret;
2192
2193 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2194 H_PUT_TCE_INDIRECT, 1);
2195 if (!ret) {
2196 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2197 H_STUFF_TCE, 1);
2198 }
2199
2200 return ret;
2201}
2202
d6ee2a7c
AK		 2203void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2204 uint64_t bus_offset, uint32_t nb_table,
2205 int *pfd, bool need_vfio)
0f5cb298 2206{
0f5cb298
DG		 2207 long len;
2208 int fd;
2209 void *table;
2210
c995e942
DG		 2211 /*
2212 * Must set fd to -1 so we don't try to munmap when called for
b5aec396
DG		 2213 * destroying the table, which the upper layers -will- do
2214 */
2215 *pfd = -1;
6a81dd17 2216 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2217 return NULL;
2218 }
2219
d6ee2a7c
AK		 2220 if (cap_spapr_tce_64) {
2221 struct kvm_create_spapr_tce_64 args = {
2222 .liobn = liobn,
2223 .page_shift = page_shift,
2224 .offset = bus_offset >> page_shift,
2225 .size = nb_table,
2226 .flags = 0
2227 };
2228 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2229 if (fd < 0) {
2230 fprintf(stderr,
2231 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2232 liobn);
2233 return NULL;
2234 }
2235 } else if (cap_spapr_tce) {
2236 uint64_t window_size = (uint64_t) nb_table << page_shift;
2237 struct kvm_create_spapr_tce args = {
2238 .liobn = liobn,
2239 .window_size = window_size,
2240 };
2241 if ((window_size != args.window_size) || bus_offset) {
2242 return NULL;
2243 }
2244 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2245 if (fd < 0) {
2246 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2247 liobn);
2248 return NULL;
2249 }
2250 } else {
0f5cb298
DG		 2251 return NULL;
2252 }
2253
d6ee2a7c 2254 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2255 /* FIXME: round this up to page size */
2256
c995e942 2257 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2258 if (table == MAP_FAILED) {
b5aec396
DG		 2259 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2260 liobn);
0f5cb298
DG		 2261 close(fd);
2262 return NULL;
2263 }
2264
2265 *pfd = fd;
2266 return table;
2267}
2268
523e7b8a 2269int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2270{
2271 long len;
2272
2273 if (fd < 0) {
2274 return -1;
2275 }
2276
523e7b8a 2277 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2278 if ((munmap(table, len) < 0) ||
2279 (close(fd) < 0)) {
b5aec396
DG		 2280 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2281 strerror(errno));
0f5cb298
DG		 2282 /* Leak the table */
2283 }
2284
2285 return 0;
2286}
2287
7f763a5d
DG		 2288int kvmppc_reset_htab(int shift_hint)
2289{
2290 uint32_t shift = shift_hint;
2291
ace9a2cb
DG		 2292 if (!kvm_enabled()) {
2293 /* Full emulation, tell caller to allocate htab itself */
2294 return 0;
2295 }
6977afda 2296 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2297 int ret;
2298 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb 2299 if (ret == -ENOTTY) {
c995e942
DG		 2300 /*
2301 * At least some versions of PR KVM advertise the
ace9a2cb
DG		 2302 * capability, but don't implement the ioctl(). Oops.
2303 * Return 0 so that we allocate the htab in qemu, as is
c995e942
DG		 2304 * correct for PR.
2305 */
ace9a2cb
DG		 2306 return 0;
2307 } else if (ret < 0) {
7f763a5d
DG		 2308 return ret;
2309 }
2310 return shift;
2311 }
2312
c995e942
DG		 2313 /*
2314 * We have a kernel that predates the htab reset calls. For PR
ace9a2cb 2315 * KVM, we need to allocate the htab ourselves, for an HV KVM of
c995e942
DG		 2316 * this era, it has allocated a 16MB fixed size hash table
2317 * already.
2318 */
96c9cff0 2319 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2320 /* PR - tell caller to allocate htab */
2321 return 0;
2322 } else {
2323 /* HV - assume 16MB kernel allocated htab */
2324 return 24;
2325 }
7f763a5d
DG		 2326}
2327
a1e98583
DG		 2328static inline uint32_t mfpvr(void)
2329{
2330 uint32_t pvr;
2331
2332 asm ("mfpvr %0"
2333 : "=r"(pvr));
2334 return pvr;
2335}
2336
a7342588
DG		 2337static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2338{
2339 if (on) {
2340 *word |= flags;
2341 } else {
2342 *word &= ~flags;
2343 }
2344}
2345
2985b86b
AF		 2346static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2347{
2348 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2349 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2350 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2351
cfe34f44 2352 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2353 pcc->pvr = mfpvr();
a7342588 2354
3f2ca480
DG		 2355 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2356 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2357 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2358 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2359 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2360 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2361
2362 if (dcache_size != -1) {
2363 pcc->l1_dcache_size = dcache_size;
2364 }
2365
2366 if (icache_size != -1) {
2367 pcc->l1_icache_size = icache_size;
2368 }
c64abd1f
SB		 2369
2370#if defined(TARGET_PPC64)
aa6edf97 2371 pcc->radix_page_info = kvmppc_get_radix_page_info();
5f3066d8
DG		 2372
2373 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2374 /*
2375 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2376 * compliant. More importantly, advertising ISA 3.00
2377 * architected mode may prevent guests from activating
2378 * necessary DD1 workarounds.
2379 */
2380 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2381 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2382 }
c64abd1f 2383#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2384}
2385
3b961124
SY		 2386bool kvmppc_has_cap_epr(void)
2387{
2388 return cap_epr;
2389}
2390
87a91de6
AG		 2391bool kvmppc_has_cap_fixup_hcalls(void)
2392{
2393 return cap_fixup_hcalls;
2394}
2395
bac3bf28
TH		 2396bool kvmppc_has_cap_htm(void)
2397{
2398 return cap_htm;
2399}
2400
cf1c4cce
SB		 2401bool kvmppc_has_cap_mmu_radix(void)
2402{
2403 return cap_mmu_radix;
2404}
2405
2406bool kvmppc_has_cap_mmu_hash_v3(void)
2407{
2408 return cap_mmu_hash_v3;
2409}
2410
072f416a
SJS		 2411static bool kvmppc_power8_host(void)
2412{
2413 bool ret = false;
2414#ifdef TARGET_PPC64
2415 {
2416 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2417 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2418 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2419 (base_pvr == CPU_POWERPC_POWER8_BASE);
2420 }
2421#endif /* TARGET_PPC64 */
2422 return ret;
2423}
2424
8fea7044
SJS		 2425static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2426{
072f416a
SJS		 2427 bool l1d_thread_priv_req = !kvmppc_power8_host();
2428
8fea7044
SJS		 2429 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2430 return 2;
072f416a
SJS		 2431 } else if ((!l1d_thread_priv_req ||
2432 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2433 (c.character & c.character_mask
2434 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2435 return 1;
2436 }
2437
2438 return 0;
2439}
2440
2441static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2442{
2443 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2444 return 2;
2445 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2446 return 1;
2447 }
2448
2449 return 0;
2450}
2451
2452static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2453{
399b2896
SJS		 2454 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2455 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2456 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2457 return SPAPR_CAP_FIXED_NA;
2458 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2459 return SPAPR_CAP_WORKAROUND;
2460 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
8fea7044
SJS		 2461 return SPAPR_CAP_FIXED_CCD;
2462 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2463 return SPAPR_CAP_FIXED_IBS;
2464 }
2465
2466 return 0;
2467}
2468
8ff43ee4
SJS		 2469static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2470{
2471 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2472 return 1;
2473 }
2474 return 0;
2475}
2476
38afd772
CLG		 2477bool kvmppc_has_cap_xive(void)
2478{
2479 return cap_xive;
2480}
2481
8acc2ae5
SJS		 2482static void kvmppc_get_cpu_characteristics(KVMState *s)
2483{
2484 struct kvm_ppc_cpu_char c;
2485 int ret;
2486
2487 /* Assume broken */
2488 cap_ppc_safe_cache = 0;
2489 cap_ppc_safe_bounds_check = 0;
2490 cap_ppc_safe_indirect_branch = 0;
2491
2492 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2493 if (!ret) {
2494 return;
2495 }
2496 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2497 if (ret < 0) {
2498 return;
2499 }
8fea7044
SJS		 2500
2501 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2502 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2503 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8ff43ee4
SJS		 2504 cap_ppc_count_cache_flush_assist =
2505 parse_cap_ppc_count_cache_flush_assist(c);
8acc2ae5
SJS		 2506}
2507
2508int kvmppc_get_cap_safe_cache(void)
2509{
2510 return cap_ppc_safe_cache;
2511}
2512
2513int kvmppc_get_cap_safe_bounds_check(void)
2514{
2515 return cap_ppc_safe_bounds_check;
2516}
2517
2518int kvmppc_get_cap_safe_indirect_branch(void)
2519{
2520 return cap_ppc_safe_indirect_branch;
2521}
2522
8ff43ee4
SJS		 2523int kvmppc_get_cap_count_cache_flush_assist(void)
2524{
2525 return cap_ppc_count_cache_flush_assist;
2526}
2527
b9a477b7
SJS		 2528bool kvmppc_has_cap_nested_kvm_hv(void)
2529{
2530 return !!cap_ppc_nested_kvm_hv;
2531}
2532
2533int kvmppc_set_cap_nested_kvm_hv(int enable)
2534{
2535 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2536}
2537
9ded780c
AK		 2538bool kvmppc_has_cap_spapr_vfio(void)
2539{
2540 return cap_spapr_vfio;
2541}
2542
7d050527
SJS		 2543int kvmppc_get_cap_large_decr(void)
2544{
2545 return cap_large_decr;
2546}
2547
2548int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2549{
2550 CPUState *cs = CPU(cpu);
59411579 2551 uint64_t lpcr = 0;
7d050527
SJS		 2552
2553 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2554 /* Do we need to modify the LPCR? */
2555 if (!!(lpcr & LPCR_LD) != !!enable) {
2556 if (enable) {
2557 lpcr |= LPCR_LD;
2558 } else {
2559 lpcr &= ~LPCR_LD;
2560 }
2561 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2562 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2563
2564 if (!!(lpcr & LPCR_LD) != !!enable) {
2565 return -1;
2566 }
2567 }
2568
2569 return 0;
2570}
2571
82123b75
BR		 2572int kvmppc_has_cap_rpt_invalidate(void)
2573{
2574 return cap_rpt_invalidate;
2575}
2576
ccc5a4c5
NP		 2577bool kvmppc_supports_ail_3(void)
2578{
2579 return cap_ail_mode_3;
2580}
2581
52b2519c
TH		 2582PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2583{
2584 uint32_t host_pvr = mfpvr();
2585 PowerPCCPUClass *pvr_pcc;
2586
2587 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2588 if (pvr_pcc == NULL) {
2589 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2590 }
2591
2592 return pvr_pcc;
2593}
2594
165dc3ed
DG		 2595static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2596{
2597 MachineClass *mc = MACHINE_CLASS(oc);
2598
2599 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2600}
2601
2602static int kvm_ppc_register_host_cpu_type(void)
5ba4576b
AF		 2603{
2604 TypeInfo type_info = {
2605 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2606 .class_init = kvmppc_host_cpu_class_init,
2607 };
5ba4576b 2608 PowerPCCPUClass *pvr_pcc;
92e926e1 2609 ObjectClass *oc;
5b79b1ca 2610 DeviceClass *dc;
715d4b96 2611 int i;
5ba4576b 2612
52b2519c 2613 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2614 if (pvr_pcc == NULL) {
2615 return -1;
2616 }
2617 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2618 type_register(&type_info);
165dc3ed
DG		 2619 /* override TCG default cpu type with 'host' cpu model */
2620 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2621 false, NULL);
5b79b1ca 2622
92e926e1
GK		 2623 oc = object_class_by_name(type_info.name);
2624 g_assert(oc);
2625
715d4b96
TH		 2626 /*
2627 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2628 * we want "POWER8" to be a "family" alias that points to the current
2629 * host CPU type, too)
2630 */
2631 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2632 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2633 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2634 char *suffix;
2635
2636 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2637 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2638 if (suffix) {
2639 *suffix = 0;
2640 }
715d4b96
TH		 2641 break;
2642 }
2643 }
2644
5ba4576b
AF		 2645 return 0;
2646}
2647
feaa64c4
DG		 2648int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2649{
2650 struct kvm_rtas_token_args args = {
2651 .token = token,
2652 };
2653
2654 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2655 return -ENOENT;
2656 }
2657
7701aeed 2658 strncpy(args.name, function, sizeof(args.name) - 1);
feaa64c4
DG		 2659
2660 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2661}
12b1143b 2662
14b0d748 2663int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2664{
2665 struct kvm_get_htab_fd s = {
2666 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2667 .start_index = index,
e68cb8b4 2668 };
82be8e73 2669 int ret;
e68cb8b4
AK		 2670
2671 if (!cap_htab_fd) {
14b0d748
GK		 2672 error_setg(errp, "KVM version doesn't support %s the HPT",
2673 write ? "writing" : "reading");
82be8e73
GK		 2674 return -ENOTSUP;
2675 }
2676
2677 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2678 if (ret < 0) {
14b0d748
GK		 2679 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2680 write ? "writing" : "reading", write ? "to" : "from",
2681 strerror(errno));
82be8e73 2682 return -errno;
e68cb8b4
AK		 2683 }
2684
82be8e73 2685 return ret;
e68cb8b4
AK		 2686}
2687
2688int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2689{
bc72ad67 2690 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2691 uint8_t buf[bufsize];
2692 ssize_t rc;
2693
2694 do {
2695 rc = read(fd, buf, bufsize);
2696 if (rc < 0) {
2697 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2698 strerror(errno));
2699 return rc;
2700 } else if (rc) {
e094c4c1
CLG		 2701 uint8_t *buffer = buf;
2702 ssize_t n = rc;
2703 while (n) {
2704 struct kvm_get_htab_header *head =
2705 (struct kvm_get_htab_header *) buffer;
2706 size_t chunksize = sizeof(*head) +
2707 HASH_PTE_SIZE_64 * head->n_valid;
2708
2709 qemu_put_be32(f, head->index);
2710 qemu_put_be16(f, head->n_valid);
2711 qemu_put_be16(f, head->n_invalid);
2712 qemu_put_buffer(f, (void *)(head + 1),
2713 HASH_PTE_SIZE_64 * head->n_valid);
2714
2715 buffer += chunksize;
2716 n -= chunksize;
2717 }
e68cb8b4
AK		 2718 }
2719 } while ((rc != 0)
c995e942
DG		 2720 && ((max_ns < 0) ||
2721 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2722
2723 return (rc == 0) ? 1 : 0;
2724}
2725
2726int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
0a06e4d6 2727 uint16_t n_valid, uint16_t n_invalid, Error **errp)
e68cb8b4
AK		 2728{
2729 struct kvm_get_htab_header *buf;
c995e942 2730 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
e68cb8b4
AK		 2731 ssize_t rc;
2732
2733 buf = alloca(chunksize);
e68cb8b4
AK		 2734 buf->index = index;
2735 buf->n_valid = n_valid;
2736 buf->n_invalid = n_invalid;
2737
c995e942 2738 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
e68cb8b4
AK		 2739
2740 rc = write(fd, buf, chunksize);
2741 if (rc < 0) {
0a06e4d6
GK		 2742 error_setg_errno(errp, errno, "Error writing the KVM hash table");
2743 return -errno;
e68cb8b4
AK		 2744 }
2745 if (rc != chunksize) {
2746 /* We should never get a short write on a single chunk */
0a06e4d6
GK		 2747 error_setg(errp, "Short write while restoring the KVM hash table");
2748 return -ENOSPC;
e68cb8b4
AK		 2749 }
2750 return 0;
2751}
2752
20d695a9 2753bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2754{
2755 return true;
2756}
a1b87fe0 2757
82169660
SW		 2758void kvm_arch_init_irq_routing(KVMState *s)
2759{
2760}
c65f9a07 2761
1ad9f0a4 2762void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2763{
1ad9f0a4
DG		 2764 int fd, rc;
2765 int i;
7c43bca0 2766
14b0d748 2767 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2768
1ad9f0a4
DG		 2769 i = 0;
2770 while (i < n) {
2771 struct kvm_get_htab_header *hdr;
2772 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2773 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2774
1ad9f0a4
DG		 2775 rc = read(fd, buf, sizeof(buf));
2776 if (rc < 0) {
2777 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2778 }
7c43bca0 2779
1ad9f0a4
DG		 2780 hdr = (struct kvm_get_htab_header *)buf;
2781 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2782 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2783
1ad9f0a4
DG		 2784 if (hdr->index != (ptex + i)) {
2785 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2786 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2787 }
2788
a36593e1
AK		 2789 if (n - i < valid) {
2790 valid = n - i;
2791 }
2792 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2793 i += valid;
7c43bca0 2794
1ad9f0a4
DG		 2795 if ((n - i) < invalid) {
2796 invalid = n - i;
2797 }
2798 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2799 i += invalid;
1ad9f0a4
DG		 2800
2801 hdr = (struct kvm_get_htab_header *)
2802 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2803 }
2804 }
2805
2806 close(fd);
7c43bca0 2807}
c1385933 2808
1ad9f0a4 2809void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2810{
1ad9f0a4 2811 int fd, rc;
1ad9f0a4
DG		 2812 struct {
2813 struct kvm_get_htab_header hdr;
2814 uint64_t pte0;
2815 uint64_t pte1;
2816 } buf;
c1385933 2817
14b0d748 2818 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2819
1ad9f0a4
DG		 2820 buf.hdr.n_valid = 1;
2821 buf.hdr.n_invalid = 0;
2822 buf.hdr.index = ptex;
2823 buf.pte0 = cpu_to_be64(pte0);
2824 buf.pte1 = cpu_to_be64(pte1);
c1385933 2825
1ad9f0a4
DG		 2826 rc = write(fd, &buf, sizeof(buf));
2827 if (rc != sizeof(buf)) {
2828 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2829 }
2830 close(fd);
c1385933 2831}
9e03a040
FB		 2832
2833int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2834 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2835{
2836 return 0;
2837}
1850b6b7 2838
38d87493
PX		 2839int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2840 int vector, PCIDevice *dev)
2841{
2842 return 0;
2843}
2844
2845int kvm_arch_release_virq_post(int virq)
2846{
2847 return 0;
2848}
2849
1850b6b7
EA		 2850int kvm_arch_msi_data_to_gsi(uint32_t data)
2851{
2852 return data & 0xffff;
2853}
4d9392be 2854
9ac703ac
AP		 2855#if defined(TARGET_PPC64)
2856int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run)
2857{
211a7784 2858 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
81fe70e4 2859
9ac703ac
AP		 2860 cpu_synchronize_state(CPU(cpu));
2861
211a7784 2862 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
9ac703ac
AP		 2863
2864 return 0;
2865}
2866#endif
2867
4d9392be
TH		 2868int kvmppc_enable_hwrng(void)
2869{
2870 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2871 return -1;
2872 }
2873
2874 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2875}
30f4b05b
DG		 2876
2877void kvmppc_check_papr_resize_hpt(Error **errp)
2878{
2879 if (!kvm_enabled()) {
b55d295e
DG		 2880 return; /* No KVM, we're good */
2881 }
2882
2883 if (cap_resize_hpt) {
2884 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2885 }
2886
b55d295e
DG		 2887 /* Otherwise fallback on looking for PR KVM */
2888 if (kvmppc_is_pr(kvm_state)) {
2889 return;
2890 }
30f4b05b
DG		 2891
2892 error_setg(errp,
2893 "Hash page table resizing not available with this KVM version");
2894}
b55d295e
DG		 2895
2896int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2897{
2898 CPUState *cs = CPU(cpu);
2899 struct kvm_ppc_resize_hpt rhpt = {
2900 .flags = flags,
2901 .shift = shift,
2902 };
2903
2904 if (!cap_resize_hpt) {
2905 return -ENOSYS;
2906 }
2907
2908 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2909}
2910
2911int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2912{
2913 CPUState *cs = CPU(cpu);
2914 struct kvm_ppc_resize_hpt rhpt = {
2915 .flags = flags,
2916 .shift = shift,
2917 };
2918
2919 if (!cap_resize_hpt) {
2920 return -ENOSYS;
2921 }
2922
2923 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2924}
2925
c363a37a
DHB		 2926/*
2927 * This is a helper function to detect a post migration scenario
2928 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2929 * the guest kernel can't handle a PVR value other than the actual host
2930 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2931 *
2932 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2933 * (so, we're HV), return true. The workaround itself is done in
2934 * cpu_post_load.
2935 *
2936 * The order here is important: we'll only check for KVM PR as a
2937 * fallback if the guest kernel can't handle the situation itself.
2938 * We need to avoid as much as possible querying the running KVM type
2939 * in QEMU level.
2940 */
2941bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2942{
2943 CPUState *cs = CPU(cpu);
2944
2945 if (!kvm_enabled()) {
2946 return false;
2947 }
2948
2949 if (cap_ppc_pvr_compat) {
2950 return false;
2951 }
2952
2953 return !kvmppc_is_pr(cs->kvm_state);
2954}
a84f7179
ND		 2955
2956void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2957{
2958 CPUState *cs = CPU(cpu);
2959
2960 if (kvm_enabled()) {
2961 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2962 }
2963}
9723295a
GK		 2964
2965void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2966{
2967 CPUState *cs = CPU(cpu);
2968
2969 if (kvm_enabled()) {
2970 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2971 }
2972}
92a5199b
TL		 2973
2974bool kvm_arch_cpu_check_are_resettable(void)
2975{
2976 return true;
2977}
3dba0a33
PB		 2978
2979void kvm_arch_accel_class_init(ObjectClass *oc)
2980{
2981}
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