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target/ppc: Move exception vector offset computation into a function
[mirror_qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
24#include "qemu-common.h"
30f4b05b 25#include "qapi/error.h"
072ed5f2 26#include "qemu/error-report.h"
33c11879 27#include "cpu.h"
715d4b96 28#include "cpu-models.h"
1de7afc9 29#include "qemu/timer.h"
9c17d615 30#include "sysemu/sysemu.h"
b3946626 31#include "sysemu/hw_accel.h"
d76d1650 32#include "kvm_ppc.h"
9c17d615
PB		 33#include "sysemu/cpus.h"
34#include "sysemu/device_tree.h"
d5aea6f3 35#include "mmu-hash64.h"
d76d1650 36
f61b4bed 37#include "hw/sysbus.h"
0d09e41a 38#include "hw/ppc/spapr.h"
7ebaf795 39#include "hw/ppc/spapr_cpu_core.h"
98a8b524 40#include "hw/ppc/ppc.h"
31f2cb8f 41#include "sysemu/watchdog.h"
b36f100e 42#include "trace.h"
88365d17 43#include "exec/gdbstub.h"
4c663752 44#include "exec/memattrs.h"
9c607668 45#include "exec/ram_addr.h"
2d103aae 46#include "sysemu/hostmem.h"
f348b6d1 47#include "qemu/cutils.h"
9c607668 48#include "qemu/mmap-alloc.h"
f3d9f303 49#include "elf.h"
c64abd1f 50#include "sysemu/kvm_int.h"
f61b4bed 51
d76d1650
AJ		 52//#define DEBUG_KVM
53
54#ifdef DEBUG_KVM
da56ff91 55#define DPRINTF(fmt, ...) \
d76d1650
AJ		 56 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
57#else
da56ff91 58#define DPRINTF(fmt, ...) \
d76d1650
AJ		 59 do { } while (0)
60#endif
61
eadaada1
AG		 62#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
63
94a8d39a
JK		 64const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
65 KVM_CAP_LAST_INFO
66};
67
fc87e185
AG		 68static int cap_interrupt_unset = false;
69static int cap_interrupt_level = false;
90dc8812 70static int cap_segstate;
90dc8812 71static int cap_booke_sregs;
e97c3636 72static int cap_ppc_smt;
fa98fbfc 73static int cap_ppc_smt_possible;
0f5cb298 74static int cap_spapr_tce;
d6ee2a7c 75static int cap_spapr_tce_64;
da95324e 76static int cap_spapr_multitce;
9bb62a07 77static int cap_spapr_vfio;
f1af19d7 78static int cap_hior;
d67d40ea 79static int cap_one_reg;
3b961124 80static int cap_epr;
31f2cb8f 81static int cap_ppc_watchdog;
9b00ea49 82static int cap_papr;
e68cb8b4 83static int cap_htab_fd;
87a91de6 84static int cap_fixup_hcalls;
bac3bf28 85static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 86static int cap_mmu_radix;
87static int cap_mmu_hash_v3;
b55d295e 88static int cap_resize_hpt;
c363a37a 89static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 90static int cap_ppc_safe_cache;
91static int cap_ppc_safe_bounds_check;
92static int cap_ppc_safe_indirect_branch;
8ff43ee4 93static int cap_ppc_count_cache_flush_assist;
b9a477b7 94static int cap_ppc_nested_kvm_hv;
7d050527 95static int cap_large_decr;
fc87e185 96
3c902d44
BB		 97static uint32_t debug_inst_opcode;
98
c821c2bd
AG		 99/* XXX We have a race condition where we actually have a level triggered
100 * interrupt, but the infrastructure can't expose that yet, so the guest
101 * takes but ignores it, goes to sleep and never gets notified that there's
102 * still an interrupt pending.
c6a94ba5 103 *
c821c2bd
AG		 104 * As a quick workaround, let's just wake up again 20 ms after we injected
105 * an interrupt. That way we can assure that we're always reinjecting
106 * interrupts in case the guest swallowed them.
c6a94ba5
AG		 107 */
108static QEMUTimer *idle_timer;
109
d5a68146 110static void kvm_kick_cpu(void *opaque)
c6a94ba5 111{
d5a68146 112 PowerPCCPU *cpu = opaque;
d5a68146 113
c08d7424 114 qemu_cpu_kick(CPU(cpu));
c6a94ba5
AG		 115}
116
96c9cff0
TH		 117/* Check whether we are running with KVM-PR (instead of KVM-HV). This
118 * should only be used for fallback tests - generally we should use
119 * explicit capabilities for the features we want, rather than
120 * assuming what is/isn't available depending on the KVM variant. */
121static bool kvmppc_is_pr(KVMState *ks)
122{
123 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 124 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 125}
126
2e9c10eb 127static int kvm_ppc_register_host_cpu_type(MachineState *ms);
8acc2ae5 128static void kvmppc_get_cpu_characteristics(KVMState *s);
7d050527 129static int kvmppc_get_dec_bits(void);
5ba4576b 130
b16565b3 131int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 132{
fc87e185 133 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
fc87e185 134 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
90dc8812 135 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 136 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 137 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 138 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 139 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 140 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 141 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 142 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 143 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 144 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 145 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
9b00ea49
DG		 146 /* Note: we don't set cap_papr here, because this capability is
147 * only activated after this by kvmppc_set_papr() */
6977afda 148 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 149 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 150 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 151 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 152 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
153 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
b55d295e 154 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 155 kvmppc_get_cpu_characteristics(s);
b9a477b7 156 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
7d050527 157 cap_large_decr = kvmppc_get_dec_bits();
c363a37a
DHB		 158 /*
159 * Note: setting it to false because there is not such capability
160 * in KVM at this moment.
161 *
162 * TODO: call kvm_vm_check_extension() with the right capability
163 * after the kernel starts implementing it.*/
164 cap_ppc_pvr_compat = false;
fc87e185
AG		 165
166 if (!cap_interrupt_level) {
167 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
168 "VM to stall at times!\n");
169 }
170
2e9c10eb 171 kvm_ppc_register_host_cpu_type(ms);
5ba4576b 172
d76d1650
AJ		 173 return 0;
174}
175
d525ffab
PB		 176int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
177{
178 return 0;
179}
180
1bc22652 181static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 182{
1bc22652
AF		 183 CPUPPCState *cenv = &cpu->env;
184 CPUState *cs = CPU(cpu);
861bbc80 185 struct kvm_sregs sregs;
5666ca4a
SW		 186 int ret;
187
188 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
64e07be5
AG		 189 /* What we're really trying to say is "if we're on BookE, we use
190 the native PVR for now". This is the only sane way to check
191 it though, so we potentially confuse users that they can run
192 BookE guests on BookS. Let's hope nobody dares enough :) */
5666ca4a
SW		 193 return 0;
194 } else {
90dc8812 195 if (!cap_segstate) {
64e07be5
AG		 196 fprintf(stderr, "kvm error: missing PVR setting capability\n");
197 return -ENOSYS;
5666ca4a 198 }
5666ca4a
SW		 199 }
200
1bc22652 201 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 202 if (ret) {
203 return ret;
204 }
861bbc80
AG		 205
206 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 207 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 208}
209
93dd5e85 210/* Set up a shared TLB array with KVM */
1bc22652 211static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 212{
1bc22652
AF		 213 CPUPPCState *env = &cpu->env;
214 CPUState *cs = CPU(cpu);
93dd5e85
SW		 215 struct kvm_book3e_206_tlb_params params = {};
216 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 217 unsigned int entries = 0;
218 int ret, i;
219
220 if (!kvm_enabled() ||
a60f24b5 221 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 222 return 0;
223 }
224
225 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
226
227 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
228 params.tlb_sizes[i] = booke206_tlb_size(env, i);
229 params.tlb_ways[i] = booke206_tlb_ways(env, i);
230 entries += params.tlb_sizes[i];
231 }
232
233 assert(entries == env->nb_tlb);
234 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
235
236 env->tlb_dirty = true;
237
238 cfg.array = (uintptr_t)env->tlb.tlbm;
239 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
240 cfg.params = (uintptr_t)&params;
241 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
242
48add816 243 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 244 if (ret < 0) {
245 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
246 __func__, strerror(-ret));
247 return ret;
248 }
249
250 env->kvm_sw_tlb = true;
251 return 0;
252}
253
4656e1f0
BH		 254
255#if defined(TARGET_PPC64)
ab256960 256static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 257{
71d0f1ea 258 int ret;
a60f24b5 259
ab256960
GK		 260 assert(kvm_state != NULL);
261
262 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 263 error_setg(errp, "KVM doesn't expose the MMU features it supports");
264 error_append_hint(errp, "Consider switching to a newer KVM\n");
265 return;
4656e1f0 266 }
4656e1f0 267
ab256960 268 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 269 if (ret == 0) {
270 return;
4656e1f0
BH		 271 }
272
71d0f1ea
GK		 273 error_setg_errno(errp, -ret,
274 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 275}
276
c64abd1f
SB		 277struct ppc_radix_page_info *kvm_get_radix_page_info(void)
278{
279 KVMState *s = KVM_STATE(current_machine->accelerator);
280 struct ppc_radix_page_info *radix_page_info;
281 struct kvm_ppc_rmmu_info rmmu_info;
282 int i;
283
284 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
285 return NULL;
286 }
287 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
288 return NULL;
289 }
290 radix_page_info = g_malloc0(sizeof(*radix_page_info));
291 radix_page_info->count = 0;
292 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
293 if (rmmu_info.ap_encodings[i]) {
294 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
295 radix_page_info->count++;
296 }
297 }
298 return radix_page_info;
299}
300
b4db5413
SJS		 301target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
302 bool radix, bool gtse,
303 uint64_t proc_tbl)
304{
305 CPUState *cs = CPU(cpu);
306 int ret;
307 uint64_t flags = 0;
308 struct kvm_ppc_mmuv3_cfg cfg = {
309 .process_table = proc_tbl,
310 };
311
312 if (radix) {
313 flags |= KVM_PPC_MMUV3_RADIX;
314 }
315 if (gtse) {
316 flags |= KVM_PPC_MMUV3_GTSE;
317 }
318 cfg.flags = flags;
319 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
320 switch (ret) {
321 case 0:
322 return H_SUCCESS;
323 case -EINVAL:
324 return H_PARAMETER;
325 case -ENODEV:
326 return H_NOT_AVAILABLE;
327 default:
328 return H_HARDWARE;
329 }
330}
331
24c6863c
DG		 332bool kvmppc_hpt_needs_host_contiguous_pages(void)
333{
24c6863c
DG		 334 static struct kvm_ppc_smmu_info smmu_info;
335
336 if (!kvm_enabled()) {
337 return false;
338 }
339
ab256960 340 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 341 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
342}
343
e5ca28ec 344void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 345{
e5ca28ec 346 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 347 int iq, ik, jq, jk;
71d0f1ea 348 Error *local_err = NULL;
4656e1f0 349
e5ca28ec
DG		 350 /* For now, we only have anything to check on hash64 MMUs */
351 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 352 return;
353 }
354
ab256960 355 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 356 if (local_err) {
357 error_propagate(errp, local_err);
358 return;
359 }
4656e1f0 360
e5ca28ec
DG		 361 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
362 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
363 error_setg(errp,
364 "KVM does not support 1TiB segments which guest expects");
365 return;
df587133 366 }
4656e1f0 367
e5ca28ec
DG		 368 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
369 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
370 smmu_info.slb_size, cpu->hash64_opts->slb_size);
371 return;
90da0d5a
BH		 372 }
373
08215d8f 374 /*
e5ca28ec
DG		 375 * Verify that every pagesize supported by the cpu model is
376 * supported by KVM with the same encodings
08215d8f 377 */
e5ca28ec 378 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 379 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 380 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 381
e5ca28ec
DG		 382 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
383 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 384 break;
385 }
386 }
e5ca28ec
DG		 387 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
388 error_setg(errp, "KVM doesn't support for base page shift %u",
389 qsps->page_shift);
390 return;
391 }
392
393 ksps = &smmu_info.sps[ik];
394 if (ksps->slb_enc != qsps->slb_enc) {
395 error_setg(errp,
396"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
397 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
398 return;
399 }
400
401 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
402 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
403 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
404 break;
405 }
406 }
407
408 if (jk >= ARRAY_SIZE(ksps->enc)) {
409 error_setg(errp, "KVM doesn't support page shift %u/%u",
410 qsps->enc[jq].page_shift, qsps->page_shift);
411 return;
412 }
413 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
414 error_setg(errp,
415"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
416 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
417 qsps->page_shift, qsps->enc[jq].pte_enc);
418 return;
419 }
4656e1f0
BH		 420 }
421 }
4656e1f0 422
e5ca28ec
DG		 423 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
424 /* Mostly what guest pagesizes we can use are related to the
425 * host pages used to map guest RAM, which is handled in the
426 * platform code. Cache-Inhibited largepages (64k) however are
427 * used for I/O, so if they're mapped to the host at all it
428 * will be a normal mapping, not a special hugepage one used
429 * for RAM. */
430 if (getpagesize() < 0x10000) {
431 error_setg(errp,
432 "KVM can't supply 64kiB CI pages, which guest expects");
433 }
434 }
4656e1f0 435}
4656e1f0
BH		 436#endif /* !defined (TARGET_PPC64) */
437
b164e48e
EH		 438unsigned long kvm_arch_vcpu_id(CPUState *cpu)
439{
2e886fb3 440 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 441}
442
88365d17
BB		 443/* e500 supports 2 h/w breakpoint and 2 watchpoint.
444 * book3s supports only 1 watchpoint, so array size
445 * of 4 is sufficient for now.
446 */
447#define MAX_HW_BKPTS 4
448
449static struct HWBreakpoint {
450 target_ulong addr;
451 int type;
452} hw_debug_points[MAX_HW_BKPTS];
453
454static CPUWatchpoint hw_watchpoint;
455
456/* Default there is no breakpoint and watchpoint supported */
457static int max_hw_breakpoint;
458static int max_hw_watchpoint;
459static int nb_hw_breakpoint;
460static int nb_hw_watchpoint;
461
462static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
463{
464 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
465 max_hw_breakpoint = 2;
466 max_hw_watchpoint = 2;
467 }
468
469 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
470 fprintf(stderr, "Error initializing h/w breakpoints\n");
471 return;
472 }
473}
474
20d695a9 475int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 476{
20d695a9
AF		 477 PowerPCCPU *cpu = POWERPC_CPU(cs);
478 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 479 int ret;
480
4656e1f0 481 /* Synchronize sregs with kvm */
1bc22652 482 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 483 if (ret) {
388e47c7
TH		 484 if (ret == -EINVAL) {
485 error_report("Register sync failed... If you're using kvm-hv.ko,"
486 " only \"-cpu host\" is possible");
487 }
5666ca4a
SW		 488 return ret;
489 }
861bbc80 490
bc72ad67 491 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu);
c821c2bd 492
93dd5e85
SW		 493 switch (cenv->mmu_model) {
494 case POWERPC_MMU_BOOKE206:
7f516c96 495 /* This target supports access to KVM's guest TLB */
1bc22652 496 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 497 break;
7f516c96
TH		 498 case POWERPC_MMU_2_07:
499 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
500 /* KVM-HV has transactional memory on POWER8 also without the
f3d9f303
SB		 501 * KVM_CAP_PPC_HTM extension, so enable it here instead as
502 * long as it's availble to userspace on the host. */
503 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
504 cap_htm = true;
505 }
7f516c96
TH		 506 }
507 break;
93dd5e85
SW		 508 default:
509 break;
510 }
511
3c902d44 512 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 513 kvmppc_hw_debug_points_init(cenv);
3c902d44 514
861bbc80 515 return ret;
d76d1650
AJ		 516}
517
1bc22652 518static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 519{
1bc22652
AF		 520 CPUPPCState *env = &cpu->env;
521 CPUState *cs = CPU(cpu);
93dd5e85
SW		 522 struct kvm_dirty_tlb dirty_tlb;
523 unsigned char *bitmap;
524 int ret;
525
526 if (!env->kvm_sw_tlb) {
527 return;
528 }
529
530 bitmap = g_malloc((env->nb_tlb + 7) / 8);
531 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
532
533 dirty_tlb.bitmap = (uintptr_t)bitmap;
534 dirty_tlb.num_dirty = env->nb_tlb;
535
1bc22652 536 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 537 if (ret) {
538 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
539 __func__, strerror(-ret));
540 }
541
542 g_free(bitmap);
543}
544
d67d40ea
DG		 545static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
546{
547 PowerPCCPU *cpu = POWERPC_CPU(cs);
548 CPUPPCState *env = &cpu->env;
549 union {
550 uint32_t u32;
551 uint64_t u64;
552 } val;
553 struct kvm_one_reg reg = {
554 .id = id,
555 .addr = (uintptr_t) &val,
556 };
557 int ret;
558
559 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
560 if (ret != 0) {
b36f100e 561 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 562 } else {
563 switch (id & KVM_REG_SIZE_MASK) {
564 case KVM_REG_SIZE_U32:
565 env->spr[spr] = val.u32;
566 break;
567
568 case KVM_REG_SIZE_U64:
569 env->spr[spr] = val.u64;
570 break;
571
572 default:
573 /* Don't handle this size yet */
574 abort();
575 }
576 }
577}
578
579static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
580{
581 PowerPCCPU *cpu = POWERPC_CPU(cs);
582 CPUPPCState *env = &cpu->env;
583 union {
584 uint32_t u32;
585 uint64_t u64;
586 } val;
587 struct kvm_one_reg reg = {
588 .id = id,
589 .addr = (uintptr_t) &val,
590 };
591 int ret;
592
593 switch (id & KVM_REG_SIZE_MASK) {
594 case KVM_REG_SIZE_U32:
595 val.u32 = env->spr[spr];
596 break;
597
598 case KVM_REG_SIZE_U64:
599 val.u64 = env->spr[spr];
600 break;
601
602 default:
603 /* Don't handle this size yet */
604 abort();
605 }
606
607 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
608 if (ret != 0) {
b36f100e 609 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 610 }
611}
612
70b79849
DG		 613static int kvm_put_fp(CPUState *cs)
614{
615 PowerPCCPU *cpu = POWERPC_CPU(cs);
616 CPUPPCState *env = &cpu->env;
617 struct kvm_one_reg reg;
618 int i;
619 int ret;
620
621 if (env->insns_flags & PPC_FLOAT) {
622 uint64_t fpscr = env->fpscr;
623 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
624
625 reg.id = KVM_REG_PPC_FPSCR;
626 reg.addr = (uintptr_t)&fpscr;
627 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
628 if (ret < 0) {
da56ff91 629 DPRINTF("Unable to set FPSCR to KVM: %s\n", strerror(errno));
70b79849
DG		 630 return ret;
631 }
632
633 for (i = 0; i < 32; i++) {
634 uint64_t vsr[2];
ef96e3ae
MCA		 635 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
636 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849 637
3a4b791b 638#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae
MCA		 639 vsr[0] = float64_val(*fpr);
640 vsr[1] = *vsrl;
3a4b791b 641#else
ef96e3ae
MCA		 642 vsr[0] = *vsrl;
643 vsr[1] = float64_val(*fpr);
3a4b791b 644#endif
70b79849
DG		 645 reg.addr = (uintptr_t) &vsr;
646 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
647
648 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
649 if (ret < 0) {
da56ff91 650 DPRINTF("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR",
70b79849
DG		 651 i, strerror(errno));
652 return ret;
653 }
654 }
655 }
656
657 if (env->insns_flags & PPC_ALTIVEC) {
658 reg.id = KVM_REG_PPC_VSCR;
659 reg.addr = (uintptr_t)&env->vscr;
660 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
661 if (ret < 0) {
da56ff91 662 DPRINTF("Unable to set VSCR to KVM: %s\n", strerror(errno));
70b79849
DG		 663 return ret;
664 }
665
666 for (i = 0; i < 32; i++) {
667 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 668 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 669 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
670 if (ret < 0) {
da56ff91 671 DPRINTF("Unable to set VR%d to KVM: %s\n", i, strerror(errno));
70b79849
DG		 672 return ret;
673 }
674 }
675 }
676
677 return 0;
678}
679
680static int kvm_get_fp(CPUState *cs)
681{
682 PowerPCCPU *cpu = POWERPC_CPU(cs);
683 CPUPPCState *env = &cpu->env;
684 struct kvm_one_reg reg;
685 int i;
686 int ret;
687
688 if (env->insns_flags & PPC_FLOAT) {
689 uint64_t fpscr;
690 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
691
692 reg.id = KVM_REG_PPC_FPSCR;
693 reg.addr = (uintptr_t)&fpscr;
694 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
695 if (ret < 0) {
da56ff91 696 DPRINTF("Unable to get FPSCR from KVM: %s\n", strerror(errno));
70b79849
DG		 697 return ret;
698 } else {
699 env->fpscr = fpscr;
700 }
701
702 for (i = 0; i < 32; i++) {
703 uint64_t vsr[2];
ef96e3ae
MCA		 704 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
705 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849
DG		 706
707 reg.addr = (uintptr_t) &vsr;
708 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
709
710 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
711 if (ret < 0) {
da56ff91 712 DPRINTF("Unable to get %s%d from KVM: %s\n",
70b79849
DG		 713 vsx ? "VSR" : "FPR", i, strerror(errno));
714 return ret;
715 } else {
3a4b791b 716#ifdef HOST_WORDS_BIGENDIAN
ef96e3ae 717 *fpr = vsr[0];
70b79849 718 if (vsx) {
ef96e3ae 719 *vsrl = vsr[1];
70b79849 720 }
3a4b791b 721#else
ef96e3ae 722 *fpr = vsr[1];
3a4b791b 723 if (vsx) {
ef96e3ae 724 *vsrl = vsr[0];
3a4b791b
GK		 725 }
726#endif
70b79849
DG		 727 }
728 }
729 }
730
731 if (env->insns_flags & PPC_ALTIVEC) {
732 reg.id = KVM_REG_PPC_VSCR;
733 reg.addr = (uintptr_t)&env->vscr;
734 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
735 if (ret < 0) {
da56ff91 736 DPRINTF("Unable to get VSCR from KVM: %s\n", strerror(errno));
70b79849
DG		 737 return ret;
738 }
739
740 for (i = 0; i < 32; i++) {
741 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 742 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 743 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
744 if (ret < 0) {
da56ff91 745 DPRINTF("Unable to get VR%d from KVM: %s\n",
70b79849
DG		 746 i, strerror(errno));
747 return ret;
748 }
749 }
750 }
751
752 return 0;
753}
754
9b00ea49
DG		 755#if defined(TARGET_PPC64)
756static int kvm_get_vpa(CPUState *cs)
757{
758 PowerPCCPU *cpu = POWERPC_CPU(cs);
7388efaf 759 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 760 struct kvm_one_reg reg;
761 int ret;
762
763 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 764 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 765 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
766 if (ret < 0) {
da56ff91 767 DPRINTF("Unable to get VPA address from KVM: %s\n", strerror(errno));
9b00ea49
DG		 768 return ret;
769 }
770
7388efaf
DG		 771 assert((uintptr_t)&spapr_cpu->slb_shadow_size
772 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 773 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 774 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 775 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
776 if (ret < 0) {
da56ff91 777 DPRINTF("Unable to get SLB shadow state from KVM: %s\n",
9b00ea49
DG		 778 strerror(errno));
779 return ret;
780 }
781
7388efaf
DG		 782 assert((uintptr_t)&spapr_cpu->dtl_size
783 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 784 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 785 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 786 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
787 if (ret < 0) {
da56ff91 788 DPRINTF("Unable to get dispatch trace log state from KVM: %s\n",
9b00ea49
DG		 789 strerror(errno));
790 return ret;
791 }
792
793 return 0;
794}
795
796static int kvm_put_vpa(CPUState *cs)
797{
798 PowerPCCPU *cpu = POWERPC_CPU(cs);
7388efaf 799 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 800 struct kvm_one_reg reg;
801 int ret;
802
803 /* SLB shadow or DTL can't be registered unless a master VPA is
804 * registered. That means when restoring state, if a VPA *is*
805 * registered, we need to set that up first. If not, we need to
806 * deregister the others before deregistering the master VPA */
7388efaf
DG		 807 assert(spapr_cpu->vpa_addr
808 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 809
7388efaf 810 if (spapr_cpu->vpa_addr) {
9b00ea49 811 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 812 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 813 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
814 if (ret < 0) {
da56ff91 815 DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
9b00ea49
DG		 816 return ret;
817 }
818 }
819
7388efaf
DG		 820 assert((uintptr_t)&spapr_cpu->slb_shadow_size
821 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 822 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 823 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 824 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
825 if (ret < 0) {
da56ff91 826 DPRINTF("Unable to set SLB shadow state to KVM: %s\n", strerror(errno));
9b00ea49
DG		 827 return ret;
828 }
829
7388efaf
DG		 830 assert((uintptr_t)&spapr_cpu->dtl_size
831 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 832 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 833 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 834 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
835 if (ret < 0) {
da56ff91 836 DPRINTF("Unable to set dispatch trace log state to KVM: %s\n",
9b00ea49
DG		 837 strerror(errno));
838 return ret;
839 }
840
7388efaf 841 if (!spapr_cpu->vpa_addr) {
9b00ea49 842 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 843 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 844 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
845 if (ret < 0) {
da56ff91 846 DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
9b00ea49
DG		 847 return ret;
848 }
849 }
850
851 return 0;
852}
853#endif /* TARGET_PPC64 */
854
e5c0d3ce 855int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 856{
857 CPUPPCState *env = &cpu->env;
858 struct kvm_sregs sregs;
859 int i;
860
861 sregs.pvr = env->spr[SPR_PVR];
862
1ec26c75
GK		 863 if (cpu->vhyp) {
864 PPCVirtualHypervisorClass *vhc =
865 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
866 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
867 } else {
868 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
869 }
a7a00a72
DG		 870
871 /* Sync SLB */
872#ifdef TARGET_PPC64
873 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
874 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
875 if (env->slb[i].esid & SLB_ESID_V) {
876 sregs.u.s.ppc64.slb[i].slbe |= i;
877 }
878 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
879 }
880#endif
881
882 /* Sync SRs */
883 for (i = 0; i < 16; i++) {
884 sregs.u.s.ppc32.sr[i] = env->sr[i];
885 }
886
887 /* Sync BATs */
888 for (i = 0; i < 8; i++) {
889 /* Beware. We have to swap upper and lower bits here */
890 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
891 | env->DBAT[1][i];
892 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
893 | env->IBAT[1][i];
894 }
895
896 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
897}
898
20d695a9 899int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 900{
20d695a9
AF		 901 PowerPCCPU *cpu = POWERPC_CPU(cs);
902 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 903 struct kvm_regs regs;
904 int ret;
905 int i;
906
1bc22652
AF		 907 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
908 if (ret < 0) {
d76d1650 909 return ret;
1bc22652 910 }
d76d1650
AJ		 911
912 regs.ctr = env->ctr;
913 regs.lr = env->lr;
da91a00f 914 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 915 regs.msr = env->msr;
916 regs.pc = env->nip;
917
918 regs.srr0 = env->spr[SPR_SRR0];
919 regs.srr1 = env->spr[SPR_SRR1];
920
921 regs.sprg0 = env->spr[SPR_SPRG0];
922 regs.sprg1 = env->spr[SPR_SPRG1];
923 regs.sprg2 = env->spr[SPR_SPRG2];
924 regs.sprg3 = env->spr[SPR_SPRG3];
925 regs.sprg4 = env->spr[SPR_SPRG4];
926 regs.sprg5 = env->spr[SPR_SPRG5];
927 regs.sprg6 = env->spr[SPR_SPRG6];
928 regs.sprg7 = env->spr[SPR_SPRG7];
929
90dc8812
SW		 930 regs.pid = env->spr[SPR_BOOKE_PID];
931
d76d1650
AJ		 932 for (i = 0;i < 32; i++)
933 regs.gpr[i] = env->gpr[i];
934
4bddaf55
AK		 935 regs.cr = 0;
936 for (i = 0; i < 8; i++) {
937 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
938 }
939
1bc22652 940 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
d76d1650
AJ		 941 if (ret < 0)
942 return ret;
943
70b79849
DG		 944 kvm_put_fp(cs);
945
93dd5e85 946 if (env->tlb_dirty) {
1bc22652 947 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 948 env->tlb_dirty = false;
949 }
950
f1af19d7 951 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 952 ret = kvmppc_put_books_sregs(cpu);
953 if (ret < 0) {
f1af19d7
DG		 954 return ret;
955 }
956 }
957
958 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 959 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
960 }
f1af19d7 961
d67d40ea
DG		 962 if (cap_one_reg) {
963 int i;
964
965 /* We deliberately ignore errors here, for kernels which have
966 * the ONE_REG calls, but don't support the specific
967 * registers, there's a reasonable chance things will still
968 * work, at least until we try to migrate. */
969 for (i = 0; i < 1024; i++) {
970 uint64_t id = env->spr_cb[i].one_reg_id;
971
972 if (id != 0) {
973 kvm_put_one_spr(cs, id, i);
974 }
f1af19d7 975 }
9b00ea49
DG		 976
977#ifdef TARGET_PPC64
80b3f79b
AK		 978 if (msr_ts) {
979 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
981 }
982 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
984 }
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
994 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
995 }
996
9b00ea49
DG		 997 if (cap_papr) {
998 if (kvm_put_vpa(cs) < 0) {
da56ff91 999 DPRINTF("Warning: Unable to set VPA information to KVM\n");
9b00ea49
DG		 1000 }
1001 }
98a8b524
AK		 1002
1003 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1004#endif /* TARGET_PPC64 */
f1af19d7
DG		 1005 }
1006
d76d1650
AJ		 1007 return ret;
1008}
1009
c371c2e3
BB		 1010static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1011{
1012 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1013}
1014
a7a00a72
DG		 1015static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1016{
1017 CPUPPCState *env = &cpu->env;
1018 struct kvm_sregs sregs;
1019 int ret;
1020
1021 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1022 if (ret < 0) {
1023 return ret;
1024 }
1025
1026 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1027 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1028 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1029 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1030 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1031 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1032 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1033 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1034 env->spr[SPR_DECR] = sregs.u.e.dec;
1035 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1036 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1037 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1038 }
1039
1040 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1041 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1042 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1043 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1044 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1045 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1046 }
1047
1048 if (sregs.u.e.features & KVM_SREGS_E_64) {
1049 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1050 }
1051
1052 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1053 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1054 }
1055
1056 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1057 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1058 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1059 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1060 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1061 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1062 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1063 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1064 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1065 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1066 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1067 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1068 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1069 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1070 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1071 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1072 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1073 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1074 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1075 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1076 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1077 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1078 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1079 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1080 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1081 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1082 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1083 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1084 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1085 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1086 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1087 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1088 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1089
1090 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1091 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1092 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1093 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1094 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1095 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1096 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1097 }
1098
1099 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1100 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1101 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1102 }
1103
1104 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1105 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1106 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1107 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1108 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1109 }
1110 }
1111
1112 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1113 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1114 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1115 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1116 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1117 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1118 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1119 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1120 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1121 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1122 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1123 }
1124
1125 if (sregs.u.e.features & KVM_SREGS_EXP) {
1126 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1127 }
1128
1129 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1130 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1131 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1132 }
1133
1134 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1135 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1136 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1137 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1138
1139 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1140 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1141 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1142 }
1143 }
1144
1145 return 0;
1146}
1147
1148static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1149{
1150 CPUPPCState *env = &cpu->env;
1151 struct kvm_sregs sregs;
1152 int ret;
1153 int i;
1154
1155 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1156 if (ret < 0) {
1157 return ret;
1158 }
1159
e57ca75c 1160 if (!cpu->vhyp) {
a7a00a72
DG		 1161 ppc_store_sdr1(env, sregs.u.s.sdr1);
1162 }
1163
1164 /* Sync SLB */
1165#ifdef TARGET_PPC64
1166 /*
1167 * The packed SLB array we get from KVM_GET_SREGS only contains
1168 * information about valid entries. So we flush our internal copy
1169 * to get rid of stale ones, then put all valid SLB entries back
1170 * in.
1171 */
1172 memset(env->slb, 0, sizeof(env->slb));
1173 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1174 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1175 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1176 /*
1177 * Only restore valid entries
1178 */
1179 if (rb & SLB_ESID_V) {
1180 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1181 }
1182 }
1183#endif
1184
1185 /* Sync SRs */
1186 for (i = 0; i < 16; i++) {
1187 env->sr[i] = sregs.u.s.ppc32.sr[i];
1188 }
1189
1190 /* Sync BATs */
1191 for (i = 0; i < 8; i++) {
1192 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1193 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1194 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1195 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1196 }
1197
1198 return 0;
1199}
1200
20d695a9 1201int kvm_arch_get_registers(CPUState *cs)
d76d1650 1202{
20d695a9
AF		 1203 PowerPCCPU *cpu = POWERPC_CPU(cs);
1204 CPUPPCState *env = &cpu->env;
d76d1650 1205 struct kvm_regs regs;
90dc8812 1206 uint32_t cr;
138b38b6 1207 int i, ret;
d76d1650 1208
1bc22652 1209 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
d76d1650
AJ		 1210 if (ret < 0)
1211 return ret;
1212
90dc8812
SW		 1213 cr = regs.cr;
1214 for (i = 7; i >= 0; i--) {
1215 env->crf[i] = cr & 15;
1216 cr >>= 4;
1217 }
ba5e5090 1218
d76d1650
AJ		 1219 env->ctr = regs.ctr;
1220 env->lr = regs.lr;
da91a00f 1221 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1222 env->msr = regs.msr;
1223 env->nip = regs.pc;
1224
1225 env->spr[SPR_SRR0] = regs.srr0;
1226 env->spr[SPR_SRR1] = regs.srr1;
1227
1228 env->spr[SPR_SPRG0] = regs.sprg0;
1229 env->spr[SPR_SPRG1] = regs.sprg1;
1230 env->spr[SPR_SPRG2] = regs.sprg2;
1231 env->spr[SPR_SPRG3] = regs.sprg3;
1232 env->spr[SPR_SPRG4] = regs.sprg4;
1233 env->spr[SPR_SPRG5] = regs.sprg5;
1234 env->spr[SPR_SPRG6] = regs.sprg6;
1235 env->spr[SPR_SPRG7] = regs.sprg7;
1236
90dc8812
SW		 1237 env->spr[SPR_BOOKE_PID] = regs.pid;
1238
d76d1650
AJ		 1239 for (i = 0;i < 32; i++)
1240 env->gpr[i] = regs.gpr[i];
1241
70b79849
DG		 1242 kvm_get_fp(cs);
1243
90dc8812 1244 if (cap_booke_sregs) {
a7a00a72 1245 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1246 if (ret < 0) {
1247 return ret;
1248 }
fafc0b6a 1249 }
90dc8812 1250
90dc8812 1251 if (cap_segstate) {
a7a00a72 1252 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1253 if (ret < 0) {
1254 return ret;
1255 }
fafc0b6a 1256 }
ba5e5090 1257
d67d40ea
DG		 1258 if (cap_hior) {
1259 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1260 }
1261
1262 if (cap_one_reg) {
1263 int i;
1264
1265 /* We deliberately ignore errors here, for kernels which have
1266 * the ONE_REG calls, but don't support the specific
1267 * registers, there's a reasonable chance things will still
1268 * work, at least until we try to migrate. */
1269 for (i = 0; i < 1024; i++) {
1270 uint64_t id = env->spr_cb[i].one_reg_id;
1271
1272 if (id != 0) {
1273 kvm_get_one_spr(cs, id, i);
1274 }
1275 }
9b00ea49
DG		 1276
1277#ifdef TARGET_PPC64
80b3f79b
AK		 1278 if (msr_ts) {
1279 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1280 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1281 }
1282 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1284 }
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1288 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1289 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1291 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1295 }
1296
9b00ea49
DG		 1297 if (cap_papr) {
1298 if (kvm_get_vpa(cs) < 0) {
da56ff91 1299 DPRINTF("Warning: Unable to get VPA information from KVM\n");
9b00ea49
DG		 1300 }
1301 }
98a8b524
AK		 1302
1303 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1304#endif
d67d40ea
DG		 1305 }
1306
d76d1650
AJ		 1307 return 0;
1308}
1309
1bc22652 1310int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1311{
1312 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1313
1314 if (irq != PPC_INTERRUPT_EXT) {
1315 return 0;
1316 }
1317
1318 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
1319 return 0;
1320 }
1321
1bc22652 1322 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1323
1324 return 0;
1325}
1326
a69dc537 1327#if defined(TARGET_PPC64)
16415335
AG		 1328#define PPC_INPUT_INT PPC970_INPUT_INT
1329#else
1330#define PPC_INPUT_INT PPC6xx_INPUT_INT
1331#endif
1332
20d695a9 1333void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1334{
20d695a9
AF		 1335 PowerPCCPU *cpu = POWERPC_CPU(cs);
1336 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 1337 int r;
1338 unsigned irq;
1339
4b8523ee
JK		 1340 qemu_mutex_lock_iothread();
1341
5cbdb3a3 1342 /* PowerPC QEMU tracks the various core input pins (interrupt, critical
d76d1650 1343 * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
fc87e185
AG		 1344 if (!cap_interrupt_level &&
1345 run->ready_for_interrupt_injection &&
259186a7 1346 (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
16415335 1347 (env->irq_input_state & (1<<PPC_INPUT_INT)))
d76d1650
AJ		 1348 {
1349 /* For now KVM disregards the 'irq' argument. However, in the
1350 * future KVM could cache it in-kernel to avoid a heavyweight exit
1351 * when reading the UIC.
1352 */
fc87e185 1353 irq = KVM_INTERRUPT_SET;
d76d1650 1354
da56ff91 1355 DPRINTF("injected interrupt %d\n", irq);
1bc22652 1356 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq);
55e5c285
AF		 1357 if (r < 0) {
1358 printf("cpu %d fail inject %x\n", cs->cpu_index, irq);
1359 }
c821c2bd
AG		 1360
1361 /* Always wake up soon in case the interrupt was level based */
bc72ad67 1362 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
73bcb24d 1363 (NANOSECONDS_PER_SECOND / 50));
d76d1650
AJ		 1364 }
1365
1366 /* We don't know if there are more interrupts pending after this. However,
1367 * the guest will return to userspace in the course of handling this one
1368 * anyways, so we will get a chance to deliver the rest. */
4b8523ee
JK		 1369
1370 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1371}
1372
4c663752 1373MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1374{
4c663752 1375 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1376}
1377
20d695a9 1378int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1379{
259186a7 1380 return cs->halted;
0af691d7
MT		 1381}
1382
259186a7 1383static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1384{
259186a7
AF		 1385 CPUState *cs = CPU(cpu);
1386 CPUPPCState *env = &cpu->env;
1387
1388 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1389 cs->halted = 1;
27103424 1390 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1391 }
1392
bb4ea393 1393 return 0;
d76d1650
AJ		 1394}
1395
1396/* map dcr access to existing qemu dcr emulation */
1328c2bf 1397static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data)
d76d1650
AJ		 1398{
1399 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
1400 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1401
bb4ea393 1402 return 0;
d76d1650
AJ		 1403}
1404
1328c2bf 1405static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data)
d76d1650
AJ		 1406{
1407 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
1408 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1409
bb4ea393 1410 return 0;
d76d1650
AJ		 1411}
1412
8a0548f9
BB		 1413int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1414{
1415 /* Mixed endian case is not handled */
1416 uint32_t sc = debug_inst_opcode;
1417
1418 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1419 sizeof(sc), 0) ||
1420 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1421 return -EINVAL;
1422 }
1423
1424 return 0;
1425}
1426
1427int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1428{
1429 uint32_t sc;
1430
1431 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1432 sc != debug_inst_opcode ||
1433 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1434 sizeof(sc), 1)) {
1435 return -EINVAL;
1436 }
1437
1438 return 0;
1439}
1440
88365d17
BB		 1441static int find_hw_breakpoint(target_ulong addr, int type)
1442{
1443 int n;
1444
1445 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1446 <= ARRAY_SIZE(hw_debug_points));
1447
1448 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1449 if (hw_debug_points[n].addr == addr &&
1450 hw_debug_points[n].type == type) {
1451 return n;
1452 }
1453 }
1454
1455 return -1;
1456}
1457
1458static int find_hw_watchpoint(target_ulong addr, int *flag)
1459{
1460 int n;
1461
1462 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1463 if (n >= 0) {
1464 *flag = BP_MEM_ACCESS;
1465 return n;
1466 }
1467
1468 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1469 if (n >= 0) {
1470 *flag = BP_MEM_WRITE;
1471 return n;
1472 }
1473
1474 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1475 if (n >= 0) {
1476 *flag = BP_MEM_READ;
1477 return n;
1478 }
1479
1480 return -1;
1481}
1482
1483int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1484 target_ulong len, int type)
1485{
1486 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1487 return -ENOBUFS;
1488 }
1489
1490 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1491 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1492
1493 switch (type) {
1494 case GDB_BREAKPOINT_HW:
1495 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1496 return -ENOBUFS;
1497 }
1498
1499 if (find_hw_breakpoint(addr, type) >= 0) {
1500 return -EEXIST;
1501 }
1502
1503 nb_hw_breakpoint++;
1504 break;
1505
1506 case GDB_WATCHPOINT_WRITE:
1507 case GDB_WATCHPOINT_READ:
1508 case GDB_WATCHPOINT_ACCESS:
1509 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1510 return -ENOBUFS;
1511 }
1512
1513 if (find_hw_breakpoint(addr, type) >= 0) {
1514 return -EEXIST;
1515 }
1516
1517 nb_hw_watchpoint++;
1518 break;
1519
1520 default:
1521 return -ENOSYS;
1522 }
1523
1524 return 0;
1525}
1526
1527int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1528 target_ulong len, int type)
1529{
1530 int n;
1531
1532 n = find_hw_breakpoint(addr, type);
1533 if (n < 0) {
1534 return -ENOENT;
1535 }
1536
1537 switch (type) {
1538 case GDB_BREAKPOINT_HW:
1539 nb_hw_breakpoint--;
1540 break;
1541
1542 case GDB_WATCHPOINT_WRITE:
1543 case GDB_WATCHPOINT_READ:
1544 case GDB_WATCHPOINT_ACCESS:
1545 nb_hw_watchpoint--;
1546 break;
1547
1548 default:
1549 return -ENOSYS;
1550 }
1551 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1552
1553 return 0;
1554}
1555
1556void kvm_arch_remove_all_hw_breakpoints(void)
1557{
1558 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1559}
1560
8a0548f9
BB		 1561void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1562{
88365d17
BB		 1563 int n;
1564
8a0548f9
BB		 1565 /* Software Breakpoint updates */
1566 if (kvm_sw_breakpoints_active(cs)) {
1567 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1568 }
88365d17
BB		 1569
1570 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1571 <= ARRAY_SIZE(hw_debug_points));
1572 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1573
1574 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1575 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1576 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1577 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1578 switch (hw_debug_points[n].type) {
1579 case GDB_BREAKPOINT_HW:
1580 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1581 break;
1582 case GDB_WATCHPOINT_WRITE:
1583 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1584 break;
1585 case GDB_WATCHPOINT_READ:
1586 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1587 break;
1588 case GDB_WATCHPOINT_ACCESS:
1589 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1590 KVMPPC_DEBUG_WATCH_READ;
1591 break;
1592 default:
1593 cpu_abort(cs, "Unsupported breakpoint type\n");
1594 }
1595 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1596 }
1597 }
8a0548f9
BB		 1598}
1599
1600static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1601{
1602 CPUState *cs = CPU(cpu);
1603 CPUPPCState *env = &cpu->env;
1604 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1605 int handle = 0;
88365d17
BB		 1606 int n;
1607 int flag = 0;
8a0548f9 1608
88365d17
BB		 1609 if (cs->singlestep_enabled) {
1610 handle = 1;
1611 } else if (arch_info->status) {
1612 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1613 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1614 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1615 if (n >= 0) {
1616 handle = 1;
1617 }
1618 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1619 KVMPPC_DEBUG_WATCH_WRITE)) {
1620 n = find_hw_watchpoint(arch_info->address, &flag);
1621 if (n >= 0) {
1622 handle = 1;
1623 cs->watchpoint_hit = &hw_watchpoint;
1624 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1625 hw_watchpoint.flags = flag;
1626 }
1627 }
1628 }
1629 } else if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
8a0548f9
BB		 1630 handle = 1;
1631 } else {
1632 /* QEMU is not able to handle debug exception, so inject
1633 * program exception to guest;
1634 * Yes program exception NOT debug exception !!
88365d17
BB		 1635 * When QEMU is using debug resources then debug exception must
1636 * be always set. To achieve this we set MSR_DE and also set
1637 * MSRP_DEP so guest cannot change MSR_DE.
1638 * When emulating debug resource for guest we want guest
1639 * to control MSR_DE (enable/disable debug interrupt on need).
1640 * Supporting both configurations are NOT possible.
1641 * So the result is that we cannot share debug resources
1642 * between QEMU and Guest on BOOKE architecture.
1643 * In the current design QEMU gets the priority over guest,
1644 * this means that if QEMU is using debug resources then guest
1645 * cannot use them;
8a0548f9
BB		 1646 * For software breakpoint QEMU uses a privileged instruction;
1647 * So there cannot be any reason that we are here for guest
1648 * set debug exception, only possibility is guest executed a
1649 * privileged / illegal instruction and that's why we are
1650 * injecting a program interrupt.
1651 */
1652
1653 cpu_synchronize_state(cs);
1654 /* env->nip is PC, so increment this by 4 to use
1655 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1656 */
1657 env->nip += 4;
1658 cs->exception_index = POWERPC_EXCP_PROGRAM;
1659 env->error_code = POWERPC_EXCP_INVAL;
1660 ppc_cpu_do_interrupt(cs);
1661 }
1662
1663 return handle;
1664}
1665
20d695a9 1666int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1667{
20d695a9
AF		 1668 PowerPCCPU *cpu = POWERPC_CPU(cs);
1669 CPUPPCState *env = &cpu->env;
bb4ea393 1670 int ret;
d76d1650 1671
4b8523ee
JK		 1672 qemu_mutex_lock_iothread();
1673
d76d1650
AJ		 1674 switch (run->exit_reason) {
1675 case KVM_EXIT_DCR:
1676 if (run->dcr.is_write) {
da56ff91 1677 DPRINTF("handle dcr write\n");
d76d1650
AJ		 1678 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1679 } else {
da56ff91 1680 DPRINTF("handle dcr read\n");
d76d1650
AJ		 1681 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1682 }
1683 break;
1684 case KVM_EXIT_HLT:
da56ff91 1685 DPRINTF("handle halt\n");
259186a7 1686 ret = kvmppc_handle_halt(cpu);
d76d1650 1687 break;
c6304a4a 1688#if defined(TARGET_PPC64)
f61b4bed 1689 case KVM_EXIT_PAPR_HCALL:
da56ff91 1690 DPRINTF("handle PAPR hypercall\n");
20d695a9 1691 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1692 run->papr_hcall.nr,
f61b4bed 1693 run->papr_hcall.args);
78e8fde2 1694 ret = 0;
f61b4bed
AG		 1695 break;
1696#endif
5b95b8b9 1697 case KVM_EXIT_EPR:
da56ff91 1698 DPRINTF("handle epr\n");
933b19ea 1699 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1700 ret = 0;
1701 break;
31f2cb8f 1702 case KVM_EXIT_WATCHDOG:
da56ff91 1703 DPRINTF("handle watchdog expiry\n");
31f2cb8f
BB		 1704 watchdog_perform_action();
1705 ret = 0;
1706 break;
1707
8a0548f9
BB		 1708 case KVM_EXIT_DEBUG:
1709 DPRINTF("handle debug exception\n");
1710 if (kvm_handle_debug(cpu, run)) {
1711 ret = EXCP_DEBUG;
1712 break;
1713 }
1714 /* re-enter, this exception was guest-internal */
1715 ret = 0;
1716 break;
1717
73aaec4a
JK		 1718 default:
1719 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1720 ret = -1;
1721 break;
d76d1650
AJ		 1722 }
1723
4b8523ee 1724 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1725 return ret;
1726}
1727
31f2cb8f
BB		 1728int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1729{
1730 CPUState *cs = CPU(cpu);
1731 uint32_t bits = tsr_bits;
1732 struct kvm_one_reg reg = {
1733 .id = KVM_REG_PPC_OR_TSR,
1734 .addr = (uintptr_t) &bits,
1735 };
1736
1737 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1738}
1739
1740int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1741{
1742
1743 CPUState *cs = CPU(cpu);
1744 uint32_t bits = tsr_bits;
1745 struct kvm_one_reg reg = {
1746 .id = KVM_REG_PPC_CLEAR_TSR,
1747 .addr = (uintptr_t) &bits,
1748 };
1749
1750 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1751}
1752
1753int kvmppc_set_tcr(PowerPCCPU *cpu)
1754{
1755 CPUState *cs = CPU(cpu);
1756 CPUPPCState *env = &cpu->env;
1757 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1758
1759 struct kvm_one_reg reg = {
1760 .id = KVM_REG_PPC_TCR,
1761 .addr = (uintptr_t) &tcr,
1762 };
1763
1764 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1765}
1766
1767int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1768{
1769 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1770 int ret;
1771
1772 if (!kvm_enabled()) {
1773 return -1;
1774 }
1775
1776 if (!cap_ppc_watchdog) {
1777 printf("warning: KVM does not support watchdog");
1778 return -1;
1779 }
1780
48add816 1781 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1782 if (ret < 0) {
1783 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1784 __func__, strerror(-ret));
1785 return ret;
1786 }
1787
1788 return ret;
1789}
1790
dc333cd6
AG		 1791static int read_cpuinfo(const char *field, char *value, int len)
1792{
1793 FILE *f;
1794 int ret = -1;
1795 int field_len = strlen(field);
1796 char line[512];
1797
1798 f = fopen("/proc/cpuinfo", "r");
1799 if (!f) {
1800 return -1;
1801 }
1802
1803 do {
ef951443 1804 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1805 break;
1806 }
1807 if (!strncmp(line, field, field_len)) {
ae215068 1808 pstrcpy(value, len, line);
dc333cd6
AG		 1809 ret = 0;
1810 break;
1811 }
1812 } while(*line);
1813
1814 fclose(f);
1815
1816 return ret;
1817}
1818
1819uint32_t kvmppc_get_tbfreq(void)
1820{
1821 char line[512];
1822 char *ns;
73bcb24d 1823 uint32_t retval = NANOSECONDS_PER_SECOND;
dc333cd6
AG		 1824
1825 if (read_cpuinfo("timebase", line, sizeof(line))) {
1826 return retval;
1827 }
1828
1829 if (!(ns = strchr(line, ':'))) {
1830 return retval;
1831 }
1832
1833 ns++;
1834
f9b8e7f6 1835 return atoi(ns);
dc333cd6 1836}
4513d923 1837
ef951443
ND		 1838bool kvmppc_get_host_serial(char **value)
1839{
1840 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1841 NULL);
1842}
1843
1844bool kvmppc_get_host_model(char **value)
1845{
1846 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1847}
1848
eadaada1
AG		 1849/* Try to find a device tree node for a CPU with clock-frequency property */
1850static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1851{
1852 struct dirent *dirp;
1853 DIR *dp;
1854
1855 if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) {
1856 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1857 return -1;
1858 }
1859
1860 buf[0] = '\0';
1861 while ((dirp = readdir(dp)) != NULL) {
1862 FILE *f;
1863 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1864 dirp->d_name);
1865 f = fopen(buf, "r");
1866 if (f) {
1867 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1868 fclose(f);
1869 break;
1870 }
1871 buf[0] = '\0';
1872 }
1873 closedir(dp);
1874 if (buf[0] == '\0') {
1875 printf("Unknown host!\n");
1876 return -1;
1877 }
1878
1879 return 0;
1880}
1881
7d94a30b 1882static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1883{
9bc884b7
DG		 1884 union {
1885 uint32_t v32;
1886 uint64_t v64;
1887 } u;
eadaada1
AG		 1888 FILE *f;
1889 int len;
1890
7d94a30b 1891 f = fopen(filename, "rb");
eadaada1
AG		 1892 if (!f) {
1893 return -1;
1894 }
1895
9bc884b7 1896 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1897 fclose(f);
1898 switch (len) {
9bc884b7
DG		 1899 case 4:
1900 /* property is a 32-bit quantity */
1901 return be32_to_cpu(u.v32);
1902 case 8:
1903 return be64_to_cpu(u.v64);
eadaada1
AG		 1904 }
1905
1906 return 0;
1907}
1908
7d94a30b
SB		 1909/* Read a CPU node property from the host device tree that's a single
1910 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1911 * (can't find or open the property, or doesn't understand the
1912 * format) */
1913static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1914{
1915 char buf[PATH_MAX], *tmp;
1916 uint64_t val;
1917
1918 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1919 return -1;
1920 }
1921
1922 tmp = g_strdup_printf("%s/%s", buf, propname);
1923 val = kvmppc_read_int_dt(tmp);
1924 g_free(tmp);
1925
1926 return val;
1927}
1928
9bc884b7
DG		 1929uint64_t kvmppc_get_clockfreq(void)
1930{
1931 return kvmppc_read_int_cpu_dt("clock-frequency");
1932}
1933
7d050527
SJS		 1934static int kvmppc_get_dec_bits(void)
1935{
1936 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1937
1938 if (nr_bits > 0) {
1939 return nr_bits;
1940 }
1941 return 0;
1942}
1943
1a61a9ae
SY		 1944static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
1945 {
1946 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1947 CPUState *cs = CPU(cpu);
1948
6fd33a75 1949 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1950 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1951 return 0;
1952 }
1953
1954 return 1;
1955}
1956
1957int kvmppc_get_hasidle(CPUPPCState *env)
1958{
1959 struct kvm_ppc_pvinfo pvinfo;
1960
1961 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1962 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1963 return 1;
1964 }
1965
1966 return 0;
1967}
1968
1328c2bf 1969int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09
AG		 1970{
1971 uint32_t *hc = (uint32_t*)buf;
45024f09
AG		 1972 struct kvm_ppc_pvinfo pvinfo;
1973
1a61a9ae 1974 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 1975 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 1976 return 0;
1977 }
45024f09
AG		 1978
1979 /*
d13fc32e 1980 * Fallback to always fail hypercalls regardless of endianness:
45024f09 1981 *
d13fc32e 1982 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 1983 * li r3, -1
d13fc32e
AG		 1984 * b .+8 (becomes nop in wrong endian)
1985 * bswap32(li r3, -1)
45024f09
AG		 1986 */
1987
d13fc32e
AG		 1988 hc[0] = cpu_to_be32(0x08000048);
1989 hc[1] = cpu_to_be32(0x3860ffff);
1990 hc[2] = cpu_to_be32(0x48000008);
1991 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 1992
0ddbd053 1993 return 1;
45024f09
AG		 1994}
1995
026bfd89
DG		 1996static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
1997{
1998 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
1999}
2000
2001void kvmppc_enable_logical_ci_hcalls(void)
2002{
2003 /*
2004 * FIXME: it would be nice if we could detect the cases where
2005 * we're using a device which requires the in kernel
2006 * implementation of these hcalls, but the kernel lacks them and
2007 * produce a warning.
2008 */
2009 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2010 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2011}
2012
ef9971dd
AK		 2013void kvmppc_enable_set_mode_hcall(void)
2014{
2015 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2016}
2017
5145ad4f
NW		 2018void kvmppc_enable_clear_ref_mod_hcalls(void)
2019{
2020 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2021 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2022}
2023
1bc22652 2024void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2025{
1bc22652 2026 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2027 int ret;
2028
da20aed1
DG		 2029 if (!kvm_enabled()) {
2030 return;
2031 }
2032
48add816 2033 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2034 if (ret) {
072ed5f2
TH		 2035 error_report("This vCPU type or KVM version does not support PAPR");
2036 exit(1);
94135e81 2037 }
9b00ea49
DG		 2038
2039 /* Update the capability flag so we sync the right information
2040 * with kvm */
2041 cap_papr = 1;
f61b4bed
AG		 2042}
2043
d6e166c0 2044int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2045{
d6e166c0 2046 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2047}
2048
5b95b8b9
AG		 2049void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2050{
5b95b8b9 2051 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2052 int ret;
2053
48add816 2054 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2055 if (ret && mpic_proxy) {
072ed5f2
TH		 2056 error_report("This KVM version does not support EPR");
2057 exit(1);
5b95b8b9
AG		 2058 }
2059}
2060
e97c3636
DG		 2061int kvmppc_smt_threads(void)
2062{
2063 return cap_ppc_smt ? cap_ppc_smt : 1;
2064}
2065
fa98fbfc
SB		 2066int kvmppc_set_smt_threads(int smt)
2067{
2068 int ret;
2069
2070 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2071 if (!ret) {
2072 cap_ppc_smt = smt;
2073 }
2074 return ret;
2075}
2076
2077void kvmppc_hint_smt_possible(Error **errp)
2078{
2079 int i;
2080 GString *g;
2081 char *s;
2082
2083 assert(kvm_enabled());
2084 if (cap_ppc_smt_possible) {
2085 g = g_string_new("Available VSMT modes:");
2086 for (i = 63; i >= 0; i--) {
2087 if ((1UL << i) & cap_ppc_smt_possible) {
2088 g_string_append_printf(g, " %lu", (1UL << i));
2089 }
2090 }
2091 s = g_string_free(g, false);
2092 error_append_hint(errp, "%s.\n", s);
2093 g_free(s);
2094 } else {
2095 error_append_hint(errp,
2096 "This KVM seems to be too old to support VSMT.\n");
2097 }
2098}
2099
2100
7f763a5d 2101#ifdef TARGET_PPC64
7f763a5d
DG		 2102uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2103{
f36951c1
DG		 2104 struct kvm_ppc_smmu_info info;
2105 long rampagesize, best_page_shift;
2106 int i;
2107
f36951c1
DG		 2108 /* Find the largest hardware supported page size that's less than
2109 * or equal to the (logical) backing page size of guest RAM */
ab256960 2110 kvm_get_smmu_info(&info, &error_fatal);
9c607668 2111 rampagesize = qemu_getrampagesize();
f36951c1
DG		 2112 best_page_shift = 0;
2113
2114 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2115 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2116
2117 if (!sps->page_shift) {
2118 continue;
2119 }
2120
2121 if ((sps->page_shift > best_page_shift)
2122 && ((1UL << sps->page_shift) <= rampagesize)) {
2123 best_page_shift = sps->page_shift;
2124 }
2125 }
2126
7f763a5d 2127 return MIN(current_size,
f36951c1 2128 1ULL << (best_page_shift + hash_shift - 7));
7f763a5d
DG		 2129}
2130#endif
2131
da95324e
AK		 2132bool kvmppc_spapr_use_multitce(void)
2133{
2134 return cap_spapr_multitce;
2135}
2136
3dc410ae
AK		 2137int kvmppc_spapr_enable_inkernel_multitce(void)
2138{
2139 int ret;
2140
2141 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2142 H_PUT_TCE_INDIRECT, 1);
2143 if (!ret) {
2144 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2145 H_STUFF_TCE, 1);
2146 }
2147
2148 return ret;
2149}
2150
d6ee2a7c
AK		 2151void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2152 uint64_t bus_offset, uint32_t nb_table,
2153 int *pfd, bool need_vfio)
0f5cb298 2154{
0f5cb298
DG		 2155 long len;
2156 int fd;
2157 void *table;
2158
b5aec396
DG		 2159 /* Must set fd to -1 so we don't try to munmap when called for
2160 * destroying the table, which the upper layers -will- do
2161 */
2162 *pfd = -1;
6a81dd17 2163 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2164 return NULL;
2165 }
2166
d6ee2a7c
AK		 2167 if (cap_spapr_tce_64) {
2168 struct kvm_create_spapr_tce_64 args = {
2169 .liobn = liobn,
2170 .page_shift = page_shift,
2171 .offset = bus_offset >> page_shift,
2172 .size = nb_table,
2173 .flags = 0
2174 };
2175 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2176 if (fd < 0) {
2177 fprintf(stderr,
2178 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2179 liobn);
2180 return NULL;
2181 }
2182 } else if (cap_spapr_tce) {
2183 uint64_t window_size = (uint64_t) nb_table << page_shift;
2184 struct kvm_create_spapr_tce args = {
2185 .liobn = liobn,
2186 .window_size = window_size,
2187 };
2188 if ((window_size != args.window_size) || bus_offset) {
2189 return NULL;
2190 }
2191 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2192 if (fd < 0) {
2193 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2194 liobn);
2195 return NULL;
2196 }
2197 } else {
0f5cb298
DG		 2198 return NULL;
2199 }
2200
d6ee2a7c 2201 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2202 /* FIXME: round this up to page size */
2203
74b41e56 2204 table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2205 if (table == MAP_FAILED) {
b5aec396
DG		 2206 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2207 liobn);
0f5cb298
DG		 2208 close(fd);
2209 return NULL;
2210 }
2211
2212 *pfd = fd;
2213 return table;
2214}
2215
523e7b8a 2216int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2217{
2218 long len;
2219
2220 if (fd < 0) {
2221 return -1;
2222 }
2223
523e7b8a 2224 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2225 if ((munmap(table, len) < 0) ||
2226 (close(fd) < 0)) {
b5aec396
DG		 2227 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2228 strerror(errno));
0f5cb298
DG		 2229 /* Leak the table */
2230 }
2231
2232 return 0;
2233}
2234
7f763a5d
DG		 2235int kvmppc_reset_htab(int shift_hint)
2236{
2237 uint32_t shift = shift_hint;
2238
ace9a2cb
DG		 2239 if (!kvm_enabled()) {
2240 /* Full emulation, tell caller to allocate htab itself */
2241 return 0;
2242 }
6977afda 2243 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2244 int ret;
2245 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb
DG		 2246 if (ret == -ENOTTY) {
2247 /* At least some versions of PR KVM advertise the
2248 * capability, but don't implement the ioctl(). Oops.
2249 * Return 0 so that we allocate the htab in qemu, as is
2250 * correct for PR. */
2251 return 0;
2252 } else if (ret < 0) {
7f763a5d
DG		 2253 return ret;
2254 }
2255 return shift;
2256 }
2257
ace9a2cb
DG		 2258 /* We have a kernel that predates the htab reset calls. For PR
2259 * KVM, we need to allocate the htab ourselves, for an HV KVM of
96c9cff0
TH		 2260 * this era, it has allocated a 16MB fixed size hash table already. */
2261 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2262 /* PR - tell caller to allocate htab */
2263 return 0;
2264 } else {
2265 /* HV - assume 16MB kernel allocated htab */
2266 return 24;
2267 }
7f763a5d
DG		 2268}
2269
a1e98583
DG		 2270static inline uint32_t mfpvr(void)
2271{
2272 uint32_t pvr;
2273
2274 asm ("mfpvr %0"
2275 : "=r"(pvr));
2276 return pvr;
2277}
2278
a7342588
DG		 2279static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2280{
2281 if (on) {
2282 *word |= flags;
2283 } else {
2284 *word &= ~flags;
2285 }
2286}
2287
2985b86b
AF		 2288static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2289{
2290 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2291 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2292 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2293
cfe34f44 2294 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2295 pcc->pvr = mfpvr();
a7342588 2296
3f2ca480
DG		 2297 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2298 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2299 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2300 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2301 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2302 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2303
2304 if (dcache_size != -1) {
2305 pcc->l1_dcache_size = dcache_size;
2306 }
2307
2308 if (icache_size != -1) {
2309 pcc->l1_icache_size = icache_size;
2310 }
c64abd1f
SB		 2311
2312#if defined(TARGET_PPC64)
2313 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2314
2315 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2316 /*
2317 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2318 * compliant. More importantly, advertising ISA 3.00
2319 * architected mode may prevent guests from activating
2320 * necessary DD1 workarounds.
2321 */
2322 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2323 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2324 }
c64abd1f 2325#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2326}
2327
3b961124
SY		 2328bool kvmppc_has_cap_epr(void)
2329{
2330 return cap_epr;
2331}
2332
87a91de6
AG		 2333bool kvmppc_has_cap_fixup_hcalls(void)
2334{
2335 return cap_fixup_hcalls;
2336}
2337
bac3bf28
TH		 2338bool kvmppc_has_cap_htm(void)
2339{
2340 return cap_htm;
2341}
2342
cf1c4cce
SB		 2343bool kvmppc_has_cap_mmu_radix(void)
2344{
2345 return cap_mmu_radix;
2346}
2347
2348bool kvmppc_has_cap_mmu_hash_v3(void)
2349{
2350 return cap_mmu_hash_v3;
2351}
2352
072f416a
SJS		 2353static bool kvmppc_power8_host(void)
2354{
2355 bool ret = false;
2356#ifdef TARGET_PPC64
2357 {
2358 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2359 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2360 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2361 (base_pvr == CPU_POWERPC_POWER8_BASE);
2362 }
2363#endif /* TARGET_PPC64 */
2364 return ret;
2365}
2366
8fea7044
SJS		 2367static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2368{
072f416a
SJS		 2369 bool l1d_thread_priv_req = !kvmppc_power8_host();
2370
8fea7044
SJS		 2371 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2372 return 2;
072f416a
SJS		 2373 } else if ((!l1d_thread_priv_req ||
2374 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2375 (c.character & c.character_mask
2376 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2377 return 1;
2378 }
2379
2380 return 0;
2381}
2382
2383static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2384{
2385 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2386 return 2;
2387 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2388 return 1;
2389 }
2390
2391 return 0;
2392}
2393
2394static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2395{
399b2896
SJS		 2396 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2397 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2398 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2399 return SPAPR_CAP_FIXED_NA;
2400 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2401 return SPAPR_CAP_WORKAROUND;
2402 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
8fea7044
SJS		 2403 return SPAPR_CAP_FIXED_CCD;
2404 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2405 return SPAPR_CAP_FIXED_IBS;
2406 }
2407
2408 return 0;
2409}
2410
8ff43ee4
SJS		 2411static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2412{
2413 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2414 return 1;
2415 }
2416 return 0;
2417}
2418
8acc2ae5
SJS		 2419static void kvmppc_get_cpu_characteristics(KVMState *s)
2420{
2421 struct kvm_ppc_cpu_char c;
2422 int ret;
2423
2424 /* Assume broken */
2425 cap_ppc_safe_cache = 0;
2426 cap_ppc_safe_bounds_check = 0;
2427 cap_ppc_safe_indirect_branch = 0;
2428
2429 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2430 if (!ret) {
2431 return;
2432 }
2433 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2434 if (ret < 0) {
2435 return;
2436 }
8fea7044
SJS		 2437
2438 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2439 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2440 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8ff43ee4
SJS		 2441 cap_ppc_count_cache_flush_assist =
2442 parse_cap_ppc_count_cache_flush_assist(c);
8acc2ae5
SJS		 2443}
2444
2445int kvmppc_get_cap_safe_cache(void)
2446{
2447 return cap_ppc_safe_cache;
2448}
2449
2450int kvmppc_get_cap_safe_bounds_check(void)
2451{
2452 return cap_ppc_safe_bounds_check;
2453}
2454
2455int kvmppc_get_cap_safe_indirect_branch(void)
2456{
2457 return cap_ppc_safe_indirect_branch;
2458}
2459
8ff43ee4
SJS		 2460int kvmppc_get_cap_count_cache_flush_assist(void)
2461{
2462 return cap_ppc_count_cache_flush_assist;
2463}
2464
b9a477b7
SJS		 2465bool kvmppc_has_cap_nested_kvm_hv(void)
2466{
2467 return !!cap_ppc_nested_kvm_hv;
2468}
2469
2470int kvmppc_set_cap_nested_kvm_hv(int enable)
2471{
2472 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2473}
2474
9ded780c
AK		 2475bool kvmppc_has_cap_spapr_vfio(void)
2476{
2477 return cap_spapr_vfio;
2478}
2479
7d050527
SJS		 2480int kvmppc_get_cap_large_decr(void)
2481{
2482 return cap_large_decr;
2483}
2484
2485int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2486{
2487 CPUState *cs = CPU(cpu);
2488 uint64_t lpcr;
2489
2490 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2491 /* Do we need to modify the LPCR? */
2492 if (!!(lpcr & LPCR_LD) != !!enable) {
2493 if (enable) {
2494 lpcr |= LPCR_LD;
2495 } else {
2496 lpcr &= ~LPCR_LD;
2497 }
2498 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2499 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2500
2501 if (!!(lpcr & LPCR_LD) != !!enable) {
2502 return -1;
2503 }
2504 }
2505
2506 return 0;
2507}
2508
52b2519c
TH		 2509PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2510{
2511 uint32_t host_pvr = mfpvr();
2512 PowerPCCPUClass *pvr_pcc;
2513
2514 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2515 if (pvr_pcc == NULL) {
2516 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2517 }
2518
2519 return pvr_pcc;
2520}
2521
2e9c10eb 2522static int kvm_ppc_register_host_cpu_type(MachineState *ms)
5ba4576b
AF		 2523{
2524 TypeInfo type_info = {
2525 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2526 .class_init = kvmppc_host_cpu_class_init,
2527 };
2e9c10eb 2528 MachineClass *mc = MACHINE_GET_CLASS(ms);
5ba4576b 2529 PowerPCCPUClass *pvr_pcc;
92e926e1 2530 ObjectClass *oc;
5b79b1ca 2531 DeviceClass *dc;
715d4b96 2532 int i;
5ba4576b 2533
52b2519c 2534 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2535 if (pvr_pcc == NULL) {
2536 return -1;
2537 }
2538 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2539 type_register(&type_info);
2e9c10eb
IM		 2540 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) {
2541 /* override TCG default cpu type with 'host' cpu model */
2542 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2543 }
5b79b1ca 2544
92e926e1
GK		 2545 oc = object_class_by_name(type_info.name);
2546 g_assert(oc);
2547
715d4b96
TH		 2548 /*
2549 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2550 * we want "POWER8" to be a "family" alias that points to the current
2551 * host CPU type, too)
2552 */
2553 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2554 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2555 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2556 char *suffix;
2557
2558 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2559 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2560 if (suffix) {
2561 *suffix = 0;
2562 }
715d4b96
TH		 2563 break;
2564 }
2565 }
2566
5ba4576b
AF		 2567 return 0;
2568}
2569
feaa64c4
DG		 2570int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2571{
2572 struct kvm_rtas_token_args args = {
2573 .token = token,
2574 };
2575
2576 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2577 return -ENOENT;
2578 }
2579
2580 strncpy(args.name, function, sizeof(args.name));
2581
2582 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2583}
12b1143b 2584
14b0d748 2585int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2586{
2587 struct kvm_get_htab_fd s = {
2588 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2589 .start_index = index,
e68cb8b4 2590 };
82be8e73 2591 int ret;
e68cb8b4
AK		 2592
2593 if (!cap_htab_fd) {
14b0d748
GK		 2594 error_setg(errp, "KVM version doesn't support %s the HPT",
2595 write ? "writing" : "reading");
82be8e73
GK		 2596 return -ENOTSUP;
2597 }
2598
2599 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2600 if (ret < 0) {
14b0d748
GK		 2601 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2602 write ? "writing" : "reading", write ? "to" : "from",
2603 strerror(errno));
82be8e73 2604 return -errno;
e68cb8b4
AK		 2605 }
2606
82be8e73 2607 return ret;
e68cb8b4
AK		 2608}
2609
2610int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2611{
bc72ad67 2612 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2613 uint8_t buf[bufsize];
2614 ssize_t rc;
2615
2616 do {
2617 rc = read(fd, buf, bufsize);
2618 if (rc < 0) {
2619 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2620 strerror(errno));
2621 return rc;
2622 } else if (rc) {
e094c4c1
CLG		 2623 uint8_t *buffer = buf;
2624 ssize_t n = rc;
2625 while (n) {
2626 struct kvm_get_htab_header *head =
2627 (struct kvm_get_htab_header *) buffer;
2628 size_t chunksize = sizeof(*head) +
2629 HASH_PTE_SIZE_64 * head->n_valid;
2630
2631 qemu_put_be32(f, head->index);
2632 qemu_put_be16(f, head->n_valid);
2633 qemu_put_be16(f, head->n_invalid);
2634 qemu_put_buffer(f, (void *)(head + 1),
2635 HASH_PTE_SIZE_64 * head->n_valid);
2636
2637 buffer += chunksize;
2638 n -= chunksize;
2639 }
e68cb8b4
AK		 2640 }
2641 } while ((rc != 0)
2642 && ((max_ns < 0)
bc72ad67 2643 || ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2644
2645 return (rc == 0) ? 1 : 0;
2646}
2647
2648int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2649 uint16_t n_valid, uint16_t n_invalid)
2650{
2651 struct kvm_get_htab_header *buf;
2652 size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64;
2653 ssize_t rc;
2654
2655 buf = alloca(chunksize);
e68cb8b4
AK		 2656 buf->index = index;
2657 buf->n_valid = n_valid;
2658 buf->n_invalid = n_invalid;
2659
2660 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid);
2661
2662 rc = write(fd, buf, chunksize);
2663 if (rc < 0) {
2664 fprintf(stderr, "Error writing KVM hash table: %s\n",
2665 strerror(errno));
2666 return rc;
2667 }
2668 if (rc != chunksize) {
2669 /* We should never get a short write on a single chunk */
2670 fprintf(stderr, "Short write, restoring KVM hash table\n");
2671 return -1;
2672 }
2673 return 0;
2674}
2675
20d695a9 2676bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2677{
2678 return true;
2679}
a1b87fe0 2680
82169660
SW		 2681void kvm_arch_init_irq_routing(KVMState *s)
2682{
2683}
c65f9a07 2684
1ad9f0a4 2685void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2686{
1ad9f0a4
DG		 2687 int fd, rc;
2688 int i;
7c43bca0 2689
14b0d748 2690 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2691
1ad9f0a4
DG		 2692 i = 0;
2693 while (i < n) {
2694 struct kvm_get_htab_header *hdr;
2695 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2696 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2697
1ad9f0a4
DG		 2698 rc = read(fd, buf, sizeof(buf));
2699 if (rc < 0) {
2700 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2701 }
7c43bca0 2702
1ad9f0a4
DG		 2703 hdr = (struct kvm_get_htab_header *)buf;
2704 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2705 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2706
1ad9f0a4
DG		 2707 if (hdr->index != (ptex + i)) {
2708 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2709 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2710 }
2711
a36593e1
AK		 2712 if (n - i < valid) {
2713 valid = n - i;
2714 }
2715 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2716 i += valid;
7c43bca0 2717
1ad9f0a4
DG		 2718 if ((n - i) < invalid) {
2719 invalid = n - i;
2720 }
2721 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2722 i += invalid;
1ad9f0a4
DG		 2723
2724 hdr = (struct kvm_get_htab_header *)
2725 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2726 }
2727 }
2728
2729 close(fd);
7c43bca0 2730}
c1385933 2731
1ad9f0a4 2732void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2733{
1ad9f0a4 2734 int fd, rc;
1ad9f0a4
DG		 2735 struct {
2736 struct kvm_get_htab_header hdr;
2737 uint64_t pte0;
2738 uint64_t pte1;
2739 } buf;
c1385933 2740
14b0d748 2741 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2742
1ad9f0a4
DG		 2743 buf.hdr.n_valid = 1;
2744 buf.hdr.n_invalid = 0;
2745 buf.hdr.index = ptex;
2746 buf.pte0 = cpu_to_be64(pte0);
2747 buf.pte1 = cpu_to_be64(pte1);
c1385933 2748
1ad9f0a4
DG		 2749 rc = write(fd, &buf, sizeof(buf));
2750 if (rc != sizeof(buf)) {
2751 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2752 }
2753 close(fd);
c1385933 2754}
9e03a040
FB		 2755
2756int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2757 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2758{
2759 return 0;
2760}
1850b6b7 2761
38d87493
PX		 2762int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2763 int vector, PCIDevice *dev)
2764{
2765 return 0;
2766}
2767
2768int kvm_arch_release_virq_post(int virq)
2769{
2770 return 0;
2771}
2772
1850b6b7
EA		 2773int kvm_arch_msi_data_to_gsi(uint32_t data)
2774{
2775 return data & 0xffff;
2776}
4d9392be
TH		 2777
2778int kvmppc_enable_hwrng(void)
2779{
2780 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2781 return -1;
2782 }
2783
2784 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2785}
30f4b05b
DG		 2786
2787void kvmppc_check_papr_resize_hpt(Error **errp)
2788{
2789 if (!kvm_enabled()) {
b55d295e
DG		 2790 return; /* No KVM, we're good */
2791 }
2792
2793 if (cap_resize_hpt) {
2794 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2795 }
2796
b55d295e
DG		 2797 /* Otherwise fallback on looking for PR KVM */
2798 if (kvmppc_is_pr(kvm_state)) {
2799 return;
2800 }
30f4b05b
DG		 2801
2802 error_setg(errp,
2803 "Hash page table resizing not available with this KVM version");
2804}
b55d295e
DG		 2805
2806int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2807{
2808 CPUState *cs = CPU(cpu);
2809 struct kvm_ppc_resize_hpt rhpt = {
2810 .flags = flags,
2811 .shift = shift,
2812 };
2813
2814 if (!cap_resize_hpt) {
2815 return -ENOSYS;
2816 }
2817
2818 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2819}
2820
2821int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2822{
2823 CPUState *cs = CPU(cpu);
2824 struct kvm_ppc_resize_hpt rhpt = {
2825 .flags = flags,
2826 .shift = shift,
2827 };
2828
2829 if (!cap_resize_hpt) {
2830 return -ENOSYS;
2831 }
2832
2833 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2834}
2835
c363a37a
DHB		 2836/*
2837 * This is a helper function to detect a post migration scenario
2838 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2839 * the guest kernel can't handle a PVR value other than the actual host
2840 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2841 *
2842 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2843 * (so, we're HV), return true. The workaround itself is done in
2844 * cpu_post_load.
2845 *
2846 * The order here is important: we'll only check for KVM PR as a
2847 * fallback if the guest kernel can't handle the situation itself.
2848 * We need to avoid as much as possible querying the running KVM type
2849 * in QEMU level.
2850 */
2851bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2852{
2853 CPUState *cs = CPU(cpu);
2854
2855 if (!kvm_enabled()) {
2856 return false;
2857 }
2858
2859 if (cap_ppc_pvr_compat) {
2860 return false;
2861 }
2862
2863 return !kvmppc_is_pr(cs->kvm_state);
2864}
a84f7179
ND		 2865
2866void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2867{
2868 CPUState *cs = CPU(cpu);
2869
2870 if (kvm_enabled()) {
2871 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2872 }
2873}
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