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target/ppc: Add one reg id for ptcr
[mirror_qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
24#include "qemu-common.h"
30f4b05b 25#include "qapi/error.h"
072ed5f2 26#include "qemu/error-report.h"
33c11879 27#include "cpu.h"
715d4b96 28#include "cpu-models.h"
1de7afc9 29#include "qemu/timer.h"
9c17d615 30#include "sysemu/sysemu.h"
b3946626 31#include "sysemu/hw_accel.h"
d76d1650 32#include "kvm_ppc.h"
9c17d615
PB		 33#include "sysemu/cpus.h"
34#include "sysemu/device_tree.h"
d5aea6f3 35#include "mmu-hash64.h"
d76d1650 36
f61b4bed 37#include "hw/sysbus.h"
0d09e41a
PB		 38#include "hw/ppc/spapr.h"
39#include "hw/ppc/spapr_vio.h"
7ebaf795 40#include "hw/ppc/spapr_cpu_core.h"
98a8b524 41#include "hw/ppc/ppc.h"
31f2cb8f 42#include "sysemu/watchdog.h"
b36f100e 43#include "trace.h"
88365d17 44#include "exec/gdbstub.h"
4c663752 45#include "exec/memattrs.h"
9c607668 46#include "exec/ram_addr.h"
2d103aae 47#include "sysemu/hostmem.h"
f348b6d1 48#include "qemu/cutils.h"
9c607668 49#include "qemu/mmap-alloc.h"
f3d9f303 50#include "elf.h"
c64abd1f 51#include "sysemu/kvm_int.h"
f61b4bed 52
d76d1650
AJ		 53//#define DEBUG_KVM
54
55#ifdef DEBUG_KVM
da56ff91 56#define DPRINTF(fmt, ...) \
d76d1650
AJ		 57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
58#else
da56ff91 59#define DPRINTF(fmt, ...) \
d76d1650
AJ		 60 do { } while (0)
61#endif
62
eadaada1
AG		 63#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
64
94a8d39a
JK		 65const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
66 KVM_CAP_LAST_INFO
67};
68
fc87e185
AG		 69static int cap_interrupt_unset = false;
70static int cap_interrupt_level = false;
90dc8812 71static int cap_segstate;
90dc8812 72static int cap_booke_sregs;
e97c3636 73static int cap_ppc_smt;
fa98fbfc 74static int cap_ppc_smt_possible;
0f5cb298 75static int cap_spapr_tce;
d6ee2a7c 76static int cap_spapr_tce_64;
da95324e 77static int cap_spapr_multitce;
9bb62a07 78static int cap_spapr_vfio;
f1af19d7 79static int cap_hior;
d67d40ea 80static int cap_one_reg;
3b961124 81static int cap_epr;
31f2cb8f 82static int cap_ppc_watchdog;
9b00ea49 83static int cap_papr;
e68cb8b4 84static int cap_htab_fd;
87a91de6 85static int cap_fixup_hcalls;
bac3bf28 86static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 87static int cap_mmu_radix;
88static int cap_mmu_hash_v3;
b55d295e 89static int cap_resize_hpt;
c363a37a 90static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 91static int cap_ppc_safe_cache;
92static int cap_ppc_safe_bounds_check;
93static int cap_ppc_safe_indirect_branch;
fc87e185 94
3c902d44
BB		 95static uint32_t debug_inst_opcode;
96
c821c2bd
AG		 97/* XXX We have a race condition where we actually have a level triggered
98 * interrupt, but the infrastructure can't expose that yet, so the guest
99 * takes but ignores it, goes to sleep and never gets notified that there's
100 * still an interrupt pending.
c6a94ba5 101 *
c821c2bd
AG		 102 * As a quick workaround, let's just wake up again 20 ms after we injected
103 * an interrupt. That way we can assure that we're always reinjecting
104 * interrupts in case the guest swallowed them.
c6a94ba5
AG		 105 */
106static QEMUTimer *idle_timer;
107
d5a68146 108static void kvm_kick_cpu(void *opaque)
c6a94ba5 109{
d5a68146 110 PowerPCCPU *cpu = opaque;
d5a68146 111
c08d7424 112 qemu_cpu_kick(CPU(cpu));
c6a94ba5
AG		 113}
114
96c9cff0
TH		 115/* Check whether we are running with KVM-PR (instead of KVM-HV). This
116 * should only be used for fallback tests - generally we should use
117 * explicit capabilities for the features we want, rather than
118 * assuming what is/isn't available depending on the KVM variant. */
119static bool kvmppc_is_pr(KVMState *ks)
120{
121 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 122 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 123}
124
2e9c10eb 125static int kvm_ppc_register_host_cpu_type(MachineState *ms);
8acc2ae5 126static void kvmppc_get_cpu_characteristics(KVMState *s);
5ba4576b 127
b16565b3 128int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 129{
fc87e185 130 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
fc87e185 131 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
90dc8812 132 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 133 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 134 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 135 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 136 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 137 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 138 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 139 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 140 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 141 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 142 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
9b00ea49
DG		 143 /* Note: we don't set cap_papr here, because this capability is
144 * only activated after this by kvmppc_set_papr() */
6977afda 145 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 146 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 147 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 148 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 149 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
150 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
b55d295e 151 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 152 kvmppc_get_cpu_characteristics(s);
c363a37a
DHB		 153 /*
154 * Note: setting it to false because there is not such capability
155 * in KVM at this moment.
156 *
157 * TODO: call kvm_vm_check_extension() with the right capability
158 * after the kernel starts implementing it.*/
159 cap_ppc_pvr_compat = false;
fc87e185
AG		 160
161 if (!cap_interrupt_level) {
162 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
163 "VM to stall at times!\n");
164 }
165
2e9c10eb 166 kvm_ppc_register_host_cpu_type(ms);
5ba4576b 167
d76d1650
AJ		 168 return 0;
169}
170
d525ffab
PB		 171int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
172{
173 return 0;
174}
175
1bc22652 176static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 177{
1bc22652
AF		 178 CPUPPCState *cenv = &cpu->env;
179 CPUState *cs = CPU(cpu);
861bbc80 180 struct kvm_sregs sregs;
5666ca4a
SW		 181 int ret;
182
183 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
64e07be5
AG		 184 /* What we're really trying to say is "if we're on BookE, we use
185 the native PVR for now". This is the only sane way to check
186 it though, so we potentially confuse users that they can run
187 BookE guests on BookS. Let's hope nobody dares enough :) */
5666ca4a
SW		 188 return 0;
189 } else {
90dc8812 190 if (!cap_segstate) {
64e07be5
AG		 191 fprintf(stderr, "kvm error: missing PVR setting capability\n");
192 return -ENOSYS;
5666ca4a 193 }
5666ca4a
SW		 194 }
195
1bc22652 196 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 197 if (ret) {
198 return ret;
199 }
861bbc80
AG		 200
201 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 202 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 203}
204
93dd5e85 205/* Set up a shared TLB array with KVM */
1bc22652 206static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 207{
1bc22652
AF		 208 CPUPPCState *env = &cpu->env;
209 CPUState *cs = CPU(cpu);
93dd5e85
SW		 210 struct kvm_book3e_206_tlb_params params = {};
211 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 212 unsigned int entries = 0;
213 int ret, i;
214
215 if (!kvm_enabled() ||
a60f24b5 216 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 217 return 0;
218 }
219
220 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
221
222 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
223 params.tlb_sizes[i] = booke206_tlb_size(env, i);
224 params.tlb_ways[i] = booke206_tlb_ways(env, i);
225 entries += params.tlb_sizes[i];
226 }
227
228 assert(entries == env->nb_tlb);
229 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
230
231 env->tlb_dirty = true;
232
233 cfg.array = (uintptr_t)env->tlb.tlbm;
234 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
235 cfg.params = (uintptr_t)&params;
236 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
237
48add816 238 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 239 if (ret < 0) {
240 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
241 __func__, strerror(-ret));
242 return ret;
243 }
244
245 env->kvm_sw_tlb = true;
246 return 0;
247}
248
4656e1f0
BH		 249
250#if defined(TARGET_PPC64)
ab256960 251static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 252{
71d0f1ea 253 int ret;
a60f24b5 254
ab256960
GK		 255 assert(kvm_state != NULL);
256
257 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 258 error_setg(errp, "KVM doesn't expose the MMU features it supports");
259 error_append_hint(errp, "Consider switching to a newer KVM\n");
260 return;
4656e1f0 261 }
4656e1f0 262
ab256960 263 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 264 if (ret == 0) {
265 return;
4656e1f0
BH		 266 }
267
71d0f1ea
GK		 268 error_setg_errno(errp, -ret,
269 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 270}
271
c64abd1f
SB		 272struct ppc_radix_page_info *kvm_get_radix_page_info(void)
273{
274 KVMState *s = KVM_STATE(current_machine->accelerator);
275 struct ppc_radix_page_info *radix_page_info;
276 struct kvm_ppc_rmmu_info rmmu_info;
277 int i;
278
279 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
280 return NULL;
281 }
282 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
283 return NULL;
284 }
285 radix_page_info = g_malloc0(sizeof(*radix_page_info));
286 radix_page_info->count = 0;
287 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
288 if (rmmu_info.ap_encodings[i]) {
289 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
290 radix_page_info->count++;
291 }
292 }
293 return radix_page_info;
294}
295
b4db5413
SJS		 296target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
297 bool radix, bool gtse,
298 uint64_t proc_tbl)
299{
300 CPUState *cs = CPU(cpu);
301 int ret;
302 uint64_t flags = 0;
303 struct kvm_ppc_mmuv3_cfg cfg = {
304 .process_table = proc_tbl,
305 };
306
307 if (radix) {
308 flags |= KVM_PPC_MMUV3_RADIX;
309 }
310 if (gtse) {
311 flags |= KVM_PPC_MMUV3_GTSE;
312 }
313 cfg.flags = flags;
314 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
315 switch (ret) {
316 case 0:
317 return H_SUCCESS;
318 case -EINVAL:
319 return H_PARAMETER;
320 case -ENODEV:
321 return H_NOT_AVAILABLE;
322 default:
323 return H_HARDWARE;
324 }
325}
326
24c6863c
DG		 327bool kvmppc_hpt_needs_host_contiguous_pages(void)
328{
24c6863c
DG		 329 static struct kvm_ppc_smmu_info smmu_info;
330
331 if (!kvm_enabled()) {
332 return false;
333 }
334
ab256960 335 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 336 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
337}
338
e5ca28ec 339void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 340{
e5ca28ec 341 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 342 int iq, ik, jq, jk;
71d0f1ea 343 Error *local_err = NULL;
4656e1f0 344
e5ca28ec
DG		 345 /* For now, we only have anything to check on hash64 MMUs */
346 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 347 return;
348 }
349
ab256960 350 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 351 if (local_err) {
352 error_propagate(errp, local_err);
353 return;
354 }
4656e1f0 355
e5ca28ec
DG		 356 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
357 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
358 error_setg(errp,
359 "KVM does not support 1TiB segments which guest expects");
360 return;
df587133 361 }
4656e1f0 362
e5ca28ec
DG		 363 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
364 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
365 smmu_info.slb_size, cpu->hash64_opts->slb_size);
366 return;
90da0d5a
BH		 367 }
368
08215d8f 369 /*
e5ca28ec
DG		 370 * Verify that every pagesize supported by the cpu model is
371 * supported by KVM with the same encodings
08215d8f 372 */
e5ca28ec 373 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 374 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 375 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 376
e5ca28ec
DG		 377 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
378 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 379 break;
380 }
381 }
e5ca28ec
DG		 382 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
383 error_setg(errp, "KVM doesn't support for base page shift %u",
384 qsps->page_shift);
385 return;
386 }
387
388 ksps = &smmu_info.sps[ik];
389 if (ksps->slb_enc != qsps->slb_enc) {
390 error_setg(errp,
391"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
392 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
393 return;
394 }
395
396 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
397 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
398 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
399 break;
400 }
401 }
402
403 if (jk >= ARRAY_SIZE(ksps->enc)) {
404 error_setg(errp, "KVM doesn't support page shift %u/%u",
405 qsps->enc[jq].page_shift, qsps->page_shift);
406 return;
407 }
408 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
409 error_setg(errp,
410"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
411 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
412 qsps->page_shift, qsps->enc[jq].pte_enc);
413 return;
414 }
4656e1f0
BH		 415 }
416 }
4656e1f0 417
e5ca28ec
DG		 418 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
419 /* Mostly what guest pagesizes we can use are related to the
420 * host pages used to map guest RAM, which is handled in the
421 * platform code. Cache-Inhibited largepages (64k) however are
422 * used for I/O, so if they're mapped to the host at all it
423 * will be a normal mapping, not a special hugepage one used
424 * for RAM. */
425 if (getpagesize() < 0x10000) {
426 error_setg(errp,
427 "KVM can't supply 64kiB CI pages, which guest expects");
428 }
429 }
4656e1f0 430}
4656e1f0
BH		 431#endif /* !defined (TARGET_PPC64) */
432
b164e48e
EH		 433unsigned long kvm_arch_vcpu_id(CPUState *cpu)
434{
2e886fb3 435 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 436}
437
88365d17
BB		 438/* e500 supports 2 h/w breakpoint and 2 watchpoint.
439 * book3s supports only 1 watchpoint, so array size
440 * of 4 is sufficient for now.
441 */
442#define MAX_HW_BKPTS 4
443
444static struct HWBreakpoint {
445 target_ulong addr;
446 int type;
447} hw_debug_points[MAX_HW_BKPTS];
448
449static CPUWatchpoint hw_watchpoint;
450
451/* Default there is no breakpoint and watchpoint supported */
452static int max_hw_breakpoint;
453static int max_hw_watchpoint;
454static int nb_hw_breakpoint;
455static int nb_hw_watchpoint;
456
457static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
458{
459 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
460 max_hw_breakpoint = 2;
461 max_hw_watchpoint = 2;
462 }
463
464 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
465 fprintf(stderr, "Error initializing h/w breakpoints\n");
466 return;
467 }
468}
469
20d695a9 470int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 471{
20d695a9
AF		 472 PowerPCCPU *cpu = POWERPC_CPU(cs);
473 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 474 int ret;
475
4656e1f0 476 /* Synchronize sregs with kvm */
1bc22652 477 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 478 if (ret) {
388e47c7
TH		 479 if (ret == -EINVAL) {
480 error_report("Register sync failed... If you're using kvm-hv.ko,"
481 " only \"-cpu host\" is possible");
482 }
5666ca4a
SW		 483 return ret;
484 }
861bbc80 485
bc72ad67 486 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu);
c821c2bd 487
93dd5e85
SW		 488 switch (cenv->mmu_model) {
489 case POWERPC_MMU_BOOKE206:
7f516c96 490 /* This target supports access to KVM's guest TLB */
1bc22652 491 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 492 break;
7f516c96
TH		 493 case POWERPC_MMU_2_07:
494 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
495 /* KVM-HV has transactional memory on POWER8 also without the
f3d9f303
SB		 496 * KVM_CAP_PPC_HTM extension, so enable it here instead as
497 * long as it's availble to userspace on the host. */
498 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
499 cap_htm = true;
500 }
7f516c96
TH		 501 }
502 break;
93dd5e85
SW		 503 default:
504 break;
505 }
506
3c902d44 507 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 508 kvmppc_hw_debug_points_init(cenv);
3c902d44 509
861bbc80 510 return ret;
d76d1650
AJ		 511}
512
1bc22652 513static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 514{
1bc22652
AF		 515 CPUPPCState *env = &cpu->env;
516 CPUState *cs = CPU(cpu);
93dd5e85
SW		 517 struct kvm_dirty_tlb dirty_tlb;
518 unsigned char *bitmap;
519 int ret;
520
521 if (!env->kvm_sw_tlb) {
522 return;
523 }
524
525 bitmap = g_malloc((env->nb_tlb + 7) / 8);
526 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
527
528 dirty_tlb.bitmap = (uintptr_t)bitmap;
529 dirty_tlb.num_dirty = env->nb_tlb;
530
1bc22652 531 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 532 if (ret) {
533 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
534 __func__, strerror(-ret));
535 }
536
537 g_free(bitmap);
538}
539
d67d40ea
DG		 540static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
541{
542 PowerPCCPU *cpu = POWERPC_CPU(cs);
543 CPUPPCState *env = &cpu->env;
544 union {
545 uint32_t u32;
546 uint64_t u64;
547 } val;
548 struct kvm_one_reg reg = {
549 .id = id,
550 .addr = (uintptr_t) &val,
551 };
552 int ret;
553
554 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
555 if (ret != 0) {
b36f100e 556 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 557 } else {
558 switch (id & KVM_REG_SIZE_MASK) {
559 case KVM_REG_SIZE_U32:
560 env->spr[spr] = val.u32;
561 break;
562
563 case KVM_REG_SIZE_U64:
564 env->spr[spr] = val.u64;
565 break;
566
567 default:
568 /* Don't handle this size yet */
569 abort();
570 }
571 }
572}
573
574static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
575{
576 PowerPCCPU *cpu = POWERPC_CPU(cs);
577 CPUPPCState *env = &cpu->env;
578 union {
579 uint32_t u32;
580 uint64_t u64;
581 } val;
582 struct kvm_one_reg reg = {
583 .id = id,
584 .addr = (uintptr_t) &val,
585 };
586 int ret;
587
588 switch (id & KVM_REG_SIZE_MASK) {
589 case KVM_REG_SIZE_U32:
590 val.u32 = env->spr[spr];
591 break;
592
593 case KVM_REG_SIZE_U64:
594 val.u64 = env->spr[spr];
595 break;
596
597 default:
598 /* Don't handle this size yet */
599 abort();
600 }
601
602 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
603 if (ret != 0) {
b36f100e 604 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 605 }
606}
607
70b79849
DG		 608static int kvm_put_fp(CPUState *cs)
609{
610 PowerPCCPU *cpu = POWERPC_CPU(cs);
611 CPUPPCState *env = &cpu->env;
612 struct kvm_one_reg reg;
613 int i;
614 int ret;
615
616 if (env->insns_flags & PPC_FLOAT) {
617 uint64_t fpscr = env->fpscr;
618 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
619
620 reg.id = KVM_REG_PPC_FPSCR;
621 reg.addr = (uintptr_t)&fpscr;
622 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
623 if (ret < 0) {
da56ff91 624 DPRINTF("Unable to set FPSCR to KVM: %s\n", strerror(errno));
70b79849
DG		 625 return ret;
626 }
627
628 for (i = 0; i < 32; i++) {
629 uint64_t vsr[2];
630
3a4b791b 631#ifdef HOST_WORDS_BIGENDIAN
70b79849
DG		 632 vsr[0] = float64_val(env->fpr[i]);
633 vsr[1] = env->vsr[i];
3a4b791b
GK		 634#else
635 vsr[0] = env->vsr[i];
636 vsr[1] = float64_val(env->fpr[i]);
637#endif
70b79849
DG		 638 reg.addr = (uintptr_t) &vsr;
639 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
640
641 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
642 if (ret < 0) {
da56ff91 643 DPRINTF("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR",
70b79849
DG		 644 i, strerror(errno));
645 return ret;
646 }
647 }
648 }
649
650 if (env->insns_flags & PPC_ALTIVEC) {
651 reg.id = KVM_REG_PPC_VSCR;
652 reg.addr = (uintptr_t)&env->vscr;
653 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
654 if (ret < 0) {
da56ff91 655 DPRINTF("Unable to set VSCR to KVM: %s\n", strerror(errno));
70b79849
DG		 656 return ret;
657 }
658
659 for (i = 0; i < 32; i++) {
660 reg.id = KVM_REG_PPC_VR(i);
661 reg.addr = (uintptr_t)&env->avr[i];
662 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
663 if (ret < 0) {
da56ff91 664 DPRINTF("Unable to set VR%d to KVM: %s\n", i, strerror(errno));
70b79849
DG		 665 return ret;
666 }
667 }
668 }
669
670 return 0;
671}
672
673static int kvm_get_fp(CPUState *cs)
674{
675 PowerPCCPU *cpu = POWERPC_CPU(cs);
676 CPUPPCState *env = &cpu->env;
677 struct kvm_one_reg reg;
678 int i;
679 int ret;
680
681 if (env->insns_flags & PPC_FLOAT) {
682 uint64_t fpscr;
683 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
684
685 reg.id = KVM_REG_PPC_FPSCR;
686 reg.addr = (uintptr_t)&fpscr;
687 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
688 if (ret < 0) {
da56ff91 689 DPRINTF("Unable to get FPSCR from KVM: %s\n", strerror(errno));
70b79849
DG		 690 return ret;
691 } else {
692 env->fpscr = fpscr;
693 }
694
695 for (i = 0; i < 32; i++) {
696 uint64_t vsr[2];
697
698 reg.addr = (uintptr_t) &vsr;
699 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
700
701 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
702 if (ret < 0) {
da56ff91 703 DPRINTF("Unable to get %s%d from KVM: %s\n",
70b79849
DG		 704 vsx ? "VSR" : "FPR", i, strerror(errno));
705 return ret;
706 } else {
3a4b791b 707#ifdef HOST_WORDS_BIGENDIAN
70b79849
DG		 708 env->fpr[i] = vsr[0];
709 if (vsx) {
710 env->vsr[i] = vsr[1];
711 }
3a4b791b
GK		 712#else
713 env->fpr[i] = vsr[1];
714 if (vsx) {
715 env->vsr[i] = vsr[0];
716 }
717#endif
70b79849
DG		 718 }
719 }
720 }
721
722 if (env->insns_flags & PPC_ALTIVEC) {
723 reg.id = KVM_REG_PPC_VSCR;
724 reg.addr = (uintptr_t)&env->vscr;
725 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
726 if (ret < 0) {
da56ff91 727 DPRINTF("Unable to get VSCR from KVM: %s\n", strerror(errno));
70b79849
DG		 728 return ret;
729 }
730
731 for (i = 0; i < 32; i++) {
732 reg.id = KVM_REG_PPC_VR(i);
733 reg.addr = (uintptr_t)&env->avr[i];
734 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
735 if (ret < 0) {
da56ff91 736 DPRINTF("Unable to get VR%d from KVM: %s\n",
70b79849
DG		 737 i, strerror(errno));
738 return ret;
739 }
740 }
741 }
742
743 return 0;
744}
745
9b00ea49
DG		 746#if defined(TARGET_PPC64)
747static int kvm_get_vpa(CPUState *cs)
748{
749 PowerPCCPU *cpu = POWERPC_CPU(cs);
7388efaf 750 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 751 struct kvm_one_reg reg;
752 int ret;
753
754 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 755 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 756 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
757 if (ret < 0) {
da56ff91 758 DPRINTF("Unable to get VPA address from KVM: %s\n", strerror(errno));
9b00ea49
DG		 759 return ret;
760 }
761
7388efaf
DG		 762 assert((uintptr_t)&spapr_cpu->slb_shadow_size
763 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 764 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 765 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 766 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
767 if (ret < 0) {
da56ff91 768 DPRINTF("Unable to get SLB shadow state from KVM: %s\n",
9b00ea49
DG		 769 strerror(errno));
770 return ret;
771 }
772
7388efaf
DG		 773 assert((uintptr_t)&spapr_cpu->dtl_size
774 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 775 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 776 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 777 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
778 if (ret < 0) {
da56ff91 779 DPRINTF("Unable to get dispatch trace log state from KVM: %s\n",
9b00ea49
DG		 780 strerror(errno));
781 return ret;
782 }
783
784 return 0;
785}
786
787static int kvm_put_vpa(CPUState *cs)
788{
789 PowerPCCPU *cpu = POWERPC_CPU(cs);
7388efaf 790 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 791 struct kvm_one_reg reg;
792 int ret;
793
794 /* SLB shadow or DTL can't be registered unless a master VPA is
795 * registered. That means when restoring state, if a VPA *is*
796 * registered, we need to set that up first. If not, we need to
797 * deregister the others before deregistering the master VPA */
7388efaf
DG		 798 assert(spapr_cpu->vpa_addr
799 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 800
7388efaf 801 if (spapr_cpu->vpa_addr) {
9b00ea49 802 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 803 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 804 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
805 if (ret < 0) {
da56ff91 806 DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
9b00ea49
DG		 807 return ret;
808 }
809 }
810
7388efaf
DG		 811 assert((uintptr_t)&spapr_cpu->slb_shadow_size
812 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 813 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 814 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 815 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
816 if (ret < 0) {
da56ff91 817 DPRINTF("Unable to set SLB shadow state to KVM: %s\n", strerror(errno));
9b00ea49
DG		 818 return ret;
819 }
820
7388efaf
DG		 821 assert((uintptr_t)&spapr_cpu->dtl_size
822 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 823 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 824 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 825 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
826 if (ret < 0) {
da56ff91 827 DPRINTF("Unable to set dispatch trace log state to KVM: %s\n",
9b00ea49
DG		 828 strerror(errno));
829 return ret;
830 }
831
7388efaf 832 if (!spapr_cpu->vpa_addr) {
9b00ea49 833 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 834 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 835 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
836 if (ret < 0) {
da56ff91 837 DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
9b00ea49
DG		 838 return ret;
839 }
840 }
841
842 return 0;
843}
844#endif /* TARGET_PPC64 */
845
e5c0d3ce 846int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 847{
848 CPUPPCState *env = &cpu->env;
849 struct kvm_sregs sregs;
850 int i;
851
852 sregs.pvr = env->spr[SPR_PVR];
853
1ec26c75
GK		 854 if (cpu->vhyp) {
855 PPCVirtualHypervisorClass *vhc =
856 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
857 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
858 } else {
859 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
860 }
a7a00a72
DG		 861
862 /* Sync SLB */
863#ifdef TARGET_PPC64
864 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
865 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
866 if (env->slb[i].esid & SLB_ESID_V) {
867 sregs.u.s.ppc64.slb[i].slbe |= i;
868 }
869 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
870 }
871#endif
872
873 /* Sync SRs */
874 for (i = 0; i < 16; i++) {
875 sregs.u.s.ppc32.sr[i] = env->sr[i];
876 }
877
878 /* Sync BATs */
879 for (i = 0; i < 8; i++) {
880 /* Beware. We have to swap upper and lower bits here */
881 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
882 | env->DBAT[1][i];
883 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
884 | env->IBAT[1][i];
885 }
886
887 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
888}
889
20d695a9 890int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 891{
20d695a9
AF		 892 PowerPCCPU *cpu = POWERPC_CPU(cs);
893 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 894 struct kvm_regs regs;
895 int ret;
896 int i;
897
1bc22652
AF		 898 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
899 if (ret < 0) {
d76d1650 900 return ret;
1bc22652 901 }
d76d1650
AJ		 902
903 regs.ctr = env->ctr;
904 regs.lr = env->lr;
da91a00f 905 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 906 regs.msr = env->msr;
907 regs.pc = env->nip;
908
909 regs.srr0 = env->spr[SPR_SRR0];
910 regs.srr1 = env->spr[SPR_SRR1];
911
912 regs.sprg0 = env->spr[SPR_SPRG0];
913 regs.sprg1 = env->spr[SPR_SPRG1];
914 regs.sprg2 = env->spr[SPR_SPRG2];
915 regs.sprg3 = env->spr[SPR_SPRG3];
916 regs.sprg4 = env->spr[SPR_SPRG4];
917 regs.sprg5 = env->spr[SPR_SPRG5];
918 regs.sprg6 = env->spr[SPR_SPRG6];
919 regs.sprg7 = env->spr[SPR_SPRG7];
920
90dc8812
SW		 921 regs.pid = env->spr[SPR_BOOKE_PID];
922
d76d1650
AJ		 923 for (i = 0;i < 32; i++)
924 regs.gpr[i] = env->gpr[i];
925
4bddaf55
AK		 926 regs.cr = 0;
927 for (i = 0; i < 8; i++) {
928 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
929 }
930
1bc22652 931 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
d76d1650
AJ		 932 if (ret < 0)
933 return ret;
934
70b79849
DG		 935 kvm_put_fp(cs);
936
93dd5e85 937 if (env->tlb_dirty) {
1bc22652 938 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 939 env->tlb_dirty = false;
940 }
941
f1af19d7 942 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 943 ret = kvmppc_put_books_sregs(cpu);
944 if (ret < 0) {
f1af19d7
DG		 945 return ret;
946 }
947 }
948
949 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 950 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
951 }
f1af19d7 952
d67d40ea
DG		 953 if (cap_one_reg) {
954 int i;
955
956 /* We deliberately ignore errors here, for kernels which have
957 * the ONE_REG calls, but don't support the specific
958 * registers, there's a reasonable chance things will still
959 * work, at least until we try to migrate. */
960 for (i = 0; i < 1024; i++) {
961 uint64_t id = env->spr_cb[i].one_reg_id;
962
963 if (id != 0) {
964 kvm_put_one_spr(cs, id, i);
965 }
f1af19d7 966 }
9b00ea49
DG		 967
968#ifdef TARGET_PPC64
80b3f79b
AK		 969 if (msr_ts) {
970 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
971 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
972 }
973 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
974 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
975 }
976 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
977 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
979 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
986 }
987
9b00ea49
DG		 988 if (cap_papr) {
989 if (kvm_put_vpa(cs) < 0) {
da56ff91 990 DPRINTF("Warning: Unable to set VPA information to KVM\n");
9b00ea49
DG		 991 }
992 }
98a8b524
AK		 993
994 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 995#endif /* TARGET_PPC64 */
f1af19d7
DG		 996 }
997
d76d1650
AJ		 998 return ret;
999}
1000
c371c2e3
BB		 1001static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1002{
1003 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1004}
1005
a7a00a72
DG		 1006static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1007{
1008 CPUPPCState *env = &cpu->env;
1009 struct kvm_sregs sregs;
1010 int ret;
1011
1012 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1013 if (ret < 0) {
1014 return ret;
1015 }
1016
1017 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1018 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1019 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1020 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1021 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1022 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1023 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1024 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1025 env->spr[SPR_DECR] = sregs.u.e.dec;
1026 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1027 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1028 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1029 }
1030
1031 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1032 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1033 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1034 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1035 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1036 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1037 }
1038
1039 if (sregs.u.e.features & KVM_SREGS_E_64) {
1040 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1041 }
1042
1043 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1044 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1045 }
1046
1047 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1048 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1049 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1050 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1051 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1052 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1053 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1054 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1055 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1056 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1057 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1058 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1059 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1060 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1061 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1062 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1063 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1064 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1065 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1066 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1067 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1068 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1069 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1070 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1071 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1072 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1073 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1074 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1075 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1076 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1077 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1078 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1079 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1080
1081 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1082 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1083 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1084 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1085 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1086 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1087 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1088 }
1089
1090 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1091 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1092 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1093 }
1094
1095 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1096 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1097 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1098 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1099 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1100 }
1101 }
1102
1103 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1104 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1105 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1106 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1107 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1108 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1109 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1110 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1111 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1112 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1113 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1114 }
1115
1116 if (sregs.u.e.features & KVM_SREGS_EXP) {
1117 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1118 }
1119
1120 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1121 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1122 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1123 }
1124
1125 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1126 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1127 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1128 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1129
1130 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1131 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1132 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1133 }
1134 }
1135
1136 return 0;
1137}
1138
1139static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1140{
1141 CPUPPCState *env = &cpu->env;
1142 struct kvm_sregs sregs;
1143 int ret;
1144 int i;
1145
1146 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1147 if (ret < 0) {
1148 return ret;
1149 }
1150
e57ca75c 1151 if (!cpu->vhyp) {
a7a00a72
DG		 1152 ppc_store_sdr1(env, sregs.u.s.sdr1);
1153 }
1154
1155 /* Sync SLB */
1156#ifdef TARGET_PPC64
1157 /*
1158 * The packed SLB array we get from KVM_GET_SREGS only contains
1159 * information about valid entries. So we flush our internal copy
1160 * to get rid of stale ones, then put all valid SLB entries back
1161 * in.
1162 */
1163 memset(env->slb, 0, sizeof(env->slb));
1164 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1165 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1166 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1167 /*
1168 * Only restore valid entries
1169 */
1170 if (rb & SLB_ESID_V) {
1171 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1172 }
1173 }
1174#endif
1175
1176 /* Sync SRs */
1177 for (i = 0; i < 16; i++) {
1178 env->sr[i] = sregs.u.s.ppc32.sr[i];
1179 }
1180
1181 /* Sync BATs */
1182 for (i = 0; i < 8; i++) {
1183 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1184 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1185 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1186 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1187 }
1188
1189 return 0;
1190}
1191
20d695a9 1192int kvm_arch_get_registers(CPUState *cs)
d76d1650 1193{
20d695a9
AF		 1194 PowerPCCPU *cpu = POWERPC_CPU(cs);
1195 CPUPPCState *env = &cpu->env;
d76d1650 1196 struct kvm_regs regs;
90dc8812 1197 uint32_t cr;
138b38b6 1198 int i, ret;
d76d1650 1199
1bc22652 1200 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
d76d1650
AJ		 1201 if (ret < 0)
1202 return ret;
1203
90dc8812
SW		 1204 cr = regs.cr;
1205 for (i = 7; i >= 0; i--) {
1206 env->crf[i] = cr & 15;
1207 cr >>= 4;
1208 }
ba5e5090 1209
d76d1650
AJ		 1210 env->ctr = regs.ctr;
1211 env->lr = regs.lr;
da91a00f 1212 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1213 env->msr = regs.msr;
1214 env->nip = regs.pc;
1215
1216 env->spr[SPR_SRR0] = regs.srr0;
1217 env->spr[SPR_SRR1] = regs.srr1;
1218
1219 env->spr[SPR_SPRG0] = regs.sprg0;
1220 env->spr[SPR_SPRG1] = regs.sprg1;
1221 env->spr[SPR_SPRG2] = regs.sprg2;
1222 env->spr[SPR_SPRG3] = regs.sprg3;
1223 env->spr[SPR_SPRG4] = regs.sprg4;
1224 env->spr[SPR_SPRG5] = regs.sprg5;
1225 env->spr[SPR_SPRG6] = regs.sprg6;
1226 env->spr[SPR_SPRG7] = regs.sprg7;
1227
90dc8812
SW		 1228 env->spr[SPR_BOOKE_PID] = regs.pid;
1229
d76d1650
AJ		 1230 for (i = 0;i < 32; i++)
1231 env->gpr[i] = regs.gpr[i];
1232
70b79849
DG		 1233 kvm_get_fp(cs);
1234
90dc8812 1235 if (cap_booke_sregs) {
a7a00a72 1236 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1237 if (ret < 0) {
1238 return ret;
1239 }
fafc0b6a 1240 }
90dc8812 1241
90dc8812 1242 if (cap_segstate) {
a7a00a72 1243 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1244 if (ret < 0) {
1245 return ret;
1246 }
fafc0b6a 1247 }
ba5e5090 1248
d67d40ea
DG		 1249 if (cap_hior) {
1250 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1251 }
1252
1253 if (cap_one_reg) {
1254 int i;
1255
1256 /* We deliberately ignore errors here, for kernels which have
1257 * the ONE_REG calls, but don't support the specific
1258 * registers, there's a reasonable chance things will still
1259 * work, at least until we try to migrate. */
1260 for (i = 0; i < 1024; i++) {
1261 uint64_t id = env->spr_cb[i].one_reg_id;
1262
1263 if (id != 0) {
1264 kvm_get_one_spr(cs, id, i);
1265 }
1266 }
9b00ea49
DG		 1267
1268#ifdef TARGET_PPC64
80b3f79b
AK		 1269 if (msr_ts) {
1270 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1271 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1272 }
1273 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1274 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1275 }
1276 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1277 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1278 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1279 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1280 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1281 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1282 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1284 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1286 }
1287
9b00ea49
DG		 1288 if (cap_papr) {
1289 if (kvm_get_vpa(cs) < 0) {
da56ff91 1290 DPRINTF("Warning: Unable to get VPA information from KVM\n");
9b00ea49
DG		 1291 }
1292 }
98a8b524
AK		 1293
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1295#endif
d67d40ea
DG		 1296 }
1297
d76d1650
AJ		 1298 return 0;
1299}
1300
1bc22652 1301int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1302{
1303 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1304
1305 if (irq != PPC_INTERRUPT_EXT) {
1306 return 0;
1307 }
1308
1309 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
1310 return 0;
1311 }
1312
1bc22652 1313 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1314
1315 return 0;
1316}
1317
a69dc537 1318#if defined(TARGET_PPC64)
16415335
AG		 1319#define PPC_INPUT_INT PPC970_INPUT_INT
1320#else
1321#define PPC_INPUT_INT PPC6xx_INPUT_INT
1322#endif
1323
20d695a9 1324void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1325{
20d695a9
AF		 1326 PowerPCCPU *cpu = POWERPC_CPU(cs);
1327 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 1328 int r;
1329 unsigned irq;
1330
4b8523ee
JK		 1331 qemu_mutex_lock_iothread();
1332
5cbdb3a3 1333 /* PowerPC QEMU tracks the various core input pins (interrupt, critical
d76d1650 1334 * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
fc87e185
AG		 1335 if (!cap_interrupt_level &&
1336 run->ready_for_interrupt_injection &&
259186a7 1337 (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
16415335 1338 (env->irq_input_state & (1<<PPC_INPUT_INT)))
d76d1650
AJ		 1339 {
1340 /* For now KVM disregards the 'irq' argument. However, in the
1341 * future KVM could cache it in-kernel to avoid a heavyweight exit
1342 * when reading the UIC.
1343 */
fc87e185 1344 irq = KVM_INTERRUPT_SET;
d76d1650 1345
da56ff91 1346 DPRINTF("injected interrupt %d\n", irq);
1bc22652 1347 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq);
55e5c285
AF		 1348 if (r < 0) {
1349 printf("cpu %d fail inject %x\n", cs->cpu_index, irq);
1350 }
c821c2bd
AG		 1351
1352 /* Always wake up soon in case the interrupt was level based */
bc72ad67 1353 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
73bcb24d 1354 (NANOSECONDS_PER_SECOND / 50));
d76d1650
AJ		 1355 }
1356
1357 /* We don't know if there are more interrupts pending after this. However,
1358 * the guest will return to userspace in the course of handling this one
1359 * anyways, so we will get a chance to deliver the rest. */
4b8523ee
JK		 1360
1361 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1362}
1363
4c663752 1364MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1365{
4c663752 1366 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1367}
1368
20d695a9 1369int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1370{
259186a7 1371 return cs->halted;
0af691d7
MT		 1372}
1373
259186a7 1374static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1375{
259186a7
AF		 1376 CPUState *cs = CPU(cpu);
1377 CPUPPCState *env = &cpu->env;
1378
1379 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1380 cs->halted = 1;
27103424 1381 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1382 }
1383
bb4ea393 1384 return 0;
d76d1650
AJ		 1385}
1386
1387/* map dcr access to existing qemu dcr emulation */
1328c2bf 1388static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data)
d76d1650
AJ		 1389{
1390 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
1391 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1392
bb4ea393 1393 return 0;
d76d1650
AJ		 1394}
1395
1328c2bf 1396static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data)
d76d1650
AJ		 1397{
1398 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
1399 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1400
bb4ea393 1401 return 0;
d76d1650
AJ		 1402}
1403
8a0548f9
BB		 1404int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1405{
1406 /* Mixed endian case is not handled */
1407 uint32_t sc = debug_inst_opcode;
1408
1409 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1410 sizeof(sc), 0) ||
1411 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1412 return -EINVAL;
1413 }
1414
1415 return 0;
1416}
1417
1418int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1419{
1420 uint32_t sc;
1421
1422 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1423 sc != debug_inst_opcode ||
1424 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1425 sizeof(sc), 1)) {
1426 return -EINVAL;
1427 }
1428
1429 return 0;
1430}
1431
88365d17
BB		 1432static int find_hw_breakpoint(target_ulong addr, int type)
1433{
1434 int n;
1435
1436 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1437 <= ARRAY_SIZE(hw_debug_points));
1438
1439 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1440 if (hw_debug_points[n].addr == addr &&
1441 hw_debug_points[n].type == type) {
1442 return n;
1443 }
1444 }
1445
1446 return -1;
1447}
1448
1449static int find_hw_watchpoint(target_ulong addr, int *flag)
1450{
1451 int n;
1452
1453 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1454 if (n >= 0) {
1455 *flag = BP_MEM_ACCESS;
1456 return n;
1457 }
1458
1459 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1460 if (n >= 0) {
1461 *flag = BP_MEM_WRITE;
1462 return n;
1463 }
1464
1465 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1466 if (n >= 0) {
1467 *flag = BP_MEM_READ;
1468 return n;
1469 }
1470
1471 return -1;
1472}
1473
1474int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1475 target_ulong len, int type)
1476{
1477 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1478 return -ENOBUFS;
1479 }
1480
1481 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1482 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1483
1484 switch (type) {
1485 case GDB_BREAKPOINT_HW:
1486 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1487 return -ENOBUFS;
1488 }
1489
1490 if (find_hw_breakpoint(addr, type) >= 0) {
1491 return -EEXIST;
1492 }
1493
1494 nb_hw_breakpoint++;
1495 break;
1496
1497 case GDB_WATCHPOINT_WRITE:
1498 case GDB_WATCHPOINT_READ:
1499 case GDB_WATCHPOINT_ACCESS:
1500 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1501 return -ENOBUFS;
1502 }
1503
1504 if (find_hw_breakpoint(addr, type) >= 0) {
1505 return -EEXIST;
1506 }
1507
1508 nb_hw_watchpoint++;
1509 break;
1510
1511 default:
1512 return -ENOSYS;
1513 }
1514
1515 return 0;
1516}
1517
1518int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1519 target_ulong len, int type)
1520{
1521 int n;
1522
1523 n = find_hw_breakpoint(addr, type);
1524 if (n < 0) {
1525 return -ENOENT;
1526 }
1527
1528 switch (type) {
1529 case GDB_BREAKPOINT_HW:
1530 nb_hw_breakpoint--;
1531 break;
1532
1533 case GDB_WATCHPOINT_WRITE:
1534 case GDB_WATCHPOINT_READ:
1535 case GDB_WATCHPOINT_ACCESS:
1536 nb_hw_watchpoint--;
1537 break;
1538
1539 default:
1540 return -ENOSYS;
1541 }
1542 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1543
1544 return 0;
1545}
1546
1547void kvm_arch_remove_all_hw_breakpoints(void)
1548{
1549 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1550}
1551
8a0548f9
BB		 1552void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1553{
88365d17
BB		 1554 int n;
1555
8a0548f9
BB		 1556 /* Software Breakpoint updates */
1557 if (kvm_sw_breakpoints_active(cs)) {
1558 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1559 }
88365d17
BB		 1560
1561 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1562 <= ARRAY_SIZE(hw_debug_points));
1563 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1564
1565 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1566 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1567 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1568 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1569 switch (hw_debug_points[n].type) {
1570 case GDB_BREAKPOINT_HW:
1571 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1572 break;
1573 case GDB_WATCHPOINT_WRITE:
1574 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1575 break;
1576 case GDB_WATCHPOINT_READ:
1577 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1578 break;
1579 case GDB_WATCHPOINT_ACCESS:
1580 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1581 KVMPPC_DEBUG_WATCH_READ;
1582 break;
1583 default:
1584 cpu_abort(cs, "Unsupported breakpoint type\n");
1585 }
1586 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1587 }
1588 }
8a0548f9
BB		 1589}
1590
1591static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1592{
1593 CPUState *cs = CPU(cpu);
1594 CPUPPCState *env = &cpu->env;
1595 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1596 int handle = 0;
88365d17
BB		 1597 int n;
1598 int flag = 0;
8a0548f9 1599
88365d17
BB		 1600 if (cs->singlestep_enabled) {
1601 handle = 1;
1602 } else if (arch_info->status) {
1603 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1604 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1605 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1606 if (n >= 0) {
1607 handle = 1;
1608 }
1609 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1610 KVMPPC_DEBUG_WATCH_WRITE)) {
1611 n = find_hw_watchpoint(arch_info->address, &flag);
1612 if (n >= 0) {
1613 handle = 1;
1614 cs->watchpoint_hit = &hw_watchpoint;
1615 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1616 hw_watchpoint.flags = flag;
1617 }
1618 }
1619 }
1620 } else if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
8a0548f9
BB		 1621 handle = 1;
1622 } else {
1623 /* QEMU is not able to handle debug exception, so inject
1624 * program exception to guest;
1625 * Yes program exception NOT debug exception !!
88365d17
BB		 1626 * When QEMU is using debug resources then debug exception must
1627 * be always set. To achieve this we set MSR_DE and also set
1628 * MSRP_DEP so guest cannot change MSR_DE.
1629 * When emulating debug resource for guest we want guest
1630 * to control MSR_DE (enable/disable debug interrupt on need).
1631 * Supporting both configurations are NOT possible.
1632 * So the result is that we cannot share debug resources
1633 * between QEMU and Guest on BOOKE architecture.
1634 * In the current design QEMU gets the priority over guest,
1635 * this means that if QEMU is using debug resources then guest
1636 * cannot use them;
8a0548f9
BB		 1637 * For software breakpoint QEMU uses a privileged instruction;
1638 * So there cannot be any reason that we are here for guest
1639 * set debug exception, only possibility is guest executed a
1640 * privileged / illegal instruction and that's why we are
1641 * injecting a program interrupt.
1642 */
1643
1644 cpu_synchronize_state(cs);
1645 /* env->nip is PC, so increment this by 4 to use
1646 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1647 */
1648 env->nip += 4;
1649 cs->exception_index = POWERPC_EXCP_PROGRAM;
1650 env->error_code = POWERPC_EXCP_INVAL;
1651 ppc_cpu_do_interrupt(cs);
1652 }
1653
1654 return handle;
1655}
1656
20d695a9 1657int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1658{
20d695a9
AF		 1659 PowerPCCPU *cpu = POWERPC_CPU(cs);
1660 CPUPPCState *env = &cpu->env;
bb4ea393 1661 int ret;
d76d1650 1662
4b8523ee
JK		 1663 qemu_mutex_lock_iothread();
1664
d76d1650
AJ		 1665 switch (run->exit_reason) {
1666 case KVM_EXIT_DCR:
1667 if (run->dcr.is_write) {
da56ff91 1668 DPRINTF("handle dcr write\n");
d76d1650
AJ		 1669 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1670 } else {
da56ff91 1671 DPRINTF("handle dcr read\n");
d76d1650
AJ		 1672 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1673 }
1674 break;
1675 case KVM_EXIT_HLT:
da56ff91 1676 DPRINTF("handle halt\n");
259186a7 1677 ret = kvmppc_handle_halt(cpu);
d76d1650 1678 break;
c6304a4a 1679#if defined(TARGET_PPC64)
f61b4bed 1680 case KVM_EXIT_PAPR_HCALL:
da56ff91 1681 DPRINTF("handle PAPR hypercall\n");
20d695a9 1682 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1683 run->papr_hcall.nr,
f61b4bed 1684 run->papr_hcall.args);
78e8fde2 1685 ret = 0;
f61b4bed
AG		 1686 break;
1687#endif
5b95b8b9 1688 case KVM_EXIT_EPR:
da56ff91 1689 DPRINTF("handle epr\n");
933b19ea 1690 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1691 ret = 0;
1692 break;
31f2cb8f 1693 case KVM_EXIT_WATCHDOG:
da56ff91 1694 DPRINTF("handle watchdog expiry\n");
31f2cb8f
BB		 1695 watchdog_perform_action();
1696 ret = 0;
1697 break;
1698
8a0548f9
BB		 1699 case KVM_EXIT_DEBUG:
1700 DPRINTF("handle debug exception\n");
1701 if (kvm_handle_debug(cpu, run)) {
1702 ret = EXCP_DEBUG;
1703 break;
1704 }
1705 /* re-enter, this exception was guest-internal */
1706 ret = 0;
1707 break;
1708
73aaec4a
JK		 1709 default:
1710 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1711 ret = -1;
1712 break;
d76d1650
AJ		 1713 }
1714
4b8523ee 1715 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1716 return ret;
1717}
1718
31f2cb8f
BB		 1719int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1720{
1721 CPUState *cs = CPU(cpu);
1722 uint32_t bits = tsr_bits;
1723 struct kvm_one_reg reg = {
1724 .id = KVM_REG_PPC_OR_TSR,
1725 .addr = (uintptr_t) &bits,
1726 };
1727
1728 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1729}
1730
1731int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1732{
1733
1734 CPUState *cs = CPU(cpu);
1735 uint32_t bits = tsr_bits;
1736 struct kvm_one_reg reg = {
1737 .id = KVM_REG_PPC_CLEAR_TSR,
1738 .addr = (uintptr_t) &bits,
1739 };
1740
1741 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1742}
1743
1744int kvmppc_set_tcr(PowerPCCPU *cpu)
1745{
1746 CPUState *cs = CPU(cpu);
1747 CPUPPCState *env = &cpu->env;
1748 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1749
1750 struct kvm_one_reg reg = {
1751 .id = KVM_REG_PPC_TCR,
1752 .addr = (uintptr_t) &tcr,
1753 };
1754
1755 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1756}
1757
1758int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1759{
1760 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1761 int ret;
1762
1763 if (!kvm_enabled()) {
1764 return -1;
1765 }
1766
1767 if (!cap_ppc_watchdog) {
1768 printf("warning: KVM does not support watchdog");
1769 return -1;
1770 }
1771
48add816 1772 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1773 if (ret < 0) {
1774 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1775 __func__, strerror(-ret));
1776 return ret;
1777 }
1778
1779 return ret;
1780}
1781
dc333cd6
AG		 1782static int read_cpuinfo(const char *field, char *value, int len)
1783{
1784 FILE *f;
1785 int ret = -1;
1786 int field_len = strlen(field);
1787 char line[512];
1788
1789 f = fopen("/proc/cpuinfo", "r");
1790 if (!f) {
1791 return -1;
1792 }
1793
1794 do {
ef951443 1795 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1796 break;
1797 }
1798 if (!strncmp(line, field, field_len)) {
ae215068 1799 pstrcpy(value, len, line);
dc333cd6
AG		 1800 ret = 0;
1801 break;
1802 }
1803 } while(*line);
1804
1805 fclose(f);
1806
1807 return ret;
1808}
1809
1810uint32_t kvmppc_get_tbfreq(void)
1811{
1812 char line[512];
1813 char *ns;
73bcb24d 1814 uint32_t retval = NANOSECONDS_PER_SECOND;
dc333cd6
AG		 1815
1816 if (read_cpuinfo("timebase", line, sizeof(line))) {
1817 return retval;
1818 }
1819
1820 if (!(ns = strchr(line, ':'))) {
1821 return retval;
1822 }
1823
1824 ns++;
1825
f9b8e7f6 1826 return atoi(ns);
dc333cd6 1827}
4513d923 1828
ef951443
ND		 1829bool kvmppc_get_host_serial(char **value)
1830{
1831 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1832 NULL);
1833}
1834
1835bool kvmppc_get_host_model(char **value)
1836{
1837 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1838}
1839
eadaada1
AG		 1840/* Try to find a device tree node for a CPU with clock-frequency property */
1841static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1842{
1843 struct dirent *dirp;
1844 DIR *dp;
1845
1846 if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) {
1847 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1848 return -1;
1849 }
1850
1851 buf[0] = '\0';
1852 while ((dirp = readdir(dp)) != NULL) {
1853 FILE *f;
1854 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1855 dirp->d_name);
1856 f = fopen(buf, "r");
1857 if (f) {
1858 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1859 fclose(f);
1860 break;
1861 }
1862 buf[0] = '\0';
1863 }
1864 closedir(dp);
1865 if (buf[0] == '\0') {
1866 printf("Unknown host!\n");
1867 return -1;
1868 }
1869
1870 return 0;
1871}
1872
7d94a30b 1873static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1874{
9bc884b7
DG		 1875 union {
1876 uint32_t v32;
1877 uint64_t v64;
1878 } u;
eadaada1
AG		 1879 FILE *f;
1880 int len;
1881
7d94a30b 1882 f = fopen(filename, "rb");
eadaada1
AG		 1883 if (!f) {
1884 return -1;
1885 }
1886
9bc884b7 1887 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1888 fclose(f);
1889 switch (len) {
9bc884b7
DG		 1890 case 4:
1891 /* property is a 32-bit quantity */
1892 return be32_to_cpu(u.v32);
1893 case 8:
1894 return be64_to_cpu(u.v64);
eadaada1
AG		 1895 }
1896
1897 return 0;
1898}
1899
7d94a30b
SB		 1900/* Read a CPU node property from the host device tree that's a single
1901 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1902 * (can't find or open the property, or doesn't understand the
1903 * format) */
1904static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1905{
1906 char buf[PATH_MAX], *tmp;
1907 uint64_t val;
1908
1909 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1910 return -1;
1911 }
1912
1913 tmp = g_strdup_printf("%s/%s", buf, propname);
1914 val = kvmppc_read_int_dt(tmp);
1915 g_free(tmp);
1916
1917 return val;
1918}
1919
9bc884b7
DG		 1920uint64_t kvmppc_get_clockfreq(void)
1921{
1922 return kvmppc_read_int_cpu_dt("clock-frequency");
1923}
1924
1a61a9ae
SY		 1925static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
1926 {
1927 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1928 CPUState *cs = CPU(cpu);
1929
6fd33a75 1930 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1931 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1932 return 0;
1933 }
1934
1935 return 1;
1936}
1937
1938int kvmppc_get_hasidle(CPUPPCState *env)
1939{
1940 struct kvm_ppc_pvinfo pvinfo;
1941
1942 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1943 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1944 return 1;
1945 }
1946
1947 return 0;
1948}
1949
1328c2bf 1950int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09
AG		 1951{
1952 uint32_t *hc = (uint32_t*)buf;
45024f09
AG		 1953 struct kvm_ppc_pvinfo pvinfo;
1954
1a61a9ae 1955 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 1956 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 1957 return 0;
1958 }
45024f09
AG		 1959
1960 /*
d13fc32e 1961 * Fallback to always fail hypercalls regardless of endianness:
45024f09 1962 *
d13fc32e 1963 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 1964 * li r3, -1
d13fc32e
AG		 1965 * b .+8 (becomes nop in wrong endian)
1966 * bswap32(li r3, -1)
45024f09
AG		 1967 */
1968
d13fc32e
AG		 1969 hc[0] = cpu_to_be32(0x08000048);
1970 hc[1] = cpu_to_be32(0x3860ffff);
1971 hc[2] = cpu_to_be32(0x48000008);
1972 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 1973
0ddbd053 1974 return 1;
45024f09
AG		 1975}
1976
026bfd89
DG		 1977static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
1978{
1979 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
1980}
1981
1982void kvmppc_enable_logical_ci_hcalls(void)
1983{
1984 /*
1985 * FIXME: it would be nice if we could detect the cases where
1986 * we're using a device which requires the in kernel
1987 * implementation of these hcalls, but the kernel lacks them and
1988 * produce a warning.
1989 */
1990 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
1991 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
1992}
1993
ef9971dd
AK		 1994void kvmppc_enable_set_mode_hcall(void)
1995{
1996 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
1997}
1998
5145ad4f
NW		 1999void kvmppc_enable_clear_ref_mod_hcalls(void)
2000{
2001 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2002 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2003}
2004
1bc22652 2005void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2006{
1bc22652 2007 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2008 int ret;
2009
da20aed1
DG		 2010 if (!kvm_enabled()) {
2011 return;
2012 }
2013
48add816 2014 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2015 if (ret) {
072ed5f2
TH		 2016 error_report("This vCPU type or KVM version does not support PAPR");
2017 exit(1);
94135e81 2018 }
9b00ea49
DG		 2019
2020 /* Update the capability flag so we sync the right information
2021 * with kvm */
2022 cap_papr = 1;
f61b4bed
AG		 2023}
2024
d6e166c0 2025int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2026{
d6e166c0 2027 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2028}
2029
5b95b8b9
AG		 2030void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2031{
5b95b8b9 2032 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2033 int ret;
2034
48add816 2035 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2036 if (ret && mpic_proxy) {
072ed5f2
TH		 2037 error_report("This KVM version does not support EPR");
2038 exit(1);
5b95b8b9
AG		 2039 }
2040}
2041
e97c3636
DG		 2042int kvmppc_smt_threads(void)
2043{
2044 return cap_ppc_smt ? cap_ppc_smt : 1;
2045}
2046
fa98fbfc
SB		 2047int kvmppc_set_smt_threads(int smt)
2048{
2049 int ret;
2050
2051 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2052 if (!ret) {
2053 cap_ppc_smt = smt;
2054 }
2055 return ret;
2056}
2057
2058void kvmppc_hint_smt_possible(Error **errp)
2059{
2060 int i;
2061 GString *g;
2062 char *s;
2063
2064 assert(kvm_enabled());
2065 if (cap_ppc_smt_possible) {
2066 g = g_string_new("Available VSMT modes:");
2067 for (i = 63; i >= 0; i--) {
2068 if ((1UL << i) & cap_ppc_smt_possible) {
2069 g_string_append_printf(g, " %lu", (1UL << i));
2070 }
2071 }
2072 s = g_string_free(g, false);
2073 error_append_hint(errp, "%s.\n", s);
2074 g_free(s);
2075 } else {
2076 error_append_hint(errp,
2077 "This KVM seems to be too old to support VSMT.\n");
2078 }
2079}
2080
2081
7f763a5d 2082#ifdef TARGET_PPC64
7f763a5d
DG		 2083uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2084{
f36951c1
DG		 2085 struct kvm_ppc_smmu_info info;
2086 long rampagesize, best_page_shift;
2087 int i;
2088
f36951c1
DG		 2089 /* Find the largest hardware supported page size that's less than
2090 * or equal to the (logical) backing page size of guest RAM */
ab256960 2091 kvm_get_smmu_info(&info, &error_fatal);
9c607668 2092 rampagesize = qemu_getrampagesize();
f36951c1
DG		 2093 best_page_shift = 0;
2094
2095 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2096 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2097
2098 if (!sps->page_shift) {
2099 continue;
2100 }
2101
2102 if ((sps->page_shift > best_page_shift)
2103 && ((1UL << sps->page_shift) <= rampagesize)) {
2104 best_page_shift = sps->page_shift;
2105 }
2106 }
2107
7f763a5d 2108 return MIN(current_size,
f36951c1 2109 1ULL << (best_page_shift + hash_shift - 7));
7f763a5d
DG		 2110}
2111#endif
2112
da95324e
AK		 2113bool kvmppc_spapr_use_multitce(void)
2114{
2115 return cap_spapr_multitce;
2116}
2117
3dc410ae
AK		 2118int kvmppc_spapr_enable_inkernel_multitce(void)
2119{
2120 int ret;
2121
2122 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2123 H_PUT_TCE_INDIRECT, 1);
2124 if (!ret) {
2125 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2126 H_STUFF_TCE, 1);
2127 }
2128
2129 return ret;
2130}
2131
d6ee2a7c
AK		 2132void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2133 uint64_t bus_offset, uint32_t nb_table,
2134 int *pfd, bool need_vfio)
0f5cb298 2135{
0f5cb298
DG		 2136 long len;
2137 int fd;
2138 void *table;
2139
b5aec396
DG		 2140 /* Must set fd to -1 so we don't try to munmap when called for
2141 * destroying the table, which the upper layers -will- do
2142 */
2143 *pfd = -1;
6a81dd17 2144 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2145 return NULL;
2146 }
2147
d6ee2a7c
AK		 2148 if (cap_spapr_tce_64) {
2149 struct kvm_create_spapr_tce_64 args = {
2150 .liobn = liobn,
2151 .page_shift = page_shift,
2152 .offset = bus_offset >> page_shift,
2153 .size = nb_table,
2154 .flags = 0
2155 };
2156 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2157 if (fd < 0) {
2158 fprintf(stderr,
2159 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2160 liobn);
2161 return NULL;
2162 }
2163 } else if (cap_spapr_tce) {
2164 uint64_t window_size = (uint64_t) nb_table << page_shift;
2165 struct kvm_create_spapr_tce args = {
2166 .liobn = liobn,
2167 .window_size = window_size,
2168 };
2169 if ((window_size != args.window_size) || bus_offset) {
2170 return NULL;
2171 }
2172 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2173 if (fd < 0) {
2174 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2175 liobn);
2176 return NULL;
2177 }
2178 } else {
0f5cb298
DG		 2179 return NULL;
2180 }
2181
d6ee2a7c 2182 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2183 /* FIXME: round this up to page size */
2184
74b41e56 2185 table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2186 if (table == MAP_FAILED) {
b5aec396
DG		 2187 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2188 liobn);
0f5cb298
DG		 2189 close(fd);
2190 return NULL;
2191 }
2192
2193 *pfd = fd;
2194 return table;
2195}
2196
523e7b8a 2197int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2198{
2199 long len;
2200
2201 if (fd < 0) {
2202 return -1;
2203 }
2204
523e7b8a 2205 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2206 if ((munmap(table, len) < 0) ||
2207 (close(fd) < 0)) {
b5aec396
DG		 2208 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2209 strerror(errno));
0f5cb298
DG		 2210 /* Leak the table */
2211 }
2212
2213 return 0;
2214}
2215
7f763a5d
DG		 2216int kvmppc_reset_htab(int shift_hint)
2217{
2218 uint32_t shift = shift_hint;
2219
ace9a2cb
DG		 2220 if (!kvm_enabled()) {
2221 /* Full emulation, tell caller to allocate htab itself */
2222 return 0;
2223 }
6977afda 2224 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2225 int ret;
2226 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb
DG		 2227 if (ret == -ENOTTY) {
2228 /* At least some versions of PR KVM advertise the
2229 * capability, but don't implement the ioctl(). Oops.
2230 * Return 0 so that we allocate the htab in qemu, as is
2231 * correct for PR. */
2232 return 0;
2233 } else if (ret < 0) {
7f763a5d
DG		 2234 return ret;
2235 }
2236 return shift;
2237 }
2238
ace9a2cb
DG		 2239 /* We have a kernel that predates the htab reset calls. For PR
2240 * KVM, we need to allocate the htab ourselves, for an HV KVM of
96c9cff0
TH		 2241 * this era, it has allocated a 16MB fixed size hash table already. */
2242 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2243 /* PR - tell caller to allocate htab */
2244 return 0;
2245 } else {
2246 /* HV - assume 16MB kernel allocated htab */
2247 return 24;
2248 }
7f763a5d
DG		 2249}
2250
a1e98583
DG		 2251static inline uint32_t mfpvr(void)
2252{
2253 uint32_t pvr;
2254
2255 asm ("mfpvr %0"
2256 : "=r"(pvr));
2257 return pvr;
2258}
2259
a7342588
DG		 2260static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2261{
2262 if (on) {
2263 *word |= flags;
2264 } else {
2265 *word &= ~flags;
2266 }
2267}
2268
2985b86b
AF		 2269static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2270{
2271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2272 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2273 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2274
cfe34f44 2275 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2276 pcc->pvr = mfpvr();
a7342588 2277
3f2ca480
DG		 2278 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2279 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2280 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2281 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2282 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2283 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2284
2285 if (dcache_size != -1) {
2286 pcc->l1_dcache_size = dcache_size;
2287 }
2288
2289 if (icache_size != -1) {
2290 pcc->l1_icache_size = icache_size;
2291 }
c64abd1f
SB		 2292
2293#if defined(TARGET_PPC64)
2294 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2295
2296 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2297 /*
2298 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2299 * compliant. More importantly, advertising ISA 3.00
2300 * architected mode may prevent guests from activating
2301 * necessary DD1 workarounds.
2302 */
2303 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2304 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2305 }
c64abd1f 2306#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2307}
2308
3b961124
SY		 2309bool kvmppc_has_cap_epr(void)
2310{
2311 return cap_epr;
2312}
2313
87a91de6
AG		 2314bool kvmppc_has_cap_fixup_hcalls(void)
2315{
2316 return cap_fixup_hcalls;
2317}
2318
bac3bf28
TH		 2319bool kvmppc_has_cap_htm(void)
2320{
2321 return cap_htm;
2322}
2323
cf1c4cce
SB		 2324bool kvmppc_has_cap_mmu_radix(void)
2325{
2326 return cap_mmu_radix;
2327}
2328
2329bool kvmppc_has_cap_mmu_hash_v3(void)
2330{
2331 return cap_mmu_hash_v3;
2332}
2333
072f416a
SJS		 2334static bool kvmppc_power8_host(void)
2335{
2336 bool ret = false;
2337#ifdef TARGET_PPC64
2338 {
2339 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2340 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2341 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2342 (base_pvr == CPU_POWERPC_POWER8_BASE);
2343 }
2344#endif /* TARGET_PPC64 */
2345 return ret;
2346}
2347
8fea7044
SJS		 2348static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2349{
072f416a
SJS		 2350 bool l1d_thread_priv_req = !kvmppc_power8_host();
2351
8fea7044
SJS		 2352 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2353 return 2;
072f416a
SJS		 2354 } else if ((!l1d_thread_priv_req ||
2355 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2356 (c.character & c.character_mask
2357 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2358 return 1;
2359 }
2360
2361 return 0;
2362}
2363
2364static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2365{
2366 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2367 return 2;
2368 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2369 return 1;
2370 }
2371
2372 return 0;
2373}
2374
2375static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2376{
2377 if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2378 return SPAPR_CAP_FIXED_CCD;
2379 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2380 return SPAPR_CAP_FIXED_IBS;
2381 }
2382
2383 return 0;
2384}
2385
8acc2ae5
SJS		 2386static void kvmppc_get_cpu_characteristics(KVMState *s)
2387{
2388 struct kvm_ppc_cpu_char c;
2389 int ret;
2390
2391 /* Assume broken */
2392 cap_ppc_safe_cache = 0;
2393 cap_ppc_safe_bounds_check = 0;
2394 cap_ppc_safe_indirect_branch = 0;
2395
2396 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2397 if (!ret) {
2398 return;
2399 }
2400 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2401 if (ret < 0) {
2402 return;
2403 }
8fea7044
SJS		 2404
2405 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2406 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2407 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8acc2ae5
SJS		 2408}
2409
2410int kvmppc_get_cap_safe_cache(void)
2411{
2412 return cap_ppc_safe_cache;
2413}
2414
2415int kvmppc_get_cap_safe_bounds_check(void)
2416{
2417 return cap_ppc_safe_bounds_check;
2418}
2419
2420int kvmppc_get_cap_safe_indirect_branch(void)
2421{
2422 return cap_ppc_safe_indirect_branch;
2423}
2424
9ded780c
AK		 2425bool kvmppc_has_cap_spapr_vfio(void)
2426{
2427 return cap_spapr_vfio;
2428}
2429
52b2519c
TH		 2430PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2431{
2432 uint32_t host_pvr = mfpvr();
2433 PowerPCCPUClass *pvr_pcc;
2434
2435 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2436 if (pvr_pcc == NULL) {
2437 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2438 }
2439
2440 return pvr_pcc;
2441}
2442
2e9c10eb 2443static int kvm_ppc_register_host_cpu_type(MachineState *ms)
5ba4576b
AF		 2444{
2445 TypeInfo type_info = {
2446 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2447 .class_init = kvmppc_host_cpu_class_init,
2448 };
2e9c10eb 2449 MachineClass *mc = MACHINE_GET_CLASS(ms);
5ba4576b 2450 PowerPCCPUClass *pvr_pcc;
92e926e1 2451 ObjectClass *oc;
5b79b1ca 2452 DeviceClass *dc;
715d4b96 2453 int i;
5ba4576b 2454
52b2519c 2455 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2456 if (pvr_pcc == NULL) {
2457 return -1;
2458 }
2459 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2460 type_register(&type_info);
2e9c10eb
IM		 2461 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) {
2462 /* override TCG default cpu type with 'host' cpu model */
2463 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2464 }
5b79b1ca 2465
92e926e1
GK		 2466 oc = object_class_by_name(type_info.name);
2467 g_assert(oc);
2468
715d4b96
TH		 2469 /*
2470 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2471 * we want "POWER8" to be a "family" alias that points to the current
2472 * host CPU type, too)
2473 */
2474 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2475 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2476 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2477 char *suffix;
2478
2479 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2480 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2481 if (suffix) {
2482 *suffix = 0;
2483 }
715d4b96
TH		 2484 break;
2485 }
2486 }
2487
5ba4576b
AF		 2488 return 0;
2489}
2490
feaa64c4
DG		 2491int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2492{
2493 struct kvm_rtas_token_args args = {
2494 .token = token,
2495 };
2496
2497 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2498 return -ENOENT;
2499 }
2500
2501 strncpy(args.name, function, sizeof(args.name));
2502
2503 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2504}
12b1143b 2505
14b0d748 2506int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2507{
2508 struct kvm_get_htab_fd s = {
2509 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2510 .start_index = index,
e68cb8b4 2511 };
82be8e73 2512 int ret;
e68cb8b4
AK		 2513
2514 if (!cap_htab_fd) {
14b0d748
GK		 2515 error_setg(errp, "KVM version doesn't support %s the HPT",
2516 write ? "writing" : "reading");
82be8e73
GK		 2517 return -ENOTSUP;
2518 }
2519
2520 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2521 if (ret < 0) {
14b0d748
GK		 2522 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2523 write ? "writing" : "reading", write ? "to" : "from",
2524 strerror(errno));
82be8e73 2525 return -errno;
e68cb8b4
AK		 2526 }
2527
82be8e73 2528 return ret;
e68cb8b4
AK		 2529}
2530
2531int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2532{
bc72ad67 2533 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2534 uint8_t buf[bufsize];
2535 ssize_t rc;
2536
2537 do {
2538 rc = read(fd, buf, bufsize);
2539 if (rc < 0) {
2540 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2541 strerror(errno));
2542 return rc;
2543 } else if (rc) {
e094c4c1
CLG		 2544 uint8_t *buffer = buf;
2545 ssize_t n = rc;
2546 while (n) {
2547 struct kvm_get_htab_header *head =
2548 (struct kvm_get_htab_header *) buffer;
2549 size_t chunksize = sizeof(*head) +
2550 HASH_PTE_SIZE_64 * head->n_valid;
2551
2552 qemu_put_be32(f, head->index);
2553 qemu_put_be16(f, head->n_valid);
2554 qemu_put_be16(f, head->n_invalid);
2555 qemu_put_buffer(f, (void *)(head + 1),
2556 HASH_PTE_SIZE_64 * head->n_valid);
2557
2558 buffer += chunksize;
2559 n -= chunksize;
2560 }
e68cb8b4
AK		 2561 }
2562 } while ((rc != 0)
2563 && ((max_ns < 0)
bc72ad67 2564 || ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2565
2566 return (rc == 0) ? 1 : 0;
2567}
2568
2569int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2570 uint16_t n_valid, uint16_t n_invalid)
2571{
2572 struct kvm_get_htab_header *buf;
2573 size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64;
2574 ssize_t rc;
2575
2576 buf = alloca(chunksize);
e68cb8b4
AK		 2577 buf->index = index;
2578 buf->n_valid = n_valid;
2579 buf->n_invalid = n_invalid;
2580
2581 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid);
2582
2583 rc = write(fd, buf, chunksize);
2584 if (rc < 0) {
2585 fprintf(stderr, "Error writing KVM hash table: %s\n",
2586 strerror(errno));
2587 return rc;
2588 }
2589 if (rc != chunksize) {
2590 /* We should never get a short write on a single chunk */
2591 fprintf(stderr, "Short write, restoring KVM hash table\n");
2592 return -1;
2593 }
2594 return 0;
2595}
2596
20d695a9 2597bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2598{
2599 return true;
2600}
a1b87fe0 2601
82169660
SW		 2602void kvm_arch_init_irq_routing(KVMState *s)
2603{
2604}
c65f9a07 2605
1ad9f0a4 2606void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2607{
1ad9f0a4
DG		 2608 int fd, rc;
2609 int i;
7c43bca0 2610
14b0d748 2611 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2612
1ad9f0a4
DG		 2613 i = 0;
2614 while (i < n) {
2615 struct kvm_get_htab_header *hdr;
2616 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2617 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2618
1ad9f0a4
DG		 2619 rc = read(fd, buf, sizeof(buf));
2620 if (rc < 0) {
2621 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2622 }
7c43bca0 2623
1ad9f0a4
DG		 2624 hdr = (struct kvm_get_htab_header *)buf;
2625 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2626 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2627
1ad9f0a4
DG		 2628 if (hdr->index != (ptex + i)) {
2629 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2630 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2631 }
2632
a36593e1
AK		 2633 if (n - i < valid) {
2634 valid = n - i;
2635 }
2636 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2637 i += valid;
7c43bca0 2638
1ad9f0a4
DG		 2639 if ((n - i) < invalid) {
2640 invalid = n - i;
2641 }
2642 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2643 i += invalid;
1ad9f0a4
DG		 2644
2645 hdr = (struct kvm_get_htab_header *)
2646 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2647 }
2648 }
2649
2650 close(fd);
7c43bca0 2651}
c1385933 2652
1ad9f0a4 2653void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2654{
1ad9f0a4 2655 int fd, rc;
1ad9f0a4
DG		 2656 struct {
2657 struct kvm_get_htab_header hdr;
2658 uint64_t pte0;
2659 uint64_t pte1;
2660 } buf;
c1385933 2661
14b0d748 2662 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2663
1ad9f0a4
DG		 2664 buf.hdr.n_valid = 1;
2665 buf.hdr.n_invalid = 0;
2666 buf.hdr.index = ptex;
2667 buf.pte0 = cpu_to_be64(pte0);
2668 buf.pte1 = cpu_to_be64(pte1);
c1385933 2669
1ad9f0a4
DG		 2670 rc = write(fd, &buf, sizeof(buf));
2671 if (rc != sizeof(buf)) {
2672 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2673 }
2674 close(fd);
c1385933 2675}
9e03a040
FB		 2676
2677int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2678 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2679{
2680 return 0;
2681}
1850b6b7 2682
38d87493
PX		 2683int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2684 int vector, PCIDevice *dev)
2685{
2686 return 0;
2687}
2688
2689int kvm_arch_release_virq_post(int virq)
2690{
2691 return 0;
2692}
2693
1850b6b7
EA		 2694int kvm_arch_msi_data_to_gsi(uint32_t data)
2695{
2696 return data & 0xffff;
2697}
4d9392be
TH		 2698
2699int kvmppc_enable_hwrng(void)
2700{
2701 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2702 return -1;
2703 }
2704
2705 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2706}
30f4b05b
DG		 2707
2708void kvmppc_check_papr_resize_hpt(Error **errp)
2709{
2710 if (!kvm_enabled()) {
b55d295e
DG		 2711 return; /* No KVM, we're good */
2712 }
2713
2714 if (cap_resize_hpt) {
2715 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2716 }
2717
b55d295e
DG		 2718 /* Otherwise fallback on looking for PR KVM */
2719 if (kvmppc_is_pr(kvm_state)) {
2720 return;
2721 }
30f4b05b
DG		 2722
2723 error_setg(errp,
2724 "Hash page table resizing not available with this KVM version");
2725}
b55d295e
DG		 2726
2727int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2728{
2729 CPUState *cs = CPU(cpu);
2730 struct kvm_ppc_resize_hpt rhpt = {
2731 .flags = flags,
2732 .shift = shift,
2733 };
2734
2735 if (!cap_resize_hpt) {
2736 return -ENOSYS;
2737 }
2738
2739 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2740}
2741
2742int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2743{
2744 CPUState *cs = CPU(cpu);
2745 struct kvm_ppc_resize_hpt rhpt = {
2746 .flags = flags,
2747 .shift = shift,
2748 };
2749
2750 if (!cap_resize_hpt) {
2751 return -ENOSYS;
2752 }
2753
2754 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2755}
2756
c363a37a
DHB		 2757/*
2758 * This is a helper function to detect a post migration scenario
2759 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2760 * the guest kernel can't handle a PVR value other than the actual host
2761 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2762 *
2763 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2764 * (so, we're HV), return true. The workaround itself is done in
2765 * cpu_post_load.
2766 *
2767 * The order here is important: we'll only check for KVM PR as a
2768 * fallback if the guest kernel can't handle the situation itself.
2769 * We need to avoid as much as possible querying the running KVM type
2770 * in QEMU level.
2771 */
2772bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2773{
2774 CPUState *cs = CPU(cpu);
2775
2776 if (!kvm_enabled()) {
2777 return false;
2778 }
2779
2780 if (cap_ppc_pvr_compat) {
2781 return false;
2782 }
2783
2784 return !kvmppc_is_pr(cs->kvm_state);
2785}
a84f7179
ND		 2786
2787void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2788{
2789 CPUState *cs = CPU(cpu);
2790
2791 if (kvm_enabled()) {
2792 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2793 }
2794}
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