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target/ppc/kvm: get rid of kvm_get_fallback_smmu_info()
[mirror_qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
24#include "qemu-common.h"
30f4b05b 25#include "qapi/error.h"
072ed5f2 26#include "qemu/error-report.h"
33c11879 27#include "cpu.h"
715d4b96 28#include "cpu-models.h"
1de7afc9 29#include "qemu/timer.h"
9c17d615 30#include "sysemu/sysemu.h"
b3946626 31#include "sysemu/hw_accel.h"
d76d1650 32#include "kvm_ppc.h"
9c17d615
PB		 33#include "sysemu/cpus.h"
34#include "sysemu/device_tree.h"
d5aea6f3 35#include "mmu-hash64.h"
d76d1650 36
f61b4bed 37#include "hw/sysbus.h"
0d09e41a
PB		 38#include "hw/ppc/spapr.h"
39#include "hw/ppc/spapr_vio.h"
7ebaf795 40#include "hw/ppc/spapr_cpu_core.h"
98a8b524 41#include "hw/ppc/ppc.h"
31f2cb8f 42#include "sysemu/watchdog.h"
b36f100e 43#include "trace.h"
88365d17 44#include "exec/gdbstub.h"
4c663752 45#include "exec/memattrs.h"
9c607668 46#include "exec/ram_addr.h"
2d103aae 47#include "sysemu/hostmem.h"
f348b6d1 48#include "qemu/cutils.h"
9c607668 49#include "qemu/mmap-alloc.h"
f3d9f303 50#include "elf.h"
c64abd1f 51#include "sysemu/kvm_int.h"
f61b4bed 52
d76d1650
AJ		 53//#define DEBUG_KVM
54
55#ifdef DEBUG_KVM
da56ff91 56#define DPRINTF(fmt, ...) \
d76d1650
AJ		 57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
58#else
da56ff91 59#define DPRINTF(fmt, ...) \
d76d1650
AJ		 60 do { } while (0)
61#endif
62
eadaada1
AG		 63#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
64
94a8d39a
JK		 65const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
66 KVM_CAP_LAST_INFO
67};
68
fc87e185
AG		 69static int cap_interrupt_unset = false;
70static int cap_interrupt_level = false;
90dc8812 71static int cap_segstate;
90dc8812 72static int cap_booke_sregs;
e97c3636 73static int cap_ppc_smt;
fa98fbfc 74static int cap_ppc_smt_possible;
0f5cb298 75static int cap_spapr_tce;
d6ee2a7c 76static int cap_spapr_tce_64;
da95324e 77static int cap_spapr_multitce;
9bb62a07 78static int cap_spapr_vfio;
f1af19d7 79static int cap_hior;
d67d40ea 80static int cap_one_reg;
3b961124 81static int cap_epr;
31f2cb8f 82static int cap_ppc_watchdog;
9b00ea49 83static int cap_papr;
e68cb8b4 84static int cap_htab_fd;
87a91de6 85static int cap_fixup_hcalls;
bac3bf28 86static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 87static int cap_mmu_radix;
88static int cap_mmu_hash_v3;
b55d295e 89static int cap_resize_hpt;
c363a37a 90static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 91static int cap_ppc_safe_cache;
92static int cap_ppc_safe_bounds_check;
93static int cap_ppc_safe_indirect_branch;
fc87e185 94
3c902d44
BB		 95static uint32_t debug_inst_opcode;
96
c821c2bd
AG		 97/* XXX We have a race condition where we actually have a level triggered
98 * interrupt, but the infrastructure can't expose that yet, so the guest
99 * takes but ignores it, goes to sleep and never gets notified that there's
100 * still an interrupt pending.
c6a94ba5 101 *
c821c2bd
AG		 102 * As a quick workaround, let's just wake up again 20 ms after we injected
103 * an interrupt. That way we can assure that we're always reinjecting
104 * interrupts in case the guest swallowed them.
c6a94ba5
AG		 105 */
106static QEMUTimer *idle_timer;
107
d5a68146 108static void kvm_kick_cpu(void *opaque)
c6a94ba5 109{
d5a68146 110 PowerPCCPU *cpu = opaque;
d5a68146 111
c08d7424 112 qemu_cpu_kick(CPU(cpu));
c6a94ba5
AG		 113}
114
96c9cff0
TH		 115/* Check whether we are running with KVM-PR (instead of KVM-HV). This
116 * should only be used for fallback tests - generally we should use
117 * explicit capabilities for the features we want, rather than
118 * assuming what is/isn't available depending on the KVM variant. */
119static bool kvmppc_is_pr(KVMState *ks)
120{
121 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 122 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 123}
124
2e9c10eb 125static int kvm_ppc_register_host_cpu_type(MachineState *ms);
8acc2ae5 126static void kvmppc_get_cpu_characteristics(KVMState *s);
5ba4576b 127
b16565b3 128int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 129{
fc87e185 130 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
fc87e185 131 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
90dc8812 132 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 133 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 134 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 135 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 136 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 137 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 138 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 139 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 140 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 141 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 142 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
9b00ea49
DG		 143 /* Note: we don't set cap_papr here, because this capability is
144 * only activated after this by kvmppc_set_papr() */
6977afda 145 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 146 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 147 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 148 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 149 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
150 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
b55d295e 151 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 152 kvmppc_get_cpu_characteristics(s);
c363a37a
DHB		 153 /*
154 * Note: setting it to false because there is not such capability
155 * in KVM at this moment.
156 *
157 * TODO: call kvm_vm_check_extension() with the right capability
158 * after the kernel starts implementing it.*/
159 cap_ppc_pvr_compat = false;
fc87e185
AG		 160
161 if (!cap_interrupt_level) {
162 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
163 "VM to stall at times!\n");
164 }
165
2e9c10eb 166 kvm_ppc_register_host_cpu_type(ms);
5ba4576b 167
d76d1650
AJ		 168 return 0;
169}
170
d525ffab
PB		 171int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
172{
173 return 0;
174}
175
1bc22652 176static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 177{
1bc22652
AF		 178 CPUPPCState *cenv = &cpu->env;
179 CPUState *cs = CPU(cpu);
861bbc80 180 struct kvm_sregs sregs;
5666ca4a
SW		 181 int ret;
182
183 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
64e07be5
AG		 184 /* What we're really trying to say is "if we're on BookE, we use
185 the native PVR for now". This is the only sane way to check
186 it though, so we potentially confuse users that they can run
187 BookE guests on BookS. Let's hope nobody dares enough :) */
5666ca4a
SW		 188 return 0;
189 } else {
90dc8812 190 if (!cap_segstate) {
64e07be5
AG		 191 fprintf(stderr, "kvm error: missing PVR setting capability\n");
192 return -ENOSYS;
5666ca4a 193 }
5666ca4a
SW		 194 }
195
1bc22652 196 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 197 if (ret) {
198 return ret;
199 }
861bbc80
AG		 200
201 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 202 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 203}
204
93dd5e85 205/* Set up a shared TLB array with KVM */
1bc22652 206static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 207{
1bc22652
AF		 208 CPUPPCState *env = &cpu->env;
209 CPUState *cs = CPU(cpu);
93dd5e85
SW		 210 struct kvm_book3e_206_tlb_params params = {};
211 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 212 unsigned int entries = 0;
213 int ret, i;
214
215 if (!kvm_enabled() ||
a60f24b5 216 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 217 return 0;
218 }
219
220 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
221
222 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
223 params.tlb_sizes[i] = booke206_tlb_size(env, i);
224 params.tlb_ways[i] = booke206_tlb_ways(env, i);
225 entries += params.tlb_sizes[i];
226 }
227
228 assert(entries == env->nb_tlb);
229 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
230
231 env->tlb_dirty = true;
232
233 cfg.array = (uintptr_t)env->tlb.tlbm;
234 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
235 cfg.params = (uintptr_t)&params;
236 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
237
48add816 238 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 239 if (ret < 0) {
240 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
241 __func__, strerror(-ret));
242 return ret;
243 }
244
245 env->kvm_sw_tlb = true;
246 return 0;
247}
248
4656e1f0
BH		 249
250#if defined(TARGET_PPC64)
71d0f1ea
GK		 251static void kvm_get_smmu_info(PowerPCCPU *cpu, struct kvm_ppc_smmu_info *info,
252 Error **errp)
4656e1f0 253{
a60f24b5 254 CPUState *cs = CPU(cpu);
71d0f1ea 255 int ret;
a60f24b5 256
71d0f1ea
GK		 257 if (!kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
258 error_setg(errp, "KVM doesn't expose the MMU features it supports");
259 error_append_hint(errp, "Consider switching to a newer KVM\n");
260 return;
4656e1f0 261 }
4656e1f0 262
71d0f1ea
GK		 263 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_SMMU_INFO, info);
264 if (ret == 0) {
265 return;
4656e1f0
BH		 266 }
267
71d0f1ea
GK		 268 error_setg_errno(errp, -ret,
269 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 270}
271
c64abd1f
SB		 272struct ppc_radix_page_info *kvm_get_radix_page_info(void)
273{
274 KVMState *s = KVM_STATE(current_machine->accelerator);
275 struct ppc_radix_page_info *radix_page_info;
276 struct kvm_ppc_rmmu_info rmmu_info;
277 int i;
278
279 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
280 return NULL;
281 }
282 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
283 return NULL;
284 }
285 radix_page_info = g_malloc0(sizeof(*radix_page_info));
286 radix_page_info->count = 0;
287 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
288 if (rmmu_info.ap_encodings[i]) {
289 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
290 radix_page_info->count++;
291 }
292 }
293 return radix_page_info;
294}
295
b4db5413
SJS		 296target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
297 bool radix, bool gtse,
298 uint64_t proc_tbl)
299{
300 CPUState *cs = CPU(cpu);
301 int ret;
302 uint64_t flags = 0;
303 struct kvm_ppc_mmuv3_cfg cfg = {
304 .process_table = proc_tbl,
305 };
306
307 if (radix) {
308 flags |= KVM_PPC_MMUV3_RADIX;
309 }
310 if (gtse) {
311 flags |= KVM_PPC_MMUV3_GTSE;
312 }
313 cfg.flags = flags;
314 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
315 switch (ret) {
316 case 0:
317 return H_SUCCESS;
318 case -EINVAL:
319 return H_PARAMETER;
320 case -ENODEV:
321 return H_NOT_AVAILABLE;
322 default:
323 return H_HARDWARE;
324 }
325}
326
24c6863c
DG		 327bool kvmppc_hpt_needs_host_contiguous_pages(void)
328{
329 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
330 static struct kvm_ppc_smmu_info smmu_info;
331
332 if (!kvm_enabled()) {
333 return false;
334 }
335
71d0f1ea 336 kvm_get_smmu_info(cpu, &smmu_info, &error_fatal);
24c6863c
DG		 337 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
338}
339
e5ca28ec 340void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 341{
e5ca28ec 342 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 343 int iq, ik, jq, jk;
71d0f1ea 344 Error *local_err = NULL;
4656e1f0 345
e5ca28ec
DG		 346 /* For now, we only have anything to check on hash64 MMUs */
347 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 348 return;
349 }
350
71d0f1ea
GK		 351 kvm_get_smmu_info(cpu, &smmu_info, &local_err);
352 if (local_err) {
353 error_propagate(errp, local_err);
354 return;
355 }
4656e1f0 356
e5ca28ec
DG		 357 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
358 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
359 error_setg(errp,
360 "KVM does not support 1TiB segments which guest expects");
361 return;
df587133 362 }
4656e1f0 363
e5ca28ec
DG		 364 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
365 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
366 smmu_info.slb_size, cpu->hash64_opts->slb_size);
367 return;
90da0d5a
BH		 368 }
369
08215d8f 370 /*
e5ca28ec
DG		 371 * Verify that every pagesize supported by the cpu model is
372 * supported by KVM with the same encodings
08215d8f 373 */
e5ca28ec 374 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 375 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 376 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 377
e5ca28ec
DG		 378 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
379 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 380 break;
381 }
382 }
e5ca28ec
DG		 383 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
384 error_setg(errp, "KVM doesn't support for base page shift %u",
385 qsps->page_shift);
386 return;
387 }
388
389 ksps = &smmu_info.sps[ik];
390 if (ksps->slb_enc != qsps->slb_enc) {
391 error_setg(errp,
392"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
393 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
394 return;
395 }
396
397 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
398 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
399 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
400 break;
401 }
402 }
403
404 if (jk >= ARRAY_SIZE(ksps->enc)) {
405 error_setg(errp, "KVM doesn't support page shift %u/%u",
406 qsps->enc[jq].page_shift, qsps->page_shift);
407 return;
408 }
409 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
410 error_setg(errp,
411"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
412 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
413 qsps->page_shift, qsps->enc[jq].pte_enc);
414 return;
415 }
4656e1f0
BH		 416 }
417 }
4656e1f0 418
e5ca28ec
DG		 419 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
420 /* Mostly what guest pagesizes we can use are related to the
421 * host pages used to map guest RAM, which is handled in the
422 * platform code. Cache-Inhibited largepages (64k) however are
423 * used for I/O, so if they're mapped to the host at all it
424 * will be a normal mapping, not a special hugepage one used
425 * for RAM. */
426 if (getpagesize() < 0x10000) {
427 error_setg(errp,
428 "KVM can't supply 64kiB CI pages, which guest expects");
429 }
430 }
4656e1f0 431}
4656e1f0
BH		 432#endif /* !defined (TARGET_PPC64) */
433
b164e48e
EH		 434unsigned long kvm_arch_vcpu_id(CPUState *cpu)
435{
2e886fb3 436 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 437}
438
88365d17
BB		 439/* e500 supports 2 h/w breakpoint and 2 watchpoint.
440 * book3s supports only 1 watchpoint, so array size
441 * of 4 is sufficient for now.
442 */
443#define MAX_HW_BKPTS 4
444
445static struct HWBreakpoint {
446 target_ulong addr;
447 int type;
448} hw_debug_points[MAX_HW_BKPTS];
449
450static CPUWatchpoint hw_watchpoint;
451
452/* Default there is no breakpoint and watchpoint supported */
453static int max_hw_breakpoint;
454static int max_hw_watchpoint;
455static int nb_hw_breakpoint;
456static int nb_hw_watchpoint;
457
458static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
459{
460 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
461 max_hw_breakpoint = 2;
462 max_hw_watchpoint = 2;
463 }
464
465 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
466 fprintf(stderr, "Error initializing h/w breakpoints\n");
467 return;
468 }
469}
470
20d695a9 471int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 472{
20d695a9
AF		 473 PowerPCCPU *cpu = POWERPC_CPU(cs);
474 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 475 int ret;
476
4656e1f0 477 /* Synchronize sregs with kvm */
1bc22652 478 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 479 if (ret) {
388e47c7
TH		 480 if (ret == -EINVAL) {
481 error_report("Register sync failed... If you're using kvm-hv.ko,"
482 " only \"-cpu host\" is possible");
483 }
5666ca4a
SW		 484 return ret;
485 }
861bbc80 486
bc72ad67 487 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu);
c821c2bd 488
93dd5e85
SW		 489 switch (cenv->mmu_model) {
490 case POWERPC_MMU_BOOKE206:
7f516c96 491 /* This target supports access to KVM's guest TLB */
1bc22652 492 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 493 break;
7f516c96
TH		 494 case POWERPC_MMU_2_07:
495 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
496 /* KVM-HV has transactional memory on POWER8 also without the
f3d9f303
SB		 497 * KVM_CAP_PPC_HTM extension, so enable it here instead as
498 * long as it's availble to userspace on the host. */
499 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
500 cap_htm = true;
501 }
7f516c96
TH		 502 }
503 break;
93dd5e85
SW		 504 default:
505 break;
506 }
507
3c902d44 508 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 509 kvmppc_hw_debug_points_init(cenv);
3c902d44 510
861bbc80 511 return ret;
d76d1650
AJ		 512}
513
1bc22652 514static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 515{
1bc22652
AF		 516 CPUPPCState *env = &cpu->env;
517 CPUState *cs = CPU(cpu);
93dd5e85
SW		 518 struct kvm_dirty_tlb dirty_tlb;
519 unsigned char *bitmap;
520 int ret;
521
522 if (!env->kvm_sw_tlb) {
523 return;
524 }
525
526 bitmap = g_malloc((env->nb_tlb + 7) / 8);
527 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
528
529 dirty_tlb.bitmap = (uintptr_t)bitmap;
530 dirty_tlb.num_dirty = env->nb_tlb;
531
1bc22652 532 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 533 if (ret) {
534 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
535 __func__, strerror(-ret));
536 }
537
538 g_free(bitmap);
539}
540
d67d40ea
DG		 541static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
542{
543 PowerPCCPU *cpu = POWERPC_CPU(cs);
544 CPUPPCState *env = &cpu->env;
545 union {
546 uint32_t u32;
547 uint64_t u64;
548 } val;
549 struct kvm_one_reg reg = {
550 .id = id,
551 .addr = (uintptr_t) &val,
552 };
553 int ret;
554
555 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
556 if (ret != 0) {
b36f100e 557 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 558 } else {
559 switch (id & KVM_REG_SIZE_MASK) {
560 case KVM_REG_SIZE_U32:
561 env->spr[spr] = val.u32;
562 break;
563
564 case KVM_REG_SIZE_U64:
565 env->spr[spr] = val.u64;
566 break;
567
568 default:
569 /* Don't handle this size yet */
570 abort();
571 }
572 }
573}
574
575static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
576{
577 PowerPCCPU *cpu = POWERPC_CPU(cs);
578 CPUPPCState *env = &cpu->env;
579 union {
580 uint32_t u32;
581 uint64_t u64;
582 } val;
583 struct kvm_one_reg reg = {
584 .id = id,
585 .addr = (uintptr_t) &val,
586 };
587 int ret;
588
589 switch (id & KVM_REG_SIZE_MASK) {
590 case KVM_REG_SIZE_U32:
591 val.u32 = env->spr[spr];
592 break;
593
594 case KVM_REG_SIZE_U64:
595 val.u64 = env->spr[spr];
596 break;
597
598 default:
599 /* Don't handle this size yet */
600 abort();
601 }
602
603 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
604 if (ret != 0) {
b36f100e 605 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 606 }
607}
608
70b79849
DG		 609static int kvm_put_fp(CPUState *cs)
610{
611 PowerPCCPU *cpu = POWERPC_CPU(cs);
612 CPUPPCState *env = &cpu->env;
613 struct kvm_one_reg reg;
614 int i;
615 int ret;
616
617 if (env->insns_flags & PPC_FLOAT) {
618 uint64_t fpscr = env->fpscr;
619 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
620
621 reg.id = KVM_REG_PPC_FPSCR;
622 reg.addr = (uintptr_t)&fpscr;
623 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
624 if (ret < 0) {
da56ff91 625 DPRINTF("Unable to set FPSCR to KVM: %s\n", strerror(errno));
70b79849
DG		 626 return ret;
627 }
628
629 for (i = 0; i < 32; i++) {
630 uint64_t vsr[2];
631
3a4b791b 632#ifdef HOST_WORDS_BIGENDIAN
70b79849
DG		 633 vsr[0] = float64_val(env->fpr[i]);
634 vsr[1] = env->vsr[i];
3a4b791b
GK		 635#else
636 vsr[0] = env->vsr[i];
637 vsr[1] = float64_val(env->fpr[i]);
638#endif
70b79849
DG		 639 reg.addr = (uintptr_t) &vsr;
640 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
641
642 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
643 if (ret < 0) {
da56ff91 644 DPRINTF("Unable to set %s%d to KVM: %s\n", vsx ? "VSR" : "FPR",
70b79849
DG		 645 i, strerror(errno));
646 return ret;
647 }
648 }
649 }
650
651 if (env->insns_flags & PPC_ALTIVEC) {
652 reg.id = KVM_REG_PPC_VSCR;
653 reg.addr = (uintptr_t)&env->vscr;
654 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
655 if (ret < 0) {
da56ff91 656 DPRINTF("Unable to set VSCR to KVM: %s\n", strerror(errno));
70b79849
DG		 657 return ret;
658 }
659
660 for (i = 0; i < 32; i++) {
661 reg.id = KVM_REG_PPC_VR(i);
662 reg.addr = (uintptr_t)&env->avr[i];
663 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
664 if (ret < 0) {
da56ff91 665 DPRINTF("Unable to set VR%d to KVM: %s\n", i, strerror(errno));
70b79849
DG		 666 return ret;
667 }
668 }
669 }
670
671 return 0;
672}
673
674static int kvm_get_fp(CPUState *cs)
675{
676 PowerPCCPU *cpu = POWERPC_CPU(cs);
677 CPUPPCState *env = &cpu->env;
678 struct kvm_one_reg reg;
679 int i;
680 int ret;
681
682 if (env->insns_flags & PPC_FLOAT) {
683 uint64_t fpscr;
684 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
685
686 reg.id = KVM_REG_PPC_FPSCR;
687 reg.addr = (uintptr_t)&fpscr;
688 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
689 if (ret < 0) {
da56ff91 690 DPRINTF("Unable to get FPSCR from KVM: %s\n", strerror(errno));
70b79849
DG		 691 return ret;
692 } else {
693 env->fpscr = fpscr;
694 }
695
696 for (i = 0; i < 32; i++) {
697 uint64_t vsr[2];
698
699 reg.addr = (uintptr_t) &vsr;
700 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
701
702 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
703 if (ret < 0) {
da56ff91 704 DPRINTF("Unable to get %s%d from KVM: %s\n",
70b79849
DG		 705 vsx ? "VSR" : "FPR", i, strerror(errno));
706 return ret;
707 } else {
3a4b791b 708#ifdef HOST_WORDS_BIGENDIAN
70b79849
DG		 709 env->fpr[i] = vsr[0];
710 if (vsx) {
711 env->vsr[i] = vsr[1];
712 }
3a4b791b
GK		 713#else
714 env->fpr[i] = vsr[1];
715 if (vsx) {
716 env->vsr[i] = vsr[0];
717 }
718#endif
70b79849
DG		 719 }
720 }
721 }
722
723 if (env->insns_flags & PPC_ALTIVEC) {
724 reg.id = KVM_REG_PPC_VSCR;
725 reg.addr = (uintptr_t)&env->vscr;
726 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
727 if (ret < 0) {
da56ff91 728 DPRINTF("Unable to get VSCR from KVM: %s\n", strerror(errno));
70b79849
DG		 729 return ret;
730 }
731
732 for (i = 0; i < 32; i++) {
733 reg.id = KVM_REG_PPC_VR(i);
734 reg.addr = (uintptr_t)&env->avr[i];
735 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
736 if (ret < 0) {
da56ff91 737 DPRINTF("Unable to get VR%d from KVM: %s\n",
70b79849
DG		 738 i, strerror(errno));
739 return ret;
740 }
741 }
742 }
743
744 return 0;
745}
746
9b00ea49
DG		 747#if defined(TARGET_PPC64)
748static int kvm_get_vpa(CPUState *cs)
749{
750 PowerPCCPU *cpu = POWERPC_CPU(cs);
7388efaf 751 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 752 struct kvm_one_reg reg;
753 int ret;
754
755 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 756 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 757 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
758 if (ret < 0) {
da56ff91 759 DPRINTF("Unable to get VPA address from KVM: %s\n", strerror(errno));
9b00ea49
DG		 760 return ret;
761 }
762
7388efaf
DG		 763 assert((uintptr_t)&spapr_cpu->slb_shadow_size
764 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 765 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 766 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 767 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
768 if (ret < 0) {
da56ff91 769 DPRINTF("Unable to get SLB shadow state from KVM: %s\n",
9b00ea49
DG		 770 strerror(errno));
771 return ret;
772 }
773
7388efaf
DG		 774 assert((uintptr_t)&spapr_cpu->dtl_size
775 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 776 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 777 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 778 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
779 if (ret < 0) {
da56ff91 780 DPRINTF("Unable to get dispatch trace log state from KVM: %s\n",
9b00ea49
DG		 781 strerror(errno));
782 return ret;
783 }
784
785 return 0;
786}
787
788static int kvm_put_vpa(CPUState *cs)
789{
790 PowerPCCPU *cpu = POWERPC_CPU(cs);
7388efaf 791 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 792 struct kvm_one_reg reg;
793 int ret;
794
795 /* SLB shadow or DTL can't be registered unless a master VPA is
796 * registered. That means when restoring state, if a VPA *is*
797 * registered, we need to set that up first. If not, we need to
798 * deregister the others before deregistering the master VPA */
7388efaf
DG		 799 assert(spapr_cpu->vpa_addr
800 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 801
7388efaf 802 if (spapr_cpu->vpa_addr) {
9b00ea49 803 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 804 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 805 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
806 if (ret < 0) {
da56ff91 807 DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
9b00ea49
DG		 808 return ret;
809 }
810 }
811
7388efaf
DG		 812 assert((uintptr_t)&spapr_cpu->slb_shadow_size
813 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 814 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 815 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 816 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
817 if (ret < 0) {
da56ff91 818 DPRINTF("Unable to set SLB shadow state to KVM: %s\n", strerror(errno));
9b00ea49
DG		 819 return ret;
820 }
821
7388efaf
DG		 822 assert((uintptr_t)&spapr_cpu->dtl_size
823 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 824 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 825 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 826 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
827 if (ret < 0) {
da56ff91 828 DPRINTF("Unable to set dispatch trace log state to KVM: %s\n",
9b00ea49
DG		 829 strerror(errno));
830 return ret;
831 }
832
7388efaf 833 if (!spapr_cpu->vpa_addr) {
9b00ea49 834 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 835 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 836 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
837 if (ret < 0) {
da56ff91 838 DPRINTF("Unable to set VPA address to KVM: %s\n", strerror(errno));
9b00ea49
DG		 839 return ret;
840 }
841 }
842
843 return 0;
844}
845#endif /* TARGET_PPC64 */
846
e5c0d3ce 847int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 848{
849 CPUPPCState *env = &cpu->env;
850 struct kvm_sregs sregs;
851 int i;
852
853 sregs.pvr = env->spr[SPR_PVR];
854
1ec26c75
GK		 855 if (cpu->vhyp) {
856 PPCVirtualHypervisorClass *vhc =
857 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
858 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
859 } else {
860 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
861 }
a7a00a72
DG		 862
863 /* Sync SLB */
864#ifdef TARGET_PPC64
865 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
866 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
867 if (env->slb[i].esid & SLB_ESID_V) {
868 sregs.u.s.ppc64.slb[i].slbe |= i;
869 }
870 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
871 }
872#endif
873
874 /* Sync SRs */
875 for (i = 0; i < 16; i++) {
876 sregs.u.s.ppc32.sr[i] = env->sr[i];
877 }
878
879 /* Sync BATs */
880 for (i = 0; i < 8; i++) {
881 /* Beware. We have to swap upper and lower bits here */
882 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
883 | env->DBAT[1][i];
884 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
885 | env->IBAT[1][i];
886 }
887
888 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
889}
890
20d695a9 891int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 892{
20d695a9
AF		 893 PowerPCCPU *cpu = POWERPC_CPU(cs);
894 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 895 struct kvm_regs regs;
896 int ret;
897 int i;
898
1bc22652
AF		 899 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
900 if (ret < 0) {
d76d1650 901 return ret;
1bc22652 902 }
d76d1650
AJ		 903
904 regs.ctr = env->ctr;
905 regs.lr = env->lr;
da91a00f 906 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 907 regs.msr = env->msr;
908 regs.pc = env->nip;
909
910 regs.srr0 = env->spr[SPR_SRR0];
911 regs.srr1 = env->spr[SPR_SRR1];
912
913 regs.sprg0 = env->spr[SPR_SPRG0];
914 regs.sprg1 = env->spr[SPR_SPRG1];
915 regs.sprg2 = env->spr[SPR_SPRG2];
916 regs.sprg3 = env->spr[SPR_SPRG3];
917 regs.sprg4 = env->spr[SPR_SPRG4];
918 regs.sprg5 = env->spr[SPR_SPRG5];
919 regs.sprg6 = env->spr[SPR_SPRG6];
920 regs.sprg7 = env->spr[SPR_SPRG7];
921
90dc8812
SW		 922 regs.pid = env->spr[SPR_BOOKE_PID];
923
d76d1650
AJ		 924 for (i = 0;i < 32; i++)
925 regs.gpr[i] = env->gpr[i];
926
4bddaf55
AK		 927 regs.cr = 0;
928 for (i = 0; i < 8; i++) {
929 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
930 }
931
1bc22652 932 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
d76d1650
AJ		 933 if (ret < 0)
934 return ret;
935
70b79849
DG		 936 kvm_put_fp(cs);
937
93dd5e85 938 if (env->tlb_dirty) {
1bc22652 939 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 940 env->tlb_dirty = false;
941 }
942
f1af19d7 943 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 944 ret = kvmppc_put_books_sregs(cpu);
945 if (ret < 0) {
f1af19d7
DG		 946 return ret;
947 }
948 }
949
950 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 951 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
952 }
f1af19d7 953
d67d40ea
DG		 954 if (cap_one_reg) {
955 int i;
956
957 /* We deliberately ignore errors here, for kernels which have
958 * the ONE_REG calls, but don't support the specific
959 * registers, there's a reasonable chance things will still
960 * work, at least until we try to migrate. */
961 for (i = 0; i < 1024; i++) {
962 uint64_t id = env->spr_cb[i].one_reg_id;
963
964 if (id != 0) {
965 kvm_put_one_spr(cs, id, i);
966 }
f1af19d7 967 }
9b00ea49
DG		 968
969#ifdef TARGET_PPC64
80b3f79b
AK		 970 if (msr_ts) {
971 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
972 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
973 }
974 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
975 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
976 }
977 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
978 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
979 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
980 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
981 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
983 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
987 }
988
9b00ea49
DG		 989 if (cap_papr) {
990 if (kvm_put_vpa(cs) < 0) {
da56ff91 991 DPRINTF("Warning: Unable to set VPA information to KVM\n");
9b00ea49
DG		 992 }
993 }
98a8b524
AK		 994
995 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 996#endif /* TARGET_PPC64 */
f1af19d7
DG		 997 }
998
d76d1650
AJ		 999 return ret;
1000}
1001
c371c2e3
BB		 1002static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1003{
1004 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1005}
1006
a7a00a72
DG		 1007static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1008{
1009 CPUPPCState *env = &cpu->env;
1010 struct kvm_sregs sregs;
1011 int ret;
1012
1013 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1014 if (ret < 0) {
1015 return ret;
1016 }
1017
1018 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1019 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1020 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1021 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1022 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1023 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1024 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1025 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1026 env->spr[SPR_DECR] = sregs.u.e.dec;
1027 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1028 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1029 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1030 }
1031
1032 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1033 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1034 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1035 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1036 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1037 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1038 }
1039
1040 if (sregs.u.e.features & KVM_SREGS_E_64) {
1041 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1042 }
1043
1044 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1045 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1046 }
1047
1048 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1049 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1050 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1051 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1052 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1053 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1054 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1055 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1056 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1057 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1058 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1059 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1060 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1061 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1062 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1063 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1064 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1065 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1066 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1067 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1068 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1069 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1070 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1071 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1072 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1073 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1074 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1075 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1076 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1077 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1078 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1079 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1080 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1081
1082 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1083 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1084 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1085 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1086 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1087 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1088 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1089 }
1090
1091 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1092 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1093 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1094 }
1095
1096 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1097 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1098 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1099 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1100 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1101 }
1102 }
1103
1104 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1105 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1106 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1107 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1108 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1109 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1110 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1111 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1112 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1113 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1114 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1115 }
1116
1117 if (sregs.u.e.features & KVM_SREGS_EXP) {
1118 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1119 }
1120
1121 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1122 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1123 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1124 }
1125
1126 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1127 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1128 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1129 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1130
1131 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1132 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1133 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1134 }
1135 }
1136
1137 return 0;
1138}
1139
1140static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1141{
1142 CPUPPCState *env = &cpu->env;
1143 struct kvm_sregs sregs;
1144 int ret;
1145 int i;
1146
1147 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1148 if (ret < 0) {
1149 return ret;
1150 }
1151
e57ca75c 1152 if (!cpu->vhyp) {
a7a00a72
DG		 1153 ppc_store_sdr1(env, sregs.u.s.sdr1);
1154 }
1155
1156 /* Sync SLB */
1157#ifdef TARGET_PPC64
1158 /*
1159 * The packed SLB array we get from KVM_GET_SREGS only contains
1160 * information about valid entries. So we flush our internal copy
1161 * to get rid of stale ones, then put all valid SLB entries back
1162 * in.
1163 */
1164 memset(env->slb, 0, sizeof(env->slb));
1165 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1166 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1167 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1168 /*
1169 * Only restore valid entries
1170 */
1171 if (rb & SLB_ESID_V) {
1172 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1173 }
1174 }
1175#endif
1176
1177 /* Sync SRs */
1178 for (i = 0; i < 16; i++) {
1179 env->sr[i] = sregs.u.s.ppc32.sr[i];
1180 }
1181
1182 /* Sync BATs */
1183 for (i = 0; i < 8; i++) {
1184 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1185 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1186 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1187 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1188 }
1189
1190 return 0;
1191}
1192
20d695a9 1193int kvm_arch_get_registers(CPUState *cs)
d76d1650 1194{
20d695a9
AF		 1195 PowerPCCPU *cpu = POWERPC_CPU(cs);
1196 CPUPPCState *env = &cpu->env;
d76d1650 1197 struct kvm_regs regs;
90dc8812 1198 uint32_t cr;
138b38b6 1199 int i, ret;
d76d1650 1200
1bc22652 1201 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
d76d1650
AJ		 1202 if (ret < 0)
1203 return ret;
1204
90dc8812
SW		 1205 cr = regs.cr;
1206 for (i = 7; i >= 0; i--) {
1207 env->crf[i] = cr & 15;
1208 cr >>= 4;
1209 }
ba5e5090 1210
d76d1650
AJ		 1211 env->ctr = regs.ctr;
1212 env->lr = regs.lr;
da91a00f 1213 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1214 env->msr = regs.msr;
1215 env->nip = regs.pc;
1216
1217 env->spr[SPR_SRR0] = regs.srr0;
1218 env->spr[SPR_SRR1] = regs.srr1;
1219
1220 env->spr[SPR_SPRG0] = regs.sprg0;
1221 env->spr[SPR_SPRG1] = regs.sprg1;
1222 env->spr[SPR_SPRG2] = regs.sprg2;
1223 env->spr[SPR_SPRG3] = regs.sprg3;
1224 env->spr[SPR_SPRG4] = regs.sprg4;
1225 env->spr[SPR_SPRG5] = regs.sprg5;
1226 env->spr[SPR_SPRG6] = regs.sprg6;
1227 env->spr[SPR_SPRG7] = regs.sprg7;
1228
90dc8812
SW		 1229 env->spr[SPR_BOOKE_PID] = regs.pid;
1230
d76d1650
AJ		 1231 for (i = 0;i < 32; i++)
1232 env->gpr[i] = regs.gpr[i];
1233
70b79849
DG		 1234 kvm_get_fp(cs);
1235
90dc8812 1236 if (cap_booke_sregs) {
a7a00a72 1237 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1238 if (ret < 0) {
1239 return ret;
1240 }
fafc0b6a 1241 }
90dc8812 1242
90dc8812 1243 if (cap_segstate) {
a7a00a72 1244 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1245 if (ret < 0) {
1246 return ret;
1247 }
fafc0b6a 1248 }
ba5e5090 1249
d67d40ea
DG		 1250 if (cap_hior) {
1251 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1252 }
1253
1254 if (cap_one_reg) {
1255 int i;
1256
1257 /* We deliberately ignore errors here, for kernels which have
1258 * the ONE_REG calls, but don't support the specific
1259 * registers, there's a reasonable chance things will still
1260 * work, at least until we try to migrate. */
1261 for (i = 0; i < 1024; i++) {
1262 uint64_t id = env->spr_cb[i].one_reg_id;
1263
1264 if (id != 0) {
1265 kvm_get_one_spr(cs, id, i);
1266 }
1267 }
9b00ea49
DG		 1268
1269#ifdef TARGET_PPC64
80b3f79b
AK		 1270 if (msr_ts) {
1271 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1272 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1273 }
1274 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1275 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1276 }
1277 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1278 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1279 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1280 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1281 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1282 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1283 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1284 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1285 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1286 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1287 }
1288
9b00ea49
DG		 1289 if (cap_papr) {
1290 if (kvm_get_vpa(cs) < 0) {
da56ff91 1291 DPRINTF("Warning: Unable to get VPA information from KVM\n");
9b00ea49
DG		 1292 }
1293 }
98a8b524
AK		 1294
1295 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
9b00ea49 1296#endif
d67d40ea
DG		 1297 }
1298
d76d1650
AJ		 1299 return 0;
1300}
1301
1bc22652 1302int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1303{
1304 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1305
1306 if (irq != PPC_INTERRUPT_EXT) {
1307 return 0;
1308 }
1309
1310 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
1311 return 0;
1312 }
1313
1bc22652 1314 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1315
1316 return 0;
1317}
1318
16415335
AG		 1319#if defined(TARGET_PPCEMB)
1320#define PPC_INPUT_INT PPC40x_INPUT_INT
1321#elif defined(TARGET_PPC64)
1322#define PPC_INPUT_INT PPC970_INPUT_INT
1323#else
1324#define PPC_INPUT_INT PPC6xx_INPUT_INT
1325#endif
1326
20d695a9 1327void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1328{
20d695a9
AF		 1329 PowerPCCPU *cpu = POWERPC_CPU(cs);
1330 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 1331 int r;
1332 unsigned irq;
1333
4b8523ee
JK		 1334 qemu_mutex_lock_iothread();
1335
5cbdb3a3 1336 /* PowerPC QEMU tracks the various core input pins (interrupt, critical
d76d1650 1337 * interrupt, reset, etc) in PPC-specific env->irq_input_state. */
fc87e185
AG		 1338 if (!cap_interrupt_level &&
1339 run->ready_for_interrupt_injection &&
259186a7 1340 (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
16415335 1341 (env->irq_input_state & (1<<PPC_INPUT_INT)))
d76d1650
AJ		 1342 {
1343 /* For now KVM disregards the 'irq' argument. However, in the
1344 * future KVM could cache it in-kernel to avoid a heavyweight exit
1345 * when reading the UIC.
1346 */
fc87e185 1347 irq = KVM_INTERRUPT_SET;
d76d1650 1348
da56ff91 1349 DPRINTF("injected interrupt %d\n", irq);
1bc22652 1350 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq);
55e5c285
AF		 1351 if (r < 0) {
1352 printf("cpu %d fail inject %x\n", cs->cpu_index, irq);
1353 }
c821c2bd
AG		 1354
1355 /* Always wake up soon in case the interrupt was level based */
bc72ad67 1356 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
73bcb24d 1357 (NANOSECONDS_PER_SECOND / 50));
d76d1650
AJ		 1358 }
1359
1360 /* We don't know if there are more interrupts pending after this. However,
1361 * the guest will return to userspace in the course of handling this one
1362 * anyways, so we will get a chance to deliver the rest. */
4b8523ee
JK		 1363
1364 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1365}
1366
4c663752 1367MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1368{
4c663752 1369 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1370}
1371
20d695a9 1372int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1373{
259186a7 1374 return cs->halted;
0af691d7
MT		 1375}
1376
259186a7 1377static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1378{
259186a7
AF		 1379 CPUState *cs = CPU(cpu);
1380 CPUPPCState *env = &cpu->env;
1381
1382 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1383 cs->halted = 1;
27103424 1384 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1385 }
1386
bb4ea393 1387 return 0;
d76d1650
AJ		 1388}
1389
1390/* map dcr access to existing qemu dcr emulation */
1328c2bf 1391static int kvmppc_handle_dcr_read(CPUPPCState *env, uint32_t dcrn, uint32_t *data)
d76d1650
AJ		 1392{
1393 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0)
1394 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1395
bb4ea393 1396 return 0;
d76d1650
AJ		 1397}
1398
1328c2bf 1399static int kvmppc_handle_dcr_write(CPUPPCState *env, uint32_t dcrn, uint32_t data)
d76d1650
AJ		 1400{
1401 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0)
1402 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1403
bb4ea393 1404 return 0;
d76d1650
AJ		 1405}
1406
8a0548f9
BB		 1407int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1408{
1409 /* Mixed endian case is not handled */
1410 uint32_t sc = debug_inst_opcode;
1411
1412 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1413 sizeof(sc), 0) ||
1414 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1415 return -EINVAL;
1416 }
1417
1418 return 0;
1419}
1420
1421int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1422{
1423 uint32_t sc;
1424
1425 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1426 sc != debug_inst_opcode ||
1427 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1428 sizeof(sc), 1)) {
1429 return -EINVAL;
1430 }
1431
1432 return 0;
1433}
1434
88365d17
BB		 1435static int find_hw_breakpoint(target_ulong addr, int type)
1436{
1437 int n;
1438
1439 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1440 <= ARRAY_SIZE(hw_debug_points));
1441
1442 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1443 if (hw_debug_points[n].addr == addr &&
1444 hw_debug_points[n].type == type) {
1445 return n;
1446 }
1447 }
1448
1449 return -1;
1450}
1451
1452static int find_hw_watchpoint(target_ulong addr, int *flag)
1453{
1454 int n;
1455
1456 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1457 if (n >= 0) {
1458 *flag = BP_MEM_ACCESS;
1459 return n;
1460 }
1461
1462 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1463 if (n >= 0) {
1464 *flag = BP_MEM_WRITE;
1465 return n;
1466 }
1467
1468 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1469 if (n >= 0) {
1470 *flag = BP_MEM_READ;
1471 return n;
1472 }
1473
1474 return -1;
1475}
1476
1477int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1478 target_ulong len, int type)
1479{
1480 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1481 return -ENOBUFS;
1482 }
1483
1484 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1485 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1486
1487 switch (type) {
1488 case GDB_BREAKPOINT_HW:
1489 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1490 return -ENOBUFS;
1491 }
1492
1493 if (find_hw_breakpoint(addr, type) >= 0) {
1494 return -EEXIST;
1495 }
1496
1497 nb_hw_breakpoint++;
1498 break;
1499
1500 case GDB_WATCHPOINT_WRITE:
1501 case GDB_WATCHPOINT_READ:
1502 case GDB_WATCHPOINT_ACCESS:
1503 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1504 return -ENOBUFS;
1505 }
1506
1507 if (find_hw_breakpoint(addr, type) >= 0) {
1508 return -EEXIST;
1509 }
1510
1511 nb_hw_watchpoint++;
1512 break;
1513
1514 default:
1515 return -ENOSYS;
1516 }
1517
1518 return 0;
1519}
1520
1521int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1522 target_ulong len, int type)
1523{
1524 int n;
1525
1526 n = find_hw_breakpoint(addr, type);
1527 if (n < 0) {
1528 return -ENOENT;
1529 }
1530
1531 switch (type) {
1532 case GDB_BREAKPOINT_HW:
1533 nb_hw_breakpoint--;
1534 break;
1535
1536 case GDB_WATCHPOINT_WRITE:
1537 case GDB_WATCHPOINT_READ:
1538 case GDB_WATCHPOINT_ACCESS:
1539 nb_hw_watchpoint--;
1540 break;
1541
1542 default:
1543 return -ENOSYS;
1544 }
1545 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1546
1547 return 0;
1548}
1549
1550void kvm_arch_remove_all_hw_breakpoints(void)
1551{
1552 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1553}
1554
8a0548f9
BB		 1555void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1556{
88365d17
BB		 1557 int n;
1558
8a0548f9
BB		 1559 /* Software Breakpoint updates */
1560 if (kvm_sw_breakpoints_active(cs)) {
1561 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1562 }
88365d17
BB		 1563
1564 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1565 <= ARRAY_SIZE(hw_debug_points));
1566 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1567
1568 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1569 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1570 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1571 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1572 switch (hw_debug_points[n].type) {
1573 case GDB_BREAKPOINT_HW:
1574 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1575 break;
1576 case GDB_WATCHPOINT_WRITE:
1577 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1578 break;
1579 case GDB_WATCHPOINT_READ:
1580 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1581 break;
1582 case GDB_WATCHPOINT_ACCESS:
1583 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1584 KVMPPC_DEBUG_WATCH_READ;
1585 break;
1586 default:
1587 cpu_abort(cs, "Unsupported breakpoint type\n");
1588 }
1589 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1590 }
1591 }
8a0548f9
BB		 1592}
1593
1594static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1595{
1596 CPUState *cs = CPU(cpu);
1597 CPUPPCState *env = &cpu->env;
1598 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1599 int handle = 0;
88365d17
BB		 1600 int n;
1601 int flag = 0;
8a0548f9 1602
88365d17
BB		 1603 if (cs->singlestep_enabled) {
1604 handle = 1;
1605 } else if (arch_info->status) {
1606 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1607 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1608 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1609 if (n >= 0) {
1610 handle = 1;
1611 }
1612 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1613 KVMPPC_DEBUG_WATCH_WRITE)) {
1614 n = find_hw_watchpoint(arch_info->address, &flag);
1615 if (n >= 0) {
1616 handle = 1;
1617 cs->watchpoint_hit = &hw_watchpoint;
1618 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1619 hw_watchpoint.flags = flag;
1620 }
1621 }
1622 }
1623 } else if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
8a0548f9
BB		 1624 handle = 1;
1625 } else {
1626 /* QEMU is not able to handle debug exception, so inject
1627 * program exception to guest;
1628 * Yes program exception NOT debug exception !!
88365d17
BB		 1629 * When QEMU is using debug resources then debug exception must
1630 * be always set. To achieve this we set MSR_DE and also set
1631 * MSRP_DEP so guest cannot change MSR_DE.
1632 * When emulating debug resource for guest we want guest
1633 * to control MSR_DE (enable/disable debug interrupt on need).
1634 * Supporting both configurations are NOT possible.
1635 * So the result is that we cannot share debug resources
1636 * between QEMU and Guest on BOOKE architecture.
1637 * In the current design QEMU gets the priority over guest,
1638 * this means that if QEMU is using debug resources then guest
1639 * cannot use them;
8a0548f9
BB		 1640 * For software breakpoint QEMU uses a privileged instruction;
1641 * So there cannot be any reason that we are here for guest
1642 * set debug exception, only possibility is guest executed a
1643 * privileged / illegal instruction and that's why we are
1644 * injecting a program interrupt.
1645 */
1646
1647 cpu_synchronize_state(cs);
1648 /* env->nip is PC, so increment this by 4 to use
1649 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1650 */
1651 env->nip += 4;
1652 cs->exception_index = POWERPC_EXCP_PROGRAM;
1653 env->error_code = POWERPC_EXCP_INVAL;
1654 ppc_cpu_do_interrupt(cs);
1655 }
1656
1657 return handle;
1658}
1659
20d695a9 1660int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1661{
20d695a9
AF		 1662 PowerPCCPU *cpu = POWERPC_CPU(cs);
1663 CPUPPCState *env = &cpu->env;
bb4ea393 1664 int ret;
d76d1650 1665
4b8523ee
JK		 1666 qemu_mutex_lock_iothread();
1667
d76d1650
AJ		 1668 switch (run->exit_reason) {
1669 case KVM_EXIT_DCR:
1670 if (run->dcr.is_write) {
da56ff91 1671 DPRINTF("handle dcr write\n");
d76d1650
AJ		 1672 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1673 } else {
da56ff91 1674 DPRINTF("handle dcr read\n");
d76d1650
AJ		 1675 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1676 }
1677 break;
1678 case KVM_EXIT_HLT:
da56ff91 1679 DPRINTF("handle halt\n");
259186a7 1680 ret = kvmppc_handle_halt(cpu);
d76d1650 1681 break;
c6304a4a 1682#if defined(TARGET_PPC64)
f61b4bed 1683 case KVM_EXIT_PAPR_HCALL:
da56ff91 1684 DPRINTF("handle PAPR hypercall\n");
20d695a9 1685 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1686 run->papr_hcall.nr,
f61b4bed 1687 run->papr_hcall.args);
78e8fde2 1688 ret = 0;
f61b4bed
AG		 1689 break;
1690#endif
5b95b8b9 1691 case KVM_EXIT_EPR:
da56ff91 1692 DPRINTF("handle epr\n");
933b19ea 1693 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1694 ret = 0;
1695 break;
31f2cb8f 1696 case KVM_EXIT_WATCHDOG:
da56ff91 1697 DPRINTF("handle watchdog expiry\n");
31f2cb8f
BB		 1698 watchdog_perform_action();
1699 ret = 0;
1700 break;
1701
8a0548f9
BB		 1702 case KVM_EXIT_DEBUG:
1703 DPRINTF("handle debug exception\n");
1704 if (kvm_handle_debug(cpu, run)) {
1705 ret = EXCP_DEBUG;
1706 break;
1707 }
1708 /* re-enter, this exception was guest-internal */
1709 ret = 0;
1710 break;
1711
73aaec4a
JK		 1712 default:
1713 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1714 ret = -1;
1715 break;
d76d1650
AJ		 1716 }
1717
4b8523ee 1718 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1719 return ret;
1720}
1721
31f2cb8f
BB		 1722int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1723{
1724 CPUState *cs = CPU(cpu);
1725 uint32_t bits = tsr_bits;
1726 struct kvm_one_reg reg = {
1727 .id = KVM_REG_PPC_OR_TSR,
1728 .addr = (uintptr_t) &bits,
1729 };
1730
1731 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1732}
1733
1734int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1735{
1736
1737 CPUState *cs = CPU(cpu);
1738 uint32_t bits = tsr_bits;
1739 struct kvm_one_reg reg = {
1740 .id = KVM_REG_PPC_CLEAR_TSR,
1741 .addr = (uintptr_t) &bits,
1742 };
1743
1744 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1745}
1746
1747int kvmppc_set_tcr(PowerPCCPU *cpu)
1748{
1749 CPUState *cs = CPU(cpu);
1750 CPUPPCState *env = &cpu->env;
1751 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1752
1753 struct kvm_one_reg reg = {
1754 .id = KVM_REG_PPC_TCR,
1755 .addr = (uintptr_t) &tcr,
1756 };
1757
1758 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1759}
1760
1761int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1762{
1763 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1764 int ret;
1765
1766 if (!kvm_enabled()) {
1767 return -1;
1768 }
1769
1770 if (!cap_ppc_watchdog) {
1771 printf("warning: KVM does not support watchdog");
1772 return -1;
1773 }
1774
48add816 1775 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1776 if (ret < 0) {
1777 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1778 __func__, strerror(-ret));
1779 return ret;
1780 }
1781
1782 return ret;
1783}
1784
dc333cd6
AG		 1785static int read_cpuinfo(const char *field, char *value, int len)
1786{
1787 FILE *f;
1788 int ret = -1;
1789 int field_len = strlen(field);
1790 char line[512];
1791
1792 f = fopen("/proc/cpuinfo", "r");
1793 if (!f) {
1794 return -1;
1795 }
1796
1797 do {
ef951443 1798 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1799 break;
1800 }
1801 if (!strncmp(line, field, field_len)) {
ae215068 1802 pstrcpy(value, len, line);
dc333cd6
AG		 1803 ret = 0;
1804 break;
1805 }
1806 } while(*line);
1807
1808 fclose(f);
1809
1810 return ret;
1811}
1812
1813uint32_t kvmppc_get_tbfreq(void)
1814{
1815 char line[512];
1816 char *ns;
73bcb24d 1817 uint32_t retval = NANOSECONDS_PER_SECOND;
dc333cd6
AG		 1818
1819 if (read_cpuinfo("timebase", line, sizeof(line))) {
1820 return retval;
1821 }
1822
1823 if (!(ns = strchr(line, ':'))) {
1824 return retval;
1825 }
1826
1827 ns++;
1828
f9b8e7f6 1829 return atoi(ns);
dc333cd6 1830}
4513d923 1831
ef951443
ND		 1832bool kvmppc_get_host_serial(char **value)
1833{
1834 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1835 NULL);
1836}
1837
1838bool kvmppc_get_host_model(char **value)
1839{
1840 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1841}
1842
eadaada1
AG		 1843/* Try to find a device tree node for a CPU with clock-frequency property */
1844static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1845{
1846 struct dirent *dirp;
1847 DIR *dp;
1848
1849 if ((dp = opendir(PROC_DEVTREE_CPU)) == NULL) {
1850 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1851 return -1;
1852 }
1853
1854 buf[0] = '\0';
1855 while ((dirp = readdir(dp)) != NULL) {
1856 FILE *f;
1857 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1858 dirp->d_name);
1859 f = fopen(buf, "r");
1860 if (f) {
1861 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1862 fclose(f);
1863 break;
1864 }
1865 buf[0] = '\0';
1866 }
1867 closedir(dp);
1868 if (buf[0] == '\0') {
1869 printf("Unknown host!\n");
1870 return -1;
1871 }
1872
1873 return 0;
1874}
1875
7d94a30b 1876static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1877{
9bc884b7
DG		 1878 union {
1879 uint32_t v32;
1880 uint64_t v64;
1881 } u;
eadaada1
AG		 1882 FILE *f;
1883 int len;
1884
7d94a30b 1885 f = fopen(filename, "rb");
eadaada1
AG		 1886 if (!f) {
1887 return -1;
1888 }
1889
9bc884b7 1890 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1891 fclose(f);
1892 switch (len) {
9bc884b7
DG		 1893 case 4:
1894 /* property is a 32-bit quantity */
1895 return be32_to_cpu(u.v32);
1896 case 8:
1897 return be64_to_cpu(u.v64);
eadaada1
AG		 1898 }
1899
1900 return 0;
1901}
1902
7d94a30b
SB		 1903/* Read a CPU node property from the host device tree that's a single
1904 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1905 * (can't find or open the property, or doesn't understand the
1906 * format) */
1907static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1908{
1909 char buf[PATH_MAX], *tmp;
1910 uint64_t val;
1911
1912 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1913 return -1;
1914 }
1915
1916 tmp = g_strdup_printf("%s/%s", buf, propname);
1917 val = kvmppc_read_int_dt(tmp);
1918 g_free(tmp);
1919
1920 return val;
1921}
1922
9bc884b7
DG		 1923uint64_t kvmppc_get_clockfreq(void)
1924{
1925 return kvmppc_read_int_cpu_dt("clock-frequency");
1926}
1927
1a61a9ae
SY		 1928static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
1929 {
1930 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1931 CPUState *cs = CPU(cpu);
1932
6fd33a75 1933 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1934 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1935 return 0;
1936 }
1937
1938 return 1;
1939}
1940
1941int kvmppc_get_hasidle(CPUPPCState *env)
1942{
1943 struct kvm_ppc_pvinfo pvinfo;
1944
1945 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1946 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1947 return 1;
1948 }
1949
1950 return 0;
1951}
1952
1328c2bf 1953int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09
AG		 1954{
1955 uint32_t *hc = (uint32_t*)buf;
45024f09
AG		 1956 struct kvm_ppc_pvinfo pvinfo;
1957
1a61a9ae 1958 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 1959 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 1960 return 0;
1961 }
45024f09
AG		 1962
1963 /*
d13fc32e 1964 * Fallback to always fail hypercalls regardless of endianness:
45024f09 1965 *
d13fc32e 1966 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 1967 * li r3, -1
d13fc32e
AG		 1968 * b .+8 (becomes nop in wrong endian)
1969 * bswap32(li r3, -1)
45024f09
AG		 1970 */
1971
d13fc32e
AG		 1972 hc[0] = cpu_to_be32(0x08000048);
1973 hc[1] = cpu_to_be32(0x3860ffff);
1974 hc[2] = cpu_to_be32(0x48000008);
1975 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 1976
0ddbd053 1977 return 1;
45024f09
AG		 1978}
1979
026bfd89
DG		 1980static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
1981{
1982 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
1983}
1984
1985void kvmppc_enable_logical_ci_hcalls(void)
1986{
1987 /*
1988 * FIXME: it would be nice if we could detect the cases where
1989 * we're using a device which requires the in kernel
1990 * implementation of these hcalls, but the kernel lacks them and
1991 * produce a warning.
1992 */
1993 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
1994 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
1995}
1996
ef9971dd
AK		 1997void kvmppc_enable_set_mode_hcall(void)
1998{
1999 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2000}
2001
5145ad4f
NW		 2002void kvmppc_enable_clear_ref_mod_hcalls(void)
2003{
2004 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2005 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2006}
2007
1bc22652 2008void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2009{
1bc22652 2010 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2011 int ret;
2012
da20aed1
DG		 2013 if (!kvm_enabled()) {
2014 return;
2015 }
2016
48add816 2017 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2018 if (ret) {
072ed5f2
TH		 2019 error_report("This vCPU type or KVM version does not support PAPR");
2020 exit(1);
94135e81 2021 }
9b00ea49
DG		 2022
2023 /* Update the capability flag so we sync the right information
2024 * with kvm */
2025 cap_papr = 1;
f61b4bed
AG		 2026}
2027
d6e166c0 2028int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2029{
d6e166c0 2030 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2031}
2032
5b95b8b9
AG		 2033void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2034{
5b95b8b9 2035 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2036 int ret;
2037
48add816 2038 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2039 if (ret && mpic_proxy) {
072ed5f2
TH		 2040 error_report("This KVM version does not support EPR");
2041 exit(1);
5b95b8b9
AG		 2042 }
2043}
2044
e97c3636
DG		 2045int kvmppc_smt_threads(void)
2046{
2047 return cap_ppc_smt ? cap_ppc_smt : 1;
2048}
2049
fa98fbfc
SB		 2050int kvmppc_set_smt_threads(int smt)
2051{
2052 int ret;
2053
2054 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2055 if (!ret) {
2056 cap_ppc_smt = smt;
2057 }
2058 return ret;
2059}
2060
2061void kvmppc_hint_smt_possible(Error **errp)
2062{
2063 int i;
2064 GString *g;
2065 char *s;
2066
2067 assert(kvm_enabled());
2068 if (cap_ppc_smt_possible) {
2069 g = g_string_new("Available VSMT modes:");
2070 for (i = 63; i >= 0; i--) {
2071 if ((1UL << i) & cap_ppc_smt_possible) {
2072 g_string_append_printf(g, " %lu", (1UL << i));
2073 }
2074 }
2075 s = g_string_free(g, false);
2076 error_append_hint(errp, "%s.\n", s);
2077 g_free(s);
2078 } else {
2079 error_append_hint(errp,
2080 "This KVM seems to be too old to support VSMT.\n");
2081 }
2082}
2083
2084
7f763a5d 2085#ifdef TARGET_PPC64
7f763a5d
DG		 2086uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2087{
f36951c1
DG		 2088 struct kvm_ppc_smmu_info info;
2089 long rampagesize, best_page_shift;
2090 int i;
2091
f36951c1
DG		 2092 /* Find the largest hardware supported page size that's less than
2093 * or equal to the (logical) backing page size of guest RAM */
71d0f1ea 2094 kvm_get_smmu_info(POWERPC_CPU(first_cpu), &info, &error_fatal);
9c607668 2095 rampagesize = qemu_getrampagesize();
f36951c1
DG		 2096 best_page_shift = 0;
2097
2098 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2099 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2100
2101 if (!sps->page_shift) {
2102 continue;
2103 }
2104
2105 if ((sps->page_shift > best_page_shift)
2106 && ((1UL << sps->page_shift) <= rampagesize)) {
2107 best_page_shift = sps->page_shift;
2108 }
2109 }
2110
7f763a5d 2111 return MIN(current_size,
f36951c1 2112 1ULL << (best_page_shift + hash_shift - 7));
7f763a5d
DG		 2113}
2114#endif
2115
da95324e
AK		 2116bool kvmppc_spapr_use_multitce(void)
2117{
2118 return cap_spapr_multitce;
2119}
2120
3dc410ae
AK		 2121int kvmppc_spapr_enable_inkernel_multitce(void)
2122{
2123 int ret;
2124
2125 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2126 H_PUT_TCE_INDIRECT, 1);
2127 if (!ret) {
2128 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2129 H_STUFF_TCE, 1);
2130 }
2131
2132 return ret;
2133}
2134
d6ee2a7c
AK		 2135void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2136 uint64_t bus_offset, uint32_t nb_table,
2137 int *pfd, bool need_vfio)
0f5cb298 2138{
0f5cb298
DG		 2139 long len;
2140 int fd;
2141 void *table;
2142
b5aec396
DG		 2143 /* Must set fd to -1 so we don't try to munmap when called for
2144 * destroying the table, which the upper layers -will- do
2145 */
2146 *pfd = -1;
6a81dd17 2147 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2148 return NULL;
2149 }
2150
d6ee2a7c
AK		 2151 if (cap_spapr_tce_64) {
2152 struct kvm_create_spapr_tce_64 args = {
2153 .liobn = liobn,
2154 .page_shift = page_shift,
2155 .offset = bus_offset >> page_shift,
2156 .size = nb_table,
2157 .flags = 0
2158 };
2159 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2160 if (fd < 0) {
2161 fprintf(stderr,
2162 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2163 liobn);
2164 return NULL;
2165 }
2166 } else if (cap_spapr_tce) {
2167 uint64_t window_size = (uint64_t) nb_table << page_shift;
2168 struct kvm_create_spapr_tce args = {
2169 .liobn = liobn,
2170 .window_size = window_size,
2171 };
2172 if ((window_size != args.window_size) || bus_offset) {
2173 return NULL;
2174 }
2175 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2176 if (fd < 0) {
2177 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2178 liobn);
2179 return NULL;
2180 }
2181 } else {
0f5cb298
DG		 2182 return NULL;
2183 }
2184
d6ee2a7c 2185 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2186 /* FIXME: round this up to page size */
2187
74b41e56 2188 table = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2189 if (table == MAP_FAILED) {
b5aec396
DG		 2190 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2191 liobn);
0f5cb298
DG		 2192 close(fd);
2193 return NULL;
2194 }
2195
2196 *pfd = fd;
2197 return table;
2198}
2199
523e7b8a 2200int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2201{
2202 long len;
2203
2204 if (fd < 0) {
2205 return -1;
2206 }
2207
523e7b8a 2208 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2209 if ((munmap(table, len) < 0) ||
2210 (close(fd) < 0)) {
b5aec396
DG		 2211 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2212 strerror(errno));
0f5cb298
DG		 2213 /* Leak the table */
2214 }
2215
2216 return 0;
2217}
2218
7f763a5d
DG		 2219int kvmppc_reset_htab(int shift_hint)
2220{
2221 uint32_t shift = shift_hint;
2222
ace9a2cb
DG		 2223 if (!kvm_enabled()) {
2224 /* Full emulation, tell caller to allocate htab itself */
2225 return 0;
2226 }
6977afda 2227 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2228 int ret;
2229 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb
DG		 2230 if (ret == -ENOTTY) {
2231 /* At least some versions of PR KVM advertise the
2232 * capability, but don't implement the ioctl(). Oops.
2233 * Return 0 so that we allocate the htab in qemu, as is
2234 * correct for PR. */
2235 return 0;
2236 } else if (ret < 0) {
7f763a5d
DG		 2237 return ret;
2238 }
2239 return shift;
2240 }
2241
ace9a2cb
DG		 2242 /* We have a kernel that predates the htab reset calls. For PR
2243 * KVM, we need to allocate the htab ourselves, for an HV KVM of
96c9cff0
TH		 2244 * this era, it has allocated a 16MB fixed size hash table already. */
2245 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2246 /* PR - tell caller to allocate htab */
2247 return 0;
2248 } else {
2249 /* HV - assume 16MB kernel allocated htab */
2250 return 24;
2251 }
7f763a5d
DG		 2252}
2253
a1e98583
DG		 2254static inline uint32_t mfpvr(void)
2255{
2256 uint32_t pvr;
2257
2258 asm ("mfpvr %0"
2259 : "=r"(pvr));
2260 return pvr;
2261}
2262
a7342588
DG		 2263static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2264{
2265 if (on) {
2266 *word |= flags;
2267 } else {
2268 *word &= ~flags;
2269 }
2270}
2271
2985b86b
AF		 2272static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2273{
2274 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2275 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2276 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2277
cfe34f44 2278 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2279 pcc->pvr = mfpvr();
a7342588 2280
3f2ca480
DG		 2281 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2282 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2283 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2284 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2285 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2286 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2287
2288 if (dcache_size != -1) {
2289 pcc->l1_dcache_size = dcache_size;
2290 }
2291
2292 if (icache_size != -1) {
2293 pcc->l1_icache_size = icache_size;
2294 }
c64abd1f
SB		 2295
2296#if defined(TARGET_PPC64)
2297 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2298
2299 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2300 /*
2301 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2302 * compliant. More importantly, advertising ISA 3.00
2303 * architected mode may prevent guests from activating
2304 * necessary DD1 workarounds.
2305 */
2306 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2307 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2308 }
c64abd1f 2309#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2310}
2311
3b961124
SY		 2312bool kvmppc_has_cap_epr(void)
2313{
2314 return cap_epr;
2315}
2316
87a91de6
AG		 2317bool kvmppc_has_cap_fixup_hcalls(void)
2318{
2319 return cap_fixup_hcalls;
2320}
2321
bac3bf28
TH		 2322bool kvmppc_has_cap_htm(void)
2323{
2324 return cap_htm;
2325}
2326
cf1c4cce
SB		 2327bool kvmppc_has_cap_mmu_radix(void)
2328{
2329 return cap_mmu_radix;
2330}
2331
2332bool kvmppc_has_cap_mmu_hash_v3(void)
2333{
2334 return cap_mmu_hash_v3;
2335}
2336
072f416a
SJS		 2337static bool kvmppc_power8_host(void)
2338{
2339 bool ret = false;
2340#ifdef TARGET_PPC64
2341 {
2342 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2343 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2344 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2345 (base_pvr == CPU_POWERPC_POWER8_BASE);
2346 }
2347#endif /* TARGET_PPC64 */
2348 return ret;
2349}
2350
8fea7044
SJS		 2351static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2352{
072f416a
SJS		 2353 bool l1d_thread_priv_req = !kvmppc_power8_host();
2354
8fea7044
SJS		 2355 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2356 return 2;
072f416a
SJS		 2357 } else if ((!l1d_thread_priv_req ||
2358 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2359 (c.character & c.character_mask
2360 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2361 return 1;
2362 }
2363
2364 return 0;
2365}
2366
2367static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2368{
2369 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2370 return 2;
2371 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2372 return 1;
2373 }
2374
2375 return 0;
2376}
2377
2378static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2379{
2380 if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2381 return SPAPR_CAP_FIXED_CCD;
2382 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2383 return SPAPR_CAP_FIXED_IBS;
2384 }
2385
2386 return 0;
2387}
2388
8acc2ae5
SJS		 2389static void kvmppc_get_cpu_characteristics(KVMState *s)
2390{
2391 struct kvm_ppc_cpu_char c;
2392 int ret;
2393
2394 /* Assume broken */
2395 cap_ppc_safe_cache = 0;
2396 cap_ppc_safe_bounds_check = 0;
2397 cap_ppc_safe_indirect_branch = 0;
2398
2399 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2400 if (!ret) {
2401 return;
2402 }
2403 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2404 if (ret < 0) {
2405 return;
2406 }
8fea7044
SJS		 2407
2408 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2409 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2410 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8acc2ae5
SJS		 2411}
2412
2413int kvmppc_get_cap_safe_cache(void)
2414{
2415 return cap_ppc_safe_cache;
2416}
2417
2418int kvmppc_get_cap_safe_bounds_check(void)
2419{
2420 return cap_ppc_safe_bounds_check;
2421}
2422
2423int kvmppc_get_cap_safe_indirect_branch(void)
2424{
2425 return cap_ppc_safe_indirect_branch;
2426}
2427
9ded780c
AK		 2428bool kvmppc_has_cap_spapr_vfio(void)
2429{
2430 return cap_spapr_vfio;
2431}
2432
52b2519c
TH		 2433PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2434{
2435 uint32_t host_pvr = mfpvr();
2436 PowerPCCPUClass *pvr_pcc;
2437
2438 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2439 if (pvr_pcc == NULL) {
2440 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2441 }
2442
2443 return pvr_pcc;
2444}
2445
2e9c10eb 2446static int kvm_ppc_register_host_cpu_type(MachineState *ms)
5ba4576b
AF		 2447{
2448 TypeInfo type_info = {
2449 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2450 .class_init = kvmppc_host_cpu_class_init,
2451 };
2e9c10eb 2452 MachineClass *mc = MACHINE_GET_CLASS(ms);
5ba4576b 2453 PowerPCCPUClass *pvr_pcc;
92e926e1 2454 ObjectClass *oc;
5b79b1ca 2455 DeviceClass *dc;
715d4b96 2456 int i;
5ba4576b 2457
52b2519c 2458 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2459 if (pvr_pcc == NULL) {
2460 return -1;
2461 }
2462 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2463 type_register(&type_info);
2e9c10eb
IM		 2464 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) {
2465 /* override TCG default cpu type with 'host' cpu model */
2466 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2467 }
5b79b1ca 2468
92e926e1
GK		 2469 oc = object_class_by_name(type_info.name);
2470 g_assert(oc);
2471
715d4b96
TH		 2472 /*
2473 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2474 * we want "POWER8" to be a "family" alias that points to the current
2475 * host CPU type, too)
2476 */
2477 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2478 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2479 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2480 char *suffix;
2481
2482 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2483 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2484 if (suffix) {
2485 *suffix = 0;
2486 }
715d4b96
TH		 2487 break;
2488 }
2489 }
2490
5ba4576b
AF		 2491 return 0;
2492}
2493
feaa64c4
DG		 2494int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2495{
2496 struct kvm_rtas_token_args args = {
2497 .token = token,
2498 };
2499
2500 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2501 return -ENOENT;
2502 }
2503
2504 strncpy(args.name, function, sizeof(args.name));
2505
2506 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2507}
12b1143b 2508
14b0d748 2509int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2510{
2511 struct kvm_get_htab_fd s = {
2512 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2513 .start_index = index,
e68cb8b4 2514 };
82be8e73 2515 int ret;
e68cb8b4
AK		 2516
2517 if (!cap_htab_fd) {
14b0d748
GK		 2518 error_setg(errp, "KVM version doesn't support %s the HPT",
2519 write ? "writing" : "reading");
82be8e73
GK		 2520 return -ENOTSUP;
2521 }
2522
2523 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2524 if (ret < 0) {
14b0d748
GK		 2525 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2526 write ? "writing" : "reading", write ? "to" : "from",
2527 strerror(errno));
82be8e73 2528 return -errno;
e68cb8b4
AK		 2529 }
2530
82be8e73 2531 return ret;
e68cb8b4
AK		 2532}
2533
2534int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2535{
bc72ad67 2536 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2537 uint8_t buf[bufsize];
2538 ssize_t rc;
2539
2540 do {
2541 rc = read(fd, buf, bufsize);
2542 if (rc < 0) {
2543 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2544 strerror(errno));
2545 return rc;
2546 } else if (rc) {
e094c4c1
CLG		 2547 uint8_t *buffer = buf;
2548 ssize_t n = rc;
2549 while (n) {
2550 struct kvm_get_htab_header *head =
2551 (struct kvm_get_htab_header *) buffer;
2552 size_t chunksize = sizeof(*head) +
2553 HASH_PTE_SIZE_64 * head->n_valid;
2554
2555 qemu_put_be32(f, head->index);
2556 qemu_put_be16(f, head->n_valid);
2557 qemu_put_be16(f, head->n_invalid);
2558 qemu_put_buffer(f, (void *)(head + 1),
2559 HASH_PTE_SIZE_64 * head->n_valid);
2560
2561 buffer += chunksize;
2562 n -= chunksize;
2563 }
e68cb8b4
AK		 2564 }
2565 } while ((rc != 0)
2566 && ((max_ns < 0)
bc72ad67 2567 || ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2568
2569 return (rc == 0) ? 1 : 0;
2570}
2571
2572int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2573 uint16_t n_valid, uint16_t n_invalid)
2574{
2575 struct kvm_get_htab_header *buf;
2576 size_t chunksize = sizeof(*buf) + n_valid*HASH_PTE_SIZE_64;
2577 ssize_t rc;
2578
2579 buf = alloca(chunksize);
e68cb8b4
AK		 2580 buf->index = index;
2581 buf->n_valid = n_valid;
2582 buf->n_invalid = n_invalid;
2583
2584 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64*n_valid);
2585
2586 rc = write(fd, buf, chunksize);
2587 if (rc < 0) {
2588 fprintf(stderr, "Error writing KVM hash table: %s\n",
2589 strerror(errno));
2590 return rc;
2591 }
2592 if (rc != chunksize) {
2593 /* We should never get a short write on a single chunk */
2594 fprintf(stderr, "Short write, restoring KVM hash table\n");
2595 return -1;
2596 }
2597 return 0;
2598}
2599
20d695a9 2600bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2601{
2602 return true;
2603}
a1b87fe0 2604
82169660
SW		 2605void kvm_arch_init_irq_routing(KVMState *s)
2606{
2607}
c65f9a07 2608
1ad9f0a4 2609void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2610{
1ad9f0a4
DG		 2611 int fd, rc;
2612 int i;
7c43bca0 2613
14b0d748 2614 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2615
1ad9f0a4
DG		 2616 i = 0;
2617 while (i < n) {
2618 struct kvm_get_htab_header *hdr;
2619 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2620 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2621
1ad9f0a4
DG		 2622 rc = read(fd, buf, sizeof(buf));
2623 if (rc < 0) {
2624 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2625 }
7c43bca0 2626
1ad9f0a4
DG		 2627 hdr = (struct kvm_get_htab_header *)buf;
2628 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2629 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2630
1ad9f0a4
DG		 2631 if (hdr->index != (ptex + i)) {
2632 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2633 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2634 }
2635
a36593e1
AK		 2636 if (n - i < valid) {
2637 valid = n - i;
2638 }
2639 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2640 i += valid;
7c43bca0 2641
1ad9f0a4
DG		 2642 if ((n - i) < invalid) {
2643 invalid = n - i;
2644 }
2645 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2646 i += invalid;
1ad9f0a4
DG		 2647
2648 hdr = (struct kvm_get_htab_header *)
2649 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2650 }
2651 }
2652
2653 close(fd);
7c43bca0 2654}
c1385933 2655
1ad9f0a4 2656void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2657{
1ad9f0a4 2658 int fd, rc;
1ad9f0a4
DG		 2659 struct {
2660 struct kvm_get_htab_header hdr;
2661 uint64_t pte0;
2662 uint64_t pte1;
2663 } buf;
c1385933 2664
14b0d748 2665 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2666
1ad9f0a4
DG		 2667 buf.hdr.n_valid = 1;
2668 buf.hdr.n_invalid = 0;
2669 buf.hdr.index = ptex;
2670 buf.pte0 = cpu_to_be64(pte0);
2671 buf.pte1 = cpu_to_be64(pte1);
c1385933 2672
1ad9f0a4
DG		 2673 rc = write(fd, &buf, sizeof(buf));
2674 if (rc != sizeof(buf)) {
2675 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2676 }
2677 close(fd);
c1385933 2678}
9e03a040
FB		 2679
2680int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2681 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2682{
2683 return 0;
2684}
1850b6b7 2685
38d87493
PX		 2686int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2687 int vector, PCIDevice *dev)
2688{
2689 return 0;
2690}
2691
2692int kvm_arch_release_virq_post(int virq)
2693{
2694 return 0;
2695}
2696
1850b6b7
EA		 2697int kvm_arch_msi_data_to_gsi(uint32_t data)
2698{
2699 return data & 0xffff;
2700}
4d9392be
TH		 2701
2702int kvmppc_enable_hwrng(void)
2703{
2704 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2705 return -1;
2706 }
2707
2708 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2709}
30f4b05b
DG		 2710
2711void kvmppc_check_papr_resize_hpt(Error **errp)
2712{
2713 if (!kvm_enabled()) {
b55d295e
DG		 2714 return; /* No KVM, we're good */
2715 }
2716
2717 if (cap_resize_hpt) {
2718 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2719 }
2720
b55d295e
DG		 2721 /* Otherwise fallback on looking for PR KVM */
2722 if (kvmppc_is_pr(kvm_state)) {
2723 return;
2724 }
30f4b05b
DG		 2725
2726 error_setg(errp,
2727 "Hash page table resizing not available with this KVM version");
2728}
b55d295e
DG		 2729
2730int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2731{
2732 CPUState *cs = CPU(cpu);
2733 struct kvm_ppc_resize_hpt rhpt = {
2734 .flags = flags,
2735 .shift = shift,
2736 };
2737
2738 if (!cap_resize_hpt) {
2739 return -ENOSYS;
2740 }
2741
2742 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2743}
2744
2745int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2746{
2747 CPUState *cs = CPU(cpu);
2748 struct kvm_ppc_resize_hpt rhpt = {
2749 .flags = flags,
2750 .shift = shift,
2751 };
2752
2753 if (!cap_resize_hpt) {
2754 return -ENOSYS;
2755 }
2756
2757 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2758}
2759
c363a37a
DHB		 2760/*
2761 * This is a helper function to detect a post migration scenario
2762 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2763 * the guest kernel can't handle a PVR value other than the actual host
2764 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2765 *
2766 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2767 * (so, we're HV), return true. The workaround itself is done in
2768 * cpu_post_load.
2769 *
2770 * The order here is important: we'll only check for KVM PR as a
2771 * fallback if the guest kernel can't handle the situation itself.
2772 * We need to avoid as much as possible querying the running KVM type
2773 * in QEMU level.
2774 */
2775bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2776{
2777 CPUState *cs = CPU(cpu);
2778
2779 if (!kvm_enabled()) {
2780 return false;
2781 }
2782
2783 if (cap_ppc_pvr_compat) {
2784 return false;
2785 }
2786
2787 return !kvmppc_is_pr(cs->kvm_state);
2788}
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