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target/ppc: Remove msr_ts macro
[mirror_qemu.git] / target / ppc / kvm.c
CommitLineData
d76d1650
AJ		 1/*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
90dc8812 5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
d76d1650
AJ		 6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
0d75590d 17#include "qemu/osdep.h"
eadaada1 18#include <dirent.h>
d76d1650 19#include <sys/ioctl.h>
4656e1f0 20#include <sys/vfs.h>
d76d1650
AJ		 21
22#include <linux/kvm.h>
23
30f4b05b 24#include "qapi/error.h"
072ed5f2 25#include "qemu/error-report.h"
33c11879 26#include "cpu.h"
715d4b96 27#include "cpu-models.h"
1de7afc9 28#include "qemu/timer.h"
b3946626 29#include "sysemu/hw_accel.h"
d76d1650 30#include "kvm_ppc.h"
9c17d615
PB		 31#include "sysemu/cpus.h"
32#include "sysemu/device_tree.h"
d5aea6f3 33#include "mmu-hash64.h"
d76d1650 34
f61b4bed 35#include "hw/sysbus.h"
0d09e41a 36#include "hw/ppc/spapr.h"
7ebaf795 37#include "hw/ppc/spapr_cpu_core.h"
650d103d 38#include "hw/hw.h"
98a8b524 39#include "hw/ppc/ppc.h"
ca77ee28 40#include "migration/qemu-file-types.h"
31f2cb8f 41#include "sysemu/watchdog.h"
b36f100e 42#include "trace.h"
88365d17 43#include "exec/gdbstub.h"
4c663752 44#include "exec/memattrs.h"
9c607668 45#include "exec/ram_addr.h"
2d103aae 46#include "sysemu/hostmem.h"
f348b6d1 47#include "qemu/cutils.h"
db725815 48#include "qemu/main-loop.h"
9c607668 49#include "qemu/mmap-alloc.h"
f3d9f303 50#include "elf.h"
c64abd1f 51#include "sysemu/kvm_int.h"
f61b4bed 52
eadaada1
AG		 53#define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
54
6e0552a3
FR		 55#define DEBUG_RETURN_GUEST 0
56#define DEBUG_RETURN_GDB 1
57
94a8d39a
JK		 58const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
59 KVM_CAP_LAST_INFO
60};
61
c995e942 62static int cap_interrupt_unset;
90dc8812 63static int cap_segstate;
90dc8812 64static int cap_booke_sregs;
e97c3636 65static int cap_ppc_smt;
fa98fbfc 66static int cap_ppc_smt_possible;
0f5cb298 67static int cap_spapr_tce;
d6ee2a7c 68static int cap_spapr_tce_64;
da95324e 69static int cap_spapr_multitce;
9bb62a07 70static int cap_spapr_vfio;
f1af19d7 71static int cap_hior;
d67d40ea 72static int cap_one_reg;
3b961124 73static int cap_epr;
31f2cb8f 74static int cap_ppc_watchdog;
9b00ea49 75static int cap_papr;
e68cb8b4 76static int cap_htab_fd;
87a91de6 77static int cap_fixup_hcalls;
bac3bf28 78static int cap_htm; /* Hardware transactional memory support */
cf1c4cce
SB		 79static int cap_mmu_radix;
80static int cap_mmu_hash_v3;
38afd772 81static int cap_xive;
b55d295e 82static int cap_resize_hpt;
c363a37a 83static int cap_ppc_pvr_compat;
8acc2ae5
SJS		 84static int cap_ppc_safe_cache;
85static int cap_ppc_safe_bounds_check;
86static int cap_ppc_safe_indirect_branch;
8ff43ee4 87static int cap_ppc_count_cache_flush_assist;
b9a477b7 88static int cap_ppc_nested_kvm_hv;
7d050527 89static int cap_large_decr;
ec010c00 90static int cap_fwnmi;
82123b75 91static int cap_rpt_invalidate;
fc87e185 92
3c902d44
BB		 93static uint32_t debug_inst_opcode;
94
c995e942
DG		 95/*
96 * Check whether we are running with KVM-PR (instead of KVM-HV). This
96c9cff0
TH		 97 * should only be used for fallback tests - generally we should use
98 * explicit capabilities for the features we want, rather than
c995e942
DG		 99 * assuming what is/isn't available depending on the KVM variant.
100 */
96c9cff0
TH		 101static bool kvmppc_is_pr(KVMState *ks)
102{
103 /* Assume KVM-PR if the GET_PVINFO capability is available */
70a0c19e 104 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
96c9cff0
TH		 105}
106
165dc3ed 107static int kvm_ppc_register_host_cpu_type(void);
8acc2ae5 108static void kvmppc_get_cpu_characteristics(KVMState *s);
7d050527 109static int kvmppc_get_dec_bits(void);
5ba4576b 110
b16565b3 111int kvm_arch_init(MachineState *ms, KVMState *s)
d76d1650 112{
fc87e185 113 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
90dc8812 114 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
90dc8812 115 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
6977afda 116 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
0f5cb298 117 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
d6ee2a7c 118 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
da95324e 119 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
9ded780c 120 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
d67d40ea 121 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
f1af19d7 122 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
3b961124 123 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
31f2cb8f 124 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
c995e942
DG		 125 /*
126 * Note: we don't set cap_papr here, because this capability is
127 * only activated after this by kvmppc_set_papr()
128 */
6977afda 129 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
87a91de6 130 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
fa98fbfc 131 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
bac3bf28 132 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
cf1c4cce
SB		 133 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
134 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
38afd772 135 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
b55d295e 136 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
8acc2ae5 137 kvmppc_get_cpu_characteristics(s);
b9a477b7 138 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
7d050527 139 cap_large_decr = kvmppc_get_dec_bits();
ec010c00 140 cap_fwnmi = kvm_vm_check_extension(s, KVM_CAP_PPC_FWNMI);
c363a37a
DHB		 141 /*
142 * Note: setting it to false because there is not such capability
143 * in KVM at this moment.
144 *
145 * TODO: call kvm_vm_check_extension() with the right capability
c995e942
DG		 146 * after the kernel starts implementing it.
147 */
c363a37a 148 cap_ppc_pvr_compat = false;
fc87e185 149
1e8f51e8
SB		 150 if (!kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL)) {
151 error_report("KVM: Host kernel doesn't have level irq capability");
152 exit(1);
fc87e185
AG		 153 }
154
82123b75 155 cap_rpt_invalidate = kvm_vm_check_extension(s, KVM_CAP_PPC_RPT_INVALIDATE);
165dc3ed 156 kvm_ppc_register_host_cpu_type();
5ba4576b 157
d76d1650
AJ		 158 return 0;
159}
160
4376c40d 161int kvm_arch_irqchip_create(KVMState *s)
d525ffab
PB		 162{
163 return 0;
164}
165
1bc22652 166static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
d76d1650 167{
1bc22652
AF		 168 CPUPPCState *cenv = &cpu->env;
169 CPUState *cs = CPU(cpu);
861bbc80 170 struct kvm_sregs sregs;
5666ca4a
SW		 171 int ret;
172
173 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
c995e942
DG		 174 /*
175 * What we're really trying to say is "if we're on BookE, we
176 * use the native PVR for now". This is the only sane way to
177 * check it though, so we potentially confuse users that they
178 * can run BookE guests on BookS. Let's hope nobody dares
179 * enough :)
180 */
5666ca4a
SW		 181 return 0;
182 } else {
90dc8812 183 if (!cap_segstate) {
64e07be5
AG		 184 fprintf(stderr, "kvm error: missing PVR setting capability\n");
185 return -ENOSYS;
5666ca4a 186 }
5666ca4a
SW		 187 }
188
1bc22652 189 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
5666ca4a
SW		 190 if (ret) {
191 return ret;
192 }
861bbc80
AG		 193
194 sregs.pvr = cenv->spr[SPR_PVR];
1bc22652 195 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
5666ca4a
SW		 196}
197
93dd5e85 198/* Set up a shared TLB array with KVM */
1bc22652 199static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
93dd5e85 200{
1bc22652
AF		 201 CPUPPCState *env = &cpu->env;
202 CPUState *cs = CPU(cpu);
93dd5e85
SW		 203 struct kvm_book3e_206_tlb_params params = {};
204 struct kvm_config_tlb cfg = {};
93dd5e85
SW		 205 unsigned int entries = 0;
206 int ret, i;
207
208 if (!kvm_enabled() ||
a60f24b5 209 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
93dd5e85
SW		 210 return 0;
211 }
212
213 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
214
215 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
216 params.tlb_sizes[i] = booke206_tlb_size(env, i);
217 params.tlb_ways[i] = booke206_tlb_ways(env, i);
218 entries += params.tlb_sizes[i];
219 }
220
221 assert(entries == env->nb_tlb);
222 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
223
224 env->tlb_dirty = true;
225
226 cfg.array = (uintptr_t)env->tlb.tlbm;
227 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
228 cfg.params = (uintptr_t)&params;
229 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
230
48add816 231 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
93dd5e85
SW		 232 if (ret < 0) {
233 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
234 __func__, strerror(-ret));
235 return ret;
236 }
237
238 env->kvm_sw_tlb = true;
239 return 0;
240}
241
4656e1f0
BH		 242
243#if defined(TARGET_PPC64)
ab256960 244static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
4656e1f0 245{
71d0f1ea 246 int ret;
a60f24b5 247
ab256960
GK		 248 assert(kvm_state != NULL);
249
250 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
71d0f1ea
GK		 251 error_setg(errp, "KVM doesn't expose the MMU features it supports");
252 error_append_hint(errp, "Consider switching to a newer KVM\n");
253 return;
4656e1f0 254 }
4656e1f0 255
ab256960 256 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
71d0f1ea
GK		 257 if (ret == 0) {
258 return;
4656e1f0
BH		 259 }
260
71d0f1ea
GK		 261 error_setg_errno(errp, -ret,
262 "KVM failed to provide the MMU features it supports");
4656e1f0
BH		 263}
264
c64abd1f
SB		 265struct ppc_radix_page_info *kvm_get_radix_page_info(void)
266{
4f7f5893 267 KVMState *s = KVM_STATE(current_accel());
c64abd1f 268 struct ppc_radix_page_info *radix_page_info;
55baf4b5 269 struct kvm_ppc_rmmu_info rmmu_info = { };
c64abd1f
SB		 270 int i;
271
272 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
273 return NULL;
274 }
275 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
276 return NULL;
277 }
278 radix_page_info = g_malloc0(sizeof(*radix_page_info));
279 radix_page_info->count = 0;
280 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
281 if (rmmu_info.ap_encodings[i]) {
282 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
283 radix_page_info->count++;
284 }
285 }
286 return radix_page_info;
287}
288
b4db5413
SJS		 289target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
290 bool radix, bool gtse,
291 uint64_t proc_tbl)
292{
293 CPUState *cs = CPU(cpu);
294 int ret;
295 uint64_t flags = 0;
296 struct kvm_ppc_mmuv3_cfg cfg = {
297 .process_table = proc_tbl,
298 };
299
300 if (radix) {
301 flags |= KVM_PPC_MMUV3_RADIX;
302 }
303 if (gtse) {
304 flags |= KVM_PPC_MMUV3_GTSE;
305 }
306 cfg.flags = flags;
307 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
308 switch (ret) {
309 case 0:
310 return H_SUCCESS;
311 case -EINVAL:
312 return H_PARAMETER;
313 case -ENODEV:
314 return H_NOT_AVAILABLE;
315 default:
316 return H_HARDWARE;
317 }
318}
319
24c6863c
DG		 320bool kvmppc_hpt_needs_host_contiguous_pages(void)
321{
24c6863c
DG		 322 static struct kvm_ppc_smmu_info smmu_info;
323
324 if (!kvm_enabled()) {
325 return false;
326 }
327
ab256960 328 kvm_get_smmu_info(&smmu_info, &error_fatal);
24c6863c
DG		 329 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
330}
331
e5ca28ec 332void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
4656e1f0 333{
e5ca28ec 334 struct kvm_ppc_smmu_info smmu_info;
4656e1f0 335 int iq, ik, jq, jk;
71d0f1ea 336 Error *local_err = NULL;
4656e1f0 337
e5ca28ec
DG		 338 /* For now, we only have anything to check on hash64 MMUs */
339 if (!cpu->hash64_opts || !kvm_enabled()) {
4656e1f0
BH		 340 return;
341 }
342
ab256960 343 kvm_get_smmu_info(&smmu_info, &local_err);
71d0f1ea
GK		 344 if (local_err) {
345 error_propagate(errp, local_err);
346 return;
347 }
4656e1f0 348
e5ca28ec
DG		 349 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
350 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
351 error_setg(errp,
352 "KVM does not support 1TiB segments which guest expects");
353 return;
df587133 354 }
4656e1f0 355
e5ca28ec
DG		 356 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
357 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
358 smmu_info.slb_size, cpu->hash64_opts->slb_size);
359 return;
90da0d5a
BH		 360 }
361
08215d8f 362 /*
e5ca28ec
DG		 363 * Verify that every pagesize supported by the cpu model is
364 * supported by KVM with the same encodings
08215d8f 365 */
e5ca28ec 366 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
b07c59f7 367 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
e5ca28ec 368 struct kvm_ppc_one_seg_page_size *ksps;
4656e1f0 369
e5ca28ec
DG		 370 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
371 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
4656e1f0
BH		 372 break;
373 }
374 }
e5ca28ec
DG		 375 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
376 error_setg(errp, "KVM doesn't support for base page shift %u",
377 qsps->page_shift);
378 return;
379 }
380
381 ksps = &smmu_info.sps[ik];
382 if (ksps->slb_enc != qsps->slb_enc) {
383 error_setg(errp,
384"KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
385 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
386 return;
387 }
388
389 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
390 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
391 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
392 break;
393 }
394 }
395
396 if (jk >= ARRAY_SIZE(ksps->enc)) {
397 error_setg(errp, "KVM doesn't support page shift %u/%u",
398 qsps->enc[jq].page_shift, qsps->page_shift);
399 return;
400 }
401 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
402 error_setg(errp,
403"KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
404 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
405 qsps->page_shift, qsps->enc[jq].pte_enc);
406 return;
407 }
4656e1f0
BH		 408 }
409 }
4656e1f0 410
e5ca28ec 411 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
c995e942
DG		 412 /*
413 * Mostly what guest pagesizes we can use are related to the
e5ca28ec
DG		 414 * host pages used to map guest RAM, which is handled in the
415 * platform code. Cache-Inhibited largepages (64k) however are
416 * used for I/O, so if they're mapped to the host at all it
417 * will be a normal mapping, not a special hugepage one used
c995e942
DG		 418 * for RAM.
419 */
8e3b0cbb 420 if (qemu_real_host_page_size() < 0x10000) {
e5ca28ec
DG		 421 error_setg(errp,
422 "KVM can't supply 64kiB CI pages, which guest expects");
423 }
424 }
4656e1f0 425}
4656e1f0
BH		 426#endif /* !defined (TARGET_PPC64) */
427
b164e48e
EH		 428unsigned long kvm_arch_vcpu_id(CPUState *cpu)
429{
2e886fb3 430 return POWERPC_CPU(cpu)->vcpu_id;
b164e48e
EH		 431}
432
c995e942
DG		 433/*
434 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
435 * only 1 watchpoint, so array size of 4 is sufficient for now.
88365d17
BB		 436 */
437#define MAX_HW_BKPTS 4
438
439static struct HWBreakpoint {
440 target_ulong addr;
441 int type;
442} hw_debug_points[MAX_HW_BKPTS];
443
444static CPUWatchpoint hw_watchpoint;
445
446/* Default there is no breakpoint and watchpoint supported */
447static int max_hw_breakpoint;
448static int max_hw_watchpoint;
449static int nb_hw_breakpoint;
450static int nb_hw_watchpoint;
451
452static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
453{
454 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
455 max_hw_breakpoint = 2;
456 max_hw_watchpoint = 2;
457 }
458
459 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
460 fprintf(stderr, "Error initializing h/w breakpoints\n");
461 return;
462 }
463}
464
20d695a9 465int kvm_arch_init_vcpu(CPUState *cs)
5666ca4a 466{
20d695a9
AF		 467 PowerPCCPU *cpu = POWERPC_CPU(cs);
468 CPUPPCState *cenv = &cpu->env;
5666ca4a
SW		 469 int ret;
470
4656e1f0 471 /* Synchronize sregs with kvm */
1bc22652 472 ret = kvm_arch_sync_sregs(cpu);
5666ca4a 473 if (ret) {
388e47c7
TH		 474 if (ret == -EINVAL) {
475 error_report("Register sync failed... If you're using kvm-hv.ko,"
476 " only \"-cpu host\" is possible");
477 }
5666ca4a
SW		 478 return ret;
479 }
861bbc80 480
93dd5e85
SW		 481 switch (cenv->mmu_model) {
482 case POWERPC_MMU_BOOKE206:
7f516c96 483 /* This target supports access to KVM's guest TLB */
1bc22652 484 ret = kvm_booke206_tlb_init(cpu);
93dd5e85 485 break;
7f516c96
TH		 486 case POWERPC_MMU_2_07:
487 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
c995e942
DG		 488 /*
489 * KVM-HV has transactional memory on POWER8 also without
490 * the KVM_CAP_PPC_HTM extension, so enable it here
136fbf65 491 * instead as long as it's available to userspace on the
c995e942
DG		 492 * host.
493 */
f3d9f303
SB		 494 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
495 cap_htm = true;
496 }
7f516c96
TH		 497 }
498 break;
93dd5e85
SW		 499 default:
500 break;
501 }
502
3c902d44 503 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
88365d17 504 kvmppc_hw_debug_points_init(cenv);
3c902d44 505
861bbc80 506 return ret;
d76d1650
AJ		 507}
508
b1115c99
LA		 509int kvm_arch_destroy_vcpu(CPUState *cs)
510{
511 return 0;
512}
513
1bc22652 514static void kvm_sw_tlb_put(PowerPCCPU *cpu)
93dd5e85 515{
1bc22652
AF		 516 CPUPPCState *env = &cpu->env;
517 CPUState *cs = CPU(cpu);
93dd5e85
SW		 518 struct kvm_dirty_tlb dirty_tlb;
519 unsigned char *bitmap;
520 int ret;
521
522 if (!env->kvm_sw_tlb) {
523 return;
524 }
525
526 bitmap = g_malloc((env->nb_tlb + 7) / 8);
527 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
528
529 dirty_tlb.bitmap = (uintptr_t)bitmap;
530 dirty_tlb.num_dirty = env->nb_tlb;
531
1bc22652 532 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
93dd5e85
SW		 533 if (ret) {
534 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
535 __func__, strerror(-ret));
536 }
537
538 g_free(bitmap);
539}
540
d67d40ea
DG		 541static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
542{
543 PowerPCCPU *cpu = POWERPC_CPU(cs);
544 CPUPPCState *env = &cpu->env;
942069e0 545 /* Init 'val' to avoid "uninitialised value" Valgrind warnings */
d67d40ea
DG		 546 union {
547 uint32_t u32;
548 uint64_t u64;
942069e0 549 } val = { };
d67d40ea
DG		 550 struct kvm_one_reg reg = {
551 .id = id,
552 .addr = (uintptr_t) &val,
553 };
554 int ret;
555
556 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
557 if (ret != 0) {
b36f100e 558 trace_kvm_failed_spr_get(spr, strerror(errno));
d67d40ea
DG		 559 } else {
560 switch (id & KVM_REG_SIZE_MASK) {
561 case KVM_REG_SIZE_U32:
562 env->spr[spr] = val.u32;
563 break;
564
565 case KVM_REG_SIZE_U64:
566 env->spr[spr] = val.u64;
567 break;
568
569 default:
570 /* Don't handle this size yet */
571 abort();
572 }
573 }
574}
575
576static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
577{
578 PowerPCCPU *cpu = POWERPC_CPU(cs);
579 CPUPPCState *env = &cpu->env;
580 union {
581 uint32_t u32;
582 uint64_t u64;
583 } val;
584 struct kvm_one_reg reg = {
585 .id = id,
586 .addr = (uintptr_t) &val,
587 };
588 int ret;
589
590 switch (id & KVM_REG_SIZE_MASK) {
591 case KVM_REG_SIZE_U32:
592 val.u32 = env->spr[spr];
593 break;
594
595 case KVM_REG_SIZE_U64:
596 val.u64 = env->spr[spr];
597 break;
598
599 default:
600 /* Don't handle this size yet */
601 abort();
602 }
603
604 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
605 if (ret != 0) {
b36f100e 606 trace_kvm_failed_spr_set(spr, strerror(errno));
d67d40ea
DG		 607 }
608}
609
70b79849
DG		 610static int kvm_put_fp(CPUState *cs)
611{
612 PowerPCCPU *cpu = POWERPC_CPU(cs);
613 CPUPPCState *env = &cpu->env;
614 struct kvm_one_reg reg;
615 int i;
616 int ret;
617
618 if (env->insns_flags & PPC_FLOAT) {
619 uint64_t fpscr = env->fpscr;
620 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
621
622 reg.id = KVM_REG_PPC_FPSCR;
623 reg.addr = (uintptr_t)&fpscr;
624 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
625 if (ret < 0) {
8d83cbf1 626 trace_kvm_failed_fpscr_set(strerror(errno));
70b79849
DG		 627 return ret;
628 }
629
630 for (i = 0; i < 32; i++) {
631 uint64_t vsr[2];
ef96e3ae
MCA		 632 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
633 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849 634
e03b5686 635#if HOST_BIG_ENDIAN
ef96e3ae
MCA		 636 vsr[0] = float64_val(*fpr);
637 vsr[1] = *vsrl;
3a4b791b 638#else
ef96e3ae
MCA		 639 vsr[0] = *vsrl;
640 vsr[1] = float64_val(*fpr);
3a4b791b 641#endif
70b79849
DG		 642 reg.addr = (uintptr_t) &vsr;
643 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
644
645 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
646 if (ret < 0) {
8d83cbf1
GK		 647 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
648 strerror(errno));
70b79849
DG		 649 return ret;
650 }
651 }
652 }
653
654 if (env->insns_flags & PPC_ALTIVEC) {
655 reg.id = KVM_REG_PPC_VSCR;
656 reg.addr = (uintptr_t)&env->vscr;
657 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
658 if (ret < 0) {
8d83cbf1 659 trace_kvm_failed_vscr_set(strerror(errno));
70b79849
DG		 660 return ret;
661 }
662
663 for (i = 0; i < 32; i++) {
664 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 665 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 666 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
667 if (ret < 0) {
8d83cbf1 668 trace_kvm_failed_vr_set(i, strerror(errno));
70b79849
DG		 669 return ret;
670 }
671 }
672 }
673
674 return 0;
675}
676
677static int kvm_get_fp(CPUState *cs)
678{
679 PowerPCCPU *cpu = POWERPC_CPU(cs);
680 CPUPPCState *env = &cpu->env;
681 struct kvm_one_reg reg;
682 int i;
683 int ret;
684
685 if (env->insns_flags & PPC_FLOAT) {
686 uint64_t fpscr;
687 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
688
689 reg.id = KVM_REG_PPC_FPSCR;
690 reg.addr = (uintptr_t)&fpscr;
691 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
692 if (ret < 0) {
8d83cbf1 693 trace_kvm_failed_fpscr_get(strerror(errno));
70b79849
DG		 694 return ret;
695 } else {
696 env->fpscr = fpscr;
697 }
698
699 for (i = 0; i < 32; i++) {
700 uint64_t vsr[2];
ef96e3ae
MCA		 701 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
702 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
70b79849
DG		 703
704 reg.addr = (uintptr_t) &vsr;
705 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
706
707 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
708 if (ret < 0) {
8d83cbf1
GK		 709 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
710 strerror(errno));
70b79849
DG		 711 return ret;
712 } else {
e03b5686 713#if HOST_BIG_ENDIAN
ef96e3ae 714 *fpr = vsr[0];
70b79849 715 if (vsx) {
ef96e3ae 716 *vsrl = vsr[1];
70b79849 717 }
3a4b791b 718#else
ef96e3ae 719 *fpr = vsr[1];
3a4b791b 720 if (vsx) {
ef96e3ae 721 *vsrl = vsr[0];
3a4b791b
GK		 722 }
723#endif
70b79849
DG		 724 }
725 }
726 }
727
728 if (env->insns_flags & PPC_ALTIVEC) {
729 reg.id = KVM_REG_PPC_VSCR;
730 reg.addr = (uintptr_t)&env->vscr;
731 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
732 if (ret < 0) {
8d83cbf1 733 trace_kvm_failed_vscr_get(strerror(errno));
70b79849
DG		 734 return ret;
735 }
736
737 for (i = 0; i < 32; i++) {
738 reg.id = KVM_REG_PPC_VR(i);
ef96e3ae 739 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
70b79849
DG		 740 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
741 if (ret < 0) {
8d83cbf1 742 trace_kvm_failed_vr_get(i, strerror(errno));
70b79849
DG		 743 return ret;
744 }
745 }
746 }
747
748 return 0;
749}
750
9b00ea49
DG		 751#if defined(TARGET_PPC64)
752static int kvm_get_vpa(CPUState *cs)
753{
754 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 755 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 756 struct kvm_one_reg reg;
757 int ret;
758
759 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 760 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 761 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
762 if (ret < 0) {
8d83cbf1 763 trace_kvm_failed_vpa_addr_get(strerror(errno));
9b00ea49
DG		 764 return ret;
765 }
766
7388efaf
DG		 767 assert((uintptr_t)&spapr_cpu->slb_shadow_size
768 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 769 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 770 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 771 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
772 if (ret < 0) {
8d83cbf1 773 trace_kvm_failed_slb_get(strerror(errno));
9b00ea49
DG		 774 return ret;
775 }
776
7388efaf
DG		 777 assert((uintptr_t)&spapr_cpu->dtl_size
778 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 779 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 780 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 781 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
782 if (ret < 0) {
8d83cbf1 783 trace_kvm_failed_dtl_get(strerror(errno));
9b00ea49
DG		 784 return ret;
785 }
786
787 return 0;
788}
789
790static int kvm_put_vpa(CPUState *cs)
791{
792 PowerPCCPU *cpu = POWERPC_CPU(cs);
ce2918cb 793 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
9b00ea49
DG		 794 struct kvm_one_reg reg;
795 int ret;
796
c995e942
DG		 797 /*
798 * SLB shadow or DTL can't be registered unless a master VPA is
9b00ea49
DG		 799 * registered. That means when restoring state, if a VPA *is*
800 * registered, we need to set that up first. If not, we need to
c995e942
DG		 801 * deregister the others before deregistering the master VPA
802 */
7388efaf
DG		 803 assert(spapr_cpu->vpa_addr
804 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
9b00ea49 805
7388efaf 806 if (spapr_cpu->vpa_addr) {
9b00ea49 807 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 808 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 809 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
810 if (ret < 0) {
8d83cbf1 811 trace_kvm_failed_vpa_addr_set(strerror(errno));
9b00ea49
DG		 812 return ret;
813 }
814 }
815
7388efaf
DG		 816 assert((uintptr_t)&spapr_cpu->slb_shadow_size
817 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
9b00ea49 818 reg.id = KVM_REG_PPC_VPA_SLB;
7388efaf 819 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
9b00ea49
DG		 820 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
821 if (ret < 0) {
8d83cbf1 822 trace_kvm_failed_slb_set(strerror(errno));
9b00ea49
DG		 823 return ret;
824 }
825
7388efaf
DG		 826 assert((uintptr_t)&spapr_cpu->dtl_size
827 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
9b00ea49 828 reg.id = KVM_REG_PPC_VPA_DTL;
7388efaf 829 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
9b00ea49
DG		 830 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
831 if (ret < 0) {
8d83cbf1 832 trace_kvm_failed_dtl_set(strerror(errno));
9b00ea49
DG		 833 return ret;
834 }
835
7388efaf 836 if (!spapr_cpu->vpa_addr) {
9b00ea49 837 reg.id = KVM_REG_PPC_VPA_ADDR;
7388efaf 838 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
9b00ea49
DG		 839 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
840 if (ret < 0) {
8d83cbf1 841 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
9b00ea49
DG		 842 return ret;
843 }
844 }
845
846 return 0;
847}
848#endif /* TARGET_PPC64 */
849
e5c0d3ce 850int kvmppc_put_books_sregs(PowerPCCPU *cpu)
a7a00a72
DG		 851{
852 CPUPPCState *env = &cpu->env;
b339427c 853 struct kvm_sregs sregs = { };
a7a00a72
DG		 854 int i;
855
856 sregs.pvr = env->spr[SPR_PVR];
857
1ec26c75
GK		 858 if (cpu->vhyp) {
859 PPCVirtualHypervisorClass *vhc =
860 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
861 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
862 } else {
863 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
864 }
a7a00a72
DG		 865
866 /* Sync SLB */
867#ifdef TARGET_PPC64
868 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
869 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
870 if (env->slb[i].esid & SLB_ESID_V) {
871 sregs.u.s.ppc64.slb[i].slbe |= i;
872 }
873 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
874 }
875#endif
876
877 /* Sync SRs */
878 for (i = 0; i < 16; i++) {
879 sregs.u.s.ppc32.sr[i] = env->sr[i];
880 }
881
882 /* Sync BATs */
883 for (i = 0; i < 8; i++) {
884 /* Beware. We have to swap upper and lower bits here */
885 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
886 | env->DBAT[1][i];
887 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
888 | env->IBAT[1][i];
889 }
890
891 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
892}
893
20d695a9 894int kvm_arch_put_registers(CPUState *cs, int level)
d76d1650 895{
20d695a9
AF		 896 PowerPCCPU *cpu = POWERPC_CPU(cs);
897 CPUPPCState *env = &cpu->env;
d76d1650
AJ		 898 struct kvm_regs regs;
899 int ret;
900 int i;
901
1bc22652
AF		 902 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
903 if (ret < 0) {
d76d1650 904 return ret;
1bc22652 905 }
d76d1650
AJ		 906
907 regs.ctr = env->ctr;
908 regs.lr = env->lr;
da91a00f 909 regs.xer = cpu_read_xer(env);
d76d1650
AJ		 910 regs.msr = env->msr;
911 regs.pc = env->nip;
912
913 regs.srr0 = env->spr[SPR_SRR0];
914 regs.srr1 = env->spr[SPR_SRR1];
915
916 regs.sprg0 = env->spr[SPR_SPRG0];
917 regs.sprg1 = env->spr[SPR_SPRG1];
918 regs.sprg2 = env->spr[SPR_SPRG2];
919 regs.sprg3 = env->spr[SPR_SPRG3];
920 regs.sprg4 = env->spr[SPR_SPRG4];
921 regs.sprg5 = env->spr[SPR_SPRG5];
922 regs.sprg6 = env->spr[SPR_SPRG6];
923 regs.sprg7 = env->spr[SPR_SPRG7];
924
90dc8812
SW		 925 regs.pid = env->spr[SPR_BOOKE_PID];
926
c995e942 927 for (i = 0; i < 32; i++) {
d76d1650 928 regs.gpr[i] = env->gpr[i];
c995e942 929 }
d76d1650 930
4bddaf55
AK		 931 regs.cr = 0;
932 for (i = 0; i < 8; i++) {
933 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
934 }
935
1bc22652 936 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
c995e942 937 if (ret < 0) {
d76d1650 938 return ret;
c995e942 939 }
d76d1650 940
70b79849
DG		 941 kvm_put_fp(cs);
942
93dd5e85 943 if (env->tlb_dirty) {
1bc22652 944 kvm_sw_tlb_put(cpu);
93dd5e85
SW		 945 env->tlb_dirty = false;
946 }
947
f1af19d7 948 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
a7a00a72
DG		 949 ret = kvmppc_put_books_sregs(cpu);
950 if (ret < 0) {
f1af19d7
DG		 951 return ret;
952 }
953 }
954
955 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
d67d40ea
DG		 956 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
957 }
f1af19d7 958
d67d40ea
DG		 959 if (cap_one_reg) {
960 int i;
961
c995e942
DG		 962 /*
963 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 964 * the ONE_REG calls, but don't support the specific
965 * registers, there's a reasonable chance things will still
c995e942
DG		 966 * work, at least until we try to migrate.
967 */
d67d40ea
DG		 968 for (i = 0; i < 1024; i++) {
969 uint64_t id = env->spr_cb[i].one_reg_id;
970
971 if (id != 0) {
972 kvm_put_one_spr(cs, id, i);
973 }
f1af19d7 974 }
9b00ea49
DG		 975
976#ifdef TARGET_PPC64
ca241959 977 if (FIELD_EX64(env->msr, MSR, TS)) {
80b3f79b
AK		 978 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
979 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
980 }
981 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
982 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
983 }
984 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
985 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
986 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
987 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
988 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
989 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
990 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
991 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
992 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
993 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
994 }
995
9b00ea49
DG		 996 if (cap_papr) {
997 if (kvm_put_vpa(cs) < 0) {
8d83cbf1 998 trace_kvm_failed_put_vpa();
9b00ea49
DG		 999 }
1000 }
98a8b524
AK		 1001
1002 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576
AK		 1003
1004 if (level > KVM_PUT_RUNTIME_STATE) {
1005 kvm_put_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
1006 }
9b00ea49 1007#endif /* TARGET_PPC64 */
f1af19d7
DG		 1008 }
1009
d76d1650
AJ		 1010 return ret;
1011}
1012
c371c2e3
BB		 1013static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1014{
1015 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1016}
1017
a7a00a72
DG		 1018static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1019{
1020 CPUPPCState *env = &cpu->env;
1021 struct kvm_sregs sregs;
1022 int ret;
1023
1024 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1025 if (ret < 0) {
1026 return ret;
1027 }
1028
1029 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1030 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1031 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1032 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1033 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1034 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1035 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1036 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1037 env->spr[SPR_DECR] = sregs.u.e.dec;
1038 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1039 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1040 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1041 }
1042
1043 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1044 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1045 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1046 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1047 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1048 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1049 }
1050
1051 if (sregs.u.e.features & KVM_SREGS_E_64) {
1052 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1053 }
1054
1055 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1056 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1057 }
1058
1059 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1060 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1061 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1062 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1063 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1064 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1065 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1066 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1067 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1068 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1069 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1070 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1071 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1072 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1073 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1074 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1075 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1076 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1077 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1078 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1079 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1080 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1081 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1082 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1083 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1084 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1085 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1086 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1087 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1088 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1089 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1090 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1091 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1092
1093 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1094 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1095 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1096 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1097 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1098 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1099 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1100 }
1101
1102 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1103 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1104 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1105 }
1106
1107 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1108 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1109 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1110 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1111 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1112 }
1113 }
1114
1115 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1116 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1117 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1118 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1119 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1120 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1121 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1122 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1123 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1124 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1125 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1126 }
1127
1128 if (sregs.u.e.features & KVM_SREGS_EXP) {
1129 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1130 }
1131
1132 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1133 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1134 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1135 }
1136
1137 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1138 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1139 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1140 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1141
1142 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1143 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1144 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1145 }
1146 }
1147
1148 return 0;
1149}
1150
1151static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1152{
1153 CPUPPCState *env = &cpu->env;
1154 struct kvm_sregs sregs;
1155 int ret;
1156 int i;
1157
1158 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1159 if (ret < 0) {
1160 return ret;
1161 }
1162
e57ca75c 1163 if (!cpu->vhyp) {
a7a00a72
DG		 1164 ppc_store_sdr1(env, sregs.u.s.sdr1);
1165 }
1166
1167 /* Sync SLB */
1168#ifdef TARGET_PPC64
1169 /*
1170 * The packed SLB array we get from KVM_GET_SREGS only contains
1171 * information about valid entries. So we flush our internal copy
1172 * to get rid of stale ones, then put all valid SLB entries back
1173 * in.
1174 */
1175 memset(env->slb, 0, sizeof(env->slb));
1176 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1177 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1178 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1179 /*
1180 * Only restore valid entries
1181 */
1182 if (rb & SLB_ESID_V) {
1183 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1184 }
1185 }
1186#endif
1187
1188 /* Sync SRs */
1189 for (i = 0; i < 16; i++) {
1190 env->sr[i] = sregs.u.s.ppc32.sr[i];
1191 }
1192
1193 /* Sync BATs */
1194 for (i = 0; i < 8; i++) {
1195 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1196 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1197 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1198 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1199 }
1200
1201 return 0;
1202}
1203
20d695a9 1204int kvm_arch_get_registers(CPUState *cs)
d76d1650 1205{
20d695a9
AF		 1206 PowerPCCPU *cpu = POWERPC_CPU(cs);
1207 CPUPPCState *env = &cpu->env;
d76d1650 1208 struct kvm_regs regs;
90dc8812 1209 uint32_t cr;
138b38b6 1210 int i, ret;
d76d1650 1211
1bc22652 1212 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
c995e942 1213 if (ret < 0) {
d76d1650 1214 return ret;
c995e942 1215 }
d76d1650 1216
90dc8812
SW		 1217 cr = regs.cr;
1218 for (i = 7; i >= 0; i--) {
1219 env->crf[i] = cr & 15;
1220 cr >>= 4;
1221 }
ba5e5090 1222
d76d1650
AJ		 1223 env->ctr = regs.ctr;
1224 env->lr = regs.lr;
da91a00f 1225 cpu_write_xer(env, regs.xer);
d76d1650
AJ		 1226 env->msr = regs.msr;
1227 env->nip = regs.pc;
1228
1229 env->spr[SPR_SRR0] = regs.srr0;
1230 env->spr[SPR_SRR1] = regs.srr1;
1231
1232 env->spr[SPR_SPRG0] = regs.sprg0;
1233 env->spr[SPR_SPRG1] = regs.sprg1;
1234 env->spr[SPR_SPRG2] = regs.sprg2;
1235 env->spr[SPR_SPRG3] = regs.sprg3;
1236 env->spr[SPR_SPRG4] = regs.sprg4;
1237 env->spr[SPR_SPRG5] = regs.sprg5;
1238 env->spr[SPR_SPRG6] = regs.sprg6;
1239 env->spr[SPR_SPRG7] = regs.sprg7;
1240
90dc8812
SW		 1241 env->spr[SPR_BOOKE_PID] = regs.pid;
1242
c995e942 1243 for (i = 0; i < 32; i++) {
d76d1650 1244 env->gpr[i] = regs.gpr[i];
c995e942 1245 }
d76d1650 1246
70b79849
DG		 1247 kvm_get_fp(cs);
1248
90dc8812 1249 if (cap_booke_sregs) {
a7a00a72 1250 ret = kvmppc_get_booke_sregs(cpu);
90dc8812
SW		 1251 if (ret < 0) {
1252 return ret;
1253 }
fafc0b6a 1254 }
90dc8812 1255
90dc8812 1256 if (cap_segstate) {
a7a00a72 1257 ret = kvmppc_get_books_sregs(cpu);
90dc8812
SW		 1258 if (ret < 0) {
1259 return ret;
1260 }
fafc0b6a 1261 }
ba5e5090 1262
d67d40ea
DG		 1263 if (cap_hior) {
1264 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1265 }
1266
1267 if (cap_one_reg) {
1268 int i;
1269
c995e942
DG		 1270 /*
1271 * We deliberately ignore errors here, for kernels which have
d67d40ea
DG		 1272 * the ONE_REG calls, but don't support the specific
1273 * registers, there's a reasonable chance things will still
c995e942
DG		 1274 * work, at least until we try to migrate.
1275 */
d67d40ea
DG		 1276 for (i = 0; i < 1024; i++) {
1277 uint64_t id = env->spr_cb[i].one_reg_id;
1278
1279 if (id != 0) {
1280 kvm_get_one_spr(cs, id, i);
1281 }
1282 }
9b00ea49
DG		 1283
1284#ifdef TARGET_PPC64
ca241959 1285 if (FIELD_EX64(env->msr, MSR, TS)) {
80b3f79b
AK		 1286 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1287 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1288 }
1289 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1290 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1291 }
1292 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1293 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1294 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1295 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1296 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1297 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1298 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1300 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1301 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1302 }
1303
9b00ea49
DG		 1304 if (cap_papr) {
1305 if (kvm_get_vpa(cs) < 0) {
8d83cbf1 1306 trace_kvm_failed_get_vpa();
9b00ea49
DG		 1307 }
1308 }
98a8b524
AK		 1309
1310 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
972bd576 1311 kvm_get_one_spr(cs, KVM_REG_PPC_DPDES, SPR_DPDES);
9b00ea49 1312#endif
d67d40ea
DG		 1313 }
1314
d76d1650
AJ		 1315 return 0;
1316}
1317
1bc22652 1318int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
fc87e185
AG		 1319{
1320 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1321
1322 if (irq != PPC_INTERRUPT_EXT) {
1323 return 0;
1324 }
1325
1e8f51e8 1326 if (!kvm_enabled() || !cap_interrupt_unset) {
fc87e185
AG		 1327 return 0;
1328 }
1329
1bc22652 1330 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
fc87e185
AG		 1331
1332 return 0;
1333}
1334
20d695a9 1335void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
d76d1650 1336{
1e8f51e8 1337 return;
d76d1650
AJ		 1338}
1339
4c663752 1340MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
d76d1650 1341{
4c663752 1342 return MEMTXATTRS_UNSPECIFIED;
d76d1650
AJ		 1343}
1344
20d695a9 1345int kvm_arch_process_async_events(CPUState *cs)
0af691d7 1346{
259186a7 1347 return cs->halted;
0af691d7
MT		 1348}
1349
259186a7 1350static int kvmppc_handle_halt(PowerPCCPU *cpu)
d76d1650 1351{
259186a7
AF		 1352 CPUState *cs = CPU(cpu);
1353 CPUPPCState *env = &cpu->env;
1354
0939b8f8
VC		 1355 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1356 FIELD_EX64(env->msr, MSR, EE)) {
259186a7 1357 cs->halted = 1;
27103424 1358 cs->exception_index = EXCP_HLT;
d76d1650
AJ		 1359 }
1360
bb4ea393 1361 return 0;
d76d1650
AJ		 1362}
1363
1364/* map dcr access to existing qemu dcr emulation */
c995e942
DG		 1365static int kvmppc_handle_dcr_read(CPUPPCState *env,
1366 uint32_t dcrn, uint32_t *data)
d76d1650 1367{
c995e942 1368 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
d76d1650 1369 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
c995e942 1370 }
d76d1650 1371
bb4ea393 1372 return 0;
d76d1650
AJ		 1373}
1374
c995e942
DG		 1375static int kvmppc_handle_dcr_write(CPUPPCState *env,
1376 uint32_t dcrn, uint32_t data)
d76d1650 1377{
c995e942 1378 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
d76d1650 1379 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
c995e942 1380 }
d76d1650 1381
bb4ea393 1382 return 0;
d76d1650
AJ		 1383}
1384
8a0548f9
BB		 1385int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1386{
1387 /* Mixed endian case is not handled */
1388 uint32_t sc = debug_inst_opcode;
1389
1390 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1391 sizeof(sc), 0) ||
1392 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1393 return -EINVAL;
1394 }
1395
1396 return 0;
1397}
1398
1399int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1400{
1401 uint32_t sc;
1402
1403 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1404 sc != debug_inst_opcode ||
1405 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1406 sizeof(sc), 1)) {
1407 return -EINVAL;
1408 }
1409
1410 return 0;
1411}
1412
88365d17
BB		 1413static int find_hw_breakpoint(target_ulong addr, int type)
1414{
1415 int n;
1416
1417 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1418 <= ARRAY_SIZE(hw_debug_points));
1419
1420 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1421 if (hw_debug_points[n].addr == addr &&
1422 hw_debug_points[n].type == type) {
1423 return n;
1424 }
1425 }
1426
1427 return -1;
1428}
1429
1430static int find_hw_watchpoint(target_ulong addr, int *flag)
1431{
1432 int n;
1433
1434 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1435 if (n >= 0) {
1436 *flag = BP_MEM_ACCESS;
1437 return n;
1438 }
1439
1440 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1441 if (n >= 0) {
1442 *flag = BP_MEM_WRITE;
1443 return n;
1444 }
1445
1446 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1447 if (n >= 0) {
1448 *flag = BP_MEM_READ;
1449 return n;
1450 }
1451
1452 return -1;
1453}
1454
1455int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1456 target_ulong len, int type)
1457{
1458 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1459 return -ENOBUFS;
1460 }
1461
1462 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1463 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1464
1465 switch (type) {
1466 case GDB_BREAKPOINT_HW:
1467 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1468 return -ENOBUFS;
1469 }
1470
1471 if (find_hw_breakpoint(addr, type) >= 0) {
1472 return -EEXIST;
1473 }
1474
1475 nb_hw_breakpoint++;
1476 break;
1477
1478 case GDB_WATCHPOINT_WRITE:
1479 case GDB_WATCHPOINT_READ:
1480 case GDB_WATCHPOINT_ACCESS:
1481 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1482 return -ENOBUFS;
1483 }
1484
1485 if (find_hw_breakpoint(addr, type) >= 0) {
1486 return -EEXIST;
1487 }
1488
1489 nb_hw_watchpoint++;
1490 break;
1491
1492 default:
1493 return -ENOSYS;
1494 }
1495
1496 return 0;
1497}
1498
1499int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1500 target_ulong len, int type)
1501{
1502 int n;
1503
1504 n = find_hw_breakpoint(addr, type);
1505 if (n < 0) {
1506 return -ENOENT;
1507 }
1508
1509 switch (type) {
1510 case GDB_BREAKPOINT_HW:
1511 nb_hw_breakpoint--;
1512 break;
1513
1514 case GDB_WATCHPOINT_WRITE:
1515 case GDB_WATCHPOINT_READ:
1516 case GDB_WATCHPOINT_ACCESS:
1517 nb_hw_watchpoint--;
1518 break;
1519
1520 default:
1521 return -ENOSYS;
1522 }
1523 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1524
1525 return 0;
1526}
1527
1528void kvm_arch_remove_all_hw_breakpoints(void)
1529{
1530 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1531}
1532
8a0548f9
BB		 1533void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1534{
88365d17
BB		 1535 int n;
1536
8a0548f9
BB		 1537 /* Software Breakpoint updates */
1538 if (kvm_sw_breakpoints_active(cs)) {
1539 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1540 }
88365d17
BB		 1541
1542 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1543 <= ARRAY_SIZE(hw_debug_points));
1544 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1545
1546 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1547 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1548 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1549 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1550 switch (hw_debug_points[n].type) {
1551 case GDB_BREAKPOINT_HW:
1552 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1553 break;
1554 case GDB_WATCHPOINT_WRITE:
1555 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1556 break;
1557 case GDB_WATCHPOINT_READ:
1558 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1559 break;
1560 case GDB_WATCHPOINT_ACCESS:
1561 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1562 KVMPPC_DEBUG_WATCH_READ;
1563 break;
1564 default:
1565 cpu_abort(cs, "Unsupported breakpoint type\n");
1566 }
1567 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1568 }
1569 }
8a0548f9
BB		 1570}
1571
2cbd1581
FR		 1572static int kvm_handle_hw_breakpoint(CPUState *cs,
1573 struct kvm_debug_exit_arch *arch_info)
1574{
6e0552a3 1575 int handle = DEBUG_RETURN_GUEST;
2cbd1581
FR		 1576 int n;
1577 int flag = 0;
1578
1579 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1580 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1581 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1582 if (n >= 0) {
6e0552a3 1583 handle = DEBUG_RETURN_GDB;
2cbd1581
FR		 1584 }
1585 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1586 KVMPPC_DEBUG_WATCH_WRITE)) {
1587 n = find_hw_watchpoint(arch_info->address, &flag);
1588 if (n >= 0) {
6e0552a3 1589 handle = DEBUG_RETURN_GDB;
2cbd1581
FR		 1590 cs->watchpoint_hit = &hw_watchpoint;
1591 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1592 hw_watchpoint.flags = flag;
1593 }
1594 }
1595 }
1596 return handle;
1597}
1598
468e3a1a
FR		 1599static int kvm_handle_singlestep(void)
1600{
6e0552a3 1601 return DEBUG_RETURN_GDB;
468e3a1a
FR		 1602}
1603
1604static int kvm_handle_sw_breakpoint(void)
1605{
6e0552a3 1606 return DEBUG_RETURN_GDB;
468e3a1a
FR		 1607}
1608
8a0548f9
BB		 1609static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1610{
1611 CPUState *cs = CPU(cpu);
1612 CPUPPCState *env = &cpu->env;
1613 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
8a0548f9 1614
88365d17 1615 if (cs->singlestep_enabled) {
468e3a1a
FR		 1616 return kvm_handle_singlestep();
1617 }
8a0548f9 1618
468e3a1a
FR		 1619 if (arch_info->status) {
1620 return kvm_handle_hw_breakpoint(cs, arch_info);
8a0548f9
BB		 1621 }
1622
468e3a1a
FR		 1623 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1624 return kvm_handle_sw_breakpoint();
1625 }
1626
1627 /*
1628 * QEMU is not able to handle debug exception, so inject
1629 * program exception to guest;
1630 * Yes program exception NOT debug exception !!
1631 * When QEMU is using debug resources then debug exception must
1632 * be always set. To achieve this we set MSR_DE and also set
1633 * MSRP_DEP so guest cannot change MSR_DE.
1634 * When emulating debug resource for guest we want guest
1635 * to control MSR_DE (enable/disable debug interrupt on need).
1636 * Supporting both configurations are NOT possible.
1637 * So the result is that we cannot share debug resources
1638 * between QEMU and Guest on BOOKE architecture.
1639 * In the current design QEMU gets the priority over guest,
1640 * this means that if QEMU is using debug resources then guest
1641 * cannot use them;
1642 * For software breakpoint QEMU uses a privileged instruction;
1643 * So there cannot be any reason that we are here for guest
1644 * set debug exception, only possibility is guest executed a
1645 * privileged / illegal instruction and that's why we are
1646 * injecting a program interrupt.
1647 */
1648 cpu_synchronize_state(cs);
1649 /*
1650 * env->nip is PC, so increment this by 4 to use
1651 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1652 */
1653 env->nip += 4;
1654 cs->exception_index = POWERPC_EXCP_PROGRAM;
1655 env->error_code = POWERPC_EXCP_INVAL;
1656 ppc_cpu_do_interrupt(cs);
1657
6e0552a3 1658 return DEBUG_RETURN_GUEST;
8a0548f9
BB		 1659}
1660
20d695a9 1661int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
d76d1650 1662{
20d695a9
AF		 1663 PowerPCCPU *cpu = POWERPC_CPU(cs);
1664 CPUPPCState *env = &cpu->env;
bb4ea393 1665 int ret;
d76d1650 1666
4b8523ee
JK		 1667 qemu_mutex_lock_iothread();
1668
d76d1650
AJ		 1669 switch (run->exit_reason) {
1670 case KVM_EXIT_DCR:
1671 if (run->dcr.is_write) {
8d83cbf1 1672 trace_kvm_handle_dcr_write();
d76d1650
AJ		 1673 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1674 } else {
228152c2 1675 trace_kvm_handle_dcr_read();
d76d1650
AJ		 1676 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1677 }
1678 break;
1679 case KVM_EXIT_HLT:
8d83cbf1 1680 trace_kvm_handle_halt();
259186a7 1681 ret = kvmppc_handle_halt(cpu);
d76d1650 1682 break;
c6304a4a 1683#if defined(TARGET_PPC64)
f61b4bed 1684 case KVM_EXIT_PAPR_HCALL:
f290a238 1685 trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
20d695a9 1686 run->papr_hcall.ret = spapr_hypercall(cpu,
aa100fa4 1687 run->papr_hcall.nr,
f61b4bed 1688 run->papr_hcall.args);
78e8fde2 1689 ret = 0;
f61b4bed
AG		 1690 break;
1691#endif
5b95b8b9 1692 case KVM_EXIT_EPR:
8d83cbf1 1693 trace_kvm_handle_epr();
933b19ea 1694 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
5b95b8b9
AG		 1695 ret = 0;
1696 break;
31f2cb8f 1697 case KVM_EXIT_WATCHDOG:
8d83cbf1 1698 trace_kvm_handle_watchdog_expiry();
31f2cb8f
BB		 1699 watchdog_perform_action();
1700 ret = 0;
1701 break;
1702
8a0548f9 1703 case KVM_EXIT_DEBUG:
8d83cbf1 1704 trace_kvm_handle_debug_exception();
8a0548f9
BB		 1705 if (kvm_handle_debug(cpu, run)) {
1706 ret = EXCP_DEBUG;
1707 break;
1708 }
1709 /* re-enter, this exception was guest-internal */
1710 ret = 0;
1711 break;
1712
9ac703ac
AP		 1713#if defined(TARGET_PPC64)
1714 case KVM_EXIT_NMI:
1715 trace_kvm_handle_nmi_exception();
1716 ret = kvm_handle_nmi(cpu, run);
1717 break;
1718#endif
1719
73aaec4a
JK		 1720 default:
1721 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1722 ret = -1;
1723 break;
d76d1650
AJ		 1724 }
1725
4b8523ee 1726 qemu_mutex_unlock_iothread();
d76d1650
AJ		 1727 return ret;
1728}
1729
31f2cb8f
BB		 1730int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1731{
1732 CPUState *cs = CPU(cpu);
1733 uint32_t bits = tsr_bits;
1734 struct kvm_one_reg reg = {
1735 .id = KVM_REG_PPC_OR_TSR,
1736 .addr = (uintptr_t) &bits,
1737 };
1738
1739 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1740}
1741
1742int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1743{
1744
1745 CPUState *cs = CPU(cpu);
1746 uint32_t bits = tsr_bits;
1747 struct kvm_one_reg reg = {
1748 .id = KVM_REG_PPC_CLEAR_TSR,
1749 .addr = (uintptr_t) &bits,
1750 };
1751
1752 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1753}
1754
1755int kvmppc_set_tcr(PowerPCCPU *cpu)
1756{
1757 CPUState *cs = CPU(cpu);
1758 CPUPPCState *env = &cpu->env;
1759 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1760
1761 struct kvm_one_reg reg = {
1762 .id = KVM_REG_PPC_TCR,
1763 .addr = (uintptr_t) &tcr,
1764 };
1765
1766 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1767}
1768
1769int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1770{
1771 CPUState *cs = CPU(cpu);
31f2cb8f
BB		 1772 int ret;
1773
1774 if (!kvm_enabled()) {
1775 return -1;
1776 }
1777
1778 if (!cap_ppc_watchdog) {
1779 printf("warning: KVM does not support watchdog");
1780 return -1;
1781 }
1782
48add816 1783 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
31f2cb8f
BB		 1784 if (ret < 0) {
1785 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1786 __func__, strerror(-ret));
1787 return ret;
1788 }
1789
1790 return ret;
1791}
1792
dc333cd6
AG		 1793static int read_cpuinfo(const char *field, char *value, int len)
1794{
1795 FILE *f;
1796 int ret = -1;
1797 int field_len = strlen(field);
1798 char line[512];
1799
1800 f = fopen("/proc/cpuinfo", "r");
1801 if (!f) {
1802 return -1;
1803 }
1804
1805 do {
ef951443 1806 if (!fgets(line, sizeof(line), f)) {
dc333cd6
AG		 1807 break;
1808 }
1809 if (!strncmp(line, field, field_len)) {
ae215068 1810 pstrcpy(value, len, line);
dc333cd6
AG		 1811 ret = 0;
1812 break;
1813 }
c995e942 1814 } while (*line);
dc333cd6
AG		 1815
1816 fclose(f);
1817
1818 return ret;
1819}
1820
9cbcfb59 1821static uint32_t kvmppc_get_tbfreq_procfs(void)
dc333cd6
AG		 1822{
1823 char line[512];
1824 char *ns;
9cbcfb59
GK		 1825 uint32_t tbfreq_fallback = NANOSECONDS_PER_SECOND;
1826 uint32_t tbfreq_procfs;
dc333cd6
AG		 1827
1828 if (read_cpuinfo("timebase", line, sizeof(line))) {
9cbcfb59 1829 return tbfreq_fallback;
dc333cd6
AG		 1830 }
1831
c995e942
DG		 1832 ns = strchr(line, ':');
1833 if (!ns) {
9cbcfb59 1834 return tbfreq_fallback;
dc333cd6
AG		 1835 }
1836
9cbcfb59
GK		 1837 tbfreq_procfs = atoi(++ns);
1838
1839 /* 0 is certainly not acceptable by the guest, return fallback value */
1840 return tbfreq_procfs ? tbfreq_procfs : tbfreq_fallback;
1841}
1842
1843uint32_t kvmppc_get_tbfreq(void)
1844{
1845 static uint32_t cached_tbfreq;
1846
1847 if (!cached_tbfreq) {
1848 cached_tbfreq = kvmppc_get_tbfreq_procfs();
1849 }
dc333cd6 1850
9cbcfb59 1851 return cached_tbfreq;
dc333cd6 1852}
4513d923 1853
ef951443
ND		 1854bool kvmppc_get_host_serial(char **value)
1855{
1856 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1857 NULL);
1858}
1859
1860bool kvmppc_get_host_model(char **value)
1861{
1862 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1863}
1864
eadaada1
AG		 1865/* Try to find a device tree node for a CPU with clock-frequency property */
1866static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1867{
1868 struct dirent *dirp;
1869 DIR *dp;
1870
c995e942
DG		 1871 dp = opendir(PROC_DEVTREE_CPU);
1872 if (!dp) {
eadaada1
AG		 1873 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1874 return -1;
1875 }
1876
1877 buf[0] = '\0';
1878 while ((dirp = readdir(dp)) != NULL) {
1879 FILE *f;
1880 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1881 dirp->d_name);
1882 f = fopen(buf, "r");
1883 if (f) {
1884 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1885 fclose(f);
1886 break;
1887 }
1888 buf[0] = '\0';
1889 }
1890 closedir(dp);
1891 if (buf[0] == '\0') {
1892 printf("Unknown host!\n");
1893 return -1;
1894 }
1895
1896 return 0;
1897}
1898
7d94a30b 1899static uint64_t kvmppc_read_int_dt(const char *filename)
eadaada1 1900{
9bc884b7
DG		 1901 union {
1902 uint32_t v32;
1903 uint64_t v64;
1904 } u;
eadaada1
AG		 1905 FILE *f;
1906 int len;
1907
7d94a30b 1908 f = fopen(filename, "rb");
eadaada1
AG		 1909 if (!f) {
1910 return -1;
1911 }
1912
9bc884b7 1913 len = fread(&u, 1, sizeof(u), f);
eadaada1
AG		 1914 fclose(f);
1915 switch (len) {
9bc884b7
DG		 1916 case 4:
1917 /* property is a 32-bit quantity */
1918 return be32_to_cpu(u.v32);
1919 case 8:
1920 return be64_to_cpu(u.v64);
eadaada1
AG		 1921 }
1922
1923 return 0;
1924}
1925
c995e942
DG		 1926/*
1927 * Read a CPU node property from the host device tree that's a single
7d94a30b 1928 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
c995e942
DG		 1929 * (can't find or open the property, or doesn't understand the format)
1930 */
7d94a30b
SB		 1931static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1932{
1933 char buf[PATH_MAX], *tmp;
1934 uint64_t val;
1935
1936 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1937 return -1;
1938 }
1939
1940 tmp = g_strdup_printf("%s/%s", buf, propname);
1941 val = kvmppc_read_int_dt(tmp);
1942 g_free(tmp);
1943
1944 return val;
1945}
1946
9bc884b7
DG		 1947uint64_t kvmppc_get_clockfreq(void)
1948{
1949 return kvmppc_read_int_cpu_dt("clock-frequency");
1950}
1951
7d050527
SJS		 1952static int kvmppc_get_dec_bits(void)
1953{
1954 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1955
1956 if (nr_bits > 0) {
1957 return nr_bits;
1958 }
1959 return 0;
1960}
1961
1a61a9ae 1962static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
db70b311
RH		 1963{
1964 CPUState *cs = env_cpu(env);
1a61a9ae 1965
6fd33a75 1966 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
1a61a9ae
SY		 1967 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
1968 return 0;
1969 }
1970
1971 return 1;
1972}
1973
1974int kvmppc_get_hasidle(CPUPPCState *env)
1975{
1976 struct kvm_ppc_pvinfo pvinfo;
1977
1978 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
1979 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
1980 return 1;
1981 }
1982
1983 return 0;
1984}
1985
1328c2bf 1986int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
45024f09 1987{
c995e942 1988 uint32_t *hc = (uint32_t *)buf;
45024f09
AG		 1989 struct kvm_ppc_pvinfo pvinfo;
1990
1a61a9ae 1991 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
45024f09 1992 memcpy(buf, pvinfo.hcall, buf_len);
45024f09
AG		 1993 return 0;
1994 }
45024f09
AG		 1995
1996 /*
d13fc32e 1997 * Fallback to always fail hypercalls regardless of endianness:
45024f09 1998 *
d13fc32e 1999 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
45024f09 2000 * li r3, -1
d13fc32e
AG		 2001 * b .+8 (becomes nop in wrong endian)
2002 * bswap32(li r3, -1)
45024f09
AG		 2003 */
2004
d13fc32e
AG		 2005 hc[0] = cpu_to_be32(0x08000048);
2006 hc[1] = cpu_to_be32(0x3860ffff);
2007 hc[2] = cpu_to_be32(0x48000008);
2008 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
45024f09 2009
0ddbd053 2010 return 1;
45024f09
AG		 2011}
2012
026bfd89
DG		 2013static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2014{
2015 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2016}
2017
2018void kvmppc_enable_logical_ci_hcalls(void)
2019{
2020 /*
2021 * FIXME: it would be nice if we could detect the cases where
2022 * we're using a device which requires the in kernel
2023 * implementation of these hcalls, but the kernel lacks them and
2024 * produce a warning.
2025 */
2026 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2027 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2028}
2029
ef9971dd
AK		 2030void kvmppc_enable_set_mode_hcall(void)
2031{
2032 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2033}
2034
5145ad4f
NW		 2035void kvmppc_enable_clear_ref_mod_hcalls(void)
2036{
2037 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2038 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2039}
2040
68f9f708
SJS		 2041void kvmppc_enable_h_page_init(void)
2042{
2043 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2044}
2045
82123b75
BR		 2046void kvmppc_enable_h_rpt_invalidate(void)
2047{
2048 kvmppc_enable_hcall(kvm_state, H_RPT_INVALIDATE);
2049}
2050
1bc22652 2051void kvmppc_set_papr(PowerPCCPU *cpu)
f61b4bed 2052{
1bc22652 2053 CPUState *cs = CPU(cpu);
f61b4bed
AG		 2054 int ret;
2055
da20aed1
DG		 2056 if (!kvm_enabled()) {
2057 return;
2058 }
2059
48add816 2060 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
f61b4bed 2061 if (ret) {
072ed5f2
TH		 2062 error_report("This vCPU type or KVM version does not support PAPR");
2063 exit(1);
94135e81 2064 }
9b00ea49 2065
c995e942
DG		 2066 /*
2067 * Update the capability flag so we sync the right information
2068 * with kvm
2069 */
9b00ea49 2070 cap_papr = 1;
f61b4bed
AG		 2071}
2072
d6e166c0 2073int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
6db5bb0f 2074{
d6e166c0 2075 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
6db5bb0f
AK		 2076}
2077
5b95b8b9
AG		 2078void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2079{
5b95b8b9 2080 CPUState *cs = CPU(cpu);
5b95b8b9
AG		 2081 int ret;
2082
48add816 2083 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
5b95b8b9 2084 if (ret && mpic_proxy) {
072ed5f2
TH		 2085 error_report("This KVM version does not support EPR");
2086 exit(1);
5b95b8b9
AG		 2087 }
2088}
2089
ec010c00
NP		 2090bool kvmppc_get_fwnmi(void)
2091{
2092 return cap_fwnmi;
2093}
2094
aef92d87 2095int kvmppc_set_fwnmi(PowerPCCPU *cpu)
9d953ce4 2096{
9d953ce4
AP		 2097 CPUState *cs = CPU(cpu);
2098
2099 return kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_FWNMI, 0);
2100}
2101
e97c3636
DG		 2102int kvmppc_smt_threads(void)
2103{
2104 return cap_ppc_smt ? cap_ppc_smt : 1;
2105}
2106
fa98fbfc
SB		 2107int kvmppc_set_smt_threads(int smt)
2108{
2109 int ret;
2110
2111 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2112 if (!ret) {
2113 cap_ppc_smt = smt;
2114 }
2115 return ret;
2116}
2117
0c115681 2118void kvmppc_error_append_smt_possible_hint(Error *const *errp)
fa98fbfc
SB		 2119{
2120 int i;
2121 GString *g;
2122 char *s;
2123
2124 assert(kvm_enabled());
2125 if (cap_ppc_smt_possible) {
2126 g = g_string_new("Available VSMT modes:");
2127 for (i = 63; i >= 0; i--) {
2128 if ((1UL << i) & cap_ppc_smt_possible) {
2129 g_string_append_printf(g, " %lu", (1UL << i));
2130 }
2131 }
2132 s = g_string_free(g, false);
1a639fdf 2133 error_append_hint(errp, "%s.\n", s);
fa98fbfc
SB		 2134 g_free(s);
2135 } else {
1a639fdf 2136 error_append_hint(errp,
fa98fbfc
SB		 2137 "This KVM seems to be too old to support VSMT.\n");
2138 }
2139}
2140
2141
7f763a5d 2142#ifdef TARGET_PPC64
6a84737c 2143uint64_t kvmppc_vrma_limit(unsigned int hash_shift)
7f763a5d 2144{
f36951c1
DG		 2145 struct kvm_ppc_smmu_info info;
2146 long rampagesize, best_page_shift;
2147 int i;
2148
c995e942
DG		 2149 /*
2150 * Find the largest hardware supported page size that's less than
2151 * or equal to the (logical) backing page size of guest RAM
2152 */
ab256960 2153 kvm_get_smmu_info(&info, &error_fatal);
905b7ee4 2154 rampagesize = qemu_minrampagesize();
f36951c1
DG		 2155 best_page_shift = 0;
2156
2157 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2158 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2159
2160 if (!sps->page_shift) {
2161 continue;
2162 }
2163
2164 if ((sps->page_shift > best_page_shift)
2165 && ((1UL << sps->page_shift) <= rampagesize)) {
2166 best_page_shift = sps->page_shift;
2167 }
2168 }
2169
6a84737c 2170 return 1ULL << (best_page_shift + hash_shift - 7);
7f763a5d
DG		 2171}
2172#endif
2173
da95324e
AK		 2174bool kvmppc_spapr_use_multitce(void)
2175{
2176 return cap_spapr_multitce;
2177}
2178
3dc410ae
AK		 2179int kvmppc_spapr_enable_inkernel_multitce(void)
2180{
2181 int ret;
2182
2183 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2184 H_PUT_TCE_INDIRECT, 1);
2185 if (!ret) {
2186 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2187 H_STUFF_TCE, 1);
2188 }
2189
2190 return ret;
2191}
2192
d6ee2a7c
AK		 2193void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2194 uint64_t bus_offset, uint32_t nb_table,
2195 int *pfd, bool need_vfio)
0f5cb298 2196{
0f5cb298
DG		 2197 long len;
2198 int fd;
2199 void *table;
2200
c995e942
DG		 2201 /*
2202 * Must set fd to -1 so we don't try to munmap when called for
b5aec396
DG		 2203 * destroying the table, which the upper layers -will- do
2204 */
2205 *pfd = -1;
6a81dd17 2206 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
0f5cb298
DG		 2207 return NULL;
2208 }
2209
d6ee2a7c
AK		 2210 if (cap_spapr_tce_64) {
2211 struct kvm_create_spapr_tce_64 args = {
2212 .liobn = liobn,
2213 .page_shift = page_shift,
2214 .offset = bus_offset >> page_shift,
2215 .size = nb_table,
2216 .flags = 0
2217 };
2218 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2219 if (fd < 0) {
2220 fprintf(stderr,
2221 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2222 liobn);
2223 return NULL;
2224 }
2225 } else if (cap_spapr_tce) {
2226 uint64_t window_size = (uint64_t) nb_table << page_shift;
2227 struct kvm_create_spapr_tce args = {
2228 .liobn = liobn,
2229 .window_size = window_size,
2230 };
2231 if ((window_size != args.window_size) || bus_offset) {
2232 return NULL;
2233 }
2234 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2235 if (fd < 0) {
2236 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2237 liobn);
2238 return NULL;
2239 }
2240 } else {
0f5cb298
DG		 2241 return NULL;
2242 }
2243
d6ee2a7c 2244 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2245 /* FIXME: round this up to page size */
2246
c995e942 2247 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
0f5cb298 2248 if (table == MAP_FAILED) {
b5aec396
DG		 2249 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2250 liobn);
0f5cb298
DG		 2251 close(fd);
2252 return NULL;
2253 }
2254
2255 *pfd = fd;
2256 return table;
2257}
2258
523e7b8a 2259int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
0f5cb298
DG		 2260{
2261 long len;
2262
2263 if (fd < 0) {
2264 return -1;
2265 }
2266
523e7b8a 2267 len = nb_table * sizeof(uint64_t);
0f5cb298
DG		 2268 if ((munmap(table, len) < 0) ||
2269 (close(fd) < 0)) {
b5aec396
DG		 2270 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2271 strerror(errno));
0f5cb298
DG		 2272 /* Leak the table */
2273 }
2274
2275 return 0;
2276}
2277
7f763a5d
DG		 2278int kvmppc_reset_htab(int shift_hint)
2279{
2280 uint32_t shift = shift_hint;
2281
ace9a2cb
DG		 2282 if (!kvm_enabled()) {
2283 /* Full emulation, tell caller to allocate htab itself */
2284 return 0;
2285 }
6977afda 2286 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
7f763a5d
DG		 2287 int ret;
2288 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
ace9a2cb 2289 if (ret == -ENOTTY) {
c995e942
DG		 2290 /*
2291 * At least some versions of PR KVM advertise the
ace9a2cb
DG		 2292 * capability, but don't implement the ioctl(). Oops.
2293 * Return 0 so that we allocate the htab in qemu, as is
c995e942
DG		 2294 * correct for PR.
2295 */
ace9a2cb
DG		 2296 return 0;
2297 } else if (ret < 0) {
7f763a5d
DG		 2298 return ret;
2299 }
2300 return shift;
2301 }
2302
c995e942
DG		 2303 /*
2304 * We have a kernel that predates the htab reset calls. For PR
ace9a2cb 2305 * KVM, we need to allocate the htab ourselves, for an HV KVM of
c995e942
DG		 2306 * this era, it has allocated a 16MB fixed size hash table
2307 * already.
2308 */
96c9cff0 2309 if (kvmppc_is_pr(kvm_state)) {
ace9a2cb
DG		 2310 /* PR - tell caller to allocate htab */
2311 return 0;
2312 } else {
2313 /* HV - assume 16MB kernel allocated htab */
2314 return 24;
2315 }
7f763a5d
DG		 2316}
2317
a1e98583
DG		 2318static inline uint32_t mfpvr(void)
2319{
2320 uint32_t pvr;
2321
2322 asm ("mfpvr %0"
2323 : "=r"(pvr));
2324 return pvr;
2325}
2326
a7342588
DG		 2327static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2328{
2329 if (on) {
2330 *word |= flags;
2331 } else {
2332 *word &= ~flags;
2333 }
2334}
2335
2985b86b
AF		 2336static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2337{
2338 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
0cbad81f
DG		 2339 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2340 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
a1e98583 2341
cfe34f44 2342 /* Now fix up the class with information we can query from the host */
3bc9ccc0 2343 pcc->pvr = mfpvr();
a7342588 2344
3f2ca480
DG		 2345 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2346 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2347 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2348 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2349 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2350 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
0cbad81f
DG		 2351
2352 if (dcache_size != -1) {
2353 pcc->l1_dcache_size = dcache_size;
2354 }
2355
2356 if (icache_size != -1) {
2357 pcc->l1_icache_size = icache_size;
2358 }
c64abd1f
SB		 2359
2360#if defined(TARGET_PPC64)
2361 pcc->radix_page_info = kvm_get_radix_page_info();
5f3066d8
DG		 2362
2363 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2364 /*
2365 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2366 * compliant. More importantly, advertising ISA 3.00
2367 * architected mode may prevent guests from activating
2368 * necessary DD1 workarounds.
2369 */
2370 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2371 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2372 }
c64abd1f 2373#endif /* defined(TARGET_PPC64) */
a1e98583
DG		 2374}
2375
3b961124
SY		 2376bool kvmppc_has_cap_epr(void)
2377{
2378 return cap_epr;
2379}
2380
87a91de6
AG		 2381bool kvmppc_has_cap_fixup_hcalls(void)
2382{
2383 return cap_fixup_hcalls;
2384}
2385
bac3bf28
TH		 2386bool kvmppc_has_cap_htm(void)
2387{
2388 return cap_htm;
2389}
2390
cf1c4cce
SB		 2391bool kvmppc_has_cap_mmu_radix(void)
2392{
2393 return cap_mmu_radix;
2394}
2395
2396bool kvmppc_has_cap_mmu_hash_v3(void)
2397{
2398 return cap_mmu_hash_v3;
2399}
2400
072f416a
SJS		 2401static bool kvmppc_power8_host(void)
2402{
2403 bool ret = false;
2404#ifdef TARGET_PPC64
2405 {
2406 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2407 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2408 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2409 (base_pvr == CPU_POWERPC_POWER8_BASE);
2410 }
2411#endif /* TARGET_PPC64 */
2412 return ret;
2413}
2414
8fea7044
SJS		 2415static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2416{
072f416a
SJS		 2417 bool l1d_thread_priv_req = !kvmppc_power8_host();
2418
8fea7044
SJS		 2419 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2420 return 2;
072f416a
SJS		 2421 } else if ((!l1d_thread_priv_req ||
2422 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
8fea7044
SJS		 2423 (c.character & c.character_mask
2424 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2425 return 1;
2426 }
2427
2428 return 0;
2429}
2430
2431static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2432{
2433 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2434 return 2;
2435 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2436 return 1;
2437 }
2438
2439 return 0;
2440}
2441
2442static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2443{
399b2896
SJS		 2444 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2445 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2446 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2447 return SPAPR_CAP_FIXED_NA;
2448 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2449 return SPAPR_CAP_WORKAROUND;
2450 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
8fea7044
SJS		 2451 return SPAPR_CAP_FIXED_CCD;
2452 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2453 return SPAPR_CAP_FIXED_IBS;
2454 }
2455
2456 return 0;
2457}
2458
8ff43ee4
SJS		 2459static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2460{
2461 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2462 return 1;
2463 }
2464 return 0;
2465}
2466
38afd772
CLG		 2467bool kvmppc_has_cap_xive(void)
2468{
2469 return cap_xive;
2470}
2471
8acc2ae5
SJS		 2472static void kvmppc_get_cpu_characteristics(KVMState *s)
2473{
2474 struct kvm_ppc_cpu_char c;
2475 int ret;
2476
2477 /* Assume broken */
2478 cap_ppc_safe_cache = 0;
2479 cap_ppc_safe_bounds_check = 0;
2480 cap_ppc_safe_indirect_branch = 0;
2481
2482 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2483 if (!ret) {
2484 return;
2485 }
2486 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2487 if (ret < 0) {
2488 return;
2489 }
8fea7044
SJS		 2490
2491 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2492 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2493 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
8ff43ee4
SJS		 2494 cap_ppc_count_cache_flush_assist =
2495 parse_cap_ppc_count_cache_flush_assist(c);
8acc2ae5
SJS		 2496}
2497
2498int kvmppc_get_cap_safe_cache(void)
2499{
2500 return cap_ppc_safe_cache;
2501}
2502
2503int kvmppc_get_cap_safe_bounds_check(void)
2504{
2505 return cap_ppc_safe_bounds_check;
2506}
2507
2508int kvmppc_get_cap_safe_indirect_branch(void)
2509{
2510 return cap_ppc_safe_indirect_branch;
2511}
2512
8ff43ee4
SJS		 2513int kvmppc_get_cap_count_cache_flush_assist(void)
2514{
2515 return cap_ppc_count_cache_flush_assist;
2516}
2517
b9a477b7
SJS		 2518bool kvmppc_has_cap_nested_kvm_hv(void)
2519{
2520 return !!cap_ppc_nested_kvm_hv;
2521}
2522
2523int kvmppc_set_cap_nested_kvm_hv(int enable)
2524{
2525 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2526}
2527
9ded780c
AK		 2528bool kvmppc_has_cap_spapr_vfio(void)
2529{
2530 return cap_spapr_vfio;
2531}
2532
7d050527
SJS		 2533int kvmppc_get_cap_large_decr(void)
2534{
2535 return cap_large_decr;
2536}
2537
2538int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2539{
2540 CPUState *cs = CPU(cpu);
59411579 2541 uint64_t lpcr = 0;
7d050527
SJS		 2542
2543 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2544 /* Do we need to modify the LPCR? */
2545 if (!!(lpcr & LPCR_LD) != !!enable) {
2546 if (enable) {
2547 lpcr |= LPCR_LD;
2548 } else {
2549 lpcr &= ~LPCR_LD;
2550 }
2551 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2552 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2553
2554 if (!!(lpcr & LPCR_LD) != !!enable) {
2555 return -1;
2556 }
2557 }
2558
2559 return 0;
2560}
2561
82123b75
BR		 2562int kvmppc_has_cap_rpt_invalidate(void)
2563{
2564 return cap_rpt_invalidate;
2565}
2566
52b2519c
TH		 2567PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2568{
2569 uint32_t host_pvr = mfpvr();
2570 PowerPCCPUClass *pvr_pcc;
2571
2572 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2573 if (pvr_pcc == NULL) {
2574 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2575 }
2576
2577 return pvr_pcc;
2578}
2579
165dc3ed
DG		 2580static void pseries_machine_class_fixup(ObjectClass *oc, void *opaque)
2581{
2582 MachineClass *mc = MACHINE_CLASS(oc);
2583
2584 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2585}
2586
2587static int kvm_ppc_register_host_cpu_type(void)
5ba4576b
AF		 2588{
2589 TypeInfo type_info = {
2590 .name = TYPE_HOST_POWERPC_CPU,
5ba4576b
AF		 2591 .class_init = kvmppc_host_cpu_class_init,
2592 };
5ba4576b 2593 PowerPCCPUClass *pvr_pcc;
92e926e1 2594 ObjectClass *oc;
5b79b1ca 2595 DeviceClass *dc;
715d4b96 2596 int i;
5ba4576b 2597
52b2519c 2598 pvr_pcc = kvm_ppc_get_host_cpu_class();
5ba4576b
AF		 2599 if (pvr_pcc == NULL) {
2600 return -1;
2601 }
2602 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2603 type_register(&type_info);
165dc3ed
DG		 2604 /* override TCG default cpu type with 'host' cpu model */
2605 object_class_foreach(pseries_machine_class_fixup, TYPE_SPAPR_MACHINE,
2606 false, NULL);
5b79b1ca 2607
92e926e1
GK		 2608 oc = object_class_by_name(type_info.name);
2609 g_assert(oc);
2610
715d4b96
TH		 2611 /*
2612 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2613 * we want "POWER8" to be a "family" alias that points to the current
2614 * host CPU type, too)
2615 */
2616 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2617 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
c5354f54 2618 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
715d4b96
TH		 2619 char *suffix;
2620
2621 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
c9137065 2622 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
715d4b96
TH		 2623 if (suffix) {
2624 *suffix = 0;
2625 }
715d4b96
TH		 2626 break;
2627 }
2628 }
2629
5ba4576b
AF		 2630 return 0;
2631}
2632
feaa64c4
DG		 2633int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2634{
2635 struct kvm_rtas_token_args args = {
2636 .token = token,
2637 };
2638
2639 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2640 return -ENOENT;
2641 }
2642
7701aeed 2643 strncpy(args.name, function, sizeof(args.name) - 1);
feaa64c4
DG		 2644
2645 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2646}
12b1143b 2647
14b0d748 2648int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
e68cb8b4
AK		 2649{
2650 struct kvm_get_htab_fd s = {
2651 .flags = write ? KVM_GET_HTAB_WRITE : 0,
14b0d748 2652 .start_index = index,
e68cb8b4 2653 };
82be8e73 2654 int ret;
e68cb8b4
AK		 2655
2656 if (!cap_htab_fd) {
14b0d748
GK		 2657 error_setg(errp, "KVM version doesn't support %s the HPT",
2658 write ? "writing" : "reading");
82be8e73
GK		 2659 return -ENOTSUP;
2660 }
2661
2662 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2663 if (ret < 0) {
14b0d748
GK		 2664 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2665 write ? "writing" : "reading", write ? "to" : "from",
2666 strerror(errno));
82be8e73 2667 return -errno;
e68cb8b4
AK		 2668 }
2669
82be8e73 2670 return ret;
e68cb8b4
AK		 2671}
2672
2673int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2674{
bc72ad67 2675 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
e68cb8b4
AK		 2676 uint8_t buf[bufsize];
2677 ssize_t rc;
2678
2679 do {
2680 rc = read(fd, buf, bufsize);
2681 if (rc < 0) {
2682 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2683 strerror(errno));
2684 return rc;
2685 } else if (rc) {
e094c4c1
CLG		 2686 uint8_t *buffer = buf;
2687 ssize_t n = rc;
2688 while (n) {
2689 struct kvm_get_htab_header *head =
2690 (struct kvm_get_htab_header *) buffer;
2691 size_t chunksize = sizeof(*head) +
2692 HASH_PTE_SIZE_64 * head->n_valid;
2693
2694 qemu_put_be32(f, head->index);
2695 qemu_put_be16(f, head->n_valid);
2696 qemu_put_be16(f, head->n_invalid);
2697 qemu_put_buffer(f, (void *)(head + 1),
2698 HASH_PTE_SIZE_64 * head->n_valid);
2699
2700 buffer += chunksize;
2701 n -= chunksize;
2702 }
e68cb8b4
AK		 2703 }
2704 } while ((rc != 0)
c995e942
DG		 2705 && ((max_ns < 0) ||
2706 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
e68cb8b4
AK		 2707
2708 return (rc == 0) ? 1 : 0;
2709}
2710
2711int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
0a06e4d6 2712 uint16_t n_valid, uint16_t n_invalid, Error **errp)
e68cb8b4
AK		 2713{
2714 struct kvm_get_htab_header *buf;
c995e942 2715 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
e68cb8b4
AK		 2716 ssize_t rc;
2717
2718 buf = alloca(chunksize);
e68cb8b4
AK		 2719 buf->index = index;
2720 buf->n_valid = n_valid;
2721 buf->n_invalid = n_invalid;
2722
c995e942 2723 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
e68cb8b4
AK		 2724
2725 rc = write(fd, buf, chunksize);
2726 if (rc < 0) {
0a06e4d6
GK		 2727 error_setg_errno(errp, errno, "Error writing the KVM hash table");
2728 return -errno;
e68cb8b4
AK		 2729 }
2730 if (rc != chunksize) {
2731 /* We should never get a short write on a single chunk */
0a06e4d6
GK		 2732 error_setg(errp, "Short write while restoring the KVM hash table");
2733 return -ENOSPC;
e68cb8b4
AK		 2734 }
2735 return 0;
2736}
2737
20d695a9 2738bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
4513d923
GN		 2739{
2740 return true;
2741}
a1b87fe0 2742
82169660
SW		 2743void kvm_arch_init_irq_routing(KVMState *s)
2744{
2745}
c65f9a07 2746
1ad9f0a4 2747void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
7c43bca0 2748{
1ad9f0a4
DG		 2749 int fd, rc;
2750 int i;
7c43bca0 2751
14b0d748 2752 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
7c43bca0 2753
1ad9f0a4
DG		 2754 i = 0;
2755 while (i < n) {
2756 struct kvm_get_htab_header *hdr;
2757 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2758 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
7c43bca0 2759
1ad9f0a4
DG		 2760 rc = read(fd, buf, sizeof(buf));
2761 if (rc < 0) {
2762 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2763 }
7c43bca0 2764
1ad9f0a4
DG		 2765 hdr = (struct kvm_get_htab_header *)buf;
2766 while ((i < n) && ((char *)hdr < (buf + rc))) {
a36593e1 2767 int invalid = hdr->n_invalid, valid = hdr->n_valid;
7c43bca0 2768
1ad9f0a4
DG		 2769 if (hdr->index != (ptex + i)) {
2770 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2771 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2772 }
2773
a36593e1
AK		 2774 if (n - i < valid) {
2775 valid = n - i;
2776 }
2777 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2778 i += valid;
7c43bca0 2779
1ad9f0a4
DG		 2780 if ((n - i) < invalid) {
2781 invalid = n - i;
2782 }
2783 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
a36593e1 2784 i += invalid;
1ad9f0a4
DG		 2785
2786 hdr = (struct kvm_get_htab_header *)
2787 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2788 }
2789 }
2790
2791 close(fd);
7c43bca0 2792}
c1385933 2793
1ad9f0a4 2794void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
c1385933 2795{
1ad9f0a4 2796 int fd, rc;
1ad9f0a4
DG		 2797 struct {
2798 struct kvm_get_htab_header hdr;
2799 uint64_t pte0;
2800 uint64_t pte1;
2801 } buf;
c1385933 2802
14b0d748 2803 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
c1385933 2804
1ad9f0a4
DG		 2805 buf.hdr.n_valid = 1;
2806 buf.hdr.n_invalid = 0;
2807 buf.hdr.index = ptex;
2808 buf.pte0 = cpu_to_be64(pte0);
2809 buf.pte1 = cpu_to_be64(pte1);
c1385933 2810
1ad9f0a4
DG		 2811 rc = write(fd, &buf, sizeof(buf));
2812 if (rc != sizeof(buf)) {
2813 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2814 }
2815 close(fd);
c1385933 2816}
9e03a040
FB		 2817
2818int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 2819 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040
FB		 2820{
2821 return 0;
2822}
1850b6b7 2823
38d87493
PX		 2824int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2825 int vector, PCIDevice *dev)
2826{
2827 return 0;
2828}
2829
2830int kvm_arch_release_virq_post(int virq)
2831{
2832 return 0;
2833}
2834
1850b6b7
EA		 2835int kvm_arch_msi_data_to_gsi(uint32_t data)
2836{
2837 return data & 0xffff;
2838}
4d9392be 2839
9ac703ac
AP		 2840#if defined(TARGET_PPC64)
2841int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run)
2842{
211a7784 2843 uint16_t flags = run->flags & KVM_RUN_PPC_NMI_DISP_MASK;
81fe70e4 2844
9ac703ac
AP		 2845 cpu_synchronize_state(CPU(cpu));
2846
211a7784 2847 spapr_mce_req_event(cpu, flags == KVM_RUN_PPC_NMI_DISP_FULLY_RECOV);
9ac703ac
AP		 2848
2849 return 0;
2850}
2851#endif
2852
4d9392be
TH		 2853int kvmppc_enable_hwrng(void)
2854{
2855 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2856 return -1;
2857 }
2858
2859 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2860}
30f4b05b
DG		 2861
2862void kvmppc_check_papr_resize_hpt(Error **errp)
2863{
2864 if (!kvm_enabled()) {
b55d295e
DG		 2865 return; /* No KVM, we're good */
2866 }
2867
2868 if (cap_resize_hpt) {
2869 return; /* Kernel has explicit support, we're good */
30f4b05b
DG		 2870 }
2871
b55d295e
DG		 2872 /* Otherwise fallback on looking for PR KVM */
2873 if (kvmppc_is_pr(kvm_state)) {
2874 return;
2875 }
30f4b05b
DG		 2876
2877 error_setg(errp,
2878 "Hash page table resizing not available with this KVM version");
2879}
b55d295e
DG		 2880
2881int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2882{
2883 CPUState *cs = CPU(cpu);
2884 struct kvm_ppc_resize_hpt rhpt = {
2885 .flags = flags,
2886 .shift = shift,
2887 };
2888
2889 if (!cap_resize_hpt) {
2890 return -ENOSYS;
2891 }
2892
2893 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2894}
2895
2896int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2897{
2898 CPUState *cs = CPU(cpu);
2899 struct kvm_ppc_resize_hpt rhpt = {
2900 .flags = flags,
2901 .shift = shift,
2902 };
2903
2904 if (!cap_resize_hpt) {
2905 return -ENOSYS;
2906 }
2907
2908 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2909}
2910
c363a37a
DHB		 2911/*
2912 * This is a helper function to detect a post migration scenario
2913 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2914 * the guest kernel can't handle a PVR value other than the actual host
2915 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2916 *
2917 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2918 * (so, we're HV), return true. The workaround itself is done in
2919 * cpu_post_load.
2920 *
2921 * The order here is important: we'll only check for KVM PR as a
2922 * fallback if the guest kernel can't handle the situation itself.
2923 * We need to avoid as much as possible querying the running KVM type
2924 * in QEMU level.
2925 */
2926bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2927{
2928 CPUState *cs = CPU(cpu);
2929
2930 if (!kvm_enabled()) {
2931 return false;
2932 }
2933
2934 if (cap_ppc_pvr_compat) {
2935 return false;
2936 }
2937
2938 return !kvmppc_is_pr(cs->kvm_state);
2939}
a84f7179
ND		 2940
2941void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2942{
2943 CPUState *cs = CPU(cpu);
2944
2945 if (kvm_enabled()) {
2946 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2947 }
2948}
9723295a
GK		 2949
2950void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2951{
2952 CPUState *cs = CPU(cpu);
2953
2954 if (kvm_enabled()) {
2955 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2956 }
2957}
92a5199b
TL		 2958
2959bool kvm_arch_cpu_check_are_resettable(void)
2960{
2961 return true;
2962}
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