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901c4eaf BS |
1 | /* |
2 | * Miscellaneous PowerPC emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
0d75590d | 19 | #include "qemu/osdep.h" |
901c4eaf | 20 | #include "cpu.h" |
63c91552 | 21 | #include "exec/exec-all.h" |
2ef6175a | 22 | #include "exec/helper-proto.h" |
6b375544 | 23 | #include "qemu/error-report.h" |
901c4eaf BS |
24 | |
25 | #include "helper_regs.h" | |
26 | ||
27 | /*****************************************************************************/ | |
28 | /* SPR accesses */ | |
d523dd00 | 29 | void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn) |
901c4eaf BS |
30 | { |
31 | qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn, | |
32 | env->spr[sprn]); | |
33 | } | |
34 | ||
d523dd00 | 35 | void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn) |
901c4eaf BS |
36 | { |
37 | qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn, | |
38 | env->spr[sprn]); | |
39 | } | |
7019cb3d AK |
40 | |
41 | #ifdef TARGET_PPC64 | |
42 | static void raise_fu_exception(CPUPPCState *env, uint32_t bit, | |
57a2988b BH |
43 | uint32_t sprn, uint32_t cause, |
44 | uintptr_t raddr) | |
7019cb3d AK |
45 | { |
46 | qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit); | |
47 | ||
48 | env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS); | |
49 | cause &= FSCR_IC_MASK; | |
50 | env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS; | |
51 | ||
57a2988b | 52 | raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr); |
7019cb3d AK |
53 | } |
54 | #endif | |
55 | ||
56 | void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, | |
57 | uint32_t sprn, uint32_t cause) | |
58 | { | |
59 | #ifdef TARGET_PPC64 | |
60 | if (env->spr[SPR_FSCR] & (1ULL << bit)) { | |
61 | /* Facility is enabled, continue */ | |
62 | return; | |
63 | } | |
57a2988b | 64 | raise_fu_exception(env, bit, sprn, cause, GETPC()); |
7019cb3d AK |
65 | #endif |
66 | } | |
67 | ||
cdcdda27 AK |
68 | void helper_msr_facility_check(CPUPPCState *env, uint32_t bit, |
69 | uint32_t sprn, uint32_t cause) | |
70 | { | |
71 | #ifdef TARGET_PPC64 | |
72 | if (env->msr & (1ULL << bit)) { | |
73 | /* Facility is enabled, continue */ | |
74 | return; | |
75 | } | |
57a2988b | 76 | raise_fu_exception(env, bit, sprn, cause, GETPC()); |
cdcdda27 AK |
77 | #endif |
78 | } | |
79 | ||
901c4eaf | 80 | #if !defined(CONFIG_USER_ONLY) |
901c4eaf | 81 | |
d523dd00 | 82 | void helper_store_sdr1(CPUPPCState *env, target_ulong val) |
901c4eaf | 83 | { |
7d6250e3 DG |
84 | if (env->spr[SPR_SDR1] != val) { |
85 | ppc_store_sdr1(env, val); | |
db70b311 | 86 | tlb_flush(env_cpu(env)); |
f3c75d42 | 87 | } |
901c4eaf BS |
88 | } |
89 | ||
4a7518e0 CLG |
90 | #if defined(TARGET_PPC64) |
91 | void helper_store_ptcr(CPUPPCState *env, target_ulong val) | |
92 | { | |
4a7518e0 CLG |
93 | if (env->spr[SPR_PTCR] != val) { |
94 | ppc_store_ptcr(env, val); | |
db70b311 | 95 | tlb_flush(env_cpu(env)); |
4a7518e0 CLG |
96 | } |
97 | } | |
6b375544 JS |
98 | |
99 | void helper_store_pcr(CPUPPCState *env, target_ulong value) | |
100 | { | |
db70b311 | 101 | PowerPCCPU *cpu = env_archcpu(env); |
6b375544 JS |
102 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
103 | ||
104 | env->spr[SPR_PCR] = value & pcc->pcr_mask; | |
105 | } | |
4a7518e0 CLG |
106 | #endif /* defined(TARGET_PPC64) */ |
107 | ||
31b2b0f8 SJS |
108 | void helper_store_pidr(CPUPPCState *env, target_ulong val) |
109 | { | |
31b2b0f8 | 110 | env->spr[SPR_BOOKS_PID] = val; |
db70b311 | 111 | tlb_flush(env_cpu(env)); |
31b2b0f8 SJS |
112 | } |
113 | ||
c4dae9cd BH |
114 | void helper_store_lpidr(CPUPPCState *env, target_ulong val) |
115 | { | |
c4dae9cd BH |
116 | env->spr[SPR_LPIDR] = val; |
117 | ||
118 | /* | |
119 | * We need to flush the TLB on LPID changes as we only tag HV vs | |
120 | * guest in TCG TLB. Also the quadrants means the HV will | |
121 | * potentially access and cache entries for the current LPID as | |
122 | * well. | |
123 | */ | |
db70b311 | 124 | tlb_flush(env_cpu(env)); |
c4dae9cd BH |
125 | } |
126 | ||
d523dd00 | 127 | void helper_store_hid0_601(CPUPPCState *env, target_ulong val) |
901c4eaf BS |
128 | { |
129 | target_ulong hid0; | |
130 | ||
131 | hid0 = env->spr[SPR_HID0]; | |
132 | if ((val ^ hid0) & 0x00000008) { | |
133 | /* Change current endianness */ | |
134 | env->hflags &= ~(1 << MSR_LE); | |
135 | env->hflags_nmsr &= ~(1 << MSR_LE); | |
136 | env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE); | |
137 | env->hflags |= env->hflags_nmsr; | |
138 | qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__, | |
139 | val & 0x8 ? 'l' : 'b', env->hflags); | |
140 | } | |
141 | env->spr[SPR_HID0] = (uint32_t)val; | |
142 | } | |
143 | ||
d523dd00 | 144 | void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value) |
901c4eaf BS |
145 | { |
146 | if (likely(env->pb[num] != value)) { | |
147 | env->pb[num] = value; | |
148 | /* Should be optimized */ | |
db70b311 | 149 | tlb_flush(env_cpu(env)); |
901c4eaf BS |
150 | } |
151 | } | |
152 | ||
d523dd00 | 153 | void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val) |
901c4eaf BS |
154 | { |
155 | store_40x_dbcr0(env, val); | |
156 | } | |
157 | ||
d523dd00 | 158 | void helper_store_40x_sler(CPUPPCState *env, target_ulong val) |
901c4eaf BS |
159 | { |
160 | store_40x_sler(env, val); | |
161 | } | |
162 | #endif | |
163 | /*****************************************************************************/ | |
164 | /* PowerPC 601 specific instructions (POWER bridge) */ | |
165 | ||
d523dd00 | 166 | target_ulong helper_clcs(CPUPPCState *env, uint32_t arg) |
901c4eaf BS |
167 | { |
168 | switch (arg) { | |
169 | case 0x0CUL: | |
170 | /* Instruction cache line size */ | |
171 | return env->icache_line_size; | |
172 | break; | |
173 | case 0x0DUL: | |
174 | /* Data cache line size */ | |
175 | return env->dcache_line_size; | |
176 | break; | |
177 | case 0x0EUL: | |
178 | /* Minimum cache line size */ | |
179 | return (env->icache_line_size < env->dcache_line_size) ? | |
180 | env->icache_line_size : env->dcache_line_size; | |
181 | break; | |
182 | case 0x0FUL: | |
183 | /* Maximum cache line size */ | |
184 | return (env->icache_line_size > env->dcache_line_size) ? | |
185 | env->icache_line_size : env->dcache_line_size; | |
186 | break; | |
187 | default: | |
188 | /* Undefined */ | |
189 | return 0; | |
190 | break; | |
191 | } | |
192 | } | |
8555f71d BS |
193 | |
194 | /*****************************************************************************/ | |
195 | /* Special registers manipulation */ | |
196 | ||
197 | /* GDBstub can read and write MSR... */ | |
198 | void ppc_store_msr(CPUPPCState *env, target_ulong value) | |
199 | { | |
200 | hreg_store_msr(env, value, 0); | |
201 | } | |
f0278900 | 202 | |
d81b4327 DG |
203 | /* |
204 | * This code is lifted from MacOnLinux. It is called whenever THRM1,2 | |
205 | * or 3 is read an fixes up the values in such a way that will make | |
206 | * MacOS not hang. These registers exist on some 75x and 74xx | |
207 | * processors. | |
f0278900 BH |
208 | */ |
209 | void helper_fixup_thrm(CPUPPCState *env) | |
210 | { | |
211 | target_ulong v, t; | |
212 | int i; | |
213 | ||
214 | #define THRM1_TIN (1 << 31) | |
215 | #define THRM1_TIV (1 << 30) | |
216 | #define THRM1_THRES(x) (((x) & 0x7f) << 23) | |
217 | #define THRM1_TID (1 << 2) | |
218 | #define THRM1_TIE (1 << 1) | |
219 | #define THRM1_V (1 << 0) | |
220 | #define THRM3_E (1 << 0) | |
221 | ||
222 | if (!(env->spr[SPR_THRM3] & THRM3_E)) { | |
223 | return; | |
224 | } | |
225 | ||
226 | /* Note: Thermal interrupts are unimplemented */ | |
227 | for (i = SPR_THRM1; i <= SPR_THRM2; i++) { | |
228 | v = env->spr[i]; | |
229 | if (!(v & THRM1_V)) { | |
230 | continue; | |
231 | } | |
232 | v |= THRM1_TIV; | |
233 | v &= ~THRM1_TIN; | |
234 | t = v & THRM1_THRES(127); | |
235 | if ((v & THRM1_TID) && t < THRM1_THRES(24)) { | |
236 | v |= THRM1_TIN; | |
237 | } | |
238 | if (!(v & THRM1_TID) && t > THRM1_THRES(24)) { | |
239 | v |= THRM1_TIN; | |
240 | } | |
241 | env->spr[i] = v; | |
242 | } | |
243 | } |