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Commit | Line | Data |
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2a6a4076 MA |
1 | #ifndef MMU_HASH32_H |
2 | #define MMU_HASH32_H | |
9d7c3f4a DG |
3 | |
4 | #ifndef CONFIG_USER_ONLY | |
5 | ||
7ef23068 | 6 | hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); |
51806b54 | 7 | bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, |
d423baf9 | 8 | hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, |
51806b54 | 9 | bool guest_visible); |
9d7c3f4a | 10 | |
d5aea6f3 DG |
11 | /* |
12 | * Segment register definitions | |
13 | */ | |
14 | ||
15 | #define SR32_T 0x80000000 | |
16 | #define SR32_KS 0x40000000 | |
17 | #define SR32_KP 0x20000000 | |
18 | #define SR32_NX 0x10000000 | |
19 | #define SR32_VSID 0x00ffffff | |
20 | ||
21 | /* | |
22 | * Block Address Translation (BAT) definitions | |
23 | */ | |
24 | ||
ba1b5df0 FR |
25 | #define BATU32_BEPIU 0xf0000000 |
26 | #define BATU32_BEPIL 0x0ffe0000 | |
d5aea6f3 DG |
27 | #define BATU32_BEPI 0xfffe0000 |
28 | #define BATU32_BL 0x00001ffc | |
29 | #define BATU32_VS 0x00000002 | |
30 | #define BATU32_VP 0x00000001 | |
31 | ||
32 | ||
d5aea6f3 DG |
33 | #define BATL32_BRPN 0xfffe0000 |
34 | #define BATL32_WIMG 0x00000078 | |
35 | #define BATL32_PP 0x00000003 | |
36 | ||
37 | /* PowerPC 601 has slightly different BAT registers */ | |
38 | ||
39 | #define BATU32_601_KS 0x00000008 | |
40 | #define BATU32_601_KP 0x00000004 | |
41 | #define BATU32_601_PP 0x00000003 | |
42 | ||
43 | #define BATL32_601_V 0x00000040 | |
44 | #define BATL32_601_BL 0x0000003f | |
45 | ||
46 | /* | |
47 | * Hash page table definitions | |
48 | */ | |
36778660 DG |
49 | #define SDR_32_HTABORG 0xFFFF0000UL |
50 | #define SDR_32_HTABMASK 0x000001FFUL | |
d5aea6f3 DG |
51 | |
52 | #define HPTES_PER_GROUP 8 | |
53 | #define HASH_PTE_SIZE_32 8 | |
54 | #define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP) | |
55 | ||
56 | #define HPTE32_V_VALID 0x80000000 | |
57 | #define HPTE32_V_VSID 0x7fffff80 | |
58 | #define HPTE32_V_SECONDARY 0x00000040 | |
59 | #define HPTE32_V_API 0x0000003f | |
60 | #define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf)) | |
61 | ||
62 | #define HPTE32_R_RPN 0xfffff000 | |
63 | #define HPTE32_R_R 0x00000100 | |
64 | #define HPTE32_R_C 0x00000080 | |
65 | #define HPTE32_R_W 0x00000040 | |
66 | #define HPTE32_R_I 0x00000020 | |
67 | #define HPTE32_R_M 0x00000010 | |
68 | #define HPTE32_R_G 0x00000008 | |
69 | #define HPTE32_R_WIMG 0x00000078 | |
70 | #define HPTE32_R_PP 0x00000003 | |
71 | ||
36778660 DG |
72 | static inline hwaddr ppc_hash32_hpt_base(PowerPCCPU *cpu) |
73 | { | |
74 | return cpu->env.spr[SPR_SDR1] & SDR_32_HTABORG; | |
75 | } | |
76 | ||
77 | static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu) | |
78 | { | |
79 | return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF; | |
80 | } | |
81 | ||
7ef23068 | 82 | static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu, |
dffdaf61 DG |
83 | hwaddr pte_offset) |
84 | { | |
36778660 | 85 | target_ulong base = ppc_hash32_hpt_base(cpu); |
33276f1b | 86 | |
36778660 | 87 | return ldl_phys(CPU(cpu)->as, base + pte_offset); |
dffdaf61 DG |
88 | } |
89 | ||
7ef23068 | 90 | static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu, |
dffdaf61 DG |
91 | hwaddr pte_offset) |
92 | { | |
36778660 | 93 | target_ulong base = ppc_hash32_hpt_base(cpu); |
33276f1b | 94 | |
36778660 | 95 | return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2); |
dffdaf61 DG |
96 | } |
97 | ||
7ef23068 | 98 | static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu, |
dffdaf61 DG |
99 | hwaddr pte_offset, target_ulong pte0) |
100 | { | |
36778660 | 101 | target_ulong base = ppc_hash32_hpt_base(cpu); |
33276f1b | 102 | |
36778660 | 103 | stl_phys(CPU(cpu)->as, base + pte_offset, pte0); |
dffdaf61 DG |
104 | } |
105 | ||
7ef23068 | 106 | static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu, |
dffdaf61 DG |
107 | hwaddr pte_offset, target_ulong pte1) |
108 | { | |
36778660 | 109 | target_ulong base = ppc_hash32_hpt_base(cpu); |
33276f1b | 110 | |
36778660 | 111 | stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); |
dffdaf61 DG |
112 | } |
113 | ||
aea390e4 DG |
114 | typedef struct { |
115 | uint32_t pte0, pte1; | |
116 | } ppc_hash_pte32_t; | |
117 | ||
9d7c3f4a DG |
118 | #endif /* CONFIG_USER_ONLY */ |
119 | ||
2a6a4076 | 120 | #endif /* MMU_HASH32_H */ |