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Commit | Line | Data |
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10b46525 DG |
1 | /* |
2 | * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * Copyright (c) 2013 David Gibson, IBM Corporation | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
6bd039cd | 10 | * version 2.1 of the License, or (at your option) any later version. |
10b46525 DG |
11 | * |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
0d75590d | 20 | #include "qemu/osdep.h" |
a864a6b3 | 21 | #include "qemu/units.h" |
10b46525 | 22 | #include "cpu.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
cd6a9bb6 | 24 | #include "qemu/error-report.h" |
fad866da | 25 | #include "qemu/qemu-print.h" |
b3946626 | 26 | #include "sysemu/hw_accel.h" |
10b46525 DG |
27 | #include "kvm_ppc.h" |
28 | #include "mmu-hash64.h" | |
508127e2 | 29 | #include "exec/log.h" |
7222b94a | 30 | #include "hw/hw.h" |
182357db | 31 | #include "internal.h" |
b2899495 | 32 | #include "mmu-book3s-v3.h" |
f03de3b4 | 33 | #include "helper_regs.h" |
10b46525 | 34 | |
2b44e219 BL |
35 | #ifdef CONFIG_TCG |
36 | #include "exec/helper-proto.h" | |
37 | #endif | |
38 | ||
d75cbae8 | 39 | /* #define DEBUG_SLB */ |
10b46525 DG |
40 | |
41 | #ifdef DEBUG_SLB | |
48880da6 | 42 | # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) |
10b46525 DG |
43 | #else |
44 | # define LOG_SLB(...) do { } while (0) | |
45 | #endif | |
46 | ||
47 | /* | |
48 | * SLB handling | |
49 | */ | |
50 | ||
7ef23068 | 51 | static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) |
10b46525 | 52 | { |
7ef23068 | 53 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
54 | uint64_t esid_256M, esid_1T; |
55 | int n; | |
56 | ||
57 | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); | |
58 | ||
59 | esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; | |
60 | esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; | |
61 | ||
67d7d66f | 62 | for (n = 0; n < cpu->hash64_opts->slb_size; n++) { |
10b46525 DG |
63 | ppc_slb_t *slb = &env->slb[n]; |
64 | ||
65 | LOG_SLB("%s: slot %d %016" PRIx64 " %016" | |
66 | PRIx64 "\n", __func__, n, slb->esid, slb->vsid); | |
d75cbae8 DG |
67 | /* |
68 | * We check for 1T matches on all MMUs here - if the MMU | |
10b46525 | 69 | * doesn't have 1T segment support, we will have prevented 1T |
d75cbae8 DG |
70 | * entries from being inserted in the slbmte code. |
71 | */ | |
10b46525 DG |
72 | if (((slb->esid == esid_256M) && |
73 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M)) | |
74 | || ((slb->esid == esid_1T) && | |
75 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) { | |
76 | return slb; | |
77 | } | |
78 | } | |
79 | ||
80 | return NULL; | |
81 | } | |
82 | ||
fad866da | 83 | void dump_slb(PowerPCCPU *cpu) |
10b46525 | 84 | { |
7ef23068 | 85 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
86 | int i; |
87 | uint64_t slbe, slbv; | |
88 | ||
7ef23068 | 89 | cpu_synchronize_state(CPU(cpu)); |
10b46525 | 90 | |
fad866da | 91 | qemu_printf("SLB\tESID\t\t\tVSID\n"); |
67d7d66f | 92 | for (i = 0; i < cpu->hash64_opts->slb_size; i++) { |
10b46525 DG |
93 | slbe = env->slb[i].esid; |
94 | slbv = env->slb[i].vsid; | |
95 | if (slbe == 0 && slbv == 0) { | |
96 | continue; | |
97 | } | |
fad866da | 98 | qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", |
10b46525 DG |
99 | i, slbe, slbv); |
100 | } | |
101 | } | |
102 | ||
2b44e219 | 103 | #ifdef CONFIG_TCG |
0418bf78 | 104 | void helper_slbia(CPUPPCState *env, uint32_t ih) |
10b46525 | 105 | { |
db70b311 | 106 | PowerPCCPU *cpu = env_archcpu(env); |
0418bf78 | 107 | int starting_entry; |
cd0c6f47 | 108 | int n; |
10b46525 | 109 | |
f9e3e1a3 NP |
110 | /* |
111 | * slbia must always flush all TLB (which is equivalent to ERAT in ppc | |
112 | * architecture). Matching on SLB_ESID_V is not good enough, because slbmte | |
113 | * can overwrite a valid SLB without flushing its lookaside information. | |
114 | * | |
115 | * It would be possible to keep the TLB in synch with the SLB by flushing | |
116 | * when a valid entry is overwritten by slbmte, and therefore slbia would | |
117 | * not have to flush unless it evicts a valid SLB entry. However it is | |
118 | * expected that slbmte is more common than slbia, and slbia is usually | |
119 | * going to evict valid SLB entries, so that tradeoff is unlikely to be a | |
120 | * good one. | |
0418bf78 NP |
121 | * |
122 | * ISA v2.05 introduced IH field with values 0,1,2,6. These all invalidate | |
123 | * the same SLB entries (everything but entry 0), but differ in what | |
124 | * "lookaside information" is invalidated. TCG can ignore this and flush | |
125 | * everything. | |
126 | * | |
127 | * ISA v3.0 introduced additional values 3,4,7, which change what SLBs are | |
128 | * invalidated. | |
f9e3e1a3 NP |
129 | */ |
130 | ||
0418bf78 | 131 | env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; |
10b46525 | 132 | |
0418bf78 NP |
133 | starting_entry = 1; /* default for IH=0,1,2,6 */ |
134 | ||
135 | if (env->mmu_model == POWERPC_MMU_3_00) { | |
136 | switch (ih) { | |
137 | case 0x7: | |
138 | /* invalidate no SLBs, but all lookaside information */ | |
139 | return; | |
140 | ||
141 | case 0x3: | |
142 | case 0x4: | |
143 | /* also considers SLB entry 0 */ | |
144 | starting_entry = 0; | |
145 | break; | |
146 | ||
147 | case 0x5: | |
148 | /* treat undefined values as ih==0, and warn */ | |
149 | qemu_log_mask(LOG_GUEST_ERROR, | |
150 | "slbia undefined IH field %u.\n", ih); | |
151 | break; | |
152 | ||
153 | default: | |
154 | /* 0,1,2,6 */ | |
155 | break; | |
10b46525 DG |
156 | } |
157 | } | |
f9e3e1a3 | 158 | |
0418bf78 NP |
159 | for (n = starting_entry; n < cpu->hash64_opts->slb_size; n++) { |
160 | ppc_slb_t *slb = &env->slb[n]; | |
161 | ||
162 | if (!(slb->esid & SLB_ESID_V)) { | |
163 | continue; | |
164 | } | |
165 | if (env->mmu_model == POWERPC_MMU_3_00) { | |
166 | if (ih == 0x3 && (slb->vsid & SLB_VSID_C) == 0) { | |
167 | /* preserves entries with a class value of 0 */ | |
168 | continue; | |
169 | } | |
170 | } | |
171 | ||
172 | slb->esid &= ~SLB_ESID_V; | |
173 | } | |
10b46525 DG |
174 | } |
175 | ||
a63f1dfc ND |
176 | static void __helper_slbie(CPUPPCState *env, target_ulong addr, |
177 | target_ulong global) | |
10b46525 | 178 | { |
db70b311 | 179 | PowerPCCPU *cpu = env_archcpu(env); |
10b46525 DG |
180 | ppc_slb_t *slb; |
181 | ||
7ef23068 | 182 | slb = slb_lookup(cpu, addr); |
10b46525 DG |
183 | if (!slb) { |
184 | return; | |
185 | } | |
186 | ||
187 | if (slb->esid & SLB_ESID_V) { | |
188 | slb->esid &= ~SLB_ESID_V; | |
189 | ||
d75cbae8 DG |
190 | /* |
191 | * XXX: given the fact that segment size is 256 MB or 1TB, | |
10b46525 DG |
192 | * and we still don't have a tlb_flush_mask(env, n, mask) |
193 | * in QEMU, we just invalidate all TLBs | |
194 | */ | |
a63f1dfc ND |
195 | env->tlb_need_flush |= |
196 | (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH); | |
10b46525 DG |
197 | } |
198 | } | |
199 | ||
a63f1dfc ND |
200 | void helper_slbie(CPUPPCState *env, target_ulong addr) |
201 | { | |
202 | __helper_slbie(env, addr, false); | |
203 | } | |
204 | ||
205 | void helper_slbieg(CPUPPCState *env, target_ulong addr) | |
206 | { | |
207 | __helper_slbie(env, addr, true); | |
208 | } | |
2b44e219 | 209 | #endif |
a63f1dfc | 210 | |
bcd81230 DG |
211 | int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, |
212 | target_ulong esid, target_ulong vsid) | |
10b46525 | 213 | { |
7ef23068 | 214 | CPUPPCState *env = &cpu->env; |
10b46525 | 215 | ppc_slb_t *slb = &env->slb[slot]; |
b07c59f7 | 216 | const PPCHash64SegmentPageSizes *sps = NULL; |
cd6a9bb6 | 217 | int i; |
10b46525 | 218 | |
67d7d66f | 219 | if (slot >= cpu->hash64_opts->slb_size) { |
bcd81230 DG |
220 | return -1; /* Bad slot number */ |
221 | } | |
222 | if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { | |
223 | return -1; /* Reserved bits set */ | |
10b46525 | 224 | } |
bcd81230 | 225 | if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { |
10b46525 DG |
226 | return -1; /* Bad segment size */ |
227 | } | |
58969eee | 228 | if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { |
10b46525 DG |
229 | return -1; /* 1T segment on MMU that doesn't support it */ |
230 | } | |
231 | ||
cd6a9bb6 | 232 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
b07c59f7 | 233 | const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; |
cd6a9bb6 DG |
234 | |
235 | if (!sps1->page_shift) { | |
236 | break; | |
237 | } | |
238 | ||
239 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { | |
240 | sps = sps1; | |
241 | break; | |
242 | } | |
243 | } | |
244 | ||
245 | if (!sps) { | |
246 | error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu | |
247 | " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx, | |
248 | slot, esid, vsid); | |
249 | return -1; | |
250 | } | |
251 | ||
bcd81230 DG |
252 | slb->esid = esid; |
253 | slb->vsid = vsid; | |
cd6a9bb6 | 254 | slb->sps = sps; |
10b46525 | 255 | |
76134d48 SJS |
256 | LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx |
257 | " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid, | |
10b46525 DG |
258 | slb->esid, slb->vsid); |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
2b44e219 | 263 | #ifdef CONFIG_TCG |
7ef23068 | 264 | static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
265 | target_ulong *rt) |
266 | { | |
7ef23068 | 267 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
268 | int slot = rb & 0xfff; |
269 | ppc_slb_t *slb = &env->slb[slot]; | |
270 | ||
67d7d66f | 271 | if (slot >= cpu->hash64_opts->slb_size) { |
10b46525 DG |
272 | return -1; |
273 | } | |
274 | ||
275 | *rt = slb->esid; | |
276 | return 0; | |
277 | } | |
278 | ||
7ef23068 | 279 | static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
280 | target_ulong *rt) |
281 | { | |
7ef23068 | 282 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
283 | int slot = rb & 0xfff; |
284 | ppc_slb_t *slb = &env->slb[slot]; | |
285 | ||
67d7d66f | 286 | if (slot >= cpu->hash64_opts->slb_size) { |
10b46525 DG |
287 | return -1; |
288 | } | |
289 | ||
290 | *rt = slb->vsid; | |
291 | return 0; | |
292 | } | |
293 | ||
c76c22d5 BH |
294 | static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
295 | target_ulong *rt) | |
296 | { | |
297 | CPUPPCState *env = &cpu->env; | |
298 | ppc_slb_t *slb; | |
299 | ||
300 | if (!msr_is_64bit(env, env->msr)) { | |
301 | rb &= 0xffffffff; | |
302 | } | |
303 | slb = slb_lookup(cpu, rb); | |
304 | if (slb == NULL) { | |
305 | *rt = (target_ulong)-1ul; | |
306 | } else { | |
307 | *rt = slb->vsid; | |
308 | } | |
309 | return 0; | |
310 | } | |
311 | ||
10b46525 DG |
312 | void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) |
313 | { | |
db70b311 | 314 | PowerPCCPU *cpu = env_archcpu(env); |
7ef23068 | 315 | |
bcd81230 | 316 | if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { |
0f72b7c6 BH |
317 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
318 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
319 | } |
320 | } | |
321 | ||
322 | target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) | |
323 | { | |
db70b311 | 324 | PowerPCCPU *cpu = env_archcpu(env); |
10b46525 DG |
325 | target_ulong rt = 0; |
326 | ||
7ef23068 | 327 | if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { |
0f72b7c6 BH |
328 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
329 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
330 | } |
331 | return rt; | |
332 | } | |
333 | ||
c76c22d5 BH |
334 | target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) |
335 | { | |
db70b311 | 336 | PowerPCCPU *cpu = env_archcpu(env); |
c76c22d5 BH |
337 | target_ulong rt = 0; |
338 | ||
339 | if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { | |
0f72b7c6 BH |
340 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
341 | POWERPC_EXCP_INVAL, GETPC()); | |
c76c22d5 BH |
342 | } |
343 | return rt; | |
344 | } | |
345 | ||
10b46525 DG |
346 | target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) |
347 | { | |
db70b311 | 348 | PowerPCCPU *cpu = env_archcpu(env); |
10b46525 DG |
349 | target_ulong rt = 0; |
350 | ||
7ef23068 | 351 | if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { |
0f72b7c6 BH |
352 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
353 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
354 | } |
355 | return rt; | |
356 | } | |
2b44e219 | 357 | #endif |
9d7c3f4a | 358 | |
07a68f99 SJS |
359 | /* Check No-Execute or Guarded Storage */ |
360 | static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, | |
361 | ppc_hash_pte64_t pte) | |
362 | { | |
363 | /* Exec permissions CANNOT take away read or write permissions */ | |
364 | return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ? | |
365 | PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
366 | } | |
367 | ||
368 | /* Check Basic Storage Protection */ | |
03695a98 | 369 | static int ppc_hash64_pte_prot(int mmu_idx, |
e01b4445 | 370 | ppc_slb_t *slb, ppc_hash_pte64_t pte) |
496272a7 | 371 | { |
e01b4445 | 372 | unsigned pp, key; |
d75cbae8 DG |
373 | /* |
374 | * Some pp bit combinations have undefined behaviour, so default | |
375 | * to no access in those cases | |
376 | */ | |
e01b4445 DG |
377 | int prot = 0; |
378 | ||
03695a98 | 379 | key = !!(mmuidx_pr(mmu_idx) ? (slb->vsid & SLB_VSID_KP) |
e01b4445 DG |
380 | : (slb->vsid & SLB_VSID_KS)); |
381 | pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); | |
496272a7 | 382 | |
496272a7 DG |
383 | if (key == 0) { |
384 | switch (pp) { | |
385 | case 0x0: | |
386 | case 0x1: | |
387 | case 0x2: | |
347a5c73 | 388 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
e01b4445 DG |
389 | break; |
390 | ||
496272a7 DG |
391 | case 0x3: |
392 | case 0x6: | |
347a5c73 | 393 | prot = PAGE_READ | PAGE_EXEC; |
496272a7 DG |
394 | break; |
395 | } | |
396 | } else { | |
397 | switch (pp) { | |
398 | case 0x0: | |
399 | case 0x6: | |
496272a7 | 400 | break; |
e01b4445 | 401 | |
496272a7 DG |
402 | case 0x1: |
403 | case 0x3: | |
347a5c73 | 404 | prot = PAGE_READ | PAGE_EXEC; |
496272a7 | 405 | break; |
e01b4445 | 406 | |
496272a7 | 407 | case 0x2: |
347a5c73 | 408 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
496272a7 DG |
409 | break; |
410 | } | |
411 | } | |
496272a7 | 412 | |
e01b4445 | 413 | return prot; |
496272a7 DG |
414 | } |
415 | ||
a6152b52 SJS |
416 | /* Check the instruction access permissions specified in the IAMR */ |
417 | static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key) | |
418 | { | |
419 | CPUPPCState *env = &cpu->env; | |
420 | int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3; | |
421 | ||
422 | /* | |
423 | * An instruction fetch is permitted if the IAMR bit is 0. | |
424 | * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit | |
425 | * can only take away EXEC permissions not READ or WRITE permissions. | |
426 | * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since | |
427 | * EXEC permissions are allowed. | |
428 | */ | |
429 | return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE : | |
430 | PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
431 | } | |
432 | ||
7ef23068 | 433 | static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) |
f80872e2 | 434 | { |
7ef23068 | 435 | CPUPPCState *env = &cpu->env; |
f80872e2 | 436 | int key, amrbits; |
363248e8 | 437 | int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
f80872e2 | 438 | |
f80872e2 | 439 | /* Only recent MMUs implement Virtual Page Class Key Protection */ |
58969eee | 440 | if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { |
363248e8 | 441 | return prot; |
f80872e2 DG |
442 | } |
443 | ||
444 | key = HPTE64_R_KEY(pte.pte1); | |
d75cbae8 | 445 | amrbits = (env->spr[SPR_AMR] >> 2 * (31 - key)) & 0x3; |
f80872e2 DG |
446 | |
447 | /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */ | |
448 | /* env->spr[SPR_AMR]); */ | |
449 | ||
363248e8 CLG |
450 | /* |
451 | * A store is permitted if the AMR bit is 0. Remove write | |
452 | * protection if it is set. | |
453 | */ | |
f80872e2 | 454 | if (amrbits & 0x2) { |
363248e8 | 455 | prot &= ~PAGE_WRITE; |
f80872e2 | 456 | } |
363248e8 CLG |
457 | /* |
458 | * A load is permitted if the AMR bit is 0. Remove read | |
459 | * protection if it is set. | |
460 | */ | |
f80872e2 | 461 | if (amrbits & 0x1) { |
363248e8 | 462 | prot &= ~PAGE_READ; |
f80872e2 DG |
463 | } |
464 | ||
a6152b52 SJS |
465 | switch (env->mmu_model) { |
466 | /* | |
467 | * MMU version 2.07 and later support IAMR | |
468 | * Check if the IAMR allows the instruction access - it will return | |
469 | * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0 | |
470 | * if it does (and prot will be unchanged indicating execution support). | |
471 | */ | |
472 | case POWERPC_MMU_2_07: | |
473 | case POWERPC_MMU_3_00: | |
474 | prot &= ppc_hash64_iamr_prot(cpu, key); | |
475 | break; | |
476 | default: | |
477 | break; | |
478 | } | |
479 | ||
f80872e2 DG |
480 | return prot; |
481 | } | |
482 | ||
7222b94a DG |
483 | const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, |
484 | hwaddr ptex, int n) | |
7c43bca0 | 485 | { |
7222b94a | 486 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; |
3367c62f | 487 | hwaddr base; |
e57ca75c DG |
488 | hwaddr plen = n * HASH_PTE_SIZE_64; |
489 | const ppc_hash_pte64_t *hptes; | |
7c43bca0 | 490 | |
e57ca75c DG |
491 | if (cpu->vhyp) { |
492 | PPCVirtualHypervisorClass *vhc = | |
493 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
494 | return vhc->map_hptes(cpu->vhyp, ptex, n); | |
495 | } | |
3367c62f | 496 | base = ppc_hash64_hpt_base(cpu); |
e57ca75c DG |
497 | |
498 | if (!base) { | |
499 | return NULL; | |
500 | } | |
501 | ||
f26404fb PM |
502 | hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false, |
503 | MEMTXATTRS_UNSPECIFIED); | |
e57ca75c DG |
504 | if (plen < (n * HASH_PTE_SIZE_64)) { |
505 | hw_error("%s: Unable to map all requested HPTEs\n", __func__); | |
7c43bca0 | 506 | } |
7222b94a | 507 | return hptes; |
7c43bca0 AK |
508 | } |
509 | ||
7222b94a DG |
510 | void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes, |
511 | hwaddr ptex, int n) | |
7c43bca0 | 512 | { |
e57ca75c DG |
513 | if (cpu->vhyp) { |
514 | PPCVirtualHypervisorClass *vhc = | |
515 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
516 | vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n); | |
517 | return; | |
7c43bca0 | 518 | } |
e57ca75c DG |
519 | |
520 | address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64, | |
521 | false, n * HASH_PTE_SIZE_64); | |
7c43bca0 AK |
522 | } |
523 | ||
b07c59f7 DG |
524 | static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps, |
525 | uint64_t pte0, uint64_t pte1) | |
4322e8ce | 526 | { |
651060ab DG |
527 | int i; |
528 | ||
529 | if (!(pte0 & HPTE64_V_LARGE)) { | |
530 | if (sps->page_shift != 12) { | |
531 | /* 4kiB page in a non 4kiB segment */ | |
532 | return 0; | |
533 | } | |
534 | /* Normal 4kiB page */ | |
4322e8ce | 535 | return 12; |
651060ab DG |
536 | } |
537 | ||
538 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
b07c59f7 | 539 | const PPCHash64PageSize *ps = &sps->enc[i]; |
651060ab DG |
540 | uint64_t mask; |
541 | ||
542 | if (!ps->page_shift) { | |
543 | break; | |
4322e8ce | 544 | } |
651060ab DG |
545 | |
546 | if (ps->page_shift == 12) { | |
547 | /* L bit is set so this can't be a 4kiB page */ | |
548 | continue; | |
549 | } | |
550 | ||
551 | mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN; | |
552 | ||
b56d417b | 553 | if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) { |
651060ab | 554 | return ps->page_shift; |
4322e8ce | 555 | } |
4322e8ce | 556 | } |
651060ab DG |
557 | |
558 | return 0; /* Bad page size encoding */ | |
4322e8ce BH |
559 | } |
560 | ||
34525595 BH |
561 | static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1) |
562 | { | |
563 | /* Insert B into pte0 */ | |
564 | *pte0 = (*pte0 & HPTE64_V_COMMON_BITS) | | |
565 | ((*pte1 & HPTE64_R_3_0_SSIZE_MASK) << | |
566 | (HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT)); | |
567 | ||
568 | /* Remove B from pte1 */ | |
569 | *pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK; | |
570 | } | |
571 | ||
572 | ||
7ef23068 | 573 | static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash, |
b07c59f7 | 574 | const PPCHash64SegmentPageSizes *sps, |
2c7ad804 | 575 | target_ulong ptem, |
94986863 | 576 | ppc_hash_pte64_t *pte, unsigned *pshift) |
aea390e4 | 577 | { |
aea390e4 | 578 | int i; |
7222b94a | 579 | const ppc_hash_pte64_t *pteg; |
7c43bca0 | 580 | target_ulong pte0, pte1; |
7222b94a | 581 | target_ulong ptex; |
aea390e4 | 582 | |
36778660 | 583 | ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP; |
7222b94a DG |
584 | pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); |
585 | if (!pteg) { | |
7c43bca0 AK |
586 | return -1; |
587 | } | |
aea390e4 | 588 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
7222b94a | 589 | pte0 = ppc_hash64_hpte0(cpu, pteg, i); |
3054b0ca BH |
590 | /* |
591 | * pte0 contains the valid bit and must be read before pte1, | |
592 | * otherwise we might see an old pte1 with a new valid bit and | |
593 | * thus an inconsistent hpte value | |
594 | */ | |
595 | smp_rmb(); | |
7222b94a | 596 | pte1 = ppc_hash64_hpte1(cpu, pteg, i); |
aea390e4 | 597 | |
34525595 BH |
598 | /* Convert format if necessary */ |
599 | if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) { | |
600 | ppc64_v3_new_to_old_hpte(&pte0, &pte1); | |
601 | } | |
602 | ||
073de86a DG |
603 | /* This compares V, B, H (secondary) and the AVPN */ |
604 | if (HPTE64_V_COMPARE(pte0, ptem)) { | |
2c7ad804 | 605 | *pshift = hpte_page_shift(sps, pte0, pte1); |
651060ab DG |
606 | /* |
607 | * If there is no match, ignore the PTE, it could simply | |
608 | * be for a different segment size encoding and the | |
609 | * architecture specifies we should not match. Linux will | |
610 | * potentially leave behind PTEs for the wrong base page | |
611 | * size when demoting segments. | |
612 | */ | |
94986863 | 613 | if (*pshift == 0) { |
4322e8ce BH |
614 | continue; |
615 | } | |
d75cbae8 DG |
616 | /* |
617 | * We don't do anything with pshift yet as qemu TLB only | |
618 | * deals with 4K pages anyway | |
4322e8ce | 619 | */ |
aea390e4 DG |
620 | pte->pte0 = pte0; |
621 | pte->pte1 = pte1; | |
7222b94a DG |
622 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
623 | return ptex + i; | |
aea390e4 | 624 | } |
aea390e4 | 625 | } |
7222b94a | 626 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
7c43bca0 AK |
627 | /* |
628 | * We didn't find a valid entry. | |
629 | */ | |
aea390e4 DG |
630 | return -1; |
631 | } | |
632 | ||
7ef23068 | 633 | static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, |
7f3bdc2d | 634 | ppc_slb_t *slb, target_ulong eaddr, |
94986863 | 635 | ppc_hash_pte64_t *pte, unsigned *pshift) |
c69b6151 | 636 | { |
7ef23068 | 637 | CPUPPCState *env = &cpu->env; |
7222b94a | 638 | hwaddr hash, ptex; |
cd6a9bb6 | 639 | uint64_t vsid, epnmask, epn, ptem; |
b07c59f7 | 640 | const PPCHash64SegmentPageSizes *sps = slb->sps; |
cd6a9bb6 | 641 | |
d75cbae8 DG |
642 | /* |
643 | * The SLB store path should prevent any bad page size encodings | |
644 | * getting in there, so: | |
645 | */ | |
2c7ad804 | 646 | assert(sps); |
a1ff751a | 647 | |
2c7ad804 BH |
648 | /* If ISL is set in LPCR we need to clamp the page size to 4K */ |
649 | if (env->spr[SPR_LPCR] & LPCR_ISL) { | |
650 | /* We assume that when using TCG, 4k is first entry of SPS */ | |
b07c59f7 | 651 | sps = &cpu->hash64_opts->sps[0]; |
2c7ad804 BH |
652 | assert(sps->page_shift == 12); |
653 | } | |
654 | ||
655 | epnmask = ~((1ULL << sps->page_shift) - 1); | |
a1ff751a | 656 | |
a1ff751a | 657 | if (slb->vsid & SLB_VSID_B) { |
18148898 DG |
658 | /* 1TB segment */ |
659 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; | |
660 | epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; | |
2c7ad804 | 661 | hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift); |
a1ff751a | 662 | } else { |
18148898 DG |
663 | /* 256M segment */ |
664 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; | |
665 | epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; | |
2c7ad804 | 666 | hash = vsid ^ (epn >> sps->page_shift); |
a1ff751a | 667 | } |
18148898 | 668 | ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); |
073de86a | 669 | ptem |= HPTE64_V_VALID; |
a1ff751a | 670 | |
a1ff751a | 671 | /* Page address translation */ |
339aaf5b AP |
672 | qemu_log_mask(CPU_LOG_MMU, |
673 | "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx | |
a1ff751a | 674 | " hash " TARGET_FMT_plx "\n", |
36778660 | 675 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); |
a1ff751a | 676 | |
a1ff751a | 677 | /* Primary PTEG lookup */ |
339aaf5b AP |
678 | qemu_log_mask(CPU_LOG_MMU, |
679 | "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a DG |
680 | " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx |
681 | " hash=" TARGET_FMT_plx "\n", | |
36778660 DG |
682 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), |
683 | vsid, ptem, hash); | |
7222b94a | 684 | ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); |
7f3bdc2d | 685 | |
7222b94a | 686 | if (ptex == -1) { |
a1ff751a | 687 | /* Secondary PTEG lookup */ |
073de86a | 688 | ptem |= HPTE64_V_SECONDARY; |
339aaf5b AP |
689 | qemu_log_mask(CPU_LOG_MMU, |
690 | "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a | 691 | " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx |
36778660 DG |
692 | " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu), |
693 | ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); | |
a1ff751a | 694 | |
7222b94a | 695 | ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); |
a1ff751a DG |
696 | } |
697 | ||
7222b94a | 698 | return ptex; |
c69b6151 | 699 | } |
0480884f | 700 | |
1114e712 | 701 | unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, |
1f0252e6 | 702 | uint64_t pte0, uint64_t pte1) |
1114e712 | 703 | { |
1114e712 DG |
704 | int i; |
705 | ||
706 | if (!(pte0 & HPTE64_V_LARGE)) { | |
1114e712 DG |
707 | return 12; |
708 | } | |
709 | ||
710 | /* | |
711 | * The encodings in env->sps need to be carefully chosen so that | |
712 | * this gives an unambiguous result. | |
713 | */ | |
714 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
b07c59f7 | 715 | const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; |
1114e712 DG |
716 | unsigned shift; |
717 | ||
718 | if (!sps->page_shift) { | |
719 | break; | |
720 | } | |
721 | ||
722 | shift = hpte_page_shift(sps, pte0, pte1); | |
723 | if (shift) { | |
1114e712 DG |
724 | return shift; |
725 | } | |
726 | } | |
727 | ||
1114e712 DG |
728 | return 0; |
729 | } | |
730 | ||
1b99e029 DG |
731 | static bool ppc_hash64_use_vrma(CPUPPCState *env) |
732 | { | |
733 | switch (env->mmu_model) { | |
734 | case POWERPC_MMU_3_00: | |
735 | /* | |
736 | * ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR | |
737 | * register no longer exist | |
738 | */ | |
739 | return true; | |
740 | ||
741 | default: | |
742 | return !!(env->spr[SPR_LPCR] & LPCR_VPM0); | |
743 | } | |
744 | } | |
745 | ||
03695a98 | 746 | static void ppc_hash64_set_isi(CPUState *cs, int mmu_idx, uint64_t error_code) |
33595dc9 | 747 | { |
8fe08fac | 748 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
33595dc9 BH |
749 | bool vpm; |
750 | ||
03695a98 | 751 | if (!mmuidx_real(mmu_idx)) { |
33595dc9 BH |
752 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); |
753 | } else { | |
1b99e029 | 754 | vpm = ppc_hash64_use_vrma(env); |
33595dc9 | 755 | } |
03695a98 | 756 | if (vpm && !mmuidx_hv(mmu_idx)) { |
33595dc9 BH |
757 | cs->exception_index = POWERPC_EXCP_HISI; |
758 | } else { | |
759 | cs->exception_index = POWERPC_EXCP_ISI; | |
760 | } | |
761 | env->error_code = error_code; | |
762 | } | |
763 | ||
03695a98 | 764 | static void ppc_hash64_set_dsi(CPUState *cs, int mmu_idx, uint64_t dar, uint64_t dsisr) |
33595dc9 | 765 | { |
8fe08fac | 766 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
33595dc9 BH |
767 | bool vpm; |
768 | ||
03695a98 | 769 | if (!mmuidx_real(mmu_idx)) { |
33595dc9 BH |
770 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); |
771 | } else { | |
1b99e029 | 772 | vpm = ppc_hash64_use_vrma(env); |
33595dc9 | 773 | } |
03695a98 | 774 | if (vpm && !mmuidx_hv(mmu_idx)) { |
33595dc9 BH |
775 | cs->exception_index = POWERPC_EXCP_HDSI; |
776 | env->spr[SPR_HDAR] = dar; | |
777 | env->spr[SPR_HDSISR] = dsisr; | |
778 | } else { | |
779 | cs->exception_index = POWERPC_EXCP_DSI; | |
780 | env->spr[SPR_DAR] = dar; | |
781 | env->spr[SPR_DSISR] = dsisr; | |
782 | } | |
783 | env->error_code = 0; | |
784 | } | |
785 | ||
786 | ||
a2dd4e83 BH |
787 | static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) |
788 | { | |
789 | hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 16; | |
790 | ||
791 | if (cpu->vhyp) { | |
792 | PPCVirtualHypervisorClass *vhc = | |
793 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
794 | vhc->hpte_set_r(cpu->vhyp, ptex, pte1); | |
795 | return; | |
796 | } | |
797 | base = ppc_hash64_hpt_base(cpu); | |
798 | ||
799 | ||
800 | /* The HW performs a non-atomic byte update */ | |
801 | stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01); | |
802 | } | |
803 | ||
804 | static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) | |
805 | { | |
806 | hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 15; | |
807 | ||
808 | if (cpu->vhyp) { | |
809 | PPCVirtualHypervisorClass *vhc = | |
810 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
811 | vhc->hpte_set_c(cpu->vhyp, ptex, pte1); | |
812 | return; | |
813 | } | |
814 | base = ppc_hash64_hpt_base(cpu); | |
815 | ||
816 | /* The HW performs a non-atomic byte update */ | |
817 | stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); | |
818 | } | |
819 | ||
a864a6b3 DG |
820 | static target_ulong rmls_limit(PowerPCCPU *cpu) |
821 | { | |
822 | CPUPPCState *env = &cpu->env; | |
823 | /* | |
d37b40da DG |
824 | * In theory the meanings of RMLS values are implementation |
825 | * dependent. In practice, this seems to have been the set from | |
826 | * POWER4+..POWER8, and RMLS is no longer supported in POWER9. | |
a864a6b3 DG |
827 | * |
828 | * Unsupported values mean the OS has shot itself in the | |
829 | * foot. Return a 0-sized RMA in this case, which we expect | |
830 | * to trigger an immediate DSI or ISI | |
831 | */ | |
832 | static const target_ulong rma_sizes[16] = { | |
d37b40da | 833 | [0] = 256 * GiB, |
a864a6b3 DG |
834 | [1] = 16 * GiB, |
835 | [2] = 1 * GiB, | |
836 | [3] = 64 * MiB, | |
837 | [4] = 256 * MiB, | |
838 | [7] = 128 * MiB, | |
839 | [8] = 32 * MiB, | |
840 | }; | |
841 | target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT; | |
842 | ||
843 | return rma_sizes[rmls]; | |
844 | } | |
845 | ||
4c24a87f DG |
846 | static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) |
847 | { | |
848 | CPUPPCState *env = &cpu->env; | |
849 | target_ulong lpcr = env->spr[SPR_LPCR]; | |
850 | uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; | |
851 | target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK); | |
852 | int i; | |
853 | ||
854 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
855 | const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; | |
856 | ||
857 | if (!sps->page_shift) { | |
858 | break; | |
859 | } | |
860 | ||
861 | if ((vsid & SLB_VSID_LLP_MASK) == sps->slb_enc) { | |
862 | slb->esid = SLB_ESID_V; | |
863 | slb->vsid = vsid; | |
864 | slb->sps = sps; | |
865 | return 0; | |
866 | } | |
867 | } | |
868 | ||
869 | error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x" | |
ff5b5d5b | 870 | TARGET_FMT_lx, lpcr); |
4c24a87f DG |
871 | |
872 | return -1; | |
873 | } | |
874 | ||
51806b54 | 875 | bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, |
03695a98 | 876 | hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, |
51806b54 | 877 | bool guest_visible) |
0480884f | 878 | { |
d0e39c5d AF |
879 | CPUState *cs = CPU(cpu); |
880 | CPUPPCState *env = &cpu->env; | |
4c24a87f | 881 | ppc_slb_t vrma_slbe; |
0480884f | 882 | ppc_slb_t *slb; |
be18b2b5 | 883 | unsigned apshift; |
7222b94a | 884 | hwaddr ptex; |
7f3bdc2d | 885 | ppc_hash_pte64_t pte; |
07a68f99 | 886 | int exec_prot, pp_prot, amr_prot, prot; |
182357db | 887 | int need_prot; |
caa597bd | 888 | hwaddr raddr; |
0480884f | 889 | |
d75cbae8 DG |
890 | /* |
891 | * Note on LPCR usage: 970 uses HID4, but our special variant of | |
892 | * store_spr copies relevant fields into env->spr[SPR_LPCR]. | |
136fbf65 | 893 | * Similarly we filter unimplemented bits when storing into LPCR |
d75cbae8 DG |
894 | * depending on the MMU version. This code can thus just use the |
895 | * LPCR "as-is". | |
912acdf4 BH |
896 | */ |
897 | ||
65d61643 | 898 | /* 1. Handle real mode accesses */ |
03695a98 | 899 | if (mmuidx_real(mmu_idx)) { |
d75cbae8 DG |
900 | /* |
901 | * Translation is supposedly "off", but in real mode the top 4 | |
902 | * effective address bits are (mostly) ignored | |
903 | */ | |
caa597bd | 904 | raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; |
912acdf4 | 905 | |
682c1dfb DG |
906 | if (cpu->vhyp) { |
907 | /* | |
908 | * In virtual hypervisor mode, there's nothing to do: | |
909 | * EA == GPA == qemu guest address | |
910 | */ | |
03695a98 | 911 | } else if (mmuidx_hv(mmu_idx) || !env->has_hv_mode) { |
682c1dfb | 912 | /* In HV mode, add HRMOR if top EA bit is clear */ |
912acdf4 BH |
913 | if (!(eaddr >> 63)) { |
914 | raddr |= env->spr[SPR_HRMOR]; | |
915 | } | |
1b99e029 | 916 | } else if (ppc_hash64_use_vrma(env)) { |
682c1dfb | 917 | /* Emulated VRMA mode */ |
4c24a87f DG |
918 | slb = &vrma_slbe; |
919 | if (build_vrma_slbe(cpu, slb) != 0) { | |
682c1dfb | 920 | /* Invalid VRMA setup, machine check */ |
1a8c647b RH |
921 | if (guest_visible) { |
922 | cs->exception_index = POWERPC_EXCP_MCHECK; | |
923 | env->error_code = 0; | |
924 | } | |
925 | return false; | |
682c1dfb DG |
926 | } |
927 | ||
928 | goto skip_slb_search; | |
929 | } else { | |
3a56a55c DG |
930 | target_ulong limit = rmls_limit(cpu); |
931 | ||
682c1dfb | 932 | /* Emulated old-style RMO mode, bounds check against RMLS */ |
3a56a55c | 933 | if (raddr >= limit) { |
1a8c647b RH |
934 | if (!guest_visible) { |
935 | return false; | |
936 | } | |
59dec5bf RH |
937 | switch (access_type) { |
938 | case MMU_INST_FETCH: | |
03695a98 | 939 | ppc_hash64_set_isi(cs, mmu_idx, SRR1_PROTFAULT); |
59dec5bf RH |
940 | break; |
941 | case MMU_DATA_LOAD: | |
03695a98 | 942 | ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_PROTFAULT); |
59dec5bf RH |
943 | break; |
944 | case MMU_DATA_STORE: | |
03695a98 | 945 | ppc_hash64_set_dsi(cs, mmu_idx, eaddr, |
59dec5bf RH |
946 | DSISR_PROTFAULT | DSISR_ISSTORE); |
947 | break; | |
948 | default: | |
949 | g_assert_not_reached(); | |
912acdf4 | 950 | } |
1a8c647b | 951 | return false; |
912acdf4 | 952 | } |
682c1dfb DG |
953 | |
954 | raddr |= env->spr[SPR_RMOR]; | |
912acdf4 | 955 | } |
1a8c647b RH |
956 | |
957 | *raddrp = raddr; | |
958 | *protp = PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
959 | *psizep = TARGET_PAGE_BITS; | |
960 | return true; | |
65d61643 DG |
961 | } |
962 | ||
bb218042 | 963 | /* 2. Translation is on, so look up the SLB */ |
7ef23068 | 964 | slb = slb_lookup(cpu, eaddr); |
0480884f | 965 | if (!slb) { |
b2899495 | 966 | /* No entry found, check if in-memory segment tables are in use */ |
ca79b3b7 | 967 | if (ppc64_use_proc_tbl(cpu)) { |
b2899495 SJS |
968 | /* TODO - Unsupported */ |
969 | error_report("Segment Table Support Unimplemented"); | |
970 | exit(1); | |
971 | } | |
972 | /* Segment still not found, generate the appropriate interrupt */ | |
1a8c647b RH |
973 | if (!guest_visible) { |
974 | return false; | |
975 | } | |
59dec5bf RH |
976 | switch (access_type) { |
977 | case MMU_INST_FETCH: | |
27103424 | 978 | cs->exception_index = POWERPC_EXCP_ISEG; |
caa597bd | 979 | env->error_code = 0; |
59dec5bf RH |
980 | break; |
981 | case MMU_DATA_LOAD: | |
982 | case MMU_DATA_STORE: | |
27103424 | 983 | cs->exception_index = POWERPC_EXCP_DSEG; |
caa597bd DG |
984 | env->error_code = 0; |
985 | env->spr[SPR_DAR] = eaddr; | |
59dec5bf RH |
986 | break; |
987 | default: | |
988 | g_assert_not_reached(); | |
caa597bd | 989 | } |
1a8c647b | 990 | return false; |
0480884f DG |
991 | } |
992 | ||
1a8c647b | 993 | skip_slb_search: |
912acdf4 | 994 | |
bb218042 | 995 | /* 3. Check for segment level no-execute violation */ |
59dec5bf | 996 | if (access_type == MMU_INST_FETCH && (slb->vsid & SLB_VSID_N)) { |
1a8c647b | 997 | if (guest_visible) { |
03695a98 | 998 | ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOEXEC_GUARD); |
1a8c647b RH |
999 | } |
1000 | return false; | |
bb218042 DG |
1001 | } |
1002 | ||
7f3bdc2d | 1003 | /* 4. Locate the PTE in the hash table */ |
7222b94a DG |
1004 | ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); |
1005 | if (ptex == -1) { | |
1a8c647b RH |
1006 | if (!guest_visible) { |
1007 | return false; | |
1008 | } | |
59dec5bf RH |
1009 | switch (access_type) { |
1010 | case MMU_INST_FETCH: | |
03695a98 | 1011 | ppc_hash64_set_isi(cs, mmu_idx, SRR1_NOPTE); |
59dec5bf RH |
1012 | break; |
1013 | case MMU_DATA_LOAD: | |
03695a98 | 1014 | ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE); |
59dec5bf RH |
1015 | break; |
1016 | case MMU_DATA_STORE: | |
03695a98 | 1017 | ppc_hash64_set_dsi(cs, mmu_idx, eaddr, DSISR_NOPTE | DSISR_ISSTORE); |
59dec5bf RH |
1018 | break; |
1019 | default: | |
1020 | g_assert_not_reached(); | |
caa597bd | 1021 | } |
1a8c647b | 1022 | return false; |
7f3bdc2d | 1023 | } |
339aaf5b | 1024 | qemu_log_mask(CPU_LOG_MMU, |
7222b94a | 1025 | "found PTE at index %08" HWADDR_PRIx "\n", ptex); |
7f3bdc2d DG |
1026 | |
1027 | /* 5. Check access permissions */ | |
7f3bdc2d | 1028 | |
07a68f99 | 1029 | exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte); |
03695a98 | 1030 | pp_prot = ppc_hash64_pte_prot(mmu_idx, slb, pte); |
7ef23068 | 1031 | amr_prot = ppc_hash64_amr_prot(cpu, pte); |
07a68f99 | 1032 | prot = exec_prot & pp_prot & amr_prot; |
6a980110 | 1033 | |
59dec5bf | 1034 | need_prot = prot_for_access_type(access_type); |
182357db | 1035 | if (need_prot & ~prot) { |
6a980110 | 1036 | /* Access right violation */ |
339aaf5b | 1037 | qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); |
1a8c647b RH |
1038 | if (!guest_visible) { |
1039 | return false; | |
1040 | } | |
59dec5bf | 1041 | if (access_type == MMU_INST_FETCH) { |
a6152b52 | 1042 | int srr1 = 0; |
07a68f99 SJS |
1043 | if (PAGE_EXEC & ~exec_prot) { |
1044 | srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */ | |
1045 | } else if (PAGE_EXEC & ~pp_prot) { | |
a6152b52 SJS |
1046 | srr1 |= SRR1_PROTFAULT; /* Access violates access authority */ |
1047 | } | |
1048 | if (PAGE_EXEC & ~amr_prot) { | |
1049 | srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */ | |
1050 | } | |
03695a98 | 1051 | ppc_hash64_set_isi(cs, mmu_idx, srr1); |
caa597bd | 1052 | } else { |
da82c73a | 1053 | int dsisr = 0; |
182357db | 1054 | if (need_prot & ~pp_prot) { |
da82c73a | 1055 | dsisr |= DSISR_PROTFAULT; |
f80872e2 | 1056 | } |
59dec5bf | 1057 | if (access_type == MMU_DATA_STORE) { |
da82c73a | 1058 | dsisr |= DSISR_ISSTORE; |
f80872e2 | 1059 | } |
182357db | 1060 | if (need_prot & ~amr_prot) { |
da82c73a | 1061 | dsisr |= DSISR_AMR; |
caa597bd | 1062 | } |
03695a98 | 1063 | ppc_hash64_set_dsi(cs, mmu_idx, eaddr, dsisr); |
caa597bd | 1064 | } |
1a8c647b | 1065 | return false; |
6a980110 DG |
1066 | } |
1067 | ||
339aaf5b | 1068 | qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); |
87dc3fd1 DG |
1069 | |
1070 | /* 6. Update PTE referenced and changed bits if necessary */ | |
1071 | ||
a2dd4e83 BH |
1072 | if (!(pte.pte1 & HPTE64_R_R)) { |
1073 | ppc_hash64_set_r(cpu, ptex, pte.pte1); | |
b3440746 | 1074 | } |
a2dd4e83 | 1075 | if (!(pte.pte1 & HPTE64_R_C)) { |
59dec5bf | 1076 | if (access_type == MMU_DATA_STORE) { |
a2dd4e83 BH |
1077 | ppc_hash64_set_c(cpu, ptex, pte.pte1); |
1078 | } else { | |
1079 | /* | |
1080 | * Treat the page as read-only for now, so that a later write | |
1081 | * will pass through this function again to set the C bit | |
1082 | */ | |
1083 | prot &= ~PAGE_WRITE; | |
1084 | } | |
7f3bdc2d | 1085 | } |
0480884f | 1086 | |
6d11d998 DG |
1087 | /* 7. Determine the real address from the PTE */ |
1088 | ||
1a8c647b RH |
1089 | *raddrp = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); |
1090 | *protp = prot; | |
1091 | *psizep = apshift; | |
1092 | return true; | |
0480884f | 1093 | } |
629bd516 | 1094 | |
7222b94a | 1095 | void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, |
61a36c9b DG |
1096 | target_ulong pte0, target_ulong pte1) |
1097 | { | |
1098 | /* | |
1099 | * XXX: given the fact that there are too many segments to | |
1100 | * invalidate, and we still don't have a tlb_flush_mask(env, n, | |
1101 | * mask) in QEMU, we just invalidate all TLBs | |
1102 | */ | |
d76ab5e1 | 1103 | cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; |
61a36c9b | 1104 | } |
4b3fc377 | 1105 | |
2b44e219 | 1106 | #ifdef CONFIG_TCG |
5ad55315 DG |
1107 | void helper_store_lpcr(CPUPPCState *env, target_ulong val) |
1108 | { | |
db70b311 | 1109 | PowerPCCPU *cpu = env_archcpu(env); |
5ad55315 DG |
1110 | |
1111 | ppc_store_lpcr(cpu, val); | |
1112 | } | |
2b44e219 | 1113 | #endif |
5ad55315 | 1114 | |
a059471d DG |
1115 | void ppc_hash64_init(PowerPCCPU *cpu) |
1116 | { | |
1117 | CPUPPCState *env = &cpu->env; | |
1118 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
1119 | ||
21e405f1 | 1120 | if (!pcc->hash64_opts) { |
d57d72a8 | 1121 | assert(!mmu_is_64bit(env->mmu_model)); |
21e405f1 | 1122 | return; |
a059471d | 1123 | } |
21e405f1 DG |
1124 | |
1125 | cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts)); | |
a059471d DG |
1126 | } |
1127 | ||
1128 | void ppc_hash64_finalize(PowerPCCPU *cpu) | |
1129 | { | |
b07c59f7 | 1130 | g_free(cpu->hash64_opts); |
a059471d | 1131 | } |
b07c59f7 | 1132 | |
21e405f1 | 1133 | const PPCHash64Options ppc_hash64_opts_basic = { |
58969eee | 1134 | .flags = 0, |
67d7d66f | 1135 | .slb_size = 64, |
21e405f1 DG |
1136 | .sps = { |
1137 | { .page_shift = 12, /* 4K */ | |
1138 | .slb_enc = 0, | |
1139 | .enc = { { .page_shift = 12, .pte_enc = 0 } } | |
1140 | }, | |
1141 | { .page_shift = 24, /* 16M */ | |
1142 | .slb_enc = 0x100, | |
1143 | .enc = { { .page_shift = 24, .pte_enc = 0 } } | |
1144 | }, | |
1145 | }, | |
1146 | }; | |
1147 | ||
b07c59f7 | 1148 | const PPCHash64Options ppc_hash64_opts_POWER7 = { |
26cd35b8 | 1149 | .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE, |
67d7d66f | 1150 | .slb_size = 32, |
b07c59f7 DG |
1151 | .sps = { |
1152 | { | |
1153 | .page_shift = 12, /* 4K */ | |
1154 | .slb_enc = 0, | |
1155 | .enc = { { .page_shift = 12, .pte_enc = 0 }, | |
1156 | { .page_shift = 16, .pte_enc = 0x7 }, | |
1157 | { .page_shift = 24, .pte_enc = 0x38 }, }, | |
1158 | }, | |
1159 | { | |
1160 | .page_shift = 16, /* 64K */ | |
1161 | .slb_enc = SLB_VSID_64K, | |
1162 | .enc = { { .page_shift = 16, .pte_enc = 0x1 }, | |
1163 | { .page_shift = 24, .pte_enc = 0x8 }, }, | |
1164 | }, | |
1165 | { | |
1166 | .page_shift = 24, /* 16M */ | |
1167 | .slb_enc = SLB_VSID_16M, | |
1168 | .enc = { { .page_shift = 24, .pte_enc = 0 }, }, | |
1169 | }, | |
1170 | { | |
1171 | .page_shift = 34, /* 16G */ | |
1172 | .slb_enc = SLB_VSID_16G, | |
1173 | .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, | |
1174 | }, | |
1175 | } | |
1176 | }; | |
27f00f0a | 1177 | |
27f00f0a | 1178 |