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Commit | Line | Data |
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10b46525 DG |
1 | /* |
2 | * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * Copyright (c) 2013 David Gibson, IBM Corporation | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
0d75590d | 20 | #include "qemu/osdep.h" |
a864a6b3 | 21 | #include "qemu/units.h" |
10b46525 | 22 | #include "cpu.h" |
63c91552 | 23 | #include "exec/exec-all.h" |
2ef6175a | 24 | #include "exec/helper-proto.h" |
cd6a9bb6 | 25 | #include "qemu/error-report.h" |
fad866da | 26 | #include "qemu/qemu-print.h" |
b3946626 | 27 | #include "sysemu/hw_accel.h" |
10b46525 DG |
28 | #include "kvm_ppc.h" |
29 | #include "mmu-hash64.h" | |
508127e2 | 30 | #include "exec/log.h" |
7222b94a | 31 | #include "hw/hw.h" |
b2899495 | 32 | #include "mmu-book3s-v3.h" |
10b46525 | 33 | |
d75cbae8 | 34 | /* #define DEBUG_SLB */ |
10b46525 DG |
35 | |
36 | #ifdef DEBUG_SLB | |
48880da6 | 37 | # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) |
10b46525 DG |
38 | #else |
39 | # define LOG_SLB(...) do { } while (0) | |
40 | #endif | |
41 | ||
42 | /* | |
43 | * SLB handling | |
44 | */ | |
45 | ||
7ef23068 | 46 | static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) |
10b46525 | 47 | { |
7ef23068 | 48 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
49 | uint64_t esid_256M, esid_1T; |
50 | int n; | |
51 | ||
52 | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); | |
53 | ||
54 | esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; | |
55 | esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; | |
56 | ||
67d7d66f | 57 | for (n = 0; n < cpu->hash64_opts->slb_size; n++) { |
10b46525 DG |
58 | ppc_slb_t *slb = &env->slb[n]; |
59 | ||
60 | LOG_SLB("%s: slot %d %016" PRIx64 " %016" | |
61 | PRIx64 "\n", __func__, n, slb->esid, slb->vsid); | |
d75cbae8 DG |
62 | /* |
63 | * We check for 1T matches on all MMUs here - if the MMU | |
10b46525 | 64 | * doesn't have 1T segment support, we will have prevented 1T |
d75cbae8 DG |
65 | * entries from being inserted in the slbmte code. |
66 | */ | |
10b46525 DG |
67 | if (((slb->esid == esid_256M) && |
68 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M)) | |
69 | || ((slb->esid == esid_1T) && | |
70 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) { | |
71 | return slb; | |
72 | } | |
73 | } | |
74 | ||
75 | return NULL; | |
76 | } | |
77 | ||
fad866da | 78 | void dump_slb(PowerPCCPU *cpu) |
10b46525 | 79 | { |
7ef23068 | 80 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
81 | int i; |
82 | uint64_t slbe, slbv; | |
83 | ||
7ef23068 | 84 | cpu_synchronize_state(CPU(cpu)); |
10b46525 | 85 | |
fad866da | 86 | qemu_printf("SLB\tESID\t\t\tVSID\n"); |
67d7d66f | 87 | for (i = 0; i < cpu->hash64_opts->slb_size; i++) { |
10b46525 DG |
88 | slbe = env->slb[i].esid; |
89 | slbv = env->slb[i].vsid; | |
90 | if (slbe == 0 && slbv == 0) { | |
91 | continue; | |
92 | } | |
fad866da | 93 | qemu_printf("%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", |
10b46525 DG |
94 | i, slbe, slbv); |
95 | } | |
96 | } | |
97 | ||
0418bf78 | 98 | void helper_slbia(CPUPPCState *env, uint32_t ih) |
10b46525 | 99 | { |
db70b311 | 100 | PowerPCCPU *cpu = env_archcpu(env); |
0418bf78 | 101 | int starting_entry; |
cd0c6f47 | 102 | int n; |
10b46525 | 103 | |
f9e3e1a3 NP |
104 | /* |
105 | * slbia must always flush all TLB (which is equivalent to ERAT in ppc | |
106 | * architecture). Matching on SLB_ESID_V is not good enough, because slbmte | |
107 | * can overwrite a valid SLB without flushing its lookaside information. | |
108 | * | |
109 | * It would be possible to keep the TLB in synch with the SLB by flushing | |
110 | * when a valid entry is overwritten by slbmte, and therefore slbia would | |
111 | * not have to flush unless it evicts a valid SLB entry. However it is | |
112 | * expected that slbmte is more common than slbia, and slbia is usually | |
113 | * going to evict valid SLB entries, so that tradeoff is unlikely to be a | |
114 | * good one. | |
0418bf78 NP |
115 | * |
116 | * ISA v2.05 introduced IH field with values 0,1,2,6. These all invalidate | |
117 | * the same SLB entries (everything but entry 0), but differ in what | |
118 | * "lookaside information" is invalidated. TCG can ignore this and flush | |
119 | * everything. | |
120 | * | |
121 | * ISA v3.0 introduced additional values 3,4,7, which change what SLBs are | |
122 | * invalidated. | |
f9e3e1a3 NP |
123 | */ |
124 | ||
0418bf78 | 125 | env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; |
10b46525 | 126 | |
0418bf78 NP |
127 | starting_entry = 1; /* default for IH=0,1,2,6 */ |
128 | ||
129 | if (env->mmu_model == POWERPC_MMU_3_00) { | |
130 | switch (ih) { | |
131 | case 0x7: | |
132 | /* invalidate no SLBs, but all lookaside information */ | |
133 | return; | |
134 | ||
135 | case 0x3: | |
136 | case 0x4: | |
137 | /* also considers SLB entry 0 */ | |
138 | starting_entry = 0; | |
139 | break; | |
140 | ||
141 | case 0x5: | |
142 | /* treat undefined values as ih==0, and warn */ | |
143 | qemu_log_mask(LOG_GUEST_ERROR, | |
144 | "slbia undefined IH field %u.\n", ih); | |
145 | break; | |
146 | ||
147 | default: | |
148 | /* 0,1,2,6 */ | |
149 | break; | |
10b46525 DG |
150 | } |
151 | } | |
f9e3e1a3 | 152 | |
0418bf78 NP |
153 | for (n = starting_entry; n < cpu->hash64_opts->slb_size; n++) { |
154 | ppc_slb_t *slb = &env->slb[n]; | |
155 | ||
156 | if (!(slb->esid & SLB_ESID_V)) { | |
157 | continue; | |
158 | } | |
159 | if (env->mmu_model == POWERPC_MMU_3_00) { | |
160 | if (ih == 0x3 && (slb->vsid & SLB_VSID_C) == 0) { | |
161 | /* preserves entries with a class value of 0 */ | |
162 | continue; | |
163 | } | |
164 | } | |
165 | ||
166 | slb->esid &= ~SLB_ESID_V; | |
167 | } | |
10b46525 DG |
168 | } |
169 | ||
a63f1dfc ND |
170 | static void __helper_slbie(CPUPPCState *env, target_ulong addr, |
171 | target_ulong global) | |
10b46525 | 172 | { |
db70b311 | 173 | PowerPCCPU *cpu = env_archcpu(env); |
10b46525 DG |
174 | ppc_slb_t *slb; |
175 | ||
7ef23068 | 176 | slb = slb_lookup(cpu, addr); |
10b46525 DG |
177 | if (!slb) { |
178 | return; | |
179 | } | |
180 | ||
181 | if (slb->esid & SLB_ESID_V) { | |
182 | slb->esid &= ~SLB_ESID_V; | |
183 | ||
d75cbae8 DG |
184 | /* |
185 | * XXX: given the fact that segment size is 256 MB or 1TB, | |
10b46525 DG |
186 | * and we still don't have a tlb_flush_mask(env, n, mask) |
187 | * in QEMU, we just invalidate all TLBs | |
188 | */ | |
a63f1dfc ND |
189 | env->tlb_need_flush |= |
190 | (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH); | |
10b46525 DG |
191 | } |
192 | } | |
193 | ||
a63f1dfc ND |
194 | void helper_slbie(CPUPPCState *env, target_ulong addr) |
195 | { | |
196 | __helper_slbie(env, addr, false); | |
197 | } | |
198 | ||
199 | void helper_slbieg(CPUPPCState *env, target_ulong addr) | |
200 | { | |
201 | __helper_slbie(env, addr, true); | |
202 | } | |
203 | ||
bcd81230 DG |
204 | int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, |
205 | target_ulong esid, target_ulong vsid) | |
10b46525 | 206 | { |
7ef23068 | 207 | CPUPPCState *env = &cpu->env; |
10b46525 | 208 | ppc_slb_t *slb = &env->slb[slot]; |
b07c59f7 | 209 | const PPCHash64SegmentPageSizes *sps = NULL; |
cd6a9bb6 | 210 | int i; |
10b46525 | 211 | |
67d7d66f | 212 | if (slot >= cpu->hash64_opts->slb_size) { |
bcd81230 DG |
213 | return -1; /* Bad slot number */ |
214 | } | |
215 | if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { | |
216 | return -1; /* Reserved bits set */ | |
10b46525 | 217 | } |
bcd81230 | 218 | if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { |
10b46525 DG |
219 | return -1; /* Bad segment size */ |
220 | } | |
58969eee | 221 | if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { |
10b46525 DG |
222 | return -1; /* 1T segment on MMU that doesn't support it */ |
223 | } | |
224 | ||
cd6a9bb6 | 225 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
b07c59f7 | 226 | const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; |
cd6a9bb6 DG |
227 | |
228 | if (!sps1->page_shift) { | |
229 | break; | |
230 | } | |
231 | ||
232 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { | |
233 | sps = sps1; | |
234 | break; | |
235 | } | |
236 | } | |
237 | ||
238 | if (!sps) { | |
239 | error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu | |
240 | " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx, | |
241 | slot, esid, vsid); | |
242 | return -1; | |
243 | } | |
244 | ||
bcd81230 DG |
245 | slb->esid = esid; |
246 | slb->vsid = vsid; | |
cd6a9bb6 | 247 | slb->sps = sps; |
10b46525 | 248 | |
76134d48 SJS |
249 | LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx |
250 | " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid, | |
10b46525 DG |
251 | slb->esid, slb->vsid); |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
7ef23068 | 256 | static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
257 | target_ulong *rt) |
258 | { | |
7ef23068 | 259 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
260 | int slot = rb & 0xfff; |
261 | ppc_slb_t *slb = &env->slb[slot]; | |
262 | ||
67d7d66f | 263 | if (slot >= cpu->hash64_opts->slb_size) { |
10b46525 DG |
264 | return -1; |
265 | } | |
266 | ||
267 | *rt = slb->esid; | |
268 | return 0; | |
269 | } | |
270 | ||
7ef23068 | 271 | static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
272 | target_ulong *rt) |
273 | { | |
7ef23068 | 274 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
275 | int slot = rb & 0xfff; |
276 | ppc_slb_t *slb = &env->slb[slot]; | |
277 | ||
67d7d66f | 278 | if (slot >= cpu->hash64_opts->slb_size) { |
10b46525 DG |
279 | return -1; |
280 | } | |
281 | ||
282 | *rt = slb->vsid; | |
283 | return 0; | |
284 | } | |
285 | ||
c76c22d5 BH |
286 | static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
287 | target_ulong *rt) | |
288 | { | |
289 | CPUPPCState *env = &cpu->env; | |
290 | ppc_slb_t *slb; | |
291 | ||
292 | if (!msr_is_64bit(env, env->msr)) { | |
293 | rb &= 0xffffffff; | |
294 | } | |
295 | slb = slb_lookup(cpu, rb); | |
296 | if (slb == NULL) { | |
297 | *rt = (target_ulong)-1ul; | |
298 | } else { | |
299 | *rt = slb->vsid; | |
300 | } | |
301 | return 0; | |
302 | } | |
303 | ||
10b46525 DG |
304 | void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) |
305 | { | |
db70b311 | 306 | PowerPCCPU *cpu = env_archcpu(env); |
7ef23068 | 307 | |
bcd81230 | 308 | if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { |
0f72b7c6 BH |
309 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
310 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
311 | } |
312 | } | |
313 | ||
314 | target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) | |
315 | { | |
db70b311 | 316 | PowerPCCPU *cpu = env_archcpu(env); |
10b46525 DG |
317 | target_ulong rt = 0; |
318 | ||
7ef23068 | 319 | if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { |
0f72b7c6 BH |
320 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
321 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
322 | } |
323 | return rt; | |
324 | } | |
325 | ||
c76c22d5 BH |
326 | target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) |
327 | { | |
db70b311 | 328 | PowerPCCPU *cpu = env_archcpu(env); |
c76c22d5 BH |
329 | target_ulong rt = 0; |
330 | ||
331 | if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { | |
0f72b7c6 BH |
332 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
333 | POWERPC_EXCP_INVAL, GETPC()); | |
c76c22d5 BH |
334 | } |
335 | return rt; | |
336 | } | |
337 | ||
10b46525 DG |
338 | target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) |
339 | { | |
db70b311 | 340 | PowerPCCPU *cpu = env_archcpu(env); |
10b46525 DG |
341 | target_ulong rt = 0; |
342 | ||
7ef23068 | 343 | if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { |
0f72b7c6 BH |
344 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
345 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
346 | } |
347 | return rt; | |
348 | } | |
9d7c3f4a | 349 | |
07a68f99 SJS |
350 | /* Check No-Execute or Guarded Storage */ |
351 | static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, | |
352 | ppc_hash_pte64_t pte) | |
353 | { | |
354 | /* Exec permissions CANNOT take away read or write permissions */ | |
355 | return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ? | |
356 | PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
357 | } | |
358 | ||
359 | /* Check Basic Storage Protection */ | |
7ef23068 | 360 | static int ppc_hash64_pte_prot(PowerPCCPU *cpu, |
e01b4445 | 361 | ppc_slb_t *slb, ppc_hash_pte64_t pte) |
496272a7 | 362 | { |
7ef23068 | 363 | CPUPPCState *env = &cpu->env; |
e01b4445 | 364 | unsigned pp, key; |
d75cbae8 DG |
365 | /* |
366 | * Some pp bit combinations have undefined behaviour, so default | |
367 | * to no access in those cases | |
368 | */ | |
e01b4445 DG |
369 | int prot = 0; |
370 | ||
371 | key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP) | |
372 | : (slb->vsid & SLB_VSID_KS)); | |
373 | pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); | |
496272a7 | 374 | |
496272a7 DG |
375 | if (key == 0) { |
376 | switch (pp) { | |
377 | case 0x0: | |
378 | case 0x1: | |
379 | case 0x2: | |
347a5c73 | 380 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
e01b4445 DG |
381 | break; |
382 | ||
496272a7 DG |
383 | case 0x3: |
384 | case 0x6: | |
347a5c73 | 385 | prot = PAGE_READ | PAGE_EXEC; |
496272a7 DG |
386 | break; |
387 | } | |
388 | } else { | |
389 | switch (pp) { | |
390 | case 0x0: | |
391 | case 0x6: | |
496272a7 | 392 | break; |
e01b4445 | 393 | |
496272a7 DG |
394 | case 0x1: |
395 | case 0x3: | |
347a5c73 | 396 | prot = PAGE_READ | PAGE_EXEC; |
496272a7 | 397 | break; |
e01b4445 | 398 | |
496272a7 | 399 | case 0x2: |
347a5c73 | 400 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
496272a7 DG |
401 | break; |
402 | } | |
403 | } | |
496272a7 | 404 | |
e01b4445 | 405 | return prot; |
496272a7 DG |
406 | } |
407 | ||
a6152b52 SJS |
408 | /* Check the instruction access permissions specified in the IAMR */ |
409 | static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key) | |
410 | { | |
411 | CPUPPCState *env = &cpu->env; | |
412 | int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3; | |
413 | ||
414 | /* | |
415 | * An instruction fetch is permitted if the IAMR bit is 0. | |
416 | * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit | |
417 | * can only take away EXEC permissions not READ or WRITE permissions. | |
418 | * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since | |
419 | * EXEC permissions are allowed. | |
420 | */ | |
421 | return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE : | |
422 | PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
423 | } | |
424 | ||
7ef23068 | 425 | static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) |
f80872e2 | 426 | { |
7ef23068 | 427 | CPUPPCState *env = &cpu->env; |
f80872e2 | 428 | int key, amrbits; |
363248e8 | 429 | int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
f80872e2 | 430 | |
f80872e2 | 431 | /* Only recent MMUs implement Virtual Page Class Key Protection */ |
58969eee | 432 | if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { |
363248e8 | 433 | return prot; |
f80872e2 DG |
434 | } |
435 | ||
436 | key = HPTE64_R_KEY(pte.pte1); | |
d75cbae8 | 437 | amrbits = (env->spr[SPR_AMR] >> 2 * (31 - key)) & 0x3; |
f80872e2 DG |
438 | |
439 | /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */ | |
440 | /* env->spr[SPR_AMR]); */ | |
441 | ||
363248e8 CLG |
442 | /* |
443 | * A store is permitted if the AMR bit is 0. Remove write | |
444 | * protection if it is set. | |
445 | */ | |
f80872e2 | 446 | if (amrbits & 0x2) { |
363248e8 | 447 | prot &= ~PAGE_WRITE; |
f80872e2 | 448 | } |
363248e8 CLG |
449 | /* |
450 | * A load is permitted if the AMR bit is 0. Remove read | |
451 | * protection if it is set. | |
452 | */ | |
f80872e2 | 453 | if (amrbits & 0x1) { |
363248e8 | 454 | prot &= ~PAGE_READ; |
f80872e2 DG |
455 | } |
456 | ||
a6152b52 SJS |
457 | switch (env->mmu_model) { |
458 | /* | |
459 | * MMU version 2.07 and later support IAMR | |
460 | * Check if the IAMR allows the instruction access - it will return | |
461 | * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0 | |
462 | * if it does (and prot will be unchanged indicating execution support). | |
463 | */ | |
464 | case POWERPC_MMU_2_07: | |
465 | case POWERPC_MMU_3_00: | |
466 | prot &= ppc_hash64_iamr_prot(cpu, key); | |
467 | break; | |
468 | default: | |
469 | break; | |
470 | } | |
471 | ||
f80872e2 DG |
472 | return prot; |
473 | } | |
474 | ||
7222b94a DG |
475 | const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, |
476 | hwaddr ptex, int n) | |
7c43bca0 | 477 | { |
7222b94a | 478 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; |
3367c62f | 479 | hwaddr base; |
e57ca75c DG |
480 | hwaddr plen = n * HASH_PTE_SIZE_64; |
481 | const ppc_hash_pte64_t *hptes; | |
7c43bca0 | 482 | |
e57ca75c DG |
483 | if (cpu->vhyp) { |
484 | PPCVirtualHypervisorClass *vhc = | |
485 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
486 | return vhc->map_hptes(cpu->vhyp, ptex, n); | |
487 | } | |
3367c62f | 488 | base = ppc_hash64_hpt_base(cpu); |
e57ca75c DG |
489 | |
490 | if (!base) { | |
491 | return NULL; | |
492 | } | |
493 | ||
f26404fb PM |
494 | hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false, |
495 | MEMTXATTRS_UNSPECIFIED); | |
e57ca75c DG |
496 | if (plen < (n * HASH_PTE_SIZE_64)) { |
497 | hw_error("%s: Unable to map all requested HPTEs\n", __func__); | |
7c43bca0 | 498 | } |
7222b94a | 499 | return hptes; |
7c43bca0 AK |
500 | } |
501 | ||
7222b94a DG |
502 | void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes, |
503 | hwaddr ptex, int n) | |
7c43bca0 | 504 | { |
e57ca75c DG |
505 | if (cpu->vhyp) { |
506 | PPCVirtualHypervisorClass *vhc = | |
507 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
508 | vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n); | |
509 | return; | |
7c43bca0 | 510 | } |
e57ca75c DG |
511 | |
512 | address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64, | |
513 | false, n * HASH_PTE_SIZE_64); | |
7c43bca0 AK |
514 | } |
515 | ||
b07c59f7 DG |
516 | static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps, |
517 | uint64_t pte0, uint64_t pte1) | |
4322e8ce | 518 | { |
651060ab DG |
519 | int i; |
520 | ||
521 | if (!(pte0 & HPTE64_V_LARGE)) { | |
522 | if (sps->page_shift != 12) { | |
523 | /* 4kiB page in a non 4kiB segment */ | |
524 | return 0; | |
525 | } | |
526 | /* Normal 4kiB page */ | |
4322e8ce | 527 | return 12; |
651060ab DG |
528 | } |
529 | ||
530 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
b07c59f7 | 531 | const PPCHash64PageSize *ps = &sps->enc[i]; |
651060ab DG |
532 | uint64_t mask; |
533 | ||
534 | if (!ps->page_shift) { | |
535 | break; | |
4322e8ce | 536 | } |
651060ab DG |
537 | |
538 | if (ps->page_shift == 12) { | |
539 | /* L bit is set so this can't be a 4kiB page */ | |
540 | continue; | |
541 | } | |
542 | ||
543 | mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN; | |
544 | ||
b56d417b | 545 | if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) { |
651060ab | 546 | return ps->page_shift; |
4322e8ce | 547 | } |
4322e8ce | 548 | } |
651060ab DG |
549 | |
550 | return 0; /* Bad page size encoding */ | |
4322e8ce BH |
551 | } |
552 | ||
34525595 BH |
553 | static void ppc64_v3_new_to_old_hpte(target_ulong *pte0, target_ulong *pte1) |
554 | { | |
555 | /* Insert B into pte0 */ | |
556 | *pte0 = (*pte0 & HPTE64_V_COMMON_BITS) | | |
557 | ((*pte1 & HPTE64_R_3_0_SSIZE_MASK) << | |
558 | (HPTE64_V_SSIZE_SHIFT - HPTE64_R_3_0_SSIZE_SHIFT)); | |
559 | ||
560 | /* Remove B from pte1 */ | |
561 | *pte1 = *pte1 & ~HPTE64_R_3_0_SSIZE_MASK; | |
562 | } | |
563 | ||
564 | ||
7ef23068 | 565 | static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash, |
b07c59f7 | 566 | const PPCHash64SegmentPageSizes *sps, |
2c7ad804 | 567 | target_ulong ptem, |
94986863 | 568 | ppc_hash_pte64_t *pte, unsigned *pshift) |
aea390e4 | 569 | { |
aea390e4 | 570 | int i; |
7222b94a | 571 | const ppc_hash_pte64_t *pteg; |
7c43bca0 | 572 | target_ulong pte0, pte1; |
7222b94a | 573 | target_ulong ptex; |
aea390e4 | 574 | |
36778660 | 575 | ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP; |
7222b94a DG |
576 | pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); |
577 | if (!pteg) { | |
7c43bca0 AK |
578 | return -1; |
579 | } | |
aea390e4 | 580 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
7222b94a | 581 | pte0 = ppc_hash64_hpte0(cpu, pteg, i); |
3054b0ca BH |
582 | /* |
583 | * pte0 contains the valid bit and must be read before pte1, | |
584 | * otherwise we might see an old pte1 with a new valid bit and | |
585 | * thus an inconsistent hpte value | |
586 | */ | |
587 | smp_rmb(); | |
7222b94a | 588 | pte1 = ppc_hash64_hpte1(cpu, pteg, i); |
aea390e4 | 589 | |
34525595 BH |
590 | /* Convert format if necessary */ |
591 | if (cpu->env.mmu_model == POWERPC_MMU_3_00 && !cpu->vhyp) { | |
592 | ppc64_v3_new_to_old_hpte(&pte0, &pte1); | |
593 | } | |
594 | ||
073de86a DG |
595 | /* This compares V, B, H (secondary) and the AVPN */ |
596 | if (HPTE64_V_COMPARE(pte0, ptem)) { | |
2c7ad804 | 597 | *pshift = hpte_page_shift(sps, pte0, pte1); |
651060ab DG |
598 | /* |
599 | * If there is no match, ignore the PTE, it could simply | |
600 | * be for a different segment size encoding and the | |
601 | * architecture specifies we should not match. Linux will | |
602 | * potentially leave behind PTEs for the wrong base page | |
603 | * size when demoting segments. | |
604 | */ | |
94986863 | 605 | if (*pshift == 0) { |
4322e8ce BH |
606 | continue; |
607 | } | |
d75cbae8 DG |
608 | /* |
609 | * We don't do anything with pshift yet as qemu TLB only | |
610 | * deals with 4K pages anyway | |
4322e8ce | 611 | */ |
aea390e4 DG |
612 | pte->pte0 = pte0; |
613 | pte->pte1 = pte1; | |
7222b94a DG |
614 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
615 | return ptex + i; | |
aea390e4 | 616 | } |
aea390e4 | 617 | } |
7222b94a | 618 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
7c43bca0 AK |
619 | /* |
620 | * We didn't find a valid entry. | |
621 | */ | |
aea390e4 DG |
622 | return -1; |
623 | } | |
624 | ||
7ef23068 | 625 | static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, |
7f3bdc2d | 626 | ppc_slb_t *slb, target_ulong eaddr, |
94986863 | 627 | ppc_hash_pte64_t *pte, unsigned *pshift) |
c69b6151 | 628 | { |
7ef23068 | 629 | CPUPPCState *env = &cpu->env; |
7222b94a | 630 | hwaddr hash, ptex; |
cd6a9bb6 | 631 | uint64_t vsid, epnmask, epn, ptem; |
b07c59f7 | 632 | const PPCHash64SegmentPageSizes *sps = slb->sps; |
cd6a9bb6 | 633 | |
d75cbae8 DG |
634 | /* |
635 | * The SLB store path should prevent any bad page size encodings | |
636 | * getting in there, so: | |
637 | */ | |
2c7ad804 | 638 | assert(sps); |
a1ff751a | 639 | |
2c7ad804 BH |
640 | /* If ISL is set in LPCR we need to clamp the page size to 4K */ |
641 | if (env->spr[SPR_LPCR] & LPCR_ISL) { | |
642 | /* We assume that when using TCG, 4k is first entry of SPS */ | |
b07c59f7 | 643 | sps = &cpu->hash64_opts->sps[0]; |
2c7ad804 BH |
644 | assert(sps->page_shift == 12); |
645 | } | |
646 | ||
647 | epnmask = ~((1ULL << sps->page_shift) - 1); | |
a1ff751a | 648 | |
a1ff751a | 649 | if (slb->vsid & SLB_VSID_B) { |
18148898 DG |
650 | /* 1TB segment */ |
651 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; | |
652 | epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; | |
2c7ad804 | 653 | hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift); |
a1ff751a | 654 | } else { |
18148898 DG |
655 | /* 256M segment */ |
656 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; | |
657 | epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; | |
2c7ad804 | 658 | hash = vsid ^ (epn >> sps->page_shift); |
a1ff751a | 659 | } |
18148898 | 660 | ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); |
073de86a | 661 | ptem |= HPTE64_V_VALID; |
a1ff751a | 662 | |
a1ff751a | 663 | /* Page address translation */ |
339aaf5b AP |
664 | qemu_log_mask(CPU_LOG_MMU, |
665 | "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx | |
a1ff751a | 666 | " hash " TARGET_FMT_plx "\n", |
36778660 | 667 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); |
a1ff751a | 668 | |
a1ff751a | 669 | /* Primary PTEG lookup */ |
339aaf5b AP |
670 | qemu_log_mask(CPU_LOG_MMU, |
671 | "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a DG |
672 | " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx |
673 | " hash=" TARGET_FMT_plx "\n", | |
36778660 DG |
674 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), |
675 | vsid, ptem, hash); | |
7222b94a | 676 | ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); |
7f3bdc2d | 677 | |
7222b94a | 678 | if (ptex == -1) { |
a1ff751a | 679 | /* Secondary PTEG lookup */ |
073de86a | 680 | ptem |= HPTE64_V_SECONDARY; |
339aaf5b AP |
681 | qemu_log_mask(CPU_LOG_MMU, |
682 | "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a | 683 | " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx |
36778660 DG |
684 | " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu), |
685 | ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); | |
a1ff751a | 686 | |
7222b94a | 687 | ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); |
a1ff751a DG |
688 | } |
689 | ||
7222b94a | 690 | return ptex; |
c69b6151 | 691 | } |
0480884f | 692 | |
1114e712 | 693 | unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, |
1f0252e6 | 694 | uint64_t pte0, uint64_t pte1) |
1114e712 | 695 | { |
1114e712 DG |
696 | int i; |
697 | ||
698 | if (!(pte0 & HPTE64_V_LARGE)) { | |
1114e712 DG |
699 | return 12; |
700 | } | |
701 | ||
702 | /* | |
703 | * The encodings in env->sps need to be carefully chosen so that | |
704 | * this gives an unambiguous result. | |
705 | */ | |
706 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
b07c59f7 | 707 | const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; |
1114e712 DG |
708 | unsigned shift; |
709 | ||
710 | if (!sps->page_shift) { | |
711 | break; | |
712 | } | |
713 | ||
714 | shift = hpte_page_shift(sps, pte0, pte1); | |
715 | if (shift) { | |
1114e712 DG |
716 | return shift; |
717 | } | |
718 | } | |
719 | ||
1114e712 DG |
720 | return 0; |
721 | } | |
722 | ||
1b99e029 DG |
723 | static bool ppc_hash64_use_vrma(CPUPPCState *env) |
724 | { | |
725 | switch (env->mmu_model) { | |
726 | case POWERPC_MMU_3_00: | |
727 | /* | |
728 | * ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR | |
729 | * register no longer exist | |
730 | */ | |
731 | return true; | |
732 | ||
733 | default: | |
734 | return !!(env->spr[SPR_LPCR] & LPCR_VPM0); | |
735 | } | |
736 | } | |
737 | ||
8fe08fac | 738 | static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) |
33595dc9 | 739 | { |
8fe08fac | 740 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
33595dc9 BH |
741 | bool vpm; |
742 | ||
743 | if (msr_ir) { | |
744 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); | |
745 | } else { | |
1b99e029 | 746 | vpm = ppc_hash64_use_vrma(env); |
33595dc9 BH |
747 | } |
748 | if (vpm && !msr_hv) { | |
749 | cs->exception_index = POWERPC_EXCP_HISI; | |
750 | } else { | |
751 | cs->exception_index = POWERPC_EXCP_ISI; | |
752 | } | |
753 | env->error_code = error_code; | |
754 | } | |
755 | ||
8fe08fac | 756 | static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr) |
33595dc9 | 757 | { |
8fe08fac | 758 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
33595dc9 BH |
759 | bool vpm; |
760 | ||
761 | if (msr_dr) { | |
762 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); | |
763 | } else { | |
1b99e029 | 764 | vpm = ppc_hash64_use_vrma(env); |
33595dc9 BH |
765 | } |
766 | if (vpm && !msr_hv) { | |
767 | cs->exception_index = POWERPC_EXCP_HDSI; | |
768 | env->spr[SPR_HDAR] = dar; | |
769 | env->spr[SPR_HDSISR] = dsisr; | |
770 | } else { | |
771 | cs->exception_index = POWERPC_EXCP_DSI; | |
772 | env->spr[SPR_DAR] = dar; | |
773 | env->spr[SPR_DSISR] = dsisr; | |
774 | } | |
775 | env->error_code = 0; | |
776 | } | |
777 | ||
778 | ||
a2dd4e83 BH |
779 | static void ppc_hash64_set_r(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) |
780 | { | |
781 | hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 16; | |
782 | ||
783 | if (cpu->vhyp) { | |
784 | PPCVirtualHypervisorClass *vhc = | |
785 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
786 | vhc->hpte_set_r(cpu->vhyp, ptex, pte1); | |
787 | return; | |
788 | } | |
789 | base = ppc_hash64_hpt_base(cpu); | |
790 | ||
791 | ||
792 | /* The HW performs a non-atomic byte update */ | |
793 | stb_phys(CPU(cpu)->as, base + offset, ((pte1 >> 8) & 0xff) | 0x01); | |
794 | } | |
795 | ||
796 | static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr ptex, uint64_t pte1) | |
797 | { | |
798 | hwaddr base, offset = ptex * HASH_PTE_SIZE_64 + 15; | |
799 | ||
800 | if (cpu->vhyp) { | |
801 | PPCVirtualHypervisorClass *vhc = | |
802 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
803 | vhc->hpte_set_c(cpu->vhyp, ptex, pte1); | |
804 | return; | |
805 | } | |
806 | base = ppc_hash64_hpt_base(cpu); | |
807 | ||
808 | /* The HW performs a non-atomic byte update */ | |
809 | stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); | |
810 | } | |
811 | ||
a864a6b3 DG |
812 | static target_ulong rmls_limit(PowerPCCPU *cpu) |
813 | { | |
814 | CPUPPCState *env = &cpu->env; | |
815 | /* | |
d37b40da DG |
816 | * In theory the meanings of RMLS values are implementation |
817 | * dependent. In practice, this seems to have been the set from | |
818 | * POWER4+..POWER8, and RMLS is no longer supported in POWER9. | |
a864a6b3 DG |
819 | * |
820 | * Unsupported values mean the OS has shot itself in the | |
821 | * foot. Return a 0-sized RMA in this case, which we expect | |
822 | * to trigger an immediate DSI or ISI | |
823 | */ | |
824 | static const target_ulong rma_sizes[16] = { | |
d37b40da | 825 | [0] = 256 * GiB, |
a864a6b3 DG |
826 | [1] = 16 * GiB, |
827 | [2] = 1 * GiB, | |
828 | [3] = 64 * MiB, | |
829 | [4] = 256 * MiB, | |
830 | [7] = 128 * MiB, | |
831 | [8] = 32 * MiB, | |
832 | }; | |
833 | target_ulong rmls = (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SHIFT; | |
834 | ||
835 | return rma_sizes[rmls]; | |
836 | } | |
837 | ||
4c24a87f DG |
838 | static int build_vrma_slbe(PowerPCCPU *cpu, ppc_slb_t *slb) |
839 | { | |
840 | CPUPPCState *env = &cpu->env; | |
841 | target_ulong lpcr = env->spr[SPR_LPCR]; | |
842 | uint32_t vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; | |
843 | target_ulong vsid = SLB_VSID_VRMA | ((vrmasd << 4) & SLB_VSID_LLP_MASK); | |
844 | int i; | |
845 | ||
846 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
847 | const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; | |
848 | ||
849 | if (!sps->page_shift) { | |
850 | break; | |
851 | } | |
852 | ||
853 | if ((vsid & SLB_VSID_LLP_MASK) == sps->slb_enc) { | |
854 | slb->esid = SLB_ESID_V; | |
855 | slb->vsid = vsid; | |
856 | slb->sps = sps; | |
857 | return 0; | |
858 | } | |
859 | } | |
860 | ||
861 | error_report("Bad page size encoding in LPCR[VRMASD]; LPCR=0x" | |
ff5b5d5b | 862 | TARGET_FMT_lx, lpcr); |
4c24a87f DG |
863 | |
864 | return -1; | |
865 | } | |
866 | ||
b2305601 | 867 | int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, |
caa597bd | 868 | int rwx, int mmu_idx) |
0480884f | 869 | { |
d0e39c5d AF |
870 | CPUState *cs = CPU(cpu); |
871 | CPUPPCState *env = &cpu->env; | |
4c24a87f | 872 | ppc_slb_t vrma_slbe; |
0480884f | 873 | ppc_slb_t *slb; |
be18b2b5 | 874 | unsigned apshift; |
7222b94a | 875 | hwaddr ptex; |
7f3bdc2d | 876 | ppc_hash_pte64_t pte; |
07a68f99 | 877 | int exec_prot, pp_prot, amr_prot, prot; |
e01b4445 | 878 | const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; |
caa597bd | 879 | hwaddr raddr; |
0480884f | 880 | |
6a980110 DG |
881 | assert((rwx == 0) || (rwx == 1) || (rwx == 2)); |
882 | ||
d75cbae8 DG |
883 | /* |
884 | * Note on LPCR usage: 970 uses HID4, but our special variant of | |
885 | * store_spr copies relevant fields into env->spr[SPR_LPCR]. | |
136fbf65 | 886 | * Similarly we filter unimplemented bits when storing into LPCR |
d75cbae8 DG |
887 | * depending on the MMU version. This code can thus just use the |
888 | * LPCR "as-is". | |
912acdf4 BH |
889 | */ |
890 | ||
65d61643 DG |
891 | /* 1. Handle real mode accesses */ |
892 | if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { | |
d75cbae8 DG |
893 | /* |
894 | * Translation is supposedly "off", but in real mode the top 4 | |
895 | * effective address bits are (mostly) ignored | |
896 | */ | |
caa597bd | 897 | raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; |
912acdf4 | 898 | |
682c1dfb DG |
899 | if (cpu->vhyp) { |
900 | /* | |
901 | * In virtual hypervisor mode, there's nothing to do: | |
902 | * EA == GPA == qemu guest address | |
903 | */ | |
904 | } else if (msr_hv || !env->has_hv_mode) { | |
905 | /* In HV mode, add HRMOR if top EA bit is clear */ | |
912acdf4 BH |
906 | if (!(eaddr >> 63)) { |
907 | raddr |= env->spr[SPR_HRMOR]; | |
908 | } | |
1b99e029 | 909 | } else if (ppc_hash64_use_vrma(env)) { |
682c1dfb | 910 | /* Emulated VRMA mode */ |
4c24a87f DG |
911 | slb = &vrma_slbe; |
912 | if (build_vrma_slbe(cpu, slb) != 0) { | |
682c1dfb | 913 | /* Invalid VRMA setup, machine check */ |
912acdf4 BH |
914 | cs->exception_index = POWERPC_EXCP_MCHECK; |
915 | env->error_code = 0; | |
916 | return 1; | |
682c1dfb DG |
917 | } |
918 | ||
919 | goto skip_slb_search; | |
920 | } else { | |
3a56a55c DG |
921 | target_ulong limit = rmls_limit(cpu); |
922 | ||
682c1dfb | 923 | /* Emulated old-style RMO mode, bounds check against RMLS */ |
3a56a55c | 924 | if (raddr >= limit) { |
912acdf4 | 925 | if (rwx == 2) { |
8fe08fac | 926 | ppc_hash64_set_isi(cs, SRR1_PROTFAULT); |
912acdf4 | 927 | } else { |
da82c73a | 928 | int dsisr = DSISR_PROTFAULT; |
912acdf4 | 929 | if (rwx == 1) { |
da82c73a | 930 | dsisr |= DSISR_ISSTORE; |
912acdf4 | 931 | } |
8fe08fac | 932 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
912acdf4 BH |
933 | } |
934 | return 1; | |
935 | } | |
682c1dfb DG |
936 | |
937 | raddr |= env->spr[SPR_RMOR]; | |
912acdf4 | 938 | } |
0c591eb0 | 939 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
caa597bd DG |
940 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, |
941 | TARGET_PAGE_SIZE); | |
65d61643 DG |
942 | return 0; |
943 | } | |
944 | ||
bb218042 | 945 | /* 2. Translation is on, so look up the SLB */ |
7ef23068 | 946 | slb = slb_lookup(cpu, eaddr); |
0480884f | 947 | if (!slb) { |
b2899495 | 948 | /* No entry found, check if in-memory segment tables are in use */ |
ca79b3b7 | 949 | if (ppc64_use_proc_tbl(cpu)) { |
b2899495 SJS |
950 | /* TODO - Unsupported */ |
951 | error_report("Segment Table Support Unimplemented"); | |
952 | exit(1); | |
953 | } | |
954 | /* Segment still not found, generate the appropriate interrupt */ | |
caa597bd | 955 | if (rwx == 2) { |
27103424 | 956 | cs->exception_index = POWERPC_EXCP_ISEG; |
caa597bd DG |
957 | env->error_code = 0; |
958 | } else { | |
27103424 | 959 | cs->exception_index = POWERPC_EXCP_DSEG; |
caa597bd DG |
960 | env->error_code = 0; |
961 | env->spr[SPR_DAR] = eaddr; | |
962 | } | |
963 | return 1; | |
0480884f DG |
964 | } |
965 | ||
912acdf4 BH |
966 | skip_slb_search: |
967 | ||
bb218042 DG |
968 | /* 3. Check for segment level no-execute violation */ |
969 | if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { | |
8fe08fac | 970 | ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); |
caa597bd | 971 | return 1; |
bb218042 DG |
972 | } |
973 | ||
7f3bdc2d | 974 | /* 4. Locate the PTE in the hash table */ |
7222b94a DG |
975 | ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); |
976 | if (ptex == -1) { | |
caa597bd | 977 | if (rwx == 2) { |
8fe08fac | 978 | ppc_hash64_set_isi(cs, SRR1_NOPTE); |
caa597bd | 979 | } else { |
da82c73a | 980 | int dsisr = DSISR_NOPTE; |
caa597bd | 981 | if (rwx == 1) { |
da82c73a | 982 | dsisr |= DSISR_ISSTORE; |
caa597bd | 983 | } |
8fe08fac | 984 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
caa597bd DG |
985 | } |
986 | return 1; | |
7f3bdc2d | 987 | } |
339aaf5b | 988 | qemu_log_mask(CPU_LOG_MMU, |
7222b94a | 989 | "found PTE at index %08" HWADDR_PRIx "\n", ptex); |
7f3bdc2d DG |
990 | |
991 | /* 5. Check access permissions */ | |
7f3bdc2d | 992 | |
07a68f99 | 993 | exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte); |
7ef23068 DG |
994 | pp_prot = ppc_hash64_pte_prot(cpu, slb, pte); |
995 | amr_prot = ppc_hash64_amr_prot(cpu, pte); | |
07a68f99 | 996 | prot = exec_prot & pp_prot & amr_prot; |
6a980110 | 997 | |
caa597bd | 998 | if ((need_prot[rwx] & ~prot) != 0) { |
6a980110 | 999 | /* Access right violation */ |
339aaf5b | 1000 | qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); |
caa597bd | 1001 | if (rwx == 2) { |
a6152b52 | 1002 | int srr1 = 0; |
07a68f99 SJS |
1003 | if (PAGE_EXEC & ~exec_prot) { |
1004 | srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */ | |
1005 | } else if (PAGE_EXEC & ~pp_prot) { | |
a6152b52 SJS |
1006 | srr1 |= SRR1_PROTFAULT; /* Access violates access authority */ |
1007 | } | |
1008 | if (PAGE_EXEC & ~amr_prot) { | |
1009 | srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */ | |
1010 | } | |
8fe08fac | 1011 | ppc_hash64_set_isi(cs, srr1); |
caa597bd | 1012 | } else { |
da82c73a | 1013 | int dsisr = 0; |
f80872e2 | 1014 | if (need_prot[rwx] & ~pp_prot) { |
da82c73a | 1015 | dsisr |= DSISR_PROTFAULT; |
f80872e2 | 1016 | } |
caa597bd | 1017 | if (rwx == 1) { |
da82c73a | 1018 | dsisr |= DSISR_ISSTORE; |
f80872e2 DG |
1019 | } |
1020 | if (need_prot[rwx] & ~amr_prot) { | |
da82c73a | 1021 | dsisr |= DSISR_AMR; |
caa597bd | 1022 | } |
8fe08fac | 1023 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
caa597bd DG |
1024 | } |
1025 | return 1; | |
6a980110 DG |
1026 | } |
1027 | ||
339aaf5b | 1028 | qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); |
87dc3fd1 DG |
1029 | |
1030 | /* 6. Update PTE referenced and changed bits if necessary */ | |
1031 | ||
a2dd4e83 BH |
1032 | if (!(pte.pte1 & HPTE64_R_R)) { |
1033 | ppc_hash64_set_r(cpu, ptex, pte.pte1); | |
b3440746 | 1034 | } |
a2dd4e83 BH |
1035 | if (!(pte.pte1 & HPTE64_R_C)) { |
1036 | if (rwx == 1) { | |
1037 | ppc_hash64_set_c(cpu, ptex, pte.pte1); | |
1038 | } else { | |
1039 | /* | |
1040 | * Treat the page as read-only for now, so that a later write | |
1041 | * will pass through this function again to set the C bit | |
1042 | */ | |
1043 | prot &= ~PAGE_WRITE; | |
1044 | } | |
7f3bdc2d | 1045 | } |
0480884f | 1046 | |
6d11d998 DG |
1047 | /* 7. Determine the real address from the PTE */ |
1048 | ||
be18b2b5 | 1049 | raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); |
caa597bd | 1050 | |
0c591eb0 | 1051 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
be18b2b5 | 1052 | prot, mmu_idx, 1ULL << apshift); |
e01b4445 | 1053 | |
e01b4445 | 1054 | return 0; |
0480884f | 1055 | } |
629bd516 | 1056 | |
7ef23068 | 1057 | hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) |
f2ad6be8 | 1058 | { |
7ef23068 | 1059 | CPUPPCState *env = &cpu->env; |
4c24a87f | 1060 | ppc_slb_t vrma_slbe; |
5883d8b2 | 1061 | ppc_slb_t *slb; |
7222b94a | 1062 | hwaddr ptex, raddr; |
5883d8b2 | 1063 | ppc_hash_pte64_t pte; |
be18b2b5 | 1064 | unsigned apshift; |
5883d8b2 | 1065 | |
912acdf4 | 1066 | /* Handle real mode */ |
5883d8b2 DG |
1067 | if (msr_dr == 0) { |
1068 | /* In real mode the top 4 effective address bits are ignored */ | |
912acdf4 | 1069 | raddr = addr & 0x0FFFFFFFFFFFFFFFULL; |
f2ad6be8 | 1070 | |
682c1dfb DG |
1071 | if (cpu->vhyp) { |
1072 | /* | |
1073 | * In virtual hypervisor mode, there's nothing to do: | |
1074 | * EA == GPA == qemu guest address | |
1075 | */ | |
1076 | return raddr; | |
1077 | } else if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { | |
1078 | /* In HV mode, add HRMOR if top EA bit is clear */ | |
912acdf4 | 1079 | return raddr | env->spr[SPR_HRMOR]; |
1b99e029 | 1080 | } else if (ppc_hash64_use_vrma(env)) { |
682c1dfb | 1081 | /* Emulated VRMA mode */ |
4c24a87f DG |
1082 | slb = &vrma_slbe; |
1083 | if (build_vrma_slbe(cpu, slb) != 0) { | |
912acdf4 BH |
1084 | return -1; |
1085 | } | |
912acdf4 | 1086 | } else { |
3a56a55c DG |
1087 | target_ulong limit = rmls_limit(cpu); |
1088 | ||
682c1dfb | 1089 | /* Emulated old-style RMO mode, bounds check against RMLS */ |
3a56a55c | 1090 | if (raddr >= limit) { |
682c1dfb DG |
1091 | return -1; |
1092 | } | |
1093 | return raddr | env->spr[SPR_RMOR]; | |
912acdf4 BH |
1094 | } |
1095 | } else { | |
1096 | slb = slb_lookup(cpu, addr); | |
1097 | if (!slb) { | |
1098 | return -1; | |
1099 | } | |
5883d8b2 DG |
1100 | } |
1101 | ||
7222b94a DG |
1102 | ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift); |
1103 | if (ptex == -1) { | |
f2ad6be8 DG |
1104 | return -1; |
1105 | } | |
1106 | ||
be18b2b5 | 1107 | return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr) |
cd6a9bb6 | 1108 | & TARGET_PAGE_MASK; |
f2ad6be8 | 1109 | } |
c1385933 | 1110 | |
7222b94a | 1111 | void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, |
61a36c9b DG |
1112 | target_ulong pte0, target_ulong pte1) |
1113 | { | |
1114 | /* | |
1115 | * XXX: given the fact that there are too many segments to | |
1116 | * invalidate, and we still don't have a tlb_flush_mask(env, n, | |
1117 | * mask) in QEMU, we just invalidate all TLBs | |
1118 | */ | |
d76ab5e1 | 1119 | cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; |
61a36c9b | 1120 | } |
4b3fc377 | 1121 | |
5ad55315 | 1122 | void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) |
4b3fc377 | 1123 | { |
e232eccc | 1124 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); |
5ad55315 | 1125 | CPUPPCState *env = &cpu->env; |
4b3fc377 | 1126 | |
e232eccc | 1127 | env->spr[SPR_LPCR] = val & pcc->lpcr_mask; |
4b3fc377 | 1128 | } |
a059471d | 1129 | |
5ad55315 DG |
1130 | void helper_store_lpcr(CPUPPCState *env, target_ulong val) |
1131 | { | |
db70b311 | 1132 | PowerPCCPU *cpu = env_archcpu(env); |
5ad55315 DG |
1133 | |
1134 | ppc_store_lpcr(cpu, val); | |
1135 | } | |
1136 | ||
a059471d DG |
1137 | void ppc_hash64_init(PowerPCCPU *cpu) |
1138 | { | |
1139 | CPUPPCState *env = &cpu->env; | |
1140 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
1141 | ||
21e405f1 DG |
1142 | if (!pcc->hash64_opts) { |
1143 | assert(!(env->mmu_model & POWERPC_MMU_64)); | |
1144 | return; | |
a059471d | 1145 | } |
21e405f1 DG |
1146 | |
1147 | cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts)); | |
a059471d DG |
1148 | } |
1149 | ||
1150 | void ppc_hash64_finalize(PowerPCCPU *cpu) | |
1151 | { | |
b07c59f7 | 1152 | g_free(cpu->hash64_opts); |
a059471d | 1153 | } |
b07c59f7 | 1154 | |
21e405f1 | 1155 | const PPCHash64Options ppc_hash64_opts_basic = { |
58969eee | 1156 | .flags = 0, |
67d7d66f | 1157 | .slb_size = 64, |
21e405f1 DG |
1158 | .sps = { |
1159 | { .page_shift = 12, /* 4K */ | |
1160 | .slb_enc = 0, | |
1161 | .enc = { { .page_shift = 12, .pte_enc = 0 } } | |
1162 | }, | |
1163 | { .page_shift = 24, /* 16M */ | |
1164 | .slb_enc = 0x100, | |
1165 | .enc = { { .page_shift = 24, .pte_enc = 0 } } | |
1166 | }, | |
1167 | }, | |
1168 | }; | |
1169 | ||
b07c59f7 | 1170 | const PPCHash64Options ppc_hash64_opts_POWER7 = { |
26cd35b8 | 1171 | .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR | PPC_HASH64_CI_LARGEPAGE, |
67d7d66f | 1172 | .slb_size = 32, |
b07c59f7 DG |
1173 | .sps = { |
1174 | { | |
1175 | .page_shift = 12, /* 4K */ | |
1176 | .slb_enc = 0, | |
1177 | .enc = { { .page_shift = 12, .pte_enc = 0 }, | |
1178 | { .page_shift = 16, .pte_enc = 0x7 }, | |
1179 | { .page_shift = 24, .pte_enc = 0x38 }, }, | |
1180 | }, | |
1181 | { | |
1182 | .page_shift = 16, /* 64K */ | |
1183 | .slb_enc = SLB_VSID_64K, | |
1184 | .enc = { { .page_shift = 16, .pte_enc = 0x1 }, | |
1185 | { .page_shift = 24, .pte_enc = 0x8 }, }, | |
1186 | }, | |
1187 | { | |
1188 | .page_shift = 24, /* 16M */ | |
1189 | .slb_enc = SLB_VSID_16M, | |
1190 | .enc = { { .page_shift = 24, .pte_enc = 0 }, }, | |
1191 | }, | |
1192 | { | |
1193 | .page_shift = 34, /* 16G */ | |
1194 | .slb_enc = SLB_VSID_16G, | |
1195 | .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, | |
1196 | }, | |
1197 | } | |
1198 | }; | |
27f00f0a DG |
1199 | |
1200 | void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu, | |
1201 | bool (*cb)(void *, uint32_t, uint32_t), | |
1202 | void *opaque) | |
1203 | { | |
1204 | PPCHash64Options *opts = cpu->hash64_opts; | |
1205 | int i; | |
1206 | int n = 0; | |
1207 | bool ci_largepage = false; | |
1208 | ||
1209 | assert(opts); | |
1210 | ||
1211 | n = 0; | |
1212 | for (i = 0; i < ARRAY_SIZE(opts->sps); i++) { | |
1213 | PPCHash64SegmentPageSizes *sps = &opts->sps[i]; | |
1214 | int j; | |
1215 | int m = 0; | |
1216 | ||
1217 | assert(n <= i); | |
1218 | ||
1219 | if (!sps->page_shift) { | |
1220 | break; | |
1221 | } | |
1222 | ||
1223 | for (j = 0; j < ARRAY_SIZE(sps->enc); j++) { | |
1224 | PPCHash64PageSize *ps = &sps->enc[j]; | |
1225 | ||
1226 | assert(m <= j); | |
1227 | if (!ps->page_shift) { | |
1228 | break; | |
1229 | } | |
1230 | ||
1231 | if (cb(opaque, sps->page_shift, ps->page_shift)) { | |
1232 | if (ps->page_shift >= 16) { | |
1233 | ci_largepage = true; | |
1234 | } | |
1235 | sps->enc[m++] = *ps; | |
1236 | } | |
1237 | } | |
1238 | ||
1239 | /* Clear rest of the row */ | |
1240 | for (j = m; j < ARRAY_SIZE(sps->enc); j++) { | |
1241 | memset(&sps->enc[j], 0, sizeof(sps->enc[j])); | |
1242 | } | |
1243 | ||
1244 | if (m) { | |
1245 | n++; | |
1246 | } | |
1247 | } | |
1248 | ||
1249 | /* Clear the rest of the table */ | |
1250 | for (i = n; i < ARRAY_SIZE(opts->sps); i++) { | |
1251 | memset(&opts->sps[i], 0, sizeof(opts->sps[i])); | |
1252 | } | |
1253 | ||
1254 | if (!ci_largepage) { | |
1255 | opts->flags &= ~PPC_HASH64_CI_LARGEPAGE; | |
1256 | } | |
1257 | } |