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Commit | Line | Data |
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10b46525 DG |
1 | /* |
2 | * PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU. | |
3 | * | |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer | |
5 | * Copyright (c) 2013 David Gibson, IBM Corporation | |
6 | * | |
7 | * This library is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU Lesser General Public | |
9 | * License as published by the Free Software Foundation; either | |
10 | * version 2 of the License, or (at your option) any later version. | |
11 | * | |
12 | * This library is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * Lesser General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU Lesser General Public | |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
0d75590d | 20 | #include "qemu/osdep.h" |
10b46525 | 21 | #include "cpu.h" |
63c91552 | 22 | #include "exec/exec-all.h" |
2ef6175a | 23 | #include "exec/helper-proto.h" |
cd6a9bb6 | 24 | #include "qemu/error-report.h" |
b3946626 | 25 | #include "sysemu/hw_accel.h" |
10b46525 DG |
26 | #include "kvm_ppc.h" |
27 | #include "mmu-hash64.h" | |
508127e2 | 28 | #include "exec/log.h" |
7222b94a | 29 | #include "hw/hw.h" |
b2899495 | 30 | #include "mmu-book3s-v3.h" |
10b46525 DG |
31 | |
32 | //#define DEBUG_SLB | |
33 | ||
34 | #ifdef DEBUG_SLB | |
48880da6 | 35 | # define LOG_SLB(...) qemu_log_mask(CPU_LOG_MMU, __VA_ARGS__) |
10b46525 DG |
36 | #else |
37 | # define LOG_SLB(...) do { } while (0) | |
38 | #endif | |
39 | ||
40 | /* | |
41 | * SLB handling | |
42 | */ | |
43 | ||
7ef23068 | 44 | static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) |
10b46525 | 45 | { |
7ef23068 | 46 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
47 | uint64_t esid_256M, esid_1T; |
48 | int n; | |
49 | ||
50 | LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr); | |
51 | ||
52 | esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V; | |
53 | esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V; | |
54 | ||
55 | for (n = 0; n < env->slb_nr; n++) { | |
56 | ppc_slb_t *slb = &env->slb[n]; | |
57 | ||
58 | LOG_SLB("%s: slot %d %016" PRIx64 " %016" | |
59 | PRIx64 "\n", __func__, n, slb->esid, slb->vsid); | |
60 | /* We check for 1T matches on all MMUs here - if the MMU | |
61 | * doesn't have 1T segment support, we will have prevented 1T | |
62 | * entries from being inserted in the slbmte code. */ | |
63 | if (((slb->esid == esid_256M) && | |
64 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M)) | |
65 | || ((slb->esid == esid_1T) && | |
66 | ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) { | |
67 | return slb; | |
68 | } | |
69 | } | |
70 | ||
71 | return NULL; | |
72 | } | |
73 | ||
7ef23068 | 74 | void dump_slb(FILE *f, fprintf_function cpu_fprintf, PowerPCCPU *cpu) |
10b46525 | 75 | { |
7ef23068 | 76 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
77 | int i; |
78 | uint64_t slbe, slbv; | |
79 | ||
7ef23068 | 80 | cpu_synchronize_state(CPU(cpu)); |
10b46525 DG |
81 | |
82 | cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n"); | |
83 | for (i = 0; i < env->slb_nr; i++) { | |
84 | slbe = env->slb[i].esid; | |
85 | slbv = env->slb[i].vsid; | |
86 | if (slbe == 0 && slbv == 0) { | |
87 | continue; | |
88 | } | |
89 | cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n", | |
90 | i, slbe, slbv); | |
91 | } | |
92 | } | |
93 | ||
94 | void helper_slbia(CPUPPCState *env) | |
95 | { | |
cd0c6f47 | 96 | int n; |
10b46525 | 97 | |
10b46525 DG |
98 | /* XXX: Warning: slbia never invalidates the first segment */ |
99 | for (n = 1; n < env->slb_nr; n++) { | |
100 | ppc_slb_t *slb = &env->slb[n]; | |
101 | ||
102 | if (slb->esid & SLB_ESID_V) { | |
103 | slb->esid &= ~SLB_ESID_V; | |
104 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
105 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
106 | * in QEMU, we just invalidate all TLBs | |
107 | */ | |
a8a6d53e | 108 | env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH; |
10b46525 DG |
109 | } |
110 | } | |
10b46525 DG |
111 | } |
112 | ||
a63f1dfc ND |
113 | static void __helper_slbie(CPUPPCState *env, target_ulong addr, |
114 | target_ulong global) | |
10b46525 | 115 | { |
00c8cb0a | 116 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
10b46525 DG |
117 | ppc_slb_t *slb; |
118 | ||
7ef23068 | 119 | slb = slb_lookup(cpu, addr); |
10b46525 DG |
120 | if (!slb) { |
121 | return; | |
122 | } | |
123 | ||
124 | if (slb->esid & SLB_ESID_V) { | |
125 | slb->esid &= ~SLB_ESID_V; | |
126 | ||
127 | /* XXX: given the fact that segment size is 256 MB or 1TB, | |
128 | * and we still don't have a tlb_flush_mask(env, n, mask) | |
129 | * in QEMU, we just invalidate all TLBs | |
130 | */ | |
a63f1dfc ND |
131 | env->tlb_need_flush |= |
132 | (global == false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_FLUSH); | |
10b46525 DG |
133 | } |
134 | } | |
135 | ||
a63f1dfc ND |
136 | void helper_slbie(CPUPPCState *env, target_ulong addr) |
137 | { | |
138 | __helper_slbie(env, addr, false); | |
139 | } | |
140 | ||
141 | void helper_slbieg(CPUPPCState *env, target_ulong addr) | |
142 | { | |
143 | __helper_slbie(env, addr, true); | |
144 | } | |
145 | ||
bcd81230 DG |
146 | int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, |
147 | target_ulong esid, target_ulong vsid) | |
10b46525 | 148 | { |
7ef23068 | 149 | CPUPPCState *env = &cpu->env; |
10b46525 | 150 | ppc_slb_t *slb = &env->slb[slot]; |
b07c59f7 | 151 | const PPCHash64SegmentPageSizes *sps = NULL; |
cd6a9bb6 | 152 | int i; |
10b46525 | 153 | |
bcd81230 DG |
154 | if (slot >= env->slb_nr) { |
155 | return -1; /* Bad slot number */ | |
156 | } | |
157 | if (esid & ~(SLB_ESID_ESID | SLB_ESID_V)) { | |
158 | return -1; /* Reserved bits set */ | |
10b46525 | 159 | } |
bcd81230 | 160 | if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { |
10b46525 DG |
161 | return -1; /* Bad segment size */ |
162 | } | |
58969eee | 163 | if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { |
10b46525 DG |
164 | return -1; /* 1T segment on MMU that doesn't support it */ |
165 | } | |
166 | ||
cd6a9bb6 | 167 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
b07c59f7 | 168 | const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; |
cd6a9bb6 DG |
169 | |
170 | if (!sps1->page_shift) { | |
171 | break; | |
172 | } | |
173 | ||
174 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { | |
175 | sps = sps1; | |
176 | break; | |
177 | } | |
178 | } | |
179 | ||
180 | if (!sps) { | |
181 | error_report("Bad page size encoding in SLB store: slot "TARGET_FMT_lu | |
182 | " esid 0x"TARGET_FMT_lx" vsid 0x"TARGET_FMT_lx, | |
183 | slot, esid, vsid); | |
184 | return -1; | |
185 | } | |
186 | ||
bcd81230 DG |
187 | slb->esid = esid; |
188 | slb->vsid = vsid; | |
cd6a9bb6 | 189 | slb->sps = sps; |
10b46525 | 190 | |
76134d48 SJS |
191 | LOG_SLB("%s: " TARGET_FMT_lu " " TARGET_FMT_lx " - " TARGET_FMT_lx |
192 | " => %016" PRIx64 " %016" PRIx64 "\n", __func__, slot, esid, vsid, | |
10b46525 DG |
193 | slb->esid, slb->vsid); |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
7ef23068 | 198 | static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
199 | target_ulong *rt) |
200 | { | |
7ef23068 | 201 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
202 | int slot = rb & 0xfff; |
203 | ppc_slb_t *slb = &env->slb[slot]; | |
204 | ||
205 | if (slot >= env->slb_nr) { | |
206 | return -1; | |
207 | } | |
208 | ||
209 | *rt = slb->esid; | |
210 | return 0; | |
211 | } | |
212 | ||
7ef23068 | 213 | static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
10b46525 DG |
214 | target_ulong *rt) |
215 | { | |
7ef23068 | 216 | CPUPPCState *env = &cpu->env; |
10b46525 DG |
217 | int slot = rb & 0xfff; |
218 | ppc_slb_t *slb = &env->slb[slot]; | |
219 | ||
220 | if (slot >= env->slb_nr) { | |
221 | return -1; | |
222 | } | |
223 | ||
224 | *rt = slb->vsid; | |
225 | return 0; | |
226 | } | |
227 | ||
c76c22d5 BH |
228 | static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, |
229 | target_ulong *rt) | |
230 | { | |
231 | CPUPPCState *env = &cpu->env; | |
232 | ppc_slb_t *slb; | |
233 | ||
234 | if (!msr_is_64bit(env, env->msr)) { | |
235 | rb &= 0xffffffff; | |
236 | } | |
237 | slb = slb_lookup(cpu, rb); | |
238 | if (slb == NULL) { | |
239 | *rt = (target_ulong)-1ul; | |
240 | } else { | |
241 | *rt = slb->vsid; | |
242 | } | |
243 | return 0; | |
244 | } | |
245 | ||
10b46525 DG |
246 | void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) |
247 | { | |
7ef23068 DG |
248 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
249 | ||
bcd81230 | 250 | if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { |
0f72b7c6 BH |
251 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
252 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
253 | } |
254 | } | |
255 | ||
256 | target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) | |
257 | { | |
7ef23068 | 258 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
10b46525 DG |
259 | target_ulong rt = 0; |
260 | ||
7ef23068 | 261 | if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { |
0f72b7c6 BH |
262 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
263 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
264 | } |
265 | return rt; | |
266 | } | |
267 | ||
c76c22d5 BH |
268 | target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) |
269 | { | |
270 | PowerPCCPU *cpu = ppc_env_get_cpu(env); | |
271 | target_ulong rt = 0; | |
272 | ||
273 | if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { | |
0f72b7c6 BH |
274 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
275 | POWERPC_EXCP_INVAL, GETPC()); | |
c76c22d5 BH |
276 | } |
277 | return rt; | |
278 | } | |
279 | ||
10b46525 DG |
280 | target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) |
281 | { | |
7ef23068 | 282 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
10b46525 DG |
283 | target_ulong rt = 0; |
284 | ||
7ef23068 | 285 | if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { |
0f72b7c6 BH |
286 | raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, |
287 | POWERPC_EXCP_INVAL, GETPC()); | |
10b46525 DG |
288 | } |
289 | return rt; | |
290 | } | |
9d7c3f4a | 291 | |
07a68f99 SJS |
292 | /* Check No-Execute or Guarded Storage */ |
293 | static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, | |
294 | ppc_hash_pte64_t pte) | |
295 | { | |
296 | /* Exec permissions CANNOT take away read or write permissions */ | |
297 | return (pte.pte1 & HPTE64_R_N) || (pte.pte1 & HPTE64_R_G) ? | |
298 | PAGE_READ | PAGE_WRITE : PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
299 | } | |
300 | ||
301 | /* Check Basic Storage Protection */ | |
7ef23068 | 302 | static int ppc_hash64_pte_prot(PowerPCCPU *cpu, |
e01b4445 | 303 | ppc_slb_t *slb, ppc_hash_pte64_t pte) |
496272a7 | 304 | { |
7ef23068 | 305 | CPUPPCState *env = &cpu->env; |
e01b4445 DG |
306 | unsigned pp, key; |
307 | /* Some pp bit combinations have undefined behaviour, so default | |
308 | * to no access in those cases */ | |
309 | int prot = 0; | |
310 | ||
311 | key = !!(msr_pr ? (slb->vsid & SLB_VSID_KP) | |
312 | : (slb->vsid & SLB_VSID_KS)); | |
313 | pp = (pte.pte1 & HPTE64_R_PP) | ((pte.pte1 & HPTE64_R_PP0) >> 61); | |
496272a7 | 314 | |
496272a7 DG |
315 | if (key == 0) { |
316 | switch (pp) { | |
317 | case 0x0: | |
318 | case 0x1: | |
319 | case 0x2: | |
347a5c73 | 320 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
e01b4445 DG |
321 | break; |
322 | ||
496272a7 DG |
323 | case 0x3: |
324 | case 0x6: | |
347a5c73 | 325 | prot = PAGE_READ | PAGE_EXEC; |
496272a7 DG |
326 | break; |
327 | } | |
328 | } else { | |
329 | switch (pp) { | |
330 | case 0x0: | |
331 | case 0x6: | |
496272a7 | 332 | break; |
e01b4445 | 333 | |
496272a7 DG |
334 | case 0x1: |
335 | case 0x3: | |
347a5c73 | 336 | prot = PAGE_READ | PAGE_EXEC; |
496272a7 | 337 | break; |
e01b4445 | 338 | |
496272a7 | 339 | case 0x2: |
347a5c73 | 340 | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
496272a7 DG |
341 | break; |
342 | } | |
343 | } | |
496272a7 | 344 | |
e01b4445 | 345 | return prot; |
496272a7 DG |
346 | } |
347 | ||
a6152b52 SJS |
348 | /* Check the instruction access permissions specified in the IAMR */ |
349 | static int ppc_hash64_iamr_prot(PowerPCCPU *cpu, int key) | |
350 | { | |
351 | CPUPPCState *env = &cpu->env; | |
352 | int iamr_bits = (env->spr[SPR_IAMR] >> 2 * (31 - key)) & 0x3; | |
353 | ||
354 | /* | |
355 | * An instruction fetch is permitted if the IAMR bit is 0. | |
356 | * If the bit is set, return PAGE_READ | PAGE_WRITE because this bit | |
357 | * can only take away EXEC permissions not READ or WRITE permissions. | |
358 | * If bit is cleared return PAGE_READ | PAGE_WRITE | PAGE_EXEC since | |
359 | * EXEC permissions are allowed. | |
360 | */ | |
361 | return (iamr_bits & 0x1) ? PAGE_READ | PAGE_WRITE : | |
362 | PAGE_READ | PAGE_WRITE | PAGE_EXEC; | |
363 | } | |
364 | ||
7ef23068 | 365 | static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) |
f80872e2 | 366 | { |
7ef23068 | 367 | CPUPPCState *env = &cpu->env; |
f80872e2 | 368 | int key, amrbits; |
363248e8 | 369 | int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
f80872e2 | 370 | |
f80872e2 | 371 | /* Only recent MMUs implement Virtual Page Class Key Protection */ |
58969eee | 372 | if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { |
363248e8 | 373 | return prot; |
f80872e2 DG |
374 | } |
375 | ||
376 | key = HPTE64_R_KEY(pte.pte1); | |
377 | amrbits = (env->spr[SPR_AMR] >> 2*(31 - key)) & 0x3; | |
378 | ||
379 | /* fprintf(stderr, "AMR protection: key=%d AMR=0x%" PRIx64 "\n", key, */ | |
380 | /* env->spr[SPR_AMR]); */ | |
381 | ||
363248e8 CLG |
382 | /* |
383 | * A store is permitted if the AMR bit is 0. Remove write | |
384 | * protection if it is set. | |
385 | */ | |
f80872e2 | 386 | if (amrbits & 0x2) { |
363248e8 | 387 | prot &= ~PAGE_WRITE; |
f80872e2 | 388 | } |
363248e8 CLG |
389 | /* |
390 | * A load is permitted if the AMR bit is 0. Remove read | |
391 | * protection if it is set. | |
392 | */ | |
f80872e2 | 393 | if (amrbits & 0x1) { |
363248e8 | 394 | prot &= ~PAGE_READ; |
f80872e2 DG |
395 | } |
396 | ||
a6152b52 SJS |
397 | switch (env->mmu_model) { |
398 | /* | |
399 | * MMU version 2.07 and later support IAMR | |
400 | * Check if the IAMR allows the instruction access - it will return | |
401 | * PAGE_EXEC if it doesn't (and thus that bit will be cleared) or 0 | |
402 | * if it does (and prot will be unchanged indicating execution support). | |
403 | */ | |
404 | case POWERPC_MMU_2_07: | |
405 | case POWERPC_MMU_3_00: | |
406 | prot &= ppc_hash64_iamr_prot(cpu, key); | |
407 | break; | |
408 | default: | |
409 | break; | |
410 | } | |
411 | ||
f80872e2 DG |
412 | return prot; |
413 | } | |
414 | ||
7222b94a DG |
415 | const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, |
416 | hwaddr ptex, int n) | |
7c43bca0 | 417 | { |
7222b94a | 418 | hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; |
e57ca75c DG |
419 | hwaddr base = ppc_hash64_hpt_base(cpu); |
420 | hwaddr plen = n * HASH_PTE_SIZE_64; | |
421 | const ppc_hash_pte64_t *hptes; | |
7c43bca0 | 422 | |
e57ca75c DG |
423 | if (cpu->vhyp) { |
424 | PPCVirtualHypervisorClass *vhc = | |
425 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
426 | return vhc->map_hptes(cpu->vhyp, ptex, n); | |
427 | } | |
428 | ||
429 | if (!base) { | |
430 | return NULL; | |
431 | } | |
432 | ||
433 | hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false); | |
434 | if (plen < (n * HASH_PTE_SIZE_64)) { | |
435 | hw_error("%s: Unable to map all requested HPTEs\n", __func__); | |
7c43bca0 | 436 | } |
7222b94a | 437 | return hptes; |
7c43bca0 AK |
438 | } |
439 | ||
7222b94a DG |
440 | void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes, |
441 | hwaddr ptex, int n) | |
7c43bca0 | 442 | { |
e57ca75c DG |
443 | if (cpu->vhyp) { |
444 | PPCVirtualHypervisorClass *vhc = | |
445 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
446 | vhc->unmap_hptes(cpu->vhyp, hptes, ptex, n); | |
447 | return; | |
7c43bca0 | 448 | } |
e57ca75c DG |
449 | |
450 | address_space_unmap(CPU(cpu)->as, (void *)hptes, n * HASH_PTE_SIZE_64, | |
451 | false, n * HASH_PTE_SIZE_64); | |
7c43bca0 AK |
452 | } |
453 | ||
b07c59f7 DG |
454 | static unsigned hpte_page_shift(const PPCHash64SegmentPageSizes *sps, |
455 | uint64_t pte0, uint64_t pte1) | |
4322e8ce | 456 | { |
651060ab DG |
457 | int i; |
458 | ||
459 | if (!(pte0 & HPTE64_V_LARGE)) { | |
460 | if (sps->page_shift != 12) { | |
461 | /* 4kiB page in a non 4kiB segment */ | |
462 | return 0; | |
463 | } | |
464 | /* Normal 4kiB page */ | |
4322e8ce | 465 | return 12; |
651060ab DG |
466 | } |
467 | ||
468 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
b07c59f7 | 469 | const PPCHash64PageSize *ps = &sps->enc[i]; |
651060ab DG |
470 | uint64_t mask; |
471 | ||
472 | if (!ps->page_shift) { | |
473 | break; | |
4322e8ce | 474 | } |
651060ab DG |
475 | |
476 | if (ps->page_shift == 12) { | |
477 | /* L bit is set so this can't be a 4kiB page */ | |
478 | continue; | |
479 | } | |
480 | ||
481 | mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN; | |
482 | ||
b56d417b | 483 | if ((pte1 & mask) == ((uint64_t)ps->pte_enc << HPTE64_R_RPN_SHIFT)) { |
651060ab | 484 | return ps->page_shift; |
4322e8ce | 485 | } |
4322e8ce | 486 | } |
651060ab DG |
487 | |
488 | return 0; /* Bad page size encoding */ | |
4322e8ce BH |
489 | } |
490 | ||
7ef23068 | 491 | static hwaddr ppc_hash64_pteg_search(PowerPCCPU *cpu, hwaddr hash, |
b07c59f7 | 492 | const PPCHash64SegmentPageSizes *sps, |
2c7ad804 | 493 | target_ulong ptem, |
94986863 | 494 | ppc_hash_pte64_t *pte, unsigned *pshift) |
aea390e4 | 495 | { |
aea390e4 | 496 | int i; |
7222b94a | 497 | const ppc_hash_pte64_t *pteg; |
7c43bca0 | 498 | target_ulong pte0, pte1; |
7222b94a | 499 | target_ulong ptex; |
aea390e4 | 500 | |
36778660 | 501 | ptex = (hash & ppc_hash64_hpt_mask(cpu)) * HPTES_PER_GROUP; |
7222b94a DG |
502 | pteg = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); |
503 | if (!pteg) { | |
7c43bca0 AK |
504 | return -1; |
505 | } | |
aea390e4 | 506 | for (i = 0; i < HPTES_PER_GROUP; i++) { |
7222b94a DG |
507 | pte0 = ppc_hash64_hpte0(cpu, pteg, i); |
508 | pte1 = ppc_hash64_hpte1(cpu, pteg, i); | |
aea390e4 | 509 | |
073de86a DG |
510 | /* This compares V, B, H (secondary) and the AVPN */ |
511 | if (HPTE64_V_COMPARE(pte0, ptem)) { | |
2c7ad804 | 512 | *pshift = hpte_page_shift(sps, pte0, pte1); |
651060ab DG |
513 | /* |
514 | * If there is no match, ignore the PTE, it could simply | |
515 | * be for a different segment size encoding and the | |
516 | * architecture specifies we should not match. Linux will | |
517 | * potentially leave behind PTEs for the wrong base page | |
518 | * size when demoting segments. | |
519 | */ | |
94986863 | 520 | if (*pshift == 0) { |
4322e8ce BH |
521 | continue; |
522 | } | |
523 | /* We don't do anything with pshift yet as qemu TLB only deals | |
524 | * with 4K pages anyway | |
525 | */ | |
aea390e4 DG |
526 | pte->pte0 = pte0; |
527 | pte->pte1 = pte1; | |
7222b94a DG |
528 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
529 | return ptex + i; | |
aea390e4 | 530 | } |
aea390e4 | 531 | } |
7222b94a | 532 | ppc_hash64_unmap_hptes(cpu, pteg, ptex, HPTES_PER_GROUP); |
7c43bca0 AK |
533 | /* |
534 | * We didn't find a valid entry. | |
535 | */ | |
aea390e4 DG |
536 | return -1; |
537 | } | |
538 | ||
7ef23068 | 539 | static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, |
7f3bdc2d | 540 | ppc_slb_t *slb, target_ulong eaddr, |
94986863 | 541 | ppc_hash_pte64_t *pte, unsigned *pshift) |
c69b6151 | 542 | { |
7ef23068 | 543 | CPUPPCState *env = &cpu->env; |
7222b94a | 544 | hwaddr hash, ptex; |
cd6a9bb6 | 545 | uint64_t vsid, epnmask, epn, ptem; |
b07c59f7 | 546 | const PPCHash64SegmentPageSizes *sps = slb->sps; |
cd6a9bb6 DG |
547 | |
548 | /* The SLB store path should prevent any bad page size encodings | |
549 | * getting in there, so: */ | |
2c7ad804 | 550 | assert(sps); |
a1ff751a | 551 | |
2c7ad804 BH |
552 | /* If ISL is set in LPCR we need to clamp the page size to 4K */ |
553 | if (env->spr[SPR_LPCR] & LPCR_ISL) { | |
554 | /* We assume that when using TCG, 4k is first entry of SPS */ | |
b07c59f7 | 555 | sps = &cpu->hash64_opts->sps[0]; |
2c7ad804 BH |
556 | assert(sps->page_shift == 12); |
557 | } | |
558 | ||
559 | epnmask = ~((1ULL << sps->page_shift) - 1); | |
a1ff751a | 560 | |
a1ff751a | 561 | if (slb->vsid & SLB_VSID_B) { |
18148898 DG |
562 | /* 1TB segment */ |
563 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T; | |
564 | epn = (eaddr & ~SEGMENT_MASK_1T) & epnmask; | |
2c7ad804 | 565 | hash = vsid ^ (vsid << 25) ^ (epn >> sps->page_shift); |
a1ff751a | 566 | } else { |
18148898 DG |
567 | /* 256M segment */ |
568 | vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT; | |
569 | epn = (eaddr & ~SEGMENT_MASK_256M) & epnmask; | |
2c7ad804 | 570 | hash = vsid ^ (epn >> sps->page_shift); |
a1ff751a | 571 | } |
18148898 | 572 | ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); |
073de86a | 573 | ptem |= HPTE64_V_VALID; |
a1ff751a | 574 | |
a1ff751a | 575 | /* Page address translation */ |
339aaf5b AP |
576 | qemu_log_mask(CPU_LOG_MMU, |
577 | "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx | |
a1ff751a | 578 | " hash " TARGET_FMT_plx "\n", |
36778660 | 579 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); |
a1ff751a | 580 | |
a1ff751a | 581 | /* Primary PTEG lookup */ |
339aaf5b AP |
582 | qemu_log_mask(CPU_LOG_MMU, |
583 | "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a DG |
584 | " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx |
585 | " hash=" TARGET_FMT_plx "\n", | |
36778660 DG |
586 | ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), |
587 | vsid, ptem, hash); | |
7222b94a | 588 | ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); |
7f3bdc2d | 589 | |
7222b94a | 590 | if (ptex == -1) { |
a1ff751a | 591 | /* Secondary PTEG lookup */ |
073de86a | 592 | ptem |= HPTE64_V_SECONDARY; |
339aaf5b AP |
593 | qemu_log_mask(CPU_LOG_MMU, |
594 | "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx | |
a1ff751a | 595 | " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx |
36778660 DG |
596 | " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu), |
597 | ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); | |
a1ff751a | 598 | |
7222b94a | 599 | ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); |
a1ff751a DG |
600 | } |
601 | ||
7222b94a | 602 | return ptex; |
c69b6151 | 603 | } |
0480884f | 604 | |
1114e712 | 605 | unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu, |
1f0252e6 | 606 | uint64_t pte0, uint64_t pte1) |
1114e712 | 607 | { |
1114e712 DG |
608 | int i; |
609 | ||
610 | if (!(pte0 & HPTE64_V_LARGE)) { | |
1114e712 DG |
611 | return 12; |
612 | } | |
613 | ||
614 | /* | |
615 | * The encodings in env->sps need to be carefully chosen so that | |
616 | * this gives an unambiguous result. | |
617 | */ | |
618 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { | |
b07c59f7 | 619 | const PPCHash64SegmentPageSizes *sps = &cpu->hash64_opts->sps[i]; |
1114e712 DG |
620 | unsigned shift; |
621 | ||
622 | if (!sps->page_shift) { | |
623 | break; | |
624 | } | |
625 | ||
626 | shift = hpte_page_shift(sps, pte0, pte1); | |
627 | if (shift) { | |
1114e712 DG |
628 | return shift; |
629 | } | |
630 | } | |
631 | ||
1114e712 DG |
632 | return 0; |
633 | } | |
634 | ||
8fe08fac | 635 | static void ppc_hash64_set_isi(CPUState *cs, uint64_t error_code) |
33595dc9 | 636 | { |
8fe08fac | 637 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
33595dc9 BH |
638 | bool vpm; |
639 | ||
640 | if (msr_ir) { | |
641 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); | |
642 | } else { | |
50659083 SJS |
643 | switch (env->mmu_model) { |
644 | case POWERPC_MMU_3_00: | |
645 | /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ | |
646 | vpm = true; | |
647 | break; | |
648 | default: | |
649 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); | |
650 | break; | |
651 | } | |
33595dc9 BH |
652 | } |
653 | if (vpm && !msr_hv) { | |
654 | cs->exception_index = POWERPC_EXCP_HISI; | |
655 | } else { | |
656 | cs->exception_index = POWERPC_EXCP_ISI; | |
657 | } | |
658 | env->error_code = error_code; | |
659 | } | |
660 | ||
8fe08fac | 661 | static void ppc_hash64_set_dsi(CPUState *cs, uint64_t dar, uint64_t dsisr) |
33595dc9 | 662 | { |
8fe08fac | 663 | CPUPPCState *env = &POWERPC_CPU(cs)->env; |
33595dc9 BH |
664 | bool vpm; |
665 | ||
666 | if (msr_dr) { | |
667 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1); | |
668 | } else { | |
50659083 SJS |
669 | switch (env->mmu_model) { |
670 | case POWERPC_MMU_3_00: | |
671 | /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */ | |
672 | vpm = true; | |
673 | break; | |
674 | default: | |
675 | vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0); | |
676 | break; | |
677 | } | |
33595dc9 BH |
678 | } |
679 | if (vpm && !msr_hv) { | |
680 | cs->exception_index = POWERPC_EXCP_HDSI; | |
681 | env->spr[SPR_HDAR] = dar; | |
682 | env->spr[SPR_HDSISR] = dsisr; | |
683 | } else { | |
684 | cs->exception_index = POWERPC_EXCP_DSI; | |
685 | env->spr[SPR_DAR] = dar; | |
686 | env->spr[SPR_DSISR] = dsisr; | |
687 | } | |
688 | env->error_code = 0; | |
689 | } | |
690 | ||
691 | ||
b2305601 | 692 | int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, |
caa597bd | 693 | int rwx, int mmu_idx) |
0480884f | 694 | { |
d0e39c5d AF |
695 | CPUState *cs = CPU(cpu); |
696 | CPUPPCState *env = &cpu->env; | |
0480884f | 697 | ppc_slb_t *slb; |
be18b2b5 | 698 | unsigned apshift; |
7222b94a | 699 | hwaddr ptex; |
7f3bdc2d | 700 | ppc_hash_pte64_t pte; |
07a68f99 | 701 | int exec_prot, pp_prot, amr_prot, prot; |
da82c73a | 702 | uint64_t new_pte1; |
e01b4445 | 703 | const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; |
caa597bd | 704 | hwaddr raddr; |
0480884f | 705 | |
6a980110 DG |
706 | assert((rwx == 0) || (rwx == 1) || (rwx == 2)); |
707 | ||
912acdf4 BH |
708 | /* Note on LPCR usage: 970 uses HID4, but our special variant |
709 | * of store_spr copies relevant fields into env->spr[SPR_LPCR]. | |
710 | * Similarily we filter unimplemented bits when storing into | |
711 | * LPCR depending on the MMU version. This code can thus just | |
712 | * use the LPCR "as-is". | |
713 | */ | |
714 | ||
65d61643 DG |
715 | /* 1. Handle real mode accesses */ |
716 | if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) { | |
912acdf4 BH |
717 | /* Translation is supposedly "off" */ |
718 | /* In real mode the top 4 effective address bits are (mostly) ignored */ | |
caa597bd | 719 | raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL; |
912acdf4 BH |
720 | |
721 | /* In HV mode, add HRMOR if top EA bit is clear */ | |
722 | if (msr_hv || !env->has_hv_mode) { | |
723 | if (!(eaddr >> 63)) { | |
724 | raddr |= env->spr[SPR_HRMOR]; | |
725 | } | |
726 | } else { | |
727 | /* Otherwise, check VPM for RMA vs VRMA */ | |
728 | if (env->spr[SPR_LPCR] & LPCR_VPM0) { | |
729 | slb = &env->vrma_slb; | |
730 | if (slb->sps) { | |
731 | goto skip_slb_search; | |
732 | } | |
733 | /* Not much else to do here */ | |
734 | cs->exception_index = POWERPC_EXCP_MCHECK; | |
735 | env->error_code = 0; | |
736 | return 1; | |
737 | } else if (raddr < env->rmls) { | |
738 | /* RMA. Check bounds in RMLS */ | |
739 | raddr |= env->spr[SPR_RMOR]; | |
740 | } else { | |
741 | /* The access failed, generate the approriate interrupt */ | |
742 | if (rwx == 2) { | |
8fe08fac | 743 | ppc_hash64_set_isi(cs, SRR1_PROTFAULT); |
912acdf4 | 744 | } else { |
da82c73a | 745 | int dsisr = DSISR_PROTFAULT; |
912acdf4 | 746 | if (rwx == 1) { |
da82c73a | 747 | dsisr |= DSISR_ISSTORE; |
912acdf4 | 748 | } |
8fe08fac | 749 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
912acdf4 BH |
750 | } |
751 | return 1; | |
752 | } | |
753 | } | |
0c591eb0 | 754 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
caa597bd DG |
755 | PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx, |
756 | TARGET_PAGE_SIZE); | |
65d61643 DG |
757 | return 0; |
758 | } | |
759 | ||
bb218042 | 760 | /* 2. Translation is on, so look up the SLB */ |
7ef23068 | 761 | slb = slb_lookup(cpu, eaddr); |
0480884f | 762 | if (!slb) { |
b2899495 SJS |
763 | /* No entry found, check if in-memory segment tables are in use */ |
764 | if ((env->mmu_model & POWERPC_MMU_V3) && ppc64_use_proc_tbl(cpu)) { | |
765 | /* TODO - Unsupported */ | |
766 | error_report("Segment Table Support Unimplemented"); | |
767 | exit(1); | |
768 | } | |
769 | /* Segment still not found, generate the appropriate interrupt */ | |
caa597bd | 770 | if (rwx == 2) { |
27103424 | 771 | cs->exception_index = POWERPC_EXCP_ISEG; |
caa597bd DG |
772 | env->error_code = 0; |
773 | } else { | |
27103424 | 774 | cs->exception_index = POWERPC_EXCP_DSEG; |
caa597bd DG |
775 | env->error_code = 0; |
776 | env->spr[SPR_DAR] = eaddr; | |
777 | } | |
778 | return 1; | |
0480884f DG |
779 | } |
780 | ||
912acdf4 BH |
781 | skip_slb_search: |
782 | ||
bb218042 DG |
783 | /* 3. Check for segment level no-execute violation */ |
784 | if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) { | |
8fe08fac | 785 | ppc_hash64_set_isi(cs, SRR1_NOEXEC_GUARD); |
caa597bd | 786 | return 1; |
bb218042 DG |
787 | } |
788 | ||
7f3bdc2d | 789 | /* 4. Locate the PTE in the hash table */ |
7222b94a DG |
790 | ptex = ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte, &apshift); |
791 | if (ptex == -1) { | |
caa597bd | 792 | if (rwx == 2) { |
8fe08fac | 793 | ppc_hash64_set_isi(cs, SRR1_NOPTE); |
caa597bd | 794 | } else { |
da82c73a | 795 | int dsisr = DSISR_NOPTE; |
caa597bd | 796 | if (rwx == 1) { |
da82c73a | 797 | dsisr |= DSISR_ISSTORE; |
caa597bd | 798 | } |
8fe08fac | 799 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
caa597bd DG |
800 | } |
801 | return 1; | |
7f3bdc2d | 802 | } |
339aaf5b | 803 | qemu_log_mask(CPU_LOG_MMU, |
7222b94a | 804 | "found PTE at index %08" HWADDR_PRIx "\n", ptex); |
7f3bdc2d DG |
805 | |
806 | /* 5. Check access permissions */ | |
7f3bdc2d | 807 | |
07a68f99 | 808 | exec_prot = ppc_hash64_pte_noexec_guard(cpu, pte); |
7ef23068 DG |
809 | pp_prot = ppc_hash64_pte_prot(cpu, slb, pte); |
810 | amr_prot = ppc_hash64_amr_prot(cpu, pte); | |
07a68f99 | 811 | prot = exec_prot & pp_prot & amr_prot; |
6a980110 | 812 | |
caa597bd | 813 | if ((need_prot[rwx] & ~prot) != 0) { |
6a980110 | 814 | /* Access right violation */ |
339aaf5b | 815 | qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); |
caa597bd | 816 | if (rwx == 2) { |
a6152b52 | 817 | int srr1 = 0; |
07a68f99 SJS |
818 | if (PAGE_EXEC & ~exec_prot) { |
819 | srr1 |= SRR1_NOEXEC_GUARD; /* Access violates noexec or guard */ | |
820 | } else if (PAGE_EXEC & ~pp_prot) { | |
a6152b52 SJS |
821 | srr1 |= SRR1_PROTFAULT; /* Access violates access authority */ |
822 | } | |
823 | if (PAGE_EXEC & ~amr_prot) { | |
824 | srr1 |= SRR1_IAMR; /* Access violates virt pg class key prot */ | |
825 | } | |
8fe08fac | 826 | ppc_hash64_set_isi(cs, srr1); |
caa597bd | 827 | } else { |
da82c73a | 828 | int dsisr = 0; |
f80872e2 | 829 | if (need_prot[rwx] & ~pp_prot) { |
da82c73a | 830 | dsisr |= DSISR_PROTFAULT; |
f80872e2 | 831 | } |
caa597bd | 832 | if (rwx == 1) { |
da82c73a | 833 | dsisr |= DSISR_ISSTORE; |
f80872e2 DG |
834 | } |
835 | if (need_prot[rwx] & ~amr_prot) { | |
da82c73a | 836 | dsisr |= DSISR_AMR; |
caa597bd | 837 | } |
8fe08fac | 838 | ppc_hash64_set_dsi(cs, eaddr, dsisr); |
caa597bd DG |
839 | } |
840 | return 1; | |
6a980110 DG |
841 | } |
842 | ||
339aaf5b | 843 | qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n"); |
87dc3fd1 DG |
844 | |
845 | /* 6. Update PTE referenced and changed bits if necessary */ | |
846 | ||
b3440746 DG |
847 | new_pte1 = pte.pte1 | HPTE64_R_R; /* set referenced bit */ |
848 | if (rwx == 1) { | |
849 | new_pte1 |= HPTE64_R_C; /* set changed (dirty) bit */ | |
850 | } else { | |
851 | /* Treat the page as read-only for now, so that a later write | |
852 | * will pass through this function again to set the C bit */ | |
caa597bd | 853 | prot &= ~PAGE_WRITE; |
b3440746 DG |
854 | } |
855 | ||
856 | if (new_pte1 != pte.pte1) { | |
7222b94a | 857 | ppc_hash64_store_hpte(cpu, ptex, pte.pte0, new_pte1); |
7f3bdc2d | 858 | } |
0480884f | 859 | |
6d11d998 DG |
860 | /* 7. Determine the real address from the PTE */ |
861 | ||
be18b2b5 | 862 | raddr = deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, eaddr); |
caa597bd | 863 | |
0c591eb0 | 864 | tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK, |
be18b2b5 | 865 | prot, mmu_idx, 1ULL << apshift); |
e01b4445 | 866 | |
e01b4445 | 867 | return 0; |
0480884f | 868 | } |
629bd516 | 869 | |
7ef23068 | 870 | hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr) |
f2ad6be8 | 871 | { |
7ef23068 | 872 | CPUPPCState *env = &cpu->env; |
5883d8b2 | 873 | ppc_slb_t *slb; |
7222b94a | 874 | hwaddr ptex, raddr; |
5883d8b2 | 875 | ppc_hash_pte64_t pte; |
be18b2b5 | 876 | unsigned apshift; |
5883d8b2 | 877 | |
912acdf4 | 878 | /* Handle real mode */ |
5883d8b2 DG |
879 | if (msr_dr == 0) { |
880 | /* In real mode the top 4 effective address bits are ignored */ | |
912acdf4 | 881 | raddr = addr & 0x0FFFFFFFFFFFFFFFULL; |
f2ad6be8 | 882 | |
912acdf4 BH |
883 | /* In HV mode, add HRMOR if top EA bit is clear */ |
884 | if ((msr_hv || !env->has_hv_mode) && !(addr >> 63)) { | |
885 | return raddr | env->spr[SPR_HRMOR]; | |
886 | } | |
887 | ||
888 | /* Otherwise, check VPM for RMA vs VRMA */ | |
889 | if (env->spr[SPR_LPCR] & LPCR_VPM0) { | |
890 | slb = &env->vrma_slb; | |
891 | if (!slb->sps) { | |
892 | return -1; | |
893 | } | |
894 | } else if (raddr < env->rmls) { | |
895 | /* RMA. Check bounds in RMLS */ | |
896 | return raddr | env->spr[SPR_RMOR]; | |
897 | } else { | |
898 | return -1; | |
899 | } | |
900 | } else { | |
901 | slb = slb_lookup(cpu, addr); | |
902 | if (!slb) { | |
903 | return -1; | |
904 | } | |
5883d8b2 DG |
905 | } |
906 | ||
7222b94a DG |
907 | ptex = ppc_hash64_htab_lookup(cpu, slb, addr, &pte, &apshift); |
908 | if (ptex == -1) { | |
f2ad6be8 DG |
909 | return -1; |
910 | } | |
911 | ||
be18b2b5 | 912 | return deposit64(pte.pte1 & HPTE64_R_RPN, 0, apshift, addr) |
cd6a9bb6 | 913 | & TARGET_PAGE_MASK; |
f2ad6be8 | 914 | } |
c1385933 | 915 | |
7222b94a DG |
916 | void ppc_hash64_store_hpte(PowerPCCPU *cpu, hwaddr ptex, |
917 | uint64_t pte0, uint64_t pte1) | |
c1385933 | 918 | { |
e57ca75c | 919 | hwaddr base = ppc_hash64_hpt_base(cpu); |
7222b94a | 920 | hwaddr offset = ptex * HASH_PTE_SIZE_64; |
c1385933 | 921 | |
e57ca75c DG |
922 | if (cpu->vhyp) { |
923 | PPCVirtualHypervisorClass *vhc = | |
924 | PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); | |
925 | vhc->store_hpte(cpu->vhyp, ptex, pte0, pte1); | |
a9ab06d1 | 926 | return; |
c1385933 AK |
927 | } |
928 | ||
e57ca75c DG |
929 | stq_phys(CPU(cpu)->as, base + offset, pte0); |
930 | stq_phys(CPU(cpu)->as, base + offset + HASH_PTE_SIZE_64 / 2, pte1); | |
c1385933 | 931 | } |
61a36c9b | 932 | |
7222b94a | 933 | void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex, |
61a36c9b DG |
934 | target_ulong pte0, target_ulong pte1) |
935 | { | |
936 | /* | |
937 | * XXX: given the fact that there are too many segments to | |
938 | * invalidate, and we still don't have a tlb_flush_mask(env, n, | |
939 | * mask) in QEMU, we just invalidate all TLBs | |
940 | */ | |
d76ab5e1 | 941 | cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; |
61a36c9b | 942 | } |
4b3fc377 | 943 | |
8fe08fac | 944 | void ppc_hash64_update_rmls(PowerPCCPU *cpu) |
912acdf4 | 945 | { |
8fe08fac | 946 | CPUPPCState *env = &cpu->env; |
912acdf4 BH |
947 | uint64_t lpcr = env->spr[SPR_LPCR]; |
948 | ||
949 | /* | |
950 | * This is the full 4 bits encoding of POWER8. Previous | |
951 | * CPUs only support a subset of these but the filtering | |
952 | * is done when writing LPCR | |
953 | */ | |
954 | switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { | |
955 | case 0x8: /* 32MB */ | |
956 | env->rmls = 0x2000000ull; | |
957 | break; | |
958 | case 0x3: /* 64MB */ | |
959 | env->rmls = 0x4000000ull; | |
960 | break; | |
961 | case 0x7: /* 128MB */ | |
962 | env->rmls = 0x8000000ull; | |
963 | break; | |
964 | case 0x4: /* 256MB */ | |
965 | env->rmls = 0x10000000ull; | |
966 | break; | |
967 | case 0x2: /* 1GB */ | |
968 | env->rmls = 0x40000000ull; | |
969 | break; | |
970 | case 0x1: /* 16GB */ | |
971 | env->rmls = 0x400000000ull; | |
972 | break; | |
973 | default: | |
974 | /* What to do here ??? */ | |
975 | env->rmls = 0; | |
976 | } | |
977 | } | |
978 | ||
8fe08fac | 979 | void ppc_hash64_update_vrma(PowerPCCPU *cpu) |
912acdf4 | 980 | { |
8fe08fac | 981 | CPUPPCState *env = &cpu->env; |
b07c59f7 | 982 | const PPCHash64SegmentPageSizes *sps = NULL; |
912acdf4 BH |
983 | target_ulong esid, vsid, lpcr; |
984 | ppc_slb_t *slb = &env->vrma_slb; | |
985 | uint32_t vrmasd; | |
986 | int i; | |
987 | ||
988 | /* First clear it */ | |
989 | slb->esid = slb->vsid = 0; | |
990 | slb->sps = NULL; | |
991 | ||
992 | /* Is VRMA enabled ? */ | |
993 | lpcr = env->spr[SPR_LPCR]; | |
994 | if (!(lpcr & LPCR_VPM0)) { | |
995 | return; | |
996 | } | |
997 | ||
998 | /* Make one up. Mostly ignore the ESID which will not be | |
999 | * needed for translation | |
1000 | */ | |
1001 | vsid = SLB_VSID_VRMA; | |
1002 | vrmasd = (lpcr & LPCR_VRMASD) >> LPCR_VRMASD_SHIFT; | |
1003 | vsid |= (vrmasd << 4) & (SLB_VSID_L | SLB_VSID_LP); | |
1004 | esid = SLB_ESID_V; | |
1005 | ||
8fe08fac | 1006 | for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { |
b07c59f7 | 1007 | const PPCHash64SegmentPageSizes *sps1 = &cpu->hash64_opts->sps[i]; |
912acdf4 BH |
1008 | |
1009 | if (!sps1->page_shift) { | |
1010 | break; | |
1011 | } | |
1012 | ||
1013 | if ((vsid & SLB_VSID_LLP_MASK) == sps1->slb_enc) { | |
1014 | sps = sps1; | |
1015 | break; | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | if (!sps) { | |
1020 | error_report("Bad page size encoding esid 0x"TARGET_FMT_lx | |
1021 | " vsid 0x"TARGET_FMT_lx, esid, vsid); | |
1022 | return; | |
1023 | } | |
1024 | ||
1025 | slb->vsid = vsid; | |
1026 | slb->esid = esid; | |
1027 | slb->sps = sps; | |
1028 | } | |
1029 | ||
4b3fc377 BH |
1030 | void helper_store_lpcr(CPUPPCState *env, target_ulong val) |
1031 | { | |
8fe08fac | 1032 | PowerPCCPU *cpu = ppc_env_get_cpu(env); |
4b3fc377 BH |
1033 | uint64_t lpcr = 0; |
1034 | ||
1035 | /* Filter out bits */ | |
ec975e83 SB |
1036 | switch (POWERPC_MMU_VER(env->mmu_model)) { |
1037 | case POWERPC_MMU_VER_64B: /* 970 */ | |
4b3fc377 BH |
1038 | if (val & 0x40) { |
1039 | lpcr |= LPCR_LPES0; | |
1040 | } | |
1041 | if (val & 0x8000000000000000ull) { | |
1042 | lpcr |= LPCR_LPES1; | |
1043 | } | |
1044 | if (val & 0x20) { | |
1045 | lpcr |= (0x4ull << LPCR_RMLS_SHIFT); | |
1046 | } | |
1047 | if (val & 0x4000000000000000ull) { | |
1048 | lpcr |= (0x2ull << LPCR_RMLS_SHIFT); | |
1049 | } | |
1050 | if (val & 0x2000000000000000ull) { | |
1051 | lpcr |= (0x1ull << LPCR_RMLS_SHIFT); | |
1052 | } | |
1053 | env->spr[SPR_RMOR] = ((lpcr >> 41) & 0xffffull) << 26; | |
1054 | ||
1055 | /* XXX We could also write LPID from HID4 here | |
1056 | * but since we don't tag any translation on it | |
1057 | * it doesn't actually matter | |
1058 | */ | |
1059 | /* XXX For proper emulation of 970 we also need | |
1060 | * to dig HRMOR out of HID5 | |
1061 | */ | |
1062 | break; | |
ec975e83 | 1063 | case POWERPC_MMU_VER_2_03: /* P5p */ |
4b3fc377 BH |
1064 | lpcr = val & (LPCR_RMLS | LPCR_ILE | |
1065 | LPCR_LPES0 | LPCR_LPES1 | | |
1066 | LPCR_RMI | LPCR_HDICE); | |
1067 | break; | |
ec975e83 | 1068 | case POWERPC_MMU_VER_2_06: /* P7 */ |
4b3fc377 BH |
1069 | lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | |
1070 | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | | |
1071 | LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | | |
1072 | LPCR_MER | LPCR_TC | | |
1073 | LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE); | |
1074 | break; | |
ec975e83 | 1075 | case POWERPC_MMU_VER_2_07: /* P8 */ |
4b3fc377 BH |
1076 | lpcr = val & (LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | |
1077 | LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | | |
1078 | LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | | |
1079 | LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | | |
1080 | LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE); | |
1081 | break; | |
ec975e83 | 1082 | case POWERPC_MMU_VER_3_00: /* P9 */ |
18aa49ec SJS |
1083 | lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | |
1084 | (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | | |
1085 | LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | | |
1086 | (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | | |
1087 | LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC | | |
1088 | LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE); | |
1089 | break; | |
4b3fc377 BH |
1090 | default: |
1091 | ; | |
1092 | } | |
1093 | env->spr[SPR_LPCR] = lpcr; | |
8fe08fac DG |
1094 | ppc_hash64_update_rmls(cpu); |
1095 | ppc_hash64_update_vrma(cpu); | |
4b3fc377 | 1096 | } |
a059471d DG |
1097 | |
1098 | void ppc_hash64_init(PowerPCCPU *cpu) | |
1099 | { | |
1100 | CPUPPCState *env = &cpu->env; | |
1101 | PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); | |
1102 | ||
21e405f1 DG |
1103 | if (!pcc->hash64_opts) { |
1104 | assert(!(env->mmu_model & POWERPC_MMU_64)); | |
1105 | return; | |
a059471d | 1106 | } |
21e405f1 DG |
1107 | |
1108 | cpu->hash64_opts = g_memdup(pcc->hash64_opts, sizeof(*cpu->hash64_opts)); | |
a059471d DG |
1109 | } |
1110 | ||
1111 | void ppc_hash64_finalize(PowerPCCPU *cpu) | |
1112 | { | |
b07c59f7 | 1113 | g_free(cpu->hash64_opts); |
a059471d | 1114 | } |
b07c59f7 | 1115 | |
21e405f1 | 1116 | const PPCHash64Options ppc_hash64_opts_basic = { |
58969eee | 1117 | .flags = 0, |
21e405f1 DG |
1118 | .sps = { |
1119 | { .page_shift = 12, /* 4K */ | |
1120 | .slb_enc = 0, | |
1121 | .enc = { { .page_shift = 12, .pte_enc = 0 } } | |
1122 | }, | |
1123 | { .page_shift = 24, /* 16M */ | |
1124 | .slb_enc = 0x100, | |
1125 | .enc = { { .page_shift = 24, .pte_enc = 0 } } | |
1126 | }, | |
1127 | }, | |
1128 | }; | |
1129 | ||
b07c59f7 | 1130 | const PPCHash64Options ppc_hash64_opts_POWER7 = { |
58969eee | 1131 | .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR, |
b07c59f7 DG |
1132 | .sps = { |
1133 | { | |
1134 | .page_shift = 12, /* 4K */ | |
1135 | .slb_enc = 0, | |
1136 | .enc = { { .page_shift = 12, .pte_enc = 0 }, | |
1137 | { .page_shift = 16, .pte_enc = 0x7 }, | |
1138 | { .page_shift = 24, .pte_enc = 0x38 }, }, | |
1139 | }, | |
1140 | { | |
1141 | .page_shift = 16, /* 64K */ | |
1142 | .slb_enc = SLB_VSID_64K, | |
1143 | .enc = { { .page_shift = 16, .pte_enc = 0x1 }, | |
1144 | { .page_shift = 24, .pte_enc = 0x8 }, }, | |
1145 | }, | |
1146 | { | |
1147 | .page_shift = 24, /* 16M */ | |
1148 | .slb_enc = SLB_VSID_16M, | |
1149 | .enc = { { .page_shift = 24, .pte_enc = 0 }, }, | |
1150 | }, | |
1151 | { | |
1152 | .page_shift = 34, /* 16G */ | |
1153 | .slb_enc = SLB_VSID_16G, | |
1154 | .enc = { { .page_shift = 34, .pte_enc = 0x3 }, }, | |
1155 | }, | |
1156 | } | |
1157 | }; |