[mirror_qemu.git] / target / ppc / mmu-hash64.h

#ifndef MMU_HASH64_H
#define MMU_HASH64_H

#ifndef CONFIG_USER_ONLY

#ifdef TARGET_PPC64
void dump_slb(PowerPCCPU *cpu);
int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
                  target_ulong esid, target_ulong vsid);
hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,
                                int mmu_idx);
void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
                               target_ulong pte_index,
                               target_ulong pte0, target_ulong pte1);
unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
                                          uint64_t pte0, uint64_t pte1);
void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
void ppc_hash64_init(PowerPCCPU *cpu);
void ppc_hash64_finalize(PowerPCCPU *cpu);
void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
                                 bool (*cb)(void *, uint32_t, uint32_t),
                                 void *opaque);
#endif

/*
 * SLB definitions
 */

/* Bits in the SLB ESID word */
#define SLB_ESID_ESID           0xFFFFFFFFF0000000ULL
#define SLB_ESID_V              0x0000000008000000ULL /* valid */

/* Bits in the SLB VSID word */
#define SLB_VSID_SHIFT          12
#define SLB_VSID_SHIFT_1T       24
#define SLB_VSID_SSIZE_SHIFT    62
#define SLB_VSID_B              0xc000000000000000ULL
#define SLB_VSID_B_256M         0x0000000000000000ULL
#define SLB_VSID_B_1T           0x4000000000000000ULL
#define SLB_VSID_VSID           0x3FFFFFFFFFFFF000ULL
#define SLB_VSID_VRMA           (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
#define SLB_VSID_PTEM           (SLB_VSID_B | SLB_VSID_VSID)
#define SLB_VSID_KS             0x0000000000000800ULL
#define SLB_VSID_KP             0x0000000000000400ULL
#define SLB_VSID_N              0x0000000000000200ULL /* no-execute */
#define SLB_VSID_L              0x0000000000000100ULL
#define SLB_VSID_C              0x0000000000000080ULL /* class */
#define SLB_VSID_LP             0x0000000000000030ULL
#define SLB_VSID_ATTR           0x0000000000000FFFULL
#define SLB_VSID_LLP_MASK       (SLB_VSID_L | SLB_VSID_LP)
#define SLB_VSID_4K             0x0000000000000000ULL
#define SLB_VSID_64K            0x0000000000000110ULL
#define SLB_VSID_16M            0x0000000000000100ULL
#define SLB_VSID_16G            0x0000000000000120ULL

/*
 * Hash page table definitions
 */

#define SDR_64_HTABORG         0x0FFFFFFFFFFC0000ULL
#define SDR_64_HTABSIZE        0x000000000000001FULL

#define PATE0_HTABORG           0x0FFFFFFFFFFC0000ULL
#define HPTES_PER_GROUP         8
#define HASH_PTE_SIZE_64        16
#define HASH_PTEG_SIZE_64       (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)

#define HPTE64_V_SSIZE          SLB_VSID_B
#define HPTE64_V_SSIZE_256M     SLB_VSID_B_256M
#define HPTE64_V_SSIZE_1T       SLB_VSID_B_1T
#define HPTE64_V_SSIZE_SHIFT    62
#define HPTE64_V_AVPN_SHIFT     7
#define HPTE64_V_AVPN           0x3fffffffffffff80ULL
#define HPTE64_V_AVPN_VAL(x)    (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
#define HPTE64_V_COMPARE(x, y)  (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
#define HPTE64_V_BOLTED         0x0000000000000010ULL
#define HPTE64_V_LARGE          0x0000000000000004ULL
#define HPTE64_V_SECONDARY      0x0000000000000002ULL
#define HPTE64_V_VALID          0x0000000000000001ULL

#define HPTE64_R_PP0            0x8000000000000000ULL
#define HPTE64_R_TS             0x4000000000000000ULL
#define HPTE64_R_KEY_HI         0x3000000000000000ULL
#define HPTE64_R_RPN_SHIFT      12
#define HPTE64_R_RPN            0x0ffffffffffff000ULL
#define HPTE64_R_FLAGS          0x00000000000003ffULL
#define HPTE64_R_PP             0x0000000000000003ULL
#define HPTE64_R_N              0x0000000000000004ULL
#define HPTE64_R_G              0x0000000000000008ULL
#define HPTE64_R_M              0x0000000000000010ULL
#define HPTE64_R_I              0x0000000000000020ULL
#define HPTE64_R_W              0x0000000000000040ULL
#define HPTE64_R_WIMG           0x0000000000000078ULL
#define HPTE64_R_C              0x0000000000000080ULL
#define HPTE64_R_R              0x0000000000000100ULL
#define HPTE64_R_KEY_LO         0x0000000000000e00ULL
#define HPTE64_R_KEY(x)         ((((x) & HPTE64_R_KEY_HI) >> 57) | \
                                 (((x) & HPTE64_R_KEY_LO) >> 9))

#define HPTE64_V_1TB_SEG        0x4000000000000000ULL
#define HPTE64_V_VRMA_MASK      0x4001ffffff000000ULL

/* Format changes for ARCH v3 */
#define HPTE64_V_COMMON_BITS    0x000fffffffffffffULL
#define HPTE64_R_3_0_SSIZE_SHIFT 58
#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)

struct ppc_hash_pte64 {
    uint64_t pte0, pte1;
};

const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
                                             hwaddr ptex, int n);
void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
                            hwaddr ptex, int n);

static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
                                        const ppc_hash_pte64_t *hptes, int i)
{
    return ldq_p(&(hptes[i].pte0));
}

static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
                                        const ppc_hash_pte64_t *hptes, int i)
{
    return ldq_p(&(hptes[i].pte1));
}

/*
 * MMU Options
 */

struct PPCHash64PageSize {
    uint32_t page_shift;  /* Page shift (or 0) */
    uint32_t pte_enc;     /* Encoding in the HPTE (>>12) */
};
typedef struct PPCHash64PageSize PPCHash64PageSize;

struct PPCHash64SegmentPageSizes {
    uint32_t page_shift;  /* Base page shift of segment (or 0) */
    uint32_t slb_enc;     /* SLB encoding for BookS */
    PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
};

struct PPCHash64Options {
#define PPC_HASH64_1TSEG        0x00001
#define PPC_HASH64_AMR          0x00002
#define PPC_HASH64_CI_LARGEPAGE 0x00004
    unsigned flags;
    unsigned slb_size;
    PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
};

extern const PPCHash64Options ppc_hash64_opts_basic;
extern const PPCHash64Options ppc_hash64_opts_POWER7;

static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
{
    return !!(cpu->hash64_opts->flags & feature);
}

#endif /* CONFIG_USER_ONLY */

#if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
static inline void ppc_hash64_init(PowerPCCPU *cpu)
{
}
static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
{
}
#endif

#endif /* MMU_HASH64_H */
Commit	Line	Data
2a6a4076 MA	1	#ifndef MMU_HASH64_H
2a6a4076 MA	2	#define MMU_HASH64_H
10b46525 DG	3
	4	#ifndef CONFIG_USER_ONLY
	5
	6	#ifdef TARGET_PPC64
fad866da	7	void dump_slb(PowerPCCPU *cpu);
bcd81230 DG	8	int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
bcd81230 DG	9	target_ulong esid, target_ulong vsid);
7ef23068	10	hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr);
b2305601	11	int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw,
25de24ab	12	int mmu_idx);
61a36c9b DG	13	void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
	14	target_ulong pte_index,
	15	target_ulong pte0, target_ulong pte1);
1114e712	16	unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
1f0252e6	17	uint64_t pte0, uint64_t pte1);
5ad55315	18	void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val);
a059471d DG	19	void ppc_hash64_init(PowerPCCPU *cpu);
a059471d DG	20	void ppc_hash64_finalize(PowerPCCPU *cpu);
27f00f0a DG	21	void ppc_hash64_filter_pagesizes(PowerPCCPU *cpu,
	22	bool (cb)(void , uint32_t, uint32_t),
	23	void *opaque);
10b46525 DG	24	#endif
10b46525 DG	25
d5aea6f3 DG	26	/*
	27	* SLB definitions
	28	*/
	29
	30	/* Bits in the SLB ESID word */
	31	#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
	32	#define SLB_ESID_V 0x0000000008000000ULL /* valid */
	33
	34	/* Bits in the SLB VSID word */
	35	#define SLB_VSID_SHIFT 12
	36	#define SLB_VSID_SHIFT_1T 24
	37	#define SLB_VSID_SSIZE_SHIFT 62
	38	#define SLB_VSID_B 0xc000000000000000ULL
	39	#define SLB_VSID_B_256M 0x0000000000000000ULL
	40	#define SLB_VSID_B_1T 0x4000000000000000ULL
	41	#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
912acdf4	42	#define SLB_VSID_VRMA (0x0001FFFFFF000000ULL \| SLB_VSID_B_1T)
d5aea6f3 DG	43	#define SLB_VSID_PTEM (SLB_VSID_B \| SLB_VSID_VSID)
	44	#define SLB_VSID_KS 0x0000000000000800ULL
	45	#define SLB_VSID_KP 0x0000000000000400ULL
	46	#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
	47	#define SLB_VSID_L 0x0000000000000100ULL
	48	#define SLB_VSID_C 0x0000000000000080ULL /* class */
	49	#define SLB_VSID_LP 0x0000000000000030ULL
	50	#define SLB_VSID_ATTR 0x0000000000000FFFULL
ad3e67d0 AK	51	#define SLB_VSID_LLP_MASK (SLB_VSID_L \| SLB_VSID_LP)
	52	#define SLB_VSID_4K 0x0000000000000000ULL
	53	#define SLB_VSID_64K 0x0000000000000110ULL
a8891fbf DG	54	#define SLB_VSID_16M 0x0000000000000100ULL
a8891fbf DG	55	#define SLB_VSID_16G 0x0000000000000120ULL
d5aea6f3 DG	56
	57	/*
	58	* Hash page table definitions
	59	*/
	60
e78308fd	61	#define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
36778660 DG	62	#define SDR_64_HTABSIZE 0x000000000000001FULL
36778660 DG	63
3367c62f	64	#define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
d5aea6f3 DG	65	#define HPTES_PER_GROUP 8
	66	#define HASH_PTE_SIZE_64 16
	67	#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
	68
0b0b8310 DG	69	#define HPTE64_V_SSIZE SLB_VSID_B
	70	#define HPTE64_V_SSIZE_256M SLB_VSID_B_256M
	71	#define HPTE64_V_SSIZE_1T SLB_VSID_B_1T
d5aea6f3 DG	72	#define HPTE64_V_SSIZE_SHIFT 62
	73	#define HPTE64_V_AVPN_SHIFT 7
	74	#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
	75	#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
073de86a	76	#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
0b0b8310	77	#define HPTE64_V_BOLTED 0x0000000000000010ULL
d5aea6f3 DG	78	#define HPTE64_V_LARGE 0x0000000000000004ULL
	79	#define HPTE64_V_SECONDARY 0x0000000000000002ULL
	80	#define HPTE64_V_VALID 0x0000000000000001ULL
	81
	82	#define HPTE64_R_PP0 0x8000000000000000ULL
	83	#define HPTE64_R_TS 0x4000000000000000ULL
	84	#define HPTE64_R_KEY_HI 0x3000000000000000ULL
	85	#define HPTE64_R_RPN_SHIFT 12
	86	#define HPTE64_R_RPN 0x0ffffffffffff000ULL
	87	#define HPTE64_R_FLAGS 0x00000000000003ffULL
	88	#define HPTE64_R_PP 0x0000000000000003ULL
	89	#define HPTE64_R_N 0x0000000000000004ULL
	90	#define HPTE64_R_G 0x0000000000000008ULL
	91	#define HPTE64_R_M 0x0000000000000010ULL
	92	#define HPTE64_R_I 0x0000000000000020ULL
	93	#define HPTE64_R_W 0x0000000000000040ULL
	94	#define HPTE64_R_WIMG 0x0000000000000078ULL
	95	#define HPTE64_R_C 0x0000000000000080ULL
	96	#define HPTE64_R_R 0x0000000000000100ULL
	97	#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
6925f12f	98	#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) \| \
f80872e2	99	(((x) & HPTE64_R_KEY_LO) >> 9))
d5aea6f3 DG	100
	101	#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
	102	#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
	103
34525595 BH	104	/* Format changes for ARCH v3 */
	105	#define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
	106	#define HPTE64_R_3_0_SSIZE_SHIFT 58
	107	#define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
	108
7222b94a DG	109	struct ppc_hash_pte64 {
	110	uint64_t pte0, pte1;
	111	};
	112
	113	const ppc_hash_pte64_t ppc_hash64_map_hptes(PowerPCCPU cpu,
	114	hwaddr ptex, int n);
	115	void ppc_hash64_unmap_hptes(PowerPCCPU cpu, const ppc_hash_pte64_t hptes,
	116	hwaddr ptex, int n);
7c43bca0	117
7222b94a DG	118	static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
7222b94a DG	119	const ppc_hash_pte64_t *hptes, int i)
dffdaf61	120	{
7222b94a	121	return ldq_p(&(hptes[i].pte0));
dffdaf61 DG	122	}
dffdaf61 DG	123
7222b94a DG	124	static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
7222b94a DG	125	const ppc_hash_pte64_t *hptes, int i)
dffdaf61	126	{
7222b94a	127	return ldq_p(&(hptes[i].pte1));
dffdaf61 DG	128	}
dffdaf61 DG	129
b07c59f7 DG	130	/*
	131	* MMU Options
	132	*/
	133
	134	struct PPCHash64PageSize {
	135	uint32_t page_shift; /* Page shift (or 0) */
	136	uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
	137	};
	138	typedef struct PPCHash64PageSize PPCHash64PageSize;
	139
	140	struct PPCHash64SegmentPageSizes {
	141	uint32_t page_shift; /* Base page shift of segment (or 0) */
	142	uint32_t slb_enc; /* SLB encoding for BookS */
	143	PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
	144	};
	145
	146	struct PPCHash64Options {
58969eee DG	147	#define PPC_HASH64_1TSEG 0x00001
58969eee DG	148	#define PPC_HASH64_AMR 0x00002
26cd35b8	149	#define PPC_HASH64_CI_LARGEPAGE 0x00004
58969eee	150	unsigned flags;
67d7d66f	151	unsigned slb_size;
b07c59f7 DG	152	PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
	153	};
	154
21e405f1	155	extern const PPCHash64Options ppc_hash64_opts_basic;
b07c59f7 DG	156	extern const PPCHash64Options ppc_hash64_opts_POWER7;
b07c59f7 DG	157
58969eee DG	158	static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
	159	{
	160	return !!(cpu->hash64_opts->flags & feature);
	161	}
	162
10b46525 DG	163	#endif /* CONFIG_USER_ONLY */
10b46525 DG	164
a059471d DG	165	#if defined(CONFIG_USER_ONLY) \|\| !defined(TARGET_PPC64)
	166	static inline void ppc_hash64_init(PowerPCCPU *cpu)
	167	{
	168	}
	169	static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
	170	{
	171	}
	172	#endif
	173
2a6a4076	174	#endif /* MMU_HASH64_H */