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target/ppc: Fix VXCVI return value
[mirror_qemu.git] / target / ppc / monitor.c
CommitLineData
bf957284
PB
1/*
2 * QEMU monitor
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
856dfd8a 24
0d75590d 25#include "qemu/osdep.h"
bf957284
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26#include "cpu.h"
27#include "monitor/monitor.h"
856dfd8a 28#include "qemu/ctype.h"
bf957284 29#include "monitor/hmp-target.h"
275307aa 30#include "monitor/hmp.h"
bf957284 31
43cf067f
KW
32static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,
33 int val)
bf957284 34{
e7cff9c6 35 CPUArchState *env = mon_get_cpu_env(mon);
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36 unsigned int u;
37 int i;
38
39 u = 0;
a6582090 40 for (i = 0; i < 8; i++) {
bf957284 41 u |= env->crf[i] << (32 - (4 * (i + 1)));
a6582090 42 }
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43
44 return u;
45}
46
3938cacd
MF
47static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md,
48 int val)
49{
50 CPUArchState *env = mon_get_cpu_env(mon);
51 return cpu_read_xer(env);
52}
53
43cf067f
KW
54static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
55 int val)
bf957284 56{
e7cff9c6 57 CPUArchState *env = mon_get_cpu_env(mon);
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58 return cpu_ppc_load_decr(env);
59}
60
43cf067f
KW
61static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
62 int val)
bf957284 63{
e7cff9c6 64 CPUArchState *env = mon_get_cpu_env(mon);
bf957284
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65 return cpu_ppc_load_tbu(env);
66}
67
43cf067f
KW
68static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
69 int val)
bf957284 70{
e7cff9c6 71 CPUArchState *env = mon_get_cpu_env(mon);
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72 return cpu_ppc_load_tbl(env);
73}
74
75void hmp_info_tlb(Monitor *mon, const QDict *qdict)
76{
e7cff9c6 77 CPUArchState *env1 = mon_get_cpu_env(mon);
bf957284 78
854e67fe
TH
79 if (!env1) {
80 monitor_printf(mon, "No CPU available\n");
81 return;
82 }
fad866da 83 dump_mmu(env1);
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84}
85
bf957284 86const MonitorDef monitor_defs[] = {
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87 { "fpscr", offsetof(CPUPPCState, fpscr) },
88 /* Next instruction pointer */
89 { "nip|pc", offsetof(CPUPPCState, nip) },
90 { "lr", offsetof(CPUPPCState, lr) },
91 { "ctr", offsetof(CPUPPCState, ctr) },
92 { "decr", 0, &monitor_get_decr, },
0a9516c2 93 { "ccr|cr", 0, &monitor_get_ccr, },
bf957284 94 /* Machine state register */
3938cacd 95 { "xer", 0, &monitor_get_xer },
0a9516c2 96 { "msr", offsetof(CPUPPCState, msr) },
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97 { "tbu", 0, &monitor_get_tbu, },
98 { "tbl", 0, &monitor_get_tbl, },
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99 { NULL },
100};
101
102const MonitorDef *target_monitor_defs(void)
103{
104 return monitor_defs;
105}
0a9516c2
AK
106
107static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)
108{
109 int regnum;
110 char *endptr = NULL;
111
112 if (!*numstr) {
113 return false;
114 }
115
116 regnum = strtoul(numstr, &endptr, 10);
117 if (*endptr || (regnum >= maxnum)) {
118 return false;
119 }
120 *pregnum = regnum;
121
122 return true;
123}
124
125int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)
126{
127 int i, regnum;
128 PowerPCCPU *cpu = POWERPC_CPU(cs);
129 CPUPPCState *env = &cpu->env;
130
131 /* General purpose registers */
95a5befc 132 if ((qemu_tolower(name[0]) == 'r') &&
0a9516c2
AK
133 ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), &regnum)) {
134 *pval = env->gpr[regnum];
135 return 0;
136 }
137
138 /* Floating point registers */
95a5befc 139 if ((qemu_tolower(name[0]) == 'f') &&
ef96e3ae
MCA
140 ppc_cpu_get_reg_num(name + 1, 32, &regnum)) {
141 *pval = *cpu_fpr_ptr(env, regnum);
0a9516c2
AK
142 return 0;
143 }
144
145 /* Special purpose registers */
146 for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {
147 ppc_spr_t *spr = &env->spr_cb[i];
148
149 if (spr->name && (strcasecmp(name, spr->name) == 0)) {
150 *pval = env->spr[i];
151 return 0;
152 }
153 }
154
155 /* Segment registers */
156#if !defined(CONFIG_USER_ONLY)
157 if ((strncasecmp(name, "sr", 2) == 0) &&
158 ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), &regnum)) {
159 *pval = env->sr[regnum];
160 return 0;
161 }
162#endif
163
164 return -EINVAL;
165}