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Commit | Line | Data |
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0304af89 BH |
1 | /* |
2 | * translate/vmx-impl.c | |
3 | * | |
4 | * Altivec/VMX translation | |
5 | */ | |
6 | ||
7 | /*** Altivec vector extension ***/ | |
8 | /* Altivec registers moves */ | |
9 | ||
10 | static inline TCGv_ptr gen_avr_ptr(int reg) | |
11 | { | |
12 | TCGv_ptr r = tcg_temp_new_ptr(); | |
c82a8a85 | 13 | tcg_gen_addi_ptr(r, cpu_env, avr_full_offset(reg)); |
0304af89 BH |
14 | return r; |
15 | } | |
16 | ||
17 | #define GEN_VR_LDX(name, opc2, opc3) \ | |
32553866 | 18 | static void glue(gen_, name)(DisasContext *ctx) \ |
0304af89 BH |
19 | { \ |
20 | TCGv EA; \ | |
c4a18dbf | 21 | TCGv_i64 avr; \ |
0304af89 BH |
22 | if (unlikely(!ctx->altivec_enabled)) { \ |
23 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
24 | return; \ | |
25 | } \ | |
26 | gen_set_access_type(ctx, ACCESS_INT); \ | |
c4a18dbf | 27 | avr = tcg_temp_new_i64(); \ |
0304af89 BH |
28 | EA = tcg_temp_new(); \ |
29 | gen_addr_reg_index(ctx, EA); \ | |
30 | tcg_gen_andi_tl(EA, EA, ~0xf); \ | |
32553866 DG |
31 | /* \ |
32 | * We only need to swap high and low halves. gen_qemu_ld64_i64 \ | |
33 | * does necessary 64-bit byteswap already. \ | |
34 | */ \ | |
0304af89 | 35 | if (ctx->le_mode) { \ |
c4a18dbf MCA |
36 | gen_qemu_ld64_i64(ctx, avr, EA); \ |
37 | set_avr64(rD(ctx->opcode), avr, false); \ | |
0304af89 | 38 | tcg_gen_addi_tl(EA, EA, 8); \ |
c4a18dbf MCA |
39 | gen_qemu_ld64_i64(ctx, avr, EA); \ |
40 | set_avr64(rD(ctx->opcode), avr, true); \ | |
0304af89 | 41 | } else { \ |
c4a18dbf MCA |
42 | gen_qemu_ld64_i64(ctx, avr, EA); \ |
43 | set_avr64(rD(ctx->opcode), avr, true); \ | |
0304af89 | 44 | tcg_gen_addi_tl(EA, EA, 8); \ |
c4a18dbf MCA |
45 | gen_qemu_ld64_i64(ctx, avr, EA); \ |
46 | set_avr64(rD(ctx->opcode), avr, false); \ | |
0304af89 BH |
47 | } \ |
48 | tcg_temp_free(EA); \ | |
c4a18dbf | 49 | tcg_temp_free_i64(avr); \ |
0304af89 BH |
50 | } |
51 | ||
52 | #define GEN_VR_STX(name, opc2, opc3) \ | |
53 | static void gen_st##name(DisasContext *ctx) \ | |
54 | { \ | |
55 | TCGv EA; \ | |
c4a18dbf | 56 | TCGv_i64 avr; \ |
0304af89 BH |
57 | if (unlikely(!ctx->altivec_enabled)) { \ |
58 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
59 | return; \ | |
60 | } \ | |
61 | gen_set_access_type(ctx, ACCESS_INT); \ | |
c4a18dbf | 62 | avr = tcg_temp_new_i64(); \ |
0304af89 BH |
63 | EA = tcg_temp_new(); \ |
64 | gen_addr_reg_index(ctx, EA); \ | |
65 | tcg_gen_andi_tl(EA, EA, ~0xf); \ | |
32553866 DG |
66 | /* \ |
67 | * We only need to swap high and low halves. gen_qemu_st64_i64 \ | |
68 | * does necessary 64-bit byteswap already. \ | |
69 | */ \ | |
0304af89 | 70 | if (ctx->le_mode) { \ |
c4a18dbf MCA |
71 | get_avr64(avr, rD(ctx->opcode), false); \ |
72 | gen_qemu_st64_i64(ctx, avr, EA); \ | |
0304af89 | 73 | tcg_gen_addi_tl(EA, EA, 8); \ |
c4a18dbf MCA |
74 | get_avr64(avr, rD(ctx->opcode), true); \ |
75 | gen_qemu_st64_i64(ctx, avr, EA); \ | |
0304af89 | 76 | } else { \ |
c4a18dbf MCA |
77 | get_avr64(avr, rD(ctx->opcode), true); \ |
78 | gen_qemu_st64_i64(ctx, avr, EA); \ | |
0304af89 | 79 | tcg_gen_addi_tl(EA, EA, 8); \ |
c4a18dbf MCA |
80 | get_avr64(avr, rD(ctx->opcode), false); \ |
81 | gen_qemu_st64_i64(ctx, avr, EA); \ | |
0304af89 BH |
82 | } \ |
83 | tcg_temp_free(EA); \ | |
c4a18dbf | 84 | tcg_temp_free_i64(avr); \ |
0304af89 BH |
85 | } |
86 | ||
87 | #define GEN_VR_LVE(name, opc2, opc3, size) \ | |
88 | static void gen_lve##name(DisasContext *ctx) \ | |
89 | { \ | |
90 | TCGv EA; \ | |
91 | TCGv_ptr rs; \ | |
92 | if (unlikely(!ctx->altivec_enabled)) { \ | |
93 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
94 | return; \ | |
95 | } \ | |
96 | gen_set_access_type(ctx, ACCESS_INT); \ | |
97 | EA = tcg_temp_new(); \ | |
98 | gen_addr_reg_index(ctx, EA); \ | |
99 | if (size > 1) { \ | |
100 | tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ | |
101 | } \ | |
102 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
103 | gen_helper_lve##name(cpu_env, rs, EA); \ | |
104 | tcg_temp_free(EA); \ | |
105 | tcg_temp_free_ptr(rs); \ | |
106 | } | |
107 | ||
108 | #define GEN_VR_STVE(name, opc2, opc3, size) \ | |
109 | static void gen_stve##name(DisasContext *ctx) \ | |
110 | { \ | |
111 | TCGv EA; \ | |
112 | TCGv_ptr rs; \ | |
113 | if (unlikely(!ctx->altivec_enabled)) { \ | |
114 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
115 | return; \ | |
116 | } \ | |
117 | gen_set_access_type(ctx, ACCESS_INT); \ | |
118 | EA = tcg_temp_new(); \ | |
119 | gen_addr_reg_index(ctx, EA); \ | |
120 | if (size > 1) { \ | |
121 | tcg_gen_andi_tl(EA, EA, ~(size - 1)); \ | |
122 | } \ | |
123 | rs = gen_avr_ptr(rS(ctx->opcode)); \ | |
124 | gen_helper_stve##name(cpu_env, rs, EA); \ | |
125 | tcg_temp_free(EA); \ | |
126 | tcg_temp_free_ptr(rs); \ | |
127 | } | |
128 | ||
129 | GEN_VR_LDX(lvx, 0x07, 0x03); | |
130 | /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */ | |
131 | GEN_VR_LDX(lvxl, 0x07, 0x0B); | |
132 | ||
133 | GEN_VR_LVE(bx, 0x07, 0x00, 1); | |
134 | GEN_VR_LVE(hx, 0x07, 0x01, 2); | |
135 | GEN_VR_LVE(wx, 0x07, 0x02, 4); | |
136 | ||
137 | GEN_VR_STX(svx, 0x07, 0x07); | |
138 | /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */ | |
139 | GEN_VR_STX(svxl, 0x07, 0x0F); | |
140 | ||
141 | GEN_VR_STVE(bx, 0x07, 0x04, 1); | |
142 | GEN_VR_STVE(hx, 0x07, 0x05, 2); | |
143 | GEN_VR_STVE(wx, 0x07, 0x06, 4); | |
144 | ||
0304af89 BH |
145 | static void gen_mfvscr(DisasContext *ctx) |
146 | { | |
147 | TCGv_i32 t; | |
c4a18dbf | 148 | TCGv_i64 avr; |
0304af89 BH |
149 | if (unlikely(!ctx->altivec_enabled)) { |
150 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
151 | return; | |
152 | } | |
c4a18dbf MCA |
153 | avr = tcg_temp_new_i64(); |
154 | tcg_gen_movi_i64(avr, 0); | |
155 | set_avr64(rD(ctx->opcode), avr, true); | |
0304af89 | 156 | t = tcg_temp_new_i32(); |
cc2b90d7 | 157 | gen_helper_mfvscr(t, cpu_env); |
c4a18dbf MCA |
158 | tcg_gen_extu_i32_i64(avr, t); |
159 | set_avr64(rD(ctx->opcode), avr, false); | |
0304af89 | 160 | tcg_temp_free_i32(t); |
c4a18dbf | 161 | tcg_temp_free_i64(avr); |
0304af89 BH |
162 | } |
163 | ||
164 | static void gen_mtvscr(DisasContext *ctx) | |
165 | { | |
dedfaac7 RH |
166 | TCGv_i32 val; |
167 | int bofs; | |
168 | ||
0304af89 BH |
169 | if (unlikely(!ctx->altivec_enabled)) { |
170 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
171 | return; | |
172 | } | |
dedfaac7 RH |
173 | |
174 | val = tcg_temp_new_i32(); | |
c82a8a85 | 175 | bofs = avr_full_offset(rB(ctx->opcode)); |
dedfaac7 RH |
176 | #ifdef HOST_WORDS_BIGENDIAN |
177 | bofs += 3 * 4; | |
178 | #endif | |
179 | ||
180 | tcg_gen_ld_i32(val, cpu_env, bofs); | |
181 | gen_helper_mtvscr(cpu_env, val); | |
182 | tcg_temp_free_i32(val); | |
0304af89 BH |
183 | } |
184 | ||
37ad52ba VH |
185 | #define GEN_VX_VMUL10(name, add_cin, ret_carry) \ |
186 | static void glue(gen_, name)(DisasContext *ctx) \ | |
187 | { \ | |
c4a18dbf MCA |
188 | TCGv_i64 t0; \ |
189 | TCGv_i64 t1; \ | |
190 | TCGv_i64 t2; \ | |
191 | TCGv_i64 avr; \ | |
37ad52ba VH |
192 | TCGv_i64 ten, z; \ |
193 | \ | |
194 | if (unlikely(!ctx->altivec_enabled)) { \ | |
195 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
196 | return; \ | |
197 | } \ | |
198 | \ | |
c4a18dbf MCA |
199 | t0 = tcg_temp_new_i64(); \ |
200 | t1 = tcg_temp_new_i64(); \ | |
201 | t2 = tcg_temp_new_i64(); \ | |
202 | avr = tcg_temp_new_i64(); \ | |
37ad52ba VH |
203 | ten = tcg_const_i64(10); \ |
204 | z = tcg_const_i64(0); \ | |
205 | \ | |
206 | if (add_cin) { \ | |
c4a18dbf MCA |
207 | get_avr64(avr, rA(ctx->opcode), false); \ |
208 | tcg_gen_mulu2_i64(t0, t1, avr, ten); \ | |
209 | get_avr64(avr, rB(ctx->opcode), false); \ | |
210 | tcg_gen_andi_i64(t2, avr, 0xF); \ | |
211 | tcg_gen_add2_i64(avr, t2, t0, t1, t2, z); \ | |
212 | set_avr64(rD(ctx->opcode), avr, false); \ | |
37ad52ba | 213 | } else { \ |
c4a18dbf MCA |
214 | get_avr64(avr, rA(ctx->opcode), false); \ |
215 | tcg_gen_mulu2_i64(avr, t2, avr, ten); \ | |
216 | set_avr64(rD(ctx->opcode), avr, false); \ | |
37ad52ba VH |
217 | } \ |
218 | \ | |
219 | if (ret_carry) { \ | |
c4a18dbf MCA |
220 | get_avr64(avr, rA(ctx->opcode), true); \ |
221 | tcg_gen_mulu2_i64(t0, t1, avr, ten); \ | |
222 | tcg_gen_add2_i64(t0, avr, t0, t1, t2, z); \ | |
223 | set_avr64(rD(ctx->opcode), avr, false); \ | |
224 | set_avr64(rD(ctx->opcode), z, true); \ | |
37ad52ba | 225 | } else { \ |
c4a18dbf MCA |
226 | get_avr64(avr, rA(ctx->opcode), true); \ |
227 | tcg_gen_mul_i64(t0, avr, ten); \ | |
228 | tcg_gen_add_i64(avr, t0, t2); \ | |
229 | set_avr64(rD(ctx->opcode), avr, true); \ | |
37ad52ba VH |
230 | } \ |
231 | \ | |
232 | tcg_temp_free_i64(t0); \ | |
233 | tcg_temp_free_i64(t1); \ | |
234 | tcg_temp_free_i64(t2); \ | |
c4a18dbf | 235 | tcg_temp_free_i64(avr); \ |
37ad52ba VH |
236 | tcg_temp_free_i64(ten); \ |
237 | tcg_temp_free_i64(z); \ | |
238 | } \ | |
239 | ||
240 | GEN_VX_VMUL10(vmul10uq, 0, 0); | |
241 | GEN_VX_VMUL10(vmul10euq, 1, 0); | |
242 | GEN_VX_VMUL10(vmul10cuq, 0, 1); | |
243 | GEN_VX_VMUL10(vmul10ecuq, 1, 1); | |
244 | ||
50d24aed MCA |
245 | #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \ |
246 | static void glue(gen_, name)(DisasContext *ctx) \ | |
0304af89 BH |
247 | { \ |
248 | if (unlikely(!ctx->altivec_enabled)) { \ | |
249 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
250 | return; \ | |
251 | } \ | |
c4a18dbf | 252 | \ |
50d24aed | 253 | tcg_op(vece, \ |
c82a8a85 MCA |
254 | avr_full_offset(rD(ctx->opcode)), \ |
255 | avr_full_offset(rA(ctx->opcode)), \ | |
256 | avr_full_offset(rB(ctx->opcode)), \ | |
50d24aed | 257 | 16, 16); \ |
0304af89 BH |
258 | } |
259 | ||
50d24aed MCA |
260 | /* Logical operations */ |
261 | GEN_VXFORM_V(vand, MO_64, tcg_gen_gvec_and, 2, 16); | |
262 | GEN_VXFORM_V(vandc, MO_64, tcg_gen_gvec_andc, 2, 17); | |
263 | GEN_VXFORM_V(vor, MO_64, tcg_gen_gvec_or, 2, 18); | |
264 | GEN_VXFORM_V(vxor, MO_64, tcg_gen_gvec_xor, 2, 19); | |
265 | GEN_VXFORM_V(vnor, MO_64, tcg_gen_gvec_nor, 2, 20); | |
266 | GEN_VXFORM_V(veqv, MO_64, tcg_gen_gvec_eqv, 2, 26); | |
267 | GEN_VXFORM_V(vnand, MO_64, tcg_gen_gvec_nand, 2, 22); | |
268 | GEN_VXFORM_V(vorc, MO_64, tcg_gen_gvec_orc, 2, 21); | |
0304af89 BH |
269 | |
270 | #define GEN_VXFORM(name, opc2, opc3) \ | |
32553866 | 271 | static void glue(gen_, name)(DisasContext *ctx) \ |
0304af89 BH |
272 | { \ |
273 | TCGv_ptr ra, rb, rd; \ | |
274 | if (unlikely(!ctx->altivec_enabled)) { \ | |
275 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
276 | return; \ | |
277 | } \ | |
278 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
279 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
280 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
32553866 | 281 | gen_helper_##name(rd, ra, rb); \ |
0304af89 BH |
282 | tcg_temp_free_ptr(ra); \ |
283 | tcg_temp_free_ptr(rb); \ | |
284 | tcg_temp_free_ptr(rd); \ | |
285 | } | |
286 | ||
1cc79269 SB |
287 | #define GEN_VXFORM_TRANS(name, opc2, opc3) \ |
288 | static void glue(gen_, name)(DisasContext *ctx) \ | |
289 | { \ | |
290 | if (unlikely(!ctx->altivec_enabled)) { \ | |
291 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
292 | return; \ | |
293 | } \ | |
294 | trans_##name(ctx); \ | |
295 | } | |
296 | ||
0304af89 BH |
297 | #define GEN_VXFORM_ENV(name, opc2, opc3) \ |
298 | static void glue(gen_, name)(DisasContext *ctx) \ | |
299 | { \ | |
300 | TCGv_ptr ra, rb, rd; \ | |
301 | if (unlikely(!ctx->altivec_enabled)) { \ | |
302 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
303 | return; \ | |
304 | } \ | |
305 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
306 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
307 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
308 | gen_helper_##name(cpu_env, rd, ra, rb); \ | |
309 | tcg_temp_free_ptr(ra); \ | |
310 | tcg_temp_free_ptr(rb); \ | |
311 | tcg_temp_free_ptr(rd); \ | |
312 | } | |
313 | ||
314 | #define GEN_VXFORM3(name, opc2, opc3) \ | |
315 | static void glue(gen_, name)(DisasContext *ctx) \ | |
316 | { \ | |
317 | TCGv_ptr ra, rb, rc, rd; \ | |
318 | if (unlikely(!ctx->altivec_enabled)) { \ | |
319 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
320 | return; \ | |
321 | } \ | |
322 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
323 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
324 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
325 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
326 | gen_helper_##name(rd, ra, rb, rc); \ | |
327 | tcg_temp_free_ptr(ra); \ | |
328 | tcg_temp_free_ptr(rb); \ | |
329 | tcg_temp_free_ptr(rc); \ | |
330 | tcg_temp_free_ptr(rd); \ | |
331 | } | |
332 | ||
333 | /* | |
334 | * Support for Altivec instruction pairs that use bit 31 (Rc) as | |
335 | * an opcode bit. In general, these pairs come from different | |
336 | * versions of the ISA, so we must also support a pair of flags for | |
337 | * each instruction. | |
338 | */ | |
339 | #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
340 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
341 | { \ | |
342 | if ((Rc(ctx->opcode) == 0) && \ | |
343 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
344 | gen_##name0(ctx); \ | |
345 | } else if ((Rc(ctx->opcode) == 1) && \ | |
346 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
347 | gen_##name1(ctx); \ | |
348 | } else { \ | |
349 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
350 | } \ | |
351 | } | |
352 | ||
37ad52ba VH |
353 | /* Adds support to provide invalid mask */ |
354 | #define GEN_VXFORM_DUAL_EXT(name0, flg0, flg2_0, inval0, \ | |
355 | name1, flg1, flg2_1, inval1) \ | |
356 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
357 | { \ | |
358 | if ((Rc(ctx->opcode) == 0) && \ | |
359 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0)) && \ | |
360 | !(ctx->opcode & inval0)) { \ | |
361 | gen_##name0(ctx); \ | |
362 | } else if ((Rc(ctx->opcode) == 1) && \ | |
363 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1)) && \ | |
364 | !(ctx->opcode & inval1)) { \ | |
365 | gen_##name1(ctx); \ | |
366 | } else { \ | |
367 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
368 | } \ | |
369 | } | |
370 | ||
60caf221 AK |
371 | #define GEN_VXFORM_HETRO(name, opc2, opc3) \ |
372 | static void glue(gen_, name)(DisasContext *ctx) \ | |
373 | { \ | |
374 | TCGv_ptr rb; \ | |
375 | if (unlikely(!ctx->altivec_enabled)) { \ | |
376 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
377 | return; \ | |
378 | } \ | |
379 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
380 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \ | |
381 | tcg_temp_free_ptr(rb); \ | |
382 | } | |
383 | ||
3e942a1a | 384 | GEN_VXFORM_V(vaddubm, MO_8, tcg_gen_gvec_add, 0, 0); |
37ad52ba VH |
385 | GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \ |
386 | vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800) | |
3e942a1a | 387 | GEN_VXFORM_V(vadduhm, MO_16, tcg_gen_gvec_add, 0, 1); |
37ad52ba VH |
388 | GEN_VXFORM_DUAL(vadduhm, PPC_ALTIVEC, PPC_NONE, \ |
389 | vmul10ecuq, PPC_NONE, PPC2_ISA300) | |
3e942a1a MCA |
390 | GEN_VXFORM_V(vadduwm, MO_32, tcg_gen_gvec_add, 0, 2); |
391 | GEN_VXFORM_V(vaddudm, MO_64, tcg_gen_gvec_add, 0, 3); | |
392 | GEN_VXFORM_V(vsububm, MO_8, tcg_gen_gvec_sub, 0, 16); | |
393 | GEN_VXFORM_V(vsubuhm, MO_16, tcg_gen_gvec_sub, 0, 17); | |
394 | GEN_VXFORM_V(vsubuwm, MO_32, tcg_gen_gvec_sub, 0, 18); | |
395 | GEN_VXFORM_V(vsubudm, MO_64, tcg_gen_gvec_sub, 0, 19); | |
73e14c6a RH |
396 | GEN_VXFORM_V(vmaxub, MO_8, tcg_gen_gvec_umax, 1, 0); |
397 | GEN_VXFORM_V(vmaxuh, MO_16, tcg_gen_gvec_umax, 1, 1); | |
398 | GEN_VXFORM_V(vmaxuw, MO_32, tcg_gen_gvec_umax, 1, 2); | |
399 | GEN_VXFORM_V(vmaxud, MO_64, tcg_gen_gvec_umax, 1, 3); | |
400 | GEN_VXFORM_V(vmaxsb, MO_8, tcg_gen_gvec_smax, 1, 4); | |
401 | GEN_VXFORM_V(vmaxsh, MO_16, tcg_gen_gvec_smax, 1, 5); | |
402 | GEN_VXFORM_V(vmaxsw, MO_32, tcg_gen_gvec_smax, 1, 6); | |
403 | GEN_VXFORM_V(vmaxsd, MO_64, tcg_gen_gvec_smax, 1, 7); | |
404 | GEN_VXFORM_V(vminub, MO_8, tcg_gen_gvec_umin, 1, 8); | |
405 | GEN_VXFORM_V(vminuh, MO_16, tcg_gen_gvec_umin, 1, 9); | |
406 | GEN_VXFORM_V(vminuw, MO_32, tcg_gen_gvec_umin, 1, 10); | |
407 | GEN_VXFORM_V(vminud, MO_64, tcg_gen_gvec_umin, 1, 11); | |
408 | GEN_VXFORM_V(vminsb, MO_8, tcg_gen_gvec_smin, 1, 12); | |
409 | GEN_VXFORM_V(vminsh, MO_16, tcg_gen_gvec_smin, 1, 13); | |
410 | GEN_VXFORM_V(vminsw, MO_32, tcg_gen_gvec_smin, 1, 14); | |
411 | GEN_VXFORM_V(vminsd, MO_64, tcg_gen_gvec_smin, 1, 15); | |
0304af89 | 412 | GEN_VXFORM(vavgub, 1, 16); |
37707059 SD |
413 | GEN_VXFORM(vabsdub, 1, 16); |
414 | GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \ | |
415 | vabsdub, PPC_NONE, PPC2_ISA300) | |
0304af89 | 416 | GEN_VXFORM(vavguh, 1, 17); |
37707059 SD |
417 | GEN_VXFORM(vabsduh, 1, 17); |
418 | GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \ | |
419 | vabsduh, PPC_NONE, PPC2_ISA300) | |
0304af89 | 420 | GEN_VXFORM(vavguw, 1, 18); |
37707059 SD |
421 | GEN_VXFORM(vabsduw, 1, 18); |
422 | GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \ | |
423 | vabsduw, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
424 | GEN_VXFORM(vavgsb, 1, 20); |
425 | GEN_VXFORM(vavgsh, 1, 21); | |
426 | GEN_VXFORM(vavgsw, 1, 22); | |
427 | GEN_VXFORM(vmrghb, 6, 0); | |
428 | GEN_VXFORM(vmrghh, 6, 1); | |
429 | GEN_VXFORM(vmrghw, 6, 2); | |
430 | GEN_VXFORM(vmrglb, 6, 4); | |
431 | GEN_VXFORM(vmrglh, 6, 5); | |
432 | GEN_VXFORM(vmrglw, 6, 6); | |
433 | ||
434 | static void gen_vmrgew(DisasContext *ctx) | |
435 | { | |
436 | TCGv_i64 tmp; | |
c4a18dbf | 437 | TCGv_i64 avr; |
0304af89 BH |
438 | int VT, VA, VB; |
439 | if (unlikely(!ctx->altivec_enabled)) { | |
440 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
441 | return; | |
442 | } | |
443 | VT = rD(ctx->opcode); | |
444 | VA = rA(ctx->opcode); | |
445 | VB = rB(ctx->opcode); | |
446 | tmp = tcg_temp_new_i64(); | |
c4a18dbf MCA |
447 | avr = tcg_temp_new_i64(); |
448 | ||
449 | get_avr64(avr, VB, true); | |
450 | tcg_gen_shri_i64(tmp, avr, 32); | |
451 | get_avr64(avr, VA, true); | |
452 | tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); | |
453 | set_avr64(VT, avr, true); | |
454 | ||
455 | get_avr64(avr, VB, false); | |
456 | tcg_gen_shri_i64(tmp, avr, 32); | |
457 | get_avr64(avr, VA, false); | |
458 | tcg_gen_deposit_i64(avr, avr, tmp, 0, 32); | |
459 | set_avr64(VT, avr, false); | |
460 | ||
0304af89 | 461 | tcg_temp_free_i64(tmp); |
c4a18dbf | 462 | tcg_temp_free_i64(avr); |
0304af89 BH |
463 | } |
464 | ||
465 | static void gen_vmrgow(DisasContext *ctx) | |
466 | { | |
c4a18dbf MCA |
467 | TCGv_i64 t0, t1; |
468 | TCGv_i64 avr; | |
0304af89 BH |
469 | int VT, VA, VB; |
470 | if (unlikely(!ctx->altivec_enabled)) { | |
471 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
472 | return; | |
473 | } | |
474 | VT = rD(ctx->opcode); | |
475 | VA = rA(ctx->opcode); | |
476 | VB = rB(ctx->opcode); | |
c4a18dbf MCA |
477 | t0 = tcg_temp_new_i64(); |
478 | t1 = tcg_temp_new_i64(); | |
479 | avr = tcg_temp_new_i64(); | |
480 | ||
481 | get_avr64(t0, VB, true); | |
482 | get_avr64(t1, VA, true); | |
483 | tcg_gen_deposit_i64(avr, t0, t1, 32, 32); | |
484 | set_avr64(VT, avr, true); | |
485 | ||
486 | get_avr64(t0, VB, false); | |
487 | get_avr64(t1, VA, false); | |
488 | tcg_gen_deposit_i64(avr, t0, t1, 32, 32); | |
489 | set_avr64(VT, avr, false); | |
490 | ||
491 | tcg_temp_free_i64(t0); | |
492 | tcg_temp_free_i64(t1); | |
493 | tcg_temp_free_i64(avr); | |
0304af89 BH |
494 | } |
495 | ||
1cc79269 SB |
496 | /* |
497 | * lvsl VRT,RA,RB - Load Vector for Shift Left | |
498 | * | |
499 | * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31]. | |
500 | * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. | |
501 | * Bytes sh:sh+15 of X are placed into vD. | |
502 | */ | |
503 | static void trans_lvsl(DisasContext *ctx) | |
504 | { | |
505 | int VT = rD(ctx->opcode); | |
506 | TCGv_i64 result = tcg_temp_new_i64(); | |
507 | TCGv_i64 sh = tcg_temp_new_i64(); | |
508 | TCGv EA = tcg_temp_new(); | |
509 | ||
510 | /* Get sh(from description) by anding EA with 0xf. */ | |
511 | gen_addr_reg_index(ctx, EA); | |
512 | tcg_gen_extu_tl_i64(sh, EA); | |
513 | tcg_gen_andi_i64(sh, sh, 0xfULL); | |
514 | ||
515 | /* | |
516 | * Create bytes sh:sh+7 of X(from description) and place them in | |
517 | * higher doubleword of vD. | |
518 | */ | |
519 | tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL); | |
520 | tcg_gen_addi_i64(result, sh, 0x0001020304050607ull); | |
521 | set_avr64(VT, result, true); | |
522 | /* | |
523 | * Create bytes sh+8:sh+15 of X(from description) and place them in | |
524 | * lower doubleword of vD. | |
525 | */ | |
526 | tcg_gen_addi_i64(result, sh, 0x08090a0b0c0d0e0fULL); | |
527 | set_avr64(VT, result, false); | |
528 | ||
529 | tcg_temp_free_i64(result); | |
530 | tcg_temp_free_i64(sh); | |
531 | tcg_temp_free(EA); | |
532 | } | |
533 | ||
534 | /* | |
535 | * lvsr VRT,RA,RB - Load Vector for Shift Right | |
536 | * | |
537 | * Let the EA be the sum (rA|0)+(rB). Let sh=EA[28–31]. | |
538 | * Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. | |
539 | * Bytes (16-sh):(31-sh) of X are placed into vD. | |
540 | */ | |
541 | static void trans_lvsr(DisasContext *ctx) | |
542 | { | |
543 | int VT = rD(ctx->opcode); | |
544 | TCGv_i64 result = tcg_temp_new_i64(); | |
545 | TCGv_i64 sh = tcg_temp_new_i64(); | |
546 | TCGv EA = tcg_temp_new(); | |
547 | ||
548 | ||
549 | /* Get sh(from description) by anding EA with 0xf. */ | |
550 | gen_addr_reg_index(ctx, EA); | |
551 | tcg_gen_extu_tl_i64(sh, EA); | |
552 | tcg_gen_andi_i64(sh, sh, 0xfULL); | |
553 | ||
554 | /* | |
555 | * Create bytes (16-sh):(23-sh) of X(from description) and place them in | |
556 | * higher doubleword of vD. | |
557 | */ | |
558 | tcg_gen_muli_i64(sh, sh, 0x0101010101010101ULL); | |
559 | tcg_gen_subfi_i64(result, 0x1011121314151617ULL, sh); | |
560 | set_avr64(VT, result, true); | |
561 | /* | |
562 | * Create bytes (24-sh):(32-sh) of X(from description) and place them in | |
563 | * lower doubleword of vD. | |
564 | */ | |
565 | tcg_gen_subfi_i64(result, 0x18191a1b1c1d1e1fULL, sh); | |
566 | set_avr64(VT, result, false); | |
567 | ||
568 | tcg_temp_free_i64(result); | |
569 | tcg_temp_free_i64(sh); | |
570 | tcg_temp_free(EA); | |
571 | } | |
572 | ||
4e6d0920 SB |
573 | /* |
574 | * vsl VRT,VRA,VRB - Vector Shift Left | |
575 | * | |
576 | * Shifting left 128 bit value of vA by value specified in bits 125-127 of vB. | |
577 | * Lowest 3 bits in each byte element of register vB must be identical or | |
578 | * result is undefined. | |
579 | */ | |
580 | static void trans_vsl(DisasContext *ctx) | |
581 | { | |
582 | int VT = rD(ctx->opcode); | |
583 | int VA = rA(ctx->opcode); | |
584 | int VB = rB(ctx->opcode); | |
585 | TCGv_i64 avrA = tcg_temp_new_i64(); | |
586 | TCGv_i64 avrB = tcg_temp_new_i64(); | |
587 | TCGv_i64 sh = tcg_temp_new_i64(); | |
588 | TCGv_i64 shifted = tcg_temp_new_i64(); | |
589 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
590 | ||
591 | /* Place bits 125-127 of vB in sh. */ | |
592 | get_avr64(avrB, VB, false); | |
593 | tcg_gen_andi_i64(sh, avrB, 0x07ULL); | |
594 | ||
595 | /* | |
596 | * Save highest sh bits of lower doubleword element of vA in variable | |
597 | * shifted and perform shift on lower doubleword. | |
598 | */ | |
599 | get_avr64(avrA, VA, false); | |
600 | tcg_gen_subfi_i64(tmp, 64, sh); | |
601 | tcg_gen_shr_i64(shifted, avrA, tmp); | |
602 | tcg_gen_andi_i64(shifted, shifted, 0x7fULL); | |
603 | tcg_gen_shl_i64(avrA, avrA, sh); | |
604 | set_avr64(VT, avrA, false); | |
605 | ||
606 | /* | |
607 | * Perform shift on higher doubleword element of vA and replace lowest | |
608 | * sh bits with shifted. | |
609 | */ | |
610 | get_avr64(avrA, VA, true); | |
611 | tcg_gen_shl_i64(avrA, avrA, sh); | |
612 | tcg_gen_or_i64(avrA, avrA, shifted); | |
613 | set_avr64(VT, avrA, true); | |
614 | ||
615 | tcg_temp_free_i64(avrA); | |
616 | tcg_temp_free_i64(avrB); | |
617 | tcg_temp_free_i64(sh); | |
618 | tcg_temp_free_i64(shifted); | |
619 | tcg_temp_free_i64(tmp); | |
620 | } | |
621 | ||
622 | /* | |
623 | * vsr VRT,VRA,VRB - Vector Shift Right | |
624 | * | |
625 | * Shifting right 128 bit value of vA by value specified in bits 125-127 of vB. | |
626 | * Lowest 3 bits in each byte element of register vB must be identical or | |
627 | * result is undefined. | |
628 | */ | |
629 | static void trans_vsr(DisasContext *ctx) | |
630 | { | |
631 | int VT = rD(ctx->opcode); | |
632 | int VA = rA(ctx->opcode); | |
633 | int VB = rB(ctx->opcode); | |
634 | TCGv_i64 avrA = tcg_temp_new_i64(); | |
635 | TCGv_i64 avrB = tcg_temp_new_i64(); | |
636 | TCGv_i64 sh = tcg_temp_new_i64(); | |
637 | TCGv_i64 shifted = tcg_temp_new_i64(); | |
638 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
639 | ||
640 | /* Place bits 125-127 of vB in sh. */ | |
641 | get_avr64(avrB, VB, false); | |
642 | tcg_gen_andi_i64(sh, avrB, 0x07ULL); | |
643 | ||
644 | /* | |
645 | * Save lowest sh bits of higher doubleword element of vA in variable | |
646 | * shifted and perform shift on higher doubleword. | |
647 | */ | |
648 | get_avr64(avrA, VA, true); | |
649 | tcg_gen_subfi_i64(tmp, 64, sh); | |
650 | tcg_gen_shl_i64(shifted, avrA, tmp); | |
651 | tcg_gen_andi_i64(shifted, shifted, 0xfe00000000000000ULL); | |
652 | tcg_gen_shr_i64(avrA, avrA, sh); | |
653 | set_avr64(VT, avrA, true); | |
654 | /* | |
655 | * Perform shift on lower doubleword element of vA and replace highest | |
656 | * sh bits with shifted. | |
657 | */ | |
658 | get_avr64(avrA, VA, false); | |
659 | tcg_gen_shr_i64(avrA, avrA, sh); | |
660 | tcg_gen_or_i64(avrA, avrA, shifted); | |
661 | set_avr64(VT, avrA, false); | |
662 | ||
663 | tcg_temp_free_i64(avrA); | |
664 | tcg_temp_free_i64(avrB); | |
665 | tcg_temp_free_i64(sh); | |
666 | tcg_temp_free_i64(shifted); | |
667 | tcg_temp_free_i64(tmp); | |
668 | } | |
669 | ||
083b3f01 SB |
670 | /* |
671 | * vgbbd VRT,VRB - Vector Gather Bits by Bytes by Doubleword | |
672 | * | |
673 | * All ith bits (i in range 1 to 8) of each byte of doubleword element in source | |
674 | * register are concatenated and placed into ith byte of appropriate doubleword | |
675 | * element in destination register. | |
676 | * | |
677 | * Following solution is done for both doubleword elements of source register | |
678 | * in parallel, in order to reduce the number of instructions needed(that's why | |
679 | * arrays are used): | |
680 | * First, both doubleword elements of source register vB are placed in | |
681 | * appropriate element of array avr. Bits are gathered in 2x8 iterations(2 for | |
682 | * loops). In first iteration bit 1 of byte 1, bit 2 of byte 2,... bit 8 of | |
683 | * byte 8 are in their final spots so avr[i], i={0,1} can be and-ed with | |
684 | * tcg_mask. For every following iteration, both avr[i] and tcg_mask variables | |
685 | * have to be shifted right for 7 and 8 places, respectively, in order to get | |
686 | * bit 1 of byte 2, bit 2 of byte 3.. bit 7 of byte 8 in their final spots so | |
687 | * shifted avr values(saved in tmp) can be and-ed with new value of tcg_mask... | |
688 | * After first 8 iteration(first loop), all the first bits are in their final | |
689 | * places, all second bits but second bit from eight byte are in their places... | |
690 | * only 1 eight bit from eight byte is in it's place). In second loop we do all | |
691 | * operations symmetrically, in order to get other half of bits in their final | |
692 | * spots. Results for first and second doubleword elements are saved in | |
693 | * result[0] and result[1] respectively. In the end those results are saved in | |
694 | * appropriate doubleword element of destination register vD. | |
695 | */ | |
696 | static void trans_vgbbd(DisasContext *ctx) | |
697 | { | |
698 | int VT = rD(ctx->opcode); | |
699 | int VB = rB(ctx->opcode); | |
700 | TCGv_i64 tmp = tcg_temp_new_i64(); | |
701 | uint64_t mask = 0x8040201008040201ULL; | |
702 | int i, j; | |
703 | ||
704 | TCGv_i64 result[2]; | |
705 | result[0] = tcg_temp_new_i64(); | |
706 | result[1] = tcg_temp_new_i64(); | |
707 | TCGv_i64 avr[2]; | |
708 | avr[0] = tcg_temp_new_i64(); | |
709 | avr[1] = tcg_temp_new_i64(); | |
710 | TCGv_i64 tcg_mask = tcg_temp_new_i64(); | |
711 | ||
712 | tcg_gen_movi_i64(tcg_mask, mask); | |
713 | for (j = 0; j < 2; j++) { | |
714 | get_avr64(avr[j], VB, j); | |
715 | tcg_gen_and_i64(result[j], avr[j], tcg_mask); | |
716 | } | |
717 | for (i = 1; i < 8; i++) { | |
718 | tcg_gen_movi_i64(tcg_mask, mask >> (i * 8)); | |
719 | for (j = 0; j < 2; j++) { | |
720 | tcg_gen_shri_i64(tmp, avr[j], i * 7); | |
721 | tcg_gen_and_i64(tmp, tmp, tcg_mask); | |
722 | tcg_gen_or_i64(result[j], result[j], tmp); | |
723 | } | |
724 | } | |
725 | for (i = 1; i < 8; i++) { | |
726 | tcg_gen_movi_i64(tcg_mask, mask << (i * 8)); | |
727 | for (j = 0; j < 2; j++) { | |
728 | tcg_gen_shli_i64(tmp, avr[j], i * 7); | |
729 | tcg_gen_and_i64(tmp, tmp, tcg_mask); | |
730 | tcg_gen_or_i64(result[j], result[j], tmp); | |
731 | } | |
732 | } | |
733 | for (j = 0; j < 2; j++) { | |
734 | set_avr64(VT, result[j], j); | |
735 | } | |
736 | ||
737 | tcg_temp_free_i64(tmp); | |
738 | tcg_temp_free_i64(tcg_mask); | |
739 | tcg_temp_free_i64(result[0]); | |
740 | tcg_temp_free_i64(result[1]); | |
741 | tcg_temp_free_i64(avr[0]); | |
742 | tcg_temp_free_i64(avr[1]); | |
743 | } | |
744 | ||
1872588e SB |
745 | /* |
746 | * vclzw VRT,VRB - Vector Count Leading Zeros Word | |
747 | * | |
748 | * Counting the number of leading zero bits of each word element in source | |
749 | * register and placing result in appropriate word element of destination | |
750 | * register. | |
751 | */ | |
752 | static void trans_vclzw(DisasContext *ctx) | |
753 | { | |
754 | int VT = rD(ctx->opcode); | |
755 | int VB = rB(ctx->opcode); | |
756 | TCGv_i32 tmp = tcg_temp_new_i32(); | |
757 | int i; | |
758 | ||
759 | /* Perform count for every word element using tcg_gen_clzi_i32. */ | |
760 | for (i = 0; i < 4; i++) { | |
761 | tcg_gen_ld_i32(tmp, cpu_env, | |
762 | offsetof(CPUPPCState, vsr[32 + VB].u64[0]) + i * 4); | |
763 | tcg_gen_clzi_i32(tmp, tmp, 32); | |
764 | tcg_gen_st_i32(tmp, cpu_env, | |
765 | offsetof(CPUPPCState, vsr[32 + VT].u64[0]) + i * 4); | |
766 | } | |
767 | ||
768 | tcg_temp_free_i32(tmp); | |
769 | } | |
770 | ||
b8313f0d SB |
771 | /* |
772 | * vclzd VRT,VRB - Vector Count Leading Zeros Doubleword | |
773 | * | |
774 | * Counting the number of leading zero bits of each doubleword element in source | |
775 | * register and placing result in appropriate doubleword element of destination | |
776 | * register. | |
777 | */ | |
778 | static void trans_vclzd(DisasContext *ctx) | |
779 | { | |
780 | int VT = rD(ctx->opcode); | |
781 | int VB = rB(ctx->opcode); | |
782 | TCGv_i64 avr = tcg_temp_new_i64(); | |
783 | ||
784 | /* high doubleword */ | |
785 | get_avr64(avr, VB, true); | |
786 | tcg_gen_clzi_i64(avr, avr, 64); | |
787 | set_avr64(VT, avr, true); | |
788 | ||
789 | /* low doubleword */ | |
790 | get_avr64(avr, VB, false); | |
791 | tcg_gen_clzi_i64(avr, avr, 64); | |
792 | set_avr64(VT, avr, false); | |
793 | ||
794 | tcg_temp_free_i64(avr); | |
795 | } | |
796 | ||
0304af89 BH |
797 | GEN_VXFORM(vmuloub, 4, 0); |
798 | GEN_VXFORM(vmulouh, 4, 1); | |
799 | GEN_VXFORM(vmulouw, 4, 2); | |
800 | GEN_VXFORM(vmuluwm, 4, 2); | |
801 | GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, | |
802 | vmuluwm, PPC_NONE, PPC2_ALTIVEC_207) | |
803 | GEN_VXFORM(vmulosb, 4, 4); | |
804 | GEN_VXFORM(vmulosh, 4, 5); | |
805 | GEN_VXFORM(vmulosw, 4, 6); | |
806 | GEN_VXFORM(vmuleub, 4, 8); | |
807 | GEN_VXFORM(vmuleuh, 4, 9); | |
808 | GEN_VXFORM(vmuleuw, 4, 10); | |
809 | GEN_VXFORM(vmulesb, 4, 12); | |
810 | GEN_VXFORM(vmulesh, 4, 13); | |
811 | GEN_VXFORM(vmulesw, 4, 14); | |
571fbe6c RH |
812 | GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4); |
813 | GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5); | |
814 | GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6); | |
09a245e1 BR |
815 | GEN_VXFORM(vrlwnm, 2, 6); |
816 | GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \ | |
817 | vrlwnm, PPC_NONE, PPC2_ISA300) | |
571fbe6c RH |
818 | GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23); |
819 | GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8); | |
820 | GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9); | |
821 | GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10); | |
822 | GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27); | |
823 | GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12); | |
824 | GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13); | |
825 | GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14); | |
826 | GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15); | |
4004c1db | 827 | GEN_VXFORM(vsrv, 2, 28); |
5644a175 | 828 | GEN_VXFORM(vslv, 2, 29); |
0304af89 BH |
829 | GEN_VXFORM(vslo, 6, 16); |
830 | GEN_VXFORM(vsro, 6, 17); | |
831 | GEN_VXFORM(vaddcuw, 0, 6); | |
832 | GEN_VXFORM(vsubcuw, 0, 22); | |
fb11ae7d RH |
833 | |
834 | #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ | |
835 | static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ | |
836 | TCGv_vec sat, TCGv_vec a, \ | |
837 | TCGv_vec b) \ | |
838 | { \ | |
839 | TCGv_vec x = tcg_temp_new_vec_matching(t); \ | |
840 | glue(glue(tcg_gen_, NORM), _vec)(VECE, x, a, b); \ | |
841 | glue(glue(tcg_gen_, SAT), _vec)(VECE, t, a, b); \ | |
842 | tcg_gen_cmp_vec(TCG_COND_NE, VECE, x, x, t); \ | |
843 | tcg_gen_or_vec(VECE, sat, sat, x); \ | |
844 | tcg_temp_free_vec(x); \ | |
845 | } \ | |
846 | static void glue(gen_, NAME)(DisasContext *ctx) \ | |
847 | { \ | |
53229a77 RH |
848 | static const TCGOpcode vecop_list[] = { \ |
849 | glue(glue(INDEX_op_, NORM), _vec), \ | |
850 | glue(glue(INDEX_op_, SAT), _vec), \ | |
851 | INDEX_op_cmp_vec, 0 \ | |
852 | }; \ | |
fb11ae7d RH |
853 | static const GVecGen4 g = { \ |
854 | .fniv = glue(glue(gen_, NAME), _vec), \ | |
855 | .fno = glue(gen_helper_, NAME), \ | |
53229a77 | 856 | .opt_opc = vecop_list, \ |
fb11ae7d RH |
857 | .write_aofs = true, \ |
858 | .vece = VECE, \ | |
859 | }; \ | |
860 | if (unlikely(!ctx->altivec_enabled)) { \ | |
861 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
862 | return; \ | |
863 | } \ | |
c82a8a85 | 864 | tcg_gen_gvec_4(avr_full_offset(rD(ctx->opcode)), \ |
fb11ae7d | 865 | offsetof(CPUPPCState, vscr_sat), \ |
c82a8a85 MCA |
866 | avr_full_offset(rA(ctx->opcode)), \ |
867 | avr_full_offset(rB(ctx->opcode)), \ | |
fb11ae7d RH |
868 | 16, 16, &g); \ |
869 | } | |
870 | ||
871 | GEN_VXFORM_SAT(vaddubs, MO_8, add, usadd, 0, 8); | |
37ad52ba VH |
872 | GEN_VXFORM_DUAL_EXT(vaddubs, PPC_ALTIVEC, PPC_NONE, 0, \ |
873 | vmul10uq, PPC_NONE, PPC2_ISA300, 0x0000F800) | |
fb11ae7d | 874 | GEN_VXFORM_SAT(vadduhs, MO_16, add, usadd, 0, 9); |
37ad52ba VH |
875 | GEN_VXFORM_DUAL(vadduhs, PPC_ALTIVEC, PPC_NONE, \ |
876 | vmul10euq, PPC_NONE, PPC2_ISA300) | |
fb11ae7d RH |
877 | GEN_VXFORM_SAT(vadduws, MO_32, add, usadd, 0, 10); |
878 | GEN_VXFORM_SAT(vaddsbs, MO_8, add, ssadd, 0, 12); | |
879 | GEN_VXFORM_SAT(vaddshs, MO_16, add, ssadd, 0, 13); | |
880 | GEN_VXFORM_SAT(vaddsws, MO_32, add, ssadd, 0, 14); | |
881 | GEN_VXFORM_SAT(vsububs, MO_8, sub, ussub, 0, 24); | |
882 | GEN_VXFORM_SAT(vsubuhs, MO_16, sub, ussub, 0, 25); | |
883 | GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26); | |
884 | GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28); | |
885 | GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29); | |
886 | GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30); | |
0304af89 BH |
887 | GEN_VXFORM(vadduqm, 0, 4); |
888 | GEN_VXFORM(vaddcuq, 0, 5); | |
889 | GEN_VXFORM3(vaddeuqm, 30, 0); | |
890 | GEN_VXFORM3(vaddecuq, 30, 0); | |
891 | GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
892 | vaddecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
893 | GEN_VXFORM(vsubuqm, 0, 20); | |
894 | GEN_VXFORM(vsubcuq, 0, 21); | |
895 | GEN_VXFORM3(vsubeuqm, 31, 0); | |
896 | GEN_VXFORM3(vsubecuq, 31, 0); | |
897 | GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ | |
898 | vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) | |
899 | GEN_VXFORM(vrlb, 2, 0); | |
900 | GEN_VXFORM(vrlh, 2, 1); | |
901 | GEN_VXFORM(vrlw, 2, 2); | |
3e00884f GS |
902 | GEN_VXFORM(vrlwmi, 2, 2); |
903 | GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ | |
904 | vrlwmi, PPC_NONE, PPC2_ISA300) | |
0304af89 | 905 | GEN_VXFORM(vrld, 2, 3); |
3e00884f GS |
906 | GEN_VXFORM(vrldmi, 2, 3); |
907 | GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ | |
908 | vrldmi, PPC_NONE, PPC2_ISA300) | |
4e6d0920 | 909 | GEN_VXFORM_TRANS(vsl, 2, 7); |
09a245e1 BR |
910 | GEN_VXFORM(vrldnm, 2, 7); |
911 | GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \ | |
912 | vrldnm, PPC_NONE, PPC2_ISA300) | |
4e6d0920 | 913 | GEN_VXFORM_TRANS(vsr, 2, 11); |
0304af89 BH |
914 | GEN_VXFORM_ENV(vpkuhum, 7, 0); |
915 | GEN_VXFORM_ENV(vpkuwum, 7, 1); | |
916 | GEN_VXFORM_ENV(vpkudum, 7, 17); | |
917 | GEN_VXFORM_ENV(vpkuhus, 7, 2); | |
918 | GEN_VXFORM_ENV(vpkuwus, 7, 3); | |
919 | GEN_VXFORM_ENV(vpkudus, 7, 19); | |
920 | GEN_VXFORM_ENV(vpkshus, 7, 4); | |
921 | GEN_VXFORM_ENV(vpkswus, 7, 5); | |
922 | GEN_VXFORM_ENV(vpksdus, 7, 21); | |
923 | GEN_VXFORM_ENV(vpkshss, 7, 6); | |
924 | GEN_VXFORM_ENV(vpkswss, 7, 7); | |
925 | GEN_VXFORM_ENV(vpksdss, 7, 23); | |
926 | GEN_VXFORM(vpkpx, 7, 12); | |
927 | GEN_VXFORM_ENV(vsum4ubs, 4, 24); | |
928 | GEN_VXFORM_ENV(vsum4sbs, 4, 28); | |
929 | GEN_VXFORM_ENV(vsum4shs, 4, 25); | |
930 | GEN_VXFORM_ENV(vsum2sws, 4, 26); | |
931 | GEN_VXFORM_ENV(vsumsws, 4, 30); | |
932 | GEN_VXFORM_ENV(vaddfp, 5, 0); | |
933 | GEN_VXFORM_ENV(vsubfp, 5, 1); | |
934 | GEN_VXFORM_ENV(vmaxfp, 5, 16); | |
935 | GEN_VXFORM_ENV(vminfp, 5, 17); | |
60caf221 AK |
936 | GEN_VXFORM_HETRO(vextublx, 6, 24) |
937 | GEN_VXFORM_HETRO(vextuhlx, 6, 25) | |
938 | GEN_VXFORM_HETRO(vextuwlx, 6, 26) | |
939 | GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207, | |
940 | vextuwlx, PPC_NONE, PPC2_ISA300) | |
941 | GEN_VXFORM_HETRO(vextubrx, 6, 28) | |
942 | GEN_VXFORM_HETRO(vextuhrx, 6, 29) | |
943 | GEN_VXFORM_HETRO(vextuwrx, 6, 30) | |
1cc79269 SB |
944 | GEN_VXFORM_TRANS(lvsl, 6, 31) |
945 | GEN_VXFORM_TRANS(lvsr, 6, 32) | |
60caf221 AK |
946 | GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \ |
947 | vextuwrx, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
948 | |
949 | #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \ | |
950 | static void glue(gen_, name)(DisasContext *ctx) \ | |
951 | { \ | |
952 | TCGv_ptr ra, rb, rd; \ | |
953 | if (unlikely(!ctx->altivec_enabled)) { \ | |
954 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
955 | return; \ | |
956 | } \ | |
957 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
958 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
959 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
960 | gen_helper_##opname(cpu_env, rd, ra, rb); \ | |
961 | tcg_temp_free_ptr(ra); \ | |
962 | tcg_temp_free_ptr(rb); \ | |
963 | tcg_temp_free_ptr(rd); \ | |
964 | } | |
965 | ||
966 | #define GEN_VXRFORM(name, opc2, opc3) \ | |
967 | GEN_VXRFORM1(name, name, #name, opc2, opc3) \ | |
968 | GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4))) | |
969 | ||
970 | /* | |
971 | * Support for Altivec instructions that use bit 31 (Rc) as an opcode | |
972 | * bit but also use bit 21 as an actual Rc bit. In general, thse pairs | |
973 | * come from different versions of the ISA, so we must also support a | |
974 | * pair of flags for each instruction. | |
975 | */ | |
976 | #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \ | |
977 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
978 | { \ | |
979 | if ((Rc(ctx->opcode) == 0) && \ | |
980 | ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \ | |
981 | if (Rc21(ctx->opcode) == 0) { \ | |
982 | gen_##name0(ctx); \ | |
983 | } else { \ | |
984 | gen_##name0##_(ctx); \ | |
985 | } \ | |
986 | } else if ((Rc(ctx->opcode) == 1) && \ | |
987 | ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \ | |
988 | if (Rc21(ctx->opcode) == 0) { \ | |
989 | gen_##name1(ctx); \ | |
990 | } else { \ | |
991 | gen_##name1##_(ctx); \ | |
992 | } \ | |
993 | } else { \ | |
994 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ | |
995 | } \ | |
996 | } | |
997 | ||
998 | GEN_VXRFORM(vcmpequb, 3, 0) | |
999 | GEN_VXRFORM(vcmpequh, 3, 1) | |
1000 | GEN_VXRFORM(vcmpequw, 3, 2) | |
1001 | GEN_VXRFORM(vcmpequd, 3, 3) | |
f7cc8466 SB |
1002 | GEN_VXRFORM(vcmpnezb, 3, 4) |
1003 | GEN_VXRFORM(vcmpnezh, 3, 5) | |
1004 | GEN_VXRFORM(vcmpnezw, 3, 6) | |
0304af89 BH |
1005 | GEN_VXRFORM(vcmpgtsb, 3, 12) |
1006 | GEN_VXRFORM(vcmpgtsh, 3, 13) | |
1007 | GEN_VXRFORM(vcmpgtsw, 3, 14) | |
1008 | GEN_VXRFORM(vcmpgtsd, 3, 15) | |
1009 | GEN_VXRFORM(vcmpgtub, 3, 8) | |
1010 | GEN_VXRFORM(vcmpgtuh, 3, 9) | |
1011 | GEN_VXRFORM(vcmpgtuw, 3, 10) | |
1012 | GEN_VXRFORM(vcmpgtud, 3, 11) | |
1013 | GEN_VXRFORM(vcmpeqfp, 3, 3) | |
1014 | GEN_VXRFORM(vcmpgefp, 3, 7) | |
1015 | GEN_VXRFORM(vcmpgtfp, 3, 11) | |
1016 | GEN_VXRFORM(vcmpbfp, 3, 15) | |
0fa59364 RS |
1017 | GEN_VXRFORM(vcmpneb, 3, 0) |
1018 | GEN_VXRFORM(vcmpneh, 3, 1) | |
1019 | GEN_VXRFORM(vcmpnew, 3, 2) | |
0304af89 | 1020 | |
2020b67d | 1021 | GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \ |
0fa59364 | 1022 | vcmpneb, PPC_NONE, PPC2_ISA300) |
2020b67d | 1023 | GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \ |
0fa59364 | 1024 | vcmpneh, PPC_NONE, PPC2_ISA300) |
2020b67d | 1025 | GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \ |
0fa59364 | 1026 | vcmpnew, PPC_NONE, PPC2_ISA300) |
0304af89 BH |
1027 | GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \ |
1028 | vcmpequd, PPC_NONE, PPC2_ALTIVEC_207) | |
1029 | GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \ | |
1030 | vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207) | |
1031 | GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \ | |
1032 | vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207) | |
1033 | ||
471ff3d0 | 1034 | #define GEN_VXFORM_DUPI(name, tcg_op, opc2, opc3) \ |
0304af89 BH |
1035 | static void glue(gen_, name)(DisasContext *ctx) \ |
1036 | { \ | |
471ff3d0 | 1037 | int simm; \ |
0304af89 BH |
1038 | if (unlikely(!ctx->altivec_enabled)) { \ |
1039 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1040 | return; \ | |
1041 | } \ | |
471ff3d0 | 1042 | simm = SIMM5(ctx->opcode); \ |
c82a8a85 | 1043 | tcg_op(avr_full_offset(rD(ctx->opcode)), 16, 16, simm); \ |
0304af89 BH |
1044 | } |
1045 | ||
471ff3d0 RH |
1046 | GEN_VXFORM_DUPI(vspltisb, tcg_gen_gvec_dup8i, 6, 12); |
1047 | GEN_VXFORM_DUPI(vspltish, tcg_gen_gvec_dup16i, 6, 13); | |
1048 | GEN_VXFORM_DUPI(vspltisw, tcg_gen_gvec_dup32i, 6, 14); | |
0304af89 BH |
1049 | |
1050 | #define GEN_VXFORM_NOA(name, opc2, opc3) \ | |
32553866 | 1051 | static void glue(gen_, name)(DisasContext *ctx) \ |
0304af89 BH |
1052 | { \ |
1053 | TCGv_ptr rb, rd; \ | |
1054 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1055 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1056 | return; \ | |
1057 | } \ | |
1058 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1059 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
32553866 | 1060 | gen_helper_##name(rd, rb); \ |
0304af89 | 1061 | tcg_temp_free_ptr(rb); \ |
32553866 | 1062 | tcg_temp_free_ptr(rd); \ |
0304af89 BH |
1063 | } |
1064 | ||
1065 | #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \ | |
1066 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1067 | { \ | |
1068 | TCGv_ptr rb, rd; \ | |
1069 | \ | |
1070 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1071 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1072 | return; \ | |
1073 | } \ | |
1074 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1075 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1076 | gen_helper_##name(cpu_env, rd, rb); \ | |
1077 | tcg_temp_free_ptr(rb); \ | |
1078 | tcg_temp_free_ptr(rd); \ | |
1079 | } | |
1080 | ||
a5ad8fbf RS |
1081 | #define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \ |
1082 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1083 | { \ | |
1084 | TCGv_ptr rb, rd; \ | |
1085 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1086 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1087 | return; \ | |
1088 | } \ | |
1089 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1090 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1091 | gen_helper_##name(rd, rb); \ | |
1092 | tcg_temp_free_ptr(rb); \ | |
1093 | tcg_temp_free_ptr(rd); \ | |
1094 | } | |
1095 | ||
4879538c RS |
1096 | #define GEN_VXFORM_NOA_3(name, opc2, opc3, opc4) \ |
1097 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1098 | { \ | |
1099 | TCGv_ptr rb; \ | |
1100 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1101 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1102 | return; \ | |
1103 | } \ | |
1104 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1105 | gen_helper_##name(cpu_gpr[rD(ctx->opcode)], rb); \ | |
1106 | tcg_temp_free_ptr(rb); \ | |
1107 | } | |
0304af89 BH |
1108 | GEN_VXFORM_NOA(vupkhsb, 7, 8); |
1109 | GEN_VXFORM_NOA(vupkhsh, 7, 9); | |
1110 | GEN_VXFORM_NOA(vupkhsw, 7, 25); | |
1111 | GEN_VXFORM_NOA(vupklsb, 7, 10); | |
1112 | GEN_VXFORM_NOA(vupklsh, 7, 11); | |
1113 | GEN_VXFORM_NOA(vupklsw, 7, 27); | |
1114 | GEN_VXFORM_NOA(vupkhpx, 7, 13); | |
1115 | GEN_VXFORM_NOA(vupklpx, 7, 15); | |
1116 | GEN_VXFORM_NOA_ENV(vrefp, 5, 4); | |
1117 | GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5); | |
1118 | GEN_VXFORM_NOA_ENV(vexptefp, 5, 6); | |
1119 | GEN_VXFORM_NOA_ENV(vlogefp, 5, 7); | |
1120 | GEN_VXFORM_NOA_ENV(vrfim, 5, 11); | |
1121 | GEN_VXFORM_NOA_ENV(vrfin, 5, 8); | |
1122 | GEN_VXFORM_NOA_ENV(vrfip, 5, 10); | |
1123 | GEN_VXFORM_NOA_ENV(vrfiz, 5, 9); | |
5c69452c AK |
1124 | GEN_VXFORM_NOA(vprtybw, 1, 24); |
1125 | GEN_VXFORM_NOA(vprtybd, 1, 24); | |
1126 | GEN_VXFORM_NOA(vprtybq, 1, 24); | |
0304af89 | 1127 | |
0f6a6d5d RH |
1128 | static void gen_vsplt(DisasContext *ctx, int vece) |
1129 | { | |
1130 | int uimm, dofs, bofs; | |
1131 | ||
1132 | if (unlikely(!ctx->altivec_enabled)) { | |
1133 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
1134 | return; | |
0304af89 BH |
1135 | } |
1136 | ||
0f6a6d5d | 1137 | uimm = UIMM5(ctx->opcode); |
c82a8a85 MCA |
1138 | bofs = avr_full_offset(rB(ctx->opcode)); |
1139 | dofs = avr_full_offset(rD(ctx->opcode)); | |
0f6a6d5d RH |
1140 | |
1141 | /* Experimental testing shows that hardware masks the immediate. */ | |
1142 | bofs += (uimm << vece) & 15; | |
1143 | #ifndef HOST_WORDS_BIGENDIAN | |
1144 | bofs ^= 15; | |
1145 | bofs &= ~((1 << vece) - 1); | |
1146 | #endif | |
1147 | ||
1148 | tcg_gen_gvec_dup_mem(vece, dofs, bofs, 16, 16); | |
1149 | } | |
1150 | ||
1151 | #define GEN_VXFORM_VSPLT(name, vece, opc2, opc3) \ | |
1152 | static void glue(gen_, name)(DisasContext *ctx) { gen_vsplt(ctx, vece); } | |
1153 | ||
0304af89 BH |
1154 | #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \ |
1155 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1156 | { \ | |
1157 | TCGv_ptr rb, rd; \ | |
1158 | TCGv_i32 uimm; \ | |
1159 | \ | |
1160 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1161 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1162 | return; \ | |
1163 | } \ | |
1164 | uimm = tcg_const_i32(UIMM5(ctx->opcode)); \ | |
1165 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1166 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1167 | gen_helper_##name(cpu_env, rd, rb, uimm); \ | |
1168 | tcg_temp_free_i32(uimm); \ | |
1169 | tcg_temp_free_ptr(rb); \ | |
1170 | tcg_temp_free_ptr(rd); \ | |
1171 | } | |
1172 | ||
e7b1e06f RS |
1173 | #define GEN_VXFORM_UIMM_SPLAT(name, opc2, opc3, splat_max) \ |
1174 | static void glue(gen_, name)(DisasContext *ctx) \ | |
1175 | { \ | |
1176 | TCGv_ptr rb, rd; \ | |
1177 | uint8_t uimm = UIMM4(ctx->opcode); \ | |
c4a18dbf | 1178 | TCGv_i32 t0; \ |
e7b1e06f RS |
1179 | if (unlikely(!ctx->altivec_enabled)) { \ |
1180 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1181 | return; \ | |
1182 | } \ | |
1183 | if (uimm > splat_max) { \ | |
1184 | uimm = 0; \ | |
1185 | } \ | |
c4a18dbf | 1186 | t0 = tcg_temp_new_i32(); \ |
e7b1e06f RS |
1187 | tcg_gen_movi_i32(t0, uimm); \ |
1188 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1189 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1190 | gen_helper_##name(rd, rb, t0); \ | |
1191 | tcg_temp_free_i32(t0); \ | |
1192 | tcg_temp_free_ptr(rb); \ | |
1193 | tcg_temp_free_ptr(rd); \ | |
1194 | } | |
1195 | ||
0f6a6d5d RH |
1196 | GEN_VXFORM_VSPLT(vspltb, MO_8, 6, 8); |
1197 | GEN_VXFORM_VSPLT(vsplth, MO_16, 6, 9); | |
1198 | GEN_VXFORM_VSPLT(vspltw, MO_32, 6, 10); | |
b5d569a1 RS |
1199 | GEN_VXFORM_UIMM_SPLAT(vextractub, 6, 8, 15); |
1200 | GEN_VXFORM_UIMM_SPLAT(vextractuh, 6, 9, 14); | |
1201 | GEN_VXFORM_UIMM_SPLAT(vextractuw, 6, 10, 12); | |
1202 | GEN_VXFORM_UIMM_SPLAT(vextractd, 6, 11, 8); | |
e7b1e06f RS |
1203 | GEN_VXFORM_UIMM_SPLAT(vinsertb, 6, 12, 15); |
1204 | GEN_VXFORM_UIMM_SPLAT(vinserth, 6, 13, 14); | |
1205 | GEN_VXFORM_UIMM_SPLAT(vinsertw, 6, 14, 12); | |
1206 | GEN_VXFORM_UIMM_SPLAT(vinsertd, 6, 15, 8); | |
0304af89 BH |
1207 | GEN_VXFORM_UIMM_ENV(vcfux, 5, 12); |
1208 | GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13); | |
1209 | GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14); | |
1210 | GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15); | |
2020b67d ND |
1211 | GEN_VXFORM_DUAL(vspltb, PPC_ALTIVEC, PPC_NONE, |
1212 | vextractub, PPC_NONE, PPC2_ISA300); | |
1213 | GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE, | |
1214 | vextractuh, PPC_NONE, PPC2_ISA300); | |
1215 | GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE, | |
1216 | vextractuw, PPC_NONE, PPC2_ISA300); | |
1217 | GEN_VXFORM_DUAL(vspltisb, PPC_ALTIVEC, PPC_NONE, | |
1218 | vinsertb, PPC_NONE, PPC2_ISA300); | |
1219 | GEN_VXFORM_DUAL(vspltish, PPC_ALTIVEC, PPC_NONE, | |
1220 | vinserth, PPC_NONE, PPC2_ISA300); | |
1221 | GEN_VXFORM_DUAL(vspltisw, PPC_ALTIVEC, PPC_NONE, | |
1222 | vinsertw, PPC_NONE, PPC2_ISA300); | |
0304af89 BH |
1223 | |
1224 | static void gen_vsldoi(DisasContext *ctx) | |
1225 | { | |
1226 | TCGv_ptr ra, rb, rd; | |
1227 | TCGv_i32 sh; | |
1228 | if (unlikely(!ctx->altivec_enabled)) { | |
1229 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
1230 | return; | |
1231 | } | |
1232 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
1233 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
1234 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
1235 | sh = tcg_const_i32(VSH(ctx->opcode)); | |
32553866 | 1236 | gen_helper_vsldoi(rd, ra, rb, sh); |
0304af89 BH |
1237 | tcg_temp_free_ptr(ra); |
1238 | tcg_temp_free_ptr(rb); | |
1239 | tcg_temp_free_ptr(rd); | |
1240 | tcg_temp_free_i32(sh); | |
1241 | } | |
1242 | ||
1243 | #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ | |
1244 | static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ | |
1245 | { \ | |
1246 | TCGv_ptr ra, rb, rc, rd; \ | |
1247 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1248 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1249 | return; \ | |
1250 | } \ | |
1251 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
1252 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1253 | rc = gen_avr_ptr(rC(ctx->opcode)); \ | |
1254 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1255 | if (Rc(ctx->opcode)) { \ | |
1256 | gen_helper_##name1(cpu_env, rd, ra, rb, rc); \ | |
1257 | } else { \ | |
1258 | gen_helper_##name0(cpu_env, rd, ra, rb, rc); \ | |
1259 | } \ | |
1260 | tcg_temp_free_ptr(ra); \ | |
1261 | tcg_temp_free_ptr(rb); \ | |
1262 | tcg_temp_free_ptr(rc); \ | |
1263 | tcg_temp_free_ptr(rd); \ | |
1264 | } | |
1265 | ||
1266 | GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) | |
1267 | ||
1268 | static void gen_vmladduhm(DisasContext *ctx) | |
1269 | { | |
1270 | TCGv_ptr ra, rb, rc, rd; | |
1271 | if (unlikely(!ctx->altivec_enabled)) { | |
1272 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
1273 | return; | |
1274 | } | |
1275 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
1276 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
1277 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
1278 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
1279 | gen_helper_vmladduhm(rd, ra, rb, rc); | |
1280 | tcg_temp_free_ptr(ra); | |
1281 | tcg_temp_free_ptr(rb); | |
1282 | tcg_temp_free_ptr(rc); | |
1283 | tcg_temp_free_ptr(rd); | |
1284 | } | |
1285 | ||
ab045436 RS |
1286 | static void gen_vpermr(DisasContext *ctx) |
1287 | { | |
1288 | TCGv_ptr ra, rb, rc, rd; | |
1289 | if (unlikely(!ctx->altivec_enabled)) { | |
1290 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
1291 | return; | |
1292 | } | |
1293 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
1294 | rb = gen_avr_ptr(rB(ctx->opcode)); | |
1295 | rc = gen_avr_ptr(rC(ctx->opcode)); | |
1296 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
1297 | gen_helper_vpermr(cpu_env, rd, ra, rb, rc); | |
1298 | tcg_temp_free_ptr(ra); | |
1299 | tcg_temp_free_ptr(rb); | |
1300 | tcg_temp_free_ptr(rc); | |
1301 | tcg_temp_free_ptr(rd); | |
1302 | } | |
1303 | ||
0304af89 BH |
1304 | GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18) |
1305 | GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19) | |
1306 | GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20) | |
1307 | GEN_VAFORM_PAIRED(vsel, vperm, 21) | |
1308 | GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23) | |
1309 | ||
1310 | GEN_VXFORM_NOA(vclzb, 1, 28) | |
1311 | GEN_VXFORM_NOA(vclzh, 1, 29) | |
1872588e | 1312 | GEN_VXFORM_TRANS(vclzw, 1, 30) |
b8313f0d | 1313 | GEN_VXFORM_TRANS(vclzd, 1, 31) |
cc8b6e76 ND |
1314 | GEN_VXFORM_NOA_2(vnegw, 1, 24, 6) |
1315 | GEN_VXFORM_NOA_2(vnegd, 1, 24, 7) | |
125a9b23 ND |
1316 | GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16) |
1317 | GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17) | |
1318 | GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24) | |
1319 | GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25) | |
1320 | GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26) | |
a5ad8fbf RS |
1321 | GEN_VXFORM_NOA_2(vctzb, 1, 24, 28) |
1322 | GEN_VXFORM_NOA_2(vctzh, 1, 24, 29) | |
1323 | GEN_VXFORM_NOA_2(vctzw, 1, 24, 30) | |
1324 | GEN_VXFORM_NOA_2(vctzd, 1, 24, 31) | |
4879538c RS |
1325 | GEN_VXFORM_NOA_3(vclzlsbb, 1, 24, 0) |
1326 | GEN_VXFORM_NOA_3(vctzlsbb, 1, 24, 1) | |
0304af89 BH |
1327 | GEN_VXFORM_NOA(vpopcntb, 1, 28) |
1328 | GEN_VXFORM_NOA(vpopcnth, 1, 29) | |
1329 | GEN_VXFORM_NOA(vpopcntw, 1, 30) | |
1330 | GEN_VXFORM_NOA(vpopcntd, 1, 31) | |
1331 | GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \ | |
1332 | vpopcntb, PPC_NONE, PPC2_ALTIVEC_207) | |
1333 | GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \ | |
1334 | vpopcnth, PPC_NONE, PPC2_ALTIVEC_207) | |
1335 | GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \ | |
1336 | vpopcntw, PPC_NONE, PPC2_ALTIVEC_207) | |
1337 | GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \ | |
1338 | vpopcntd, PPC_NONE, PPC2_ALTIVEC_207) | |
01fe9a47 | 1339 | GEN_VXFORM(vbpermd, 6, 23); |
0304af89 | 1340 | GEN_VXFORM(vbpermq, 6, 21); |
083b3f01 | 1341 | GEN_VXFORM_TRANS(vgbbd, 6, 20); |
0304af89 BH |
1342 | GEN_VXFORM(vpmsumb, 4, 16) |
1343 | GEN_VXFORM(vpmsumh, 4, 17) | |
1344 | GEN_VXFORM(vpmsumw, 4, 18) | |
1345 | GEN_VXFORM(vpmsumd, 4, 19) | |
1346 | ||
1347 | #define GEN_BCD(op) \ | |
1348 | static void gen_##op(DisasContext *ctx) \ | |
1349 | { \ | |
1350 | TCGv_ptr ra, rb, rd; \ | |
1351 | TCGv_i32 ps; \ | |
1352 | \ | |
1353 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1354 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1355 | return; \ | |
1356 | } \ | |
1357 | \ | |
1358 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
1359 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1360 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1361 | \ | |
1362 | ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ | |
1363 | \ | |
1364 | gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \ | |
1365 | \ | |
1366 | tcg_temp_free_ptr(ra); \ | |
1367 | tcg_temp_free_ptr(rb); \ | |
1368 | tcg_temp_free_ptr(rd); \ | |
1369 | tcg_temp_free_i32(ps); \ | |
1370 | } | |
1371 | ||
b8155872 JRZ |
1372 | #define GEN_BCD2(op) \ |
1373 | static void gen_##op(DisasContext *ctx) \ | |
1374 | { \ | |
1375 | TCGv_ptr rd, rb; \ | |
1376 | TCGv_i32 ps; \ | |
1377 | \ | |
1378 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1379 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1380 | return; \ | |
1381 | } \ | |
1382 | \ | |
1383 | rb = gen_avr_ptr(rB(ctx->opcode)); \ | |
1384 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1385 | \ | |
1386 | ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \ | |
1387 | \ | |
1388 | gen_helper_##op(cpu_crf[6], rd, rb, ps); \ | |
1389 | \ | |
1390 | tcg_temp_free_ptr(rb); \ | |
1391 | tcg_temp_free_ptr(rd); \ | |
1392 | tcg_temp_free_i32(ps); \ | |
1393 | } | |
1394 | ||
0304af89 BH |
1395 | GEN_BCD(bcdadd) |
1396 | GEN_BCD(bcdsub) | |
b8155872 | 1397 | GEN_BCD2(bcdcfn) |
e2106d73 | 1398 | GEN_BCD2(bcdctn) |
38f4cb04 | 1399 | GEN_BCD2(bcdcfz) |
0a890b31 | 1400 | GEN_BCD2(bcdctz) |
a406c058 | 1401 | GEN_BCD2(bcdcfsq) |
c85bc7dd | 1402 | GEN_BCD2(bcdctsq) |
466a3f9c | 1403 | GEN_BCD2(bcdsetsgn) |
c3025c3b | 1404 | GEN_BCD(bcdcpsgn); |
e04797f7 | 1405 | GEN_BCD(bcds); |
a49a95e9 | 1406 | GEN_BCD(bcdus); |
a54238ad | 1407 | GEN_BCD(bcdsr); |
31bc4d11 | 1408 | GEN_BCD(bcdtrunc); |
5c32e2e4 | 1409 | GEN_BCD(bcdutrunc); |
b8155872 JRZ |
1410 | |
1411 | static void gen_xpnd04_1(DisasContext *ctx) | |
1412 | { | |
1413 | switch (opc4(ctx->opcode)) { | |
c85bc7dd JRZ |
1414 | case 0: |
1415 | gen_bcdctsq(ctx); | |
1416 | break; | |
a406c058 JRZ |
1417 | case 2: |
1418 | gen_bcdcfsq(ctx); | |
1419 | break; | |
0a890b31 JRZ |
1420 | case 4: |
1421 | gen_bcdctz(ctx); | |
1422 | break; | |
e2106d73 JRZ |
1423 | case 5: |
1424 | gen_bcdctn(ctx); | |
1425 | break; | |
38f4cb04 JRZ |
1426 | case 6: |
1427 | gen_bcdcfz(ctx); | |
1428 | break; | |
b8155872 JRZ |
1429 | case 7: |
1430 | gen_bcdcfn(ctx); | |
1431 | break; | |
466a3f9c JRZ |
1432 | case 31: |
1433 | gen_bcdsetsgn(ctx); | |
1434 | break; | |
b8155872 JRZ |
1435 | default: |
1436 | gen_invalid(ctx); | |
1437 | break; | |
1438 | } | |
1439 | } | |
1440 | ||
1441 | static void gen_xpnd04_2(DisasContext *ctx) | |
1442 | { | |
1443 | switch (opc4(ctx->opcode)) { | |
c85bc7dd JRZ |
1444 | case 0: |
1445 | gen_bcdctsq(ctx); | |
1446 | break; | |
a406c058 JRZ |
1447 | case 2: |
1448 | gen_bcdcfsq(ctx); | |
1449 | break; | |
0a890b31 JRZ |
1450 | case 4: |
1451 | gen_bcdctz(ctx); | |
1452 | break; | |
38f4cb04 JRZ |
1453 | case 6: |
1454 | gen_bcdcfz(ctx); | |
1455 | break; | |
b8155872 JRZ |
1456 | case 7: |
1457 | gen_bcdcfn(ctx); | |
1458 | break; | |
466a3f9c JRZ |
1459 | case 31: |
1460 | gen_bcdsetsgn(ctx); | |
1461 | break; | |
b8155872 JRZ |
1462 | default: |
1463 | gen_invalid(ctx); | |
1464 | break; | |
1465 | } | |
1466 | } | |
1467 | ||
466a3f9c | 1468 | |
b8155872 JRZ |
1469 | GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \ |
1470 | xpnd04_1, PPC_NONE, PPC2_ISA300) | |
1471 | GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \ | |
1472 | xpnd04_2, PPC_NONE, PPC2_ISA300) | |
0304af89 BH |
1473 | |
1474 | GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \ | |
1475 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
1476 | GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \ | |
1477 | bcdadd, PPC_NONE, PPC2_ALTIVEC_207) | |
1478 | GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \ | |
1479 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
1480 | GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \ | |
1481 | bcdsub, PPC_NONE, PPC2_ALTIVEC_207) | |
c3025c3b JRZ |
1482 | GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \ |
1483 | bcdcpsgn, PPC_NONE, PPC2_ISA300) | |
e04797f7 JRZ |
1484 | GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \ |
1485 | bcds, PPC_NONE, PPC2_ISA300) | |
a49a95e9 JRZ |
1486 | GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \ |
1487 | bcdus, PPC_NONE, PPC2_ISA300) | |
31bc4d11 JRZ |
1488 | GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \ |
1489 | bcdtrunc, PPC_NONE, PPC2_ISA300) | |
1490 | GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \ | |
1491 | bcdtrunc, PPC_NONE, PPC2_ISA300) | |
5c32e2e4 JRZ |
1492 | GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \ |
1493 | bcdutrunc, PPC_NONE, PPC2_ISA300) | |
1494 | ||
0304af89 BH |
1495 | |
1496 | static void gen_vsbox(DisasContext *ctx) | |
1497 | { | |
1498 | TCGv_ptr ra, rd; | |
1499 | if (unlikely(!ctx->altivec_enabled)) { | |
1500 | gen_exception(ctx, POWERPC_EXCP_VPU); | |
1501 | return; | |
1502 | } | |
1503 | ra = gen_avr_ptr(rA(ctx->opcode)); | |
1504 | rd = gen_avr_ptr(rD(ctx->opcode)); | |
1505 | gen_helper_vsbox(rd, ra); | |
1506 | tcg_temp_free_ptr(ra); | |
1507 | tcg_temp_free_ptr(rd); | |
1508 | } | |
1509 | ||
1510 | GEN_VXFORM(vcipher, 4, 20) | |
1511 | GEN_VXFORM(vcipherlast, 4, 20) | |
1512 | GEN_VXFORM(vncipher, 4, 21) | |
1513 | GEN_VXFORM(vncipherlast, 4, 21) | |
1514 | ||
1515 | GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207, | |
1516 | vcipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
1517 | GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207, | |
1518 | vncipherlast, PPC_NONE, PPC2_ALTIVEC_207) | |
1519 | ||
1520 | #define VSHASIGMA(op) \ | |
1521 | static void gen_##op(DisasContext *ctx) \ | |
1522 | { \ | |
1523 | TCGv_ptr ra, rd; \ | |
1524 | TCGv_i32 st_six; \ | |
1525 | if (unlikely(!ctx->altivec_enabled)) { \ | |
1526 | gen_exception(ctx, POWERPC_EXCP_VPU); \ | |
1527 | return; \ | |
1528 | } \ | |
1529 | ra = gen_avr_ptr(rA(ctx->opcode)); \ | |
1530 | rd = gen_avr_ptr(rD(ctx->opcode)); \ | |
1531 | st_six = tcg_const_i32(rB(ctx->opcode)); \ | |
1532 | gen_helper_##op(rd, ra, st_six); \ | |
1533 | tcg_temp_free_ptr(ra); \ | |
1534 | tcg_temp_free_ptr(rd); \ | |
1535 | tcg_temp_free_i32(st_six); \ | |
1536 | } | |
1537 | ||
1538 | VSHASIGMA(vshasigmaw) | |
1539 | VSHASIGMA(vshasigmad) | |
1540 | ||
1541 | GEN_VXFORM3(vpermxor, 22, 0xFF) | |
1542 | GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE, | |
1543 | vpermxor, PPC_NONE, PPC2_ALTIVEC_207) | |
1544 | ||
1545 | #undef GEN_VR_LDX | |
1546 | #undef GEN_VR_STX | |
1547 | #undef GEN_VR_LVE | |
1548 | #undef GEN_VR_STVE | |
1549 | ||
1550 | #undef GEN_VX_LOGICAL | |
1551 | #undef GEN_VX_LOGICAL_207 | |
1552 | #undef GEN_VXFORM | |
1553 | #undef GEN_VXFORM_207 | |
1554 | #undef GEN_VXFORM_DUAL | |
1555 | #undef GEN_VXRFORM_DUAL | |
1556 | #undef GEN_VXRFORM1 | |
1557 | #undef GEN_VXRFORM | |
471ff3d0 | 1558 | #undef GEN_VXFORM_DUPI |
0304af89 BH |
1559 | #undef GEN_VXFORM_NOA |
1560 | #undef GEN_VXFORM_UIMM | |
1561 | #undef GEN_VAFORM_PAIRED | |
b8155872 JRZ |
1562 | |
1563 | #undef GEN_BCD2 |